Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1680	1			T16	2		T104	3		T47	4
all_values[1]	1596	1			T16	5		T104	3		T47	2
all_values[2]	1584	1			T16	6		T104	2		T47	3
all_values[3]	1640	1			T16	6		T53	1		T104	6
all_values[4]	1585	1			T16	2		T53	2		T104	1
all_values[5]	1644	1			T104	4		T47	3		T39	4
all_values[6]	1607	1			T16	2		T53	1		T104	1
all_values[7]	1601	1			T16	1		T53	1		T104	3
all_values[8]	1612	1			T16	2		T53	1		T104	5
all_values[9]	1591	1			T16	1		T104	2		T47	1
all_values[10]	1623	1			T16	2		T53	1		T104	4
all_values[11]	1662	1			T16	2		T104	2		T47	2
all_values[12]	1618	1			T16	5		T104	4		T47	1
all_values[13]	1624	1			T16	2		T53	1		T104	6
all_values[14]	1545	1			T104	3		T47	1		T39	4
all_values[15]	1643	1			T104	8		T39	3		T244	1
all_values[16]	1637	1			T104	4		T47	1		T39	4
all_values[17]	1593	1			T16	1		T53	2		T104	2
all_values[18]	1551	1			T16	1		T53	1		T104	3
all_values[19]	1570	1			T16	4		T53	1		T47	3
all_values[20]	1614	1			T104	2		T39	3		T244	3
all_values[21]	1594	1			T16	2		T53	1		T104	1
all_values[22]	1654	1			T16	4		T104	1		T47	4
all_values[23]	1620	1			T16	2		T104	1		T47	2
all_values[24]	1626	1			T16	2		T104	1		T47	2
all_values[25]	1660	1			T16	2		T104	4		T47	1
all_values[26]	1656	1			T16	2		T104	5		T47	3
all_values[27]	1661	1			T16	2		T104	4		T47	1
all_values[28]	1607	1			T16	3		T53	1		T47	1
all_values[29]	1628	1			T16	3		T53	1		T104	4
all_values[30]	1606	1			T16	2		T53	1		T104	3
all_values[31]	1563	1			T16	1		T53	2		T104	2
all_values[32]	1676	1			T16	2		T53	2		T104	2
all_values[33]	1636	1			T16	3		T53	1		T104	6
all_values[34]	1664	1			T16	5		T104	1		T39	1
all_values[35]	1583	1			T16	1		T104	1		T47	1
all_values[36]	1616	1			T16	4		T104	3		T47	6
all_values[37]	1632	1			T16	2		T53	1		T104	6
all_values[38]	1554	1			T16	3		T53	2		T104	2
all_values[39]	1571	1			T16	3		T104	1		T47	2
all_values[40]	1614	1			T16	2		T53	1		T104	2
all_values[41]	1642	1			T16	3		T39	4		T244	3
all_values[42]	1591	1			T16	3		T53	1		T104	3
all_values[43]	1565	1			T16	2		T104	2		T47	3
all_values[44]	1581	1			T16	4		T104	3		T47	1
all_values[45]	1603	1			T16	1		T53	3		T104	3
all_values[46]	1568	1			T104	3		T47	2		T39	1
all_values[47]	1576	1			T16	2		T53	1		T104	6
all_values[48]	1578	1			T16	2		T53	2		T47	2
all_values[49]	1620	1			T16	1		T104	1		T47	1
all_values[50]	1623	1			T16	4		T104	4		T47	2
all_values[51]	1677	1			T16	4		T53	1		T47	3
all_values[52]	1571	1			T16	6		T104	3		T47	3
all_values[53]	1660	1			T16	3		T104	2		T47	3
all_values[54]	1621	1			T16	1		T104	4		T47	2
all_values[55]	1634	1			T16	3		T53	1		T39	1
all_values[56]	1598	1			T16	5		T104	1		T47	1
all_values[57]	1596	1			T16	2		T104	2		T47	4
all_values[58]	1597	1			T16	3		T104	6		T39	4
all_values[59]	1581	1			T104	1		T47	1		T39	3
all_values[60]	1655	1			T16	3		T53	2		T104	1
all_values[61]	1629	1			T16	2		T104	6		T39	1
all_values[62]	1600	1			T16	2		T39	4		T244	4
all_values[63]	1570	1			T16	1		T104	4		T47	2