| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.02 | 99.26 | 88.89 | 98.80 | 95.88 | 99.26 | 100.00 |
| T764 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.482328414 | Sep 09 04:06:23 AM UTC 24 | Sep 09 04:11:28 AM UTC 24 | 3079499717 ps | ||
| T765 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.44308429 | Sep 09 04:11:00 AM UTC 24 | Sep 09 04:11:31 AM UTC 24 | 3759524447 ps | ||
| T766 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.4206101405 | Sep 09 04:11:30 AM UTC 24 | Sep 09 04:11:34 AM UTC 24 | 55856598 ps | ||
| T767 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1077435509 | Sep 09 04:11:32 AM UTC 24 | Sep 09 04:11:36 AM UTC 24 | 85662988 ps | ||
| T768 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.3348463151 | Sep 09 04:11:03 AM UTC 24 | Sep 09 04:11:37 AM UTC 24 | 595572769 ps | ||
| T769 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.29886243 | Sep 09 04:11:05 AM UTC 24 | Sep 09 04:11:38 AM UTC 24 | 304393911 ps | ||
| T770 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2140989837 | Sep 09 04:11:19 AM UTC 24 | Sep 09 04:11:40 AM UTC 24 | 150273433 ps | ||
| T771 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.4235337832 | Sep 09 04:11:16 AM UTC 24 | Sep 09 04:11:40 AM UTC 24 | 121110308 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.4132621612 | Sep 09 04:09:08 AM UTC 24 | Sep 09 04:11:41 AM UTC 24 | 31613318980 ps | ||
| T772 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.93915503 | Sep 09 04:10:54 AM UTC 24 | Sep 09 04:11:42 AM UTC 24 | 157244691 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1548154502 | Sep 09 03:57:48 AM UTC 24 | Sep 09 04:11:43 AM UTC 24 | 100284164992 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3274983982 | Sep 09 04:11:13 AM UTC 24 | Sep 09 04:11:47 AM UTC 24 | 3289370440 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1274588858 | Sep 09 04:10:58 AM UTC 24 | Sep 09 04:11:48 AM UTC 24 | 37004758300 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.4134946555 | Sep 09 04:11:02 AM UTC 24 | Sep 09 04:11:48 AM UTC 24 | 2951371340 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1175895193 | Sep 09 04:11:44 AM UTC 24 | Sep 09 04:11:48 AM UTC 24 | 34128815 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1991391865 | Sep 09 04:08:46 AM UTC 24 | Sep 09 04:11:49 AM UTC 24 | 29591886507 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2062927646 | Sep 09 04:11:15 AM UTC 24 | Sep 09 04:11:52 AM UTC 24 | 1124636618 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1715894663 | Sep 09 04:11:49 AM UTC 24 | Sep 09 04:11:54 AM UTC 24 | 68025426 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2980680604 | Sep 09 04:10:22 AM UTC 24 | Sep 09 04:11:58 AM UTC 24 | 695475085 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.812936669 | Sep 09 04:05:08 AM UTC 24 | Sep 09 04:11:59 AM UTC 24 | 4323476380 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1241474748 | Sep 09 04:11:38 AM UTC 24 | Sep 09 04:11:59 AM UTC 24 | 209193425 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3114821939 | Sep 09 04:04:22 AM UTC 24 | Sep 09 04:12:00 AM UTC 24 | 58592847314 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.1122234998 | Sep 09 04:09:08 AM UTC 24 | Sep 09 04:12:01 AM UTC 24 | 30980034730 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.382389741 | Sep 09 04:11:39 AM UTC 24 | Sep 09 04:12:03 AM UTC 24 | 363624492 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.2106592360 | Sep 09 04:11:59 AM UTC 24 | Sep 09 04:12:04 AM UTC 24 | 46322178 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.4131696138 | Sep 09 04:11:49 AM UTC 24 | Sep 09 04:12:05 AM UTC 24 | 73758646 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1125694248 | Sep 09 04:12:02 AM UTC 24 | Sep 09 04:12:05 AM UTC 24 | 41562306 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3767762205 | Sep 09 04:10:22 AM UTC 24 | Sep 09 04:12:08 AM UTC 24 | 5420133961 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2295779385 | Sep 09 04:08:10 AM UTC 24 | Sep 09 04:12:10 AM UTC 24 | 39761070425 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.4197540230 | Sep 09 04:11:36 AM UTC 24 | Sep 09 04:12:12 AM UTC 24 | 4540605287 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.678064414 | Sep 09 04:11:35 AM UTC 24 | Sep 09 04:12:13 AM UTC 24 | 4750050799 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3786161530 | Sep 09 04:11:49 AM UTC 24 | Sep 09 04:12:17 AM UTC 24 | 2671962512 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.1325967421 | Sep 09 04:12:04 AM UTC 24 | Sep 09 04:12:18 AM UTC 24 | 128880631 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.2409875912 | Sep 09 04:12:11 AM UTC 24 | Sep 09 04:12:19 AM UTC 24 | 72058419 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1270651642 | Sep 09 04:12:13 AM UTC 24 | Sep 09 04:12:20 AM UTC 24 | 139145574 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3689747271 | Sep 09 04:12:18 AM UTC 24 | Sep 09 04:12:23 AM UTC 24 | 64220334 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.260778529 | Sep 09 04:11:42 AM UTC 24 | Sep 09 04:12:25 AM UTC 24 | 502561242 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.2732606283 | Sep 09 04:12:05 AM UTC 24 | Sep 09 04:12:32 AM UTC 24 | 3589951577 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3627083239 | Sep 09 04:12:02 AM UTC 24 | Sep 09 04:12:34 AM UTC 24 | 7652740586 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.643446400 | Sep 09 04:12:02 AM UTC 24 | Sep 09 04:12:35 AM UTC 24 | 530942980 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3209720257 | Sep 09 04:12:02 AM UTC 24 | Sep 09 04:12:38 AM UTC 24 | 3833176068 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3234520666 | Sep 09 04:11:05 AM UTC 24 | Sep 09 04:12:40 AM UTC 24 | 24427768731 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2571697480 | Sep 09 04:10:01 AM UTC 24 | Sep 09 04:12:42 AM UTC 24 | 7786792847 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.39129749 | Sep 09 04:05:27 AM UTC 24 | Sep 09 04:12:43 AM UTC 24 | 64848388094 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2171561843 | Sep 09 04:02:19 AM UTC 24 | Sep 09 04:12:44 AM UTC 24 | 67884793628 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2010307925 | Sep 09 04:08:53 AM UTC 24 | Sep 09 04:12:47 AM UTC 24 | 16754117250 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3627484788 | Sep 09 04:08:11 AM UTC 24 | Sep 09 04:12:48 AM UTC 24 | 77533620859 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.1753177176 | Sep 09 04:12:07 AM UTC 24 | Sep 09 04:12:52 AM UTC 24 | 1176142311 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.757209511 | Sep 09 04:09:15 AM UTC 24 | Sep 09 04:12:52 AM UTC 24 | 1199618031 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3538490635 | Sep 09 04:12:48 AM UTC 24 | Sep 09 04:12:53 AM UTC 24 | 24430994 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.86897046 | Sep 09 04:12:30 AM UTC 24 | Sep 09 04:12:56 AM UTC 24 | 199186721 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.644950286 | Sep 09 04:12:44 AM UTC 24 | Sep 09 04:12:58 AM UTC 24 | 92653340 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3141780177 | Sep 09 04:12:30 AM UTC 24 | Sep 09 04:12:59 AM UTC 24 | 2931093031 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.621422895 | Sep 09 04:12:43 AM UTC 24 | Sep 09 04:13:00 AM UTC 24 | 942736417 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2052175514 | Sep 09 04:11:21 AM UTC 24 | Sep 09 04:13:01 AM UTC 24 | 212522057 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.740334451 | Sep 09 04:08:41 AM UTC 24 | Sep 09 04:13:03 AM UTC 24 | 24020346492 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1692071831 | Sep 09 04:12:57 AM UTC 24 | Sep 09 04:13:04 AM UTC 24 | 194484610 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2051694172 | Sep 09 04:13:00 AM UTC 24 | Sep 09 04:13:05 AM UTC 24 | 46615251 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2770709959 | Sep 09 04:12:34 AM UTC 24 | Sep 09 04:13:09 AM UTC 24 | 192267629 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.4034701510 | Sep 09 04:10:09 AM UTC 24 | Sep 09 04:13:15 AM UTC 24 | 41683364635 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.207480850 | Sep 09 04:12:46 AM UTC 24 | Sep 09 04:13:16 AM UTC 24 | 669062913 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1271929458 | Sep 09 04:09:52 AM UTC 24 | Sep 09 04:13:16 AM UTC 24 | 42295174797 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.3655890741 | Sep 09 04:11:21 AM UTC 24 | Sep 09 04:13:18 AM UTC 24 | 4319872962 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.2226206538 | Sep 09 04:09:50 AM UTC 24 | Sep 09 04:13:20 AM UTC 24 | 75098699509 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3736401387 | Sep 09 04:11:53 AM UTC 24 | Sep 09 04:13:20 AM UTC 24 | 2089121727 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.117242890 | Sep 09 04:12:55 AM UTC 24 | Sep 09 04:13:24 AM UTC 24 | 105616950 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3129757242 | Sep 09 04:11:49 AM UTC 24 | Sep 09 04:13:25 AM UTC 24 | 1202803261 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.3894508690 | Sep 09 04:13:05 AM UTC 24 | Sep 09 04:13:29 AM UTC 24 | 175727109 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.832735125 | Sep 09 04:12:39 AM UTC 24 | Sep 09 04:13:29 AM UTC 24 | 497808368 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.2021478550 | Sep 09 04:13:17 AM UTC 24 | Sep 09 04:13:31 AM UTC 24 | 191772018 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1379078014 | Sep 09 04:11:22 AM UTC 24 | Sep 09 04:13:33 AM UTC 24 | 10246056882 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.744311125 | Sep 09 04:13:31 AM UTC 24 | Sep 09 04:13:35 AM UTC 24 | 34572935 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2703741173 | Sep 09 04:13:03 AM UTC 24 | Sep 09 04:13:35 AM UTC 24 | 1321559013 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.4050618498 | Sep 09 04:12:26 AM UTC 24 | Sep 09 04:13:36 AM UTC 24 | 27612995301 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.1969915273 | Sep 09 04:09:59 AM UTC 24 | Sep 09 04:13:36 AM UTC 24 | 7010726402 ps | ||
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| T835 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.106332560 | Sep 09 04:13:20 AM UTC 24 | Sep 09 04:13:37 AM UTC 24 | 183073059 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.133292408 | Sep 09 04:13:33 AM UTC 24 | Sep 09 04:13:37 AM UTC 24 | 31783940 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2544190111 | Sep 09 04:03:40 AM UTC 24 | Sep 09 04:13:37 AM UTC 24 | 114166099057 ps | ||
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| T839 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.344961237 | Sep 09 04:13:18 AM UTC 24 | Sep 09 04:13:46 AM UTC 24 | 2001945941 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1728211894 | Sep 09 04:10:18 AM UTC 24 | Sep 09 04:13:47 AM UTC 24 | 3237687224 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1397907962 | Sep 09 04:13:02 AM UTC 24 | Sep 09 04:13:47 AM UTC 24 | 11890315001 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.368734351 | Sep 09 04:13:01 AM UTC 24 | Sep 09 04:13:47 AM UTC 24 | 4130986809 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1620222178 | Sep 09 04:09:18 AM UTC 24 | Sep 09 04:13:48 AM UTC 24 | 4568947563 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2715279864 | Sep 09 04:13:21 AM UTC 24 | Sep 09 04:13:50 AM UTC 24 | 1425386144 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1908832822 | Sep 09 04:08:00 AM UTC 24 | Sep 09 04:13:50 AM UTC 24 | 1281692577 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2565675271 | Sep 09 04:13:38 AM UTC 24 | Sep 09 04:13:53 AM UTC 24 | 150524627 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3634155930 | Sep 09 04:13:49 AM UTC 24 | Sep 09 04:13:55 AM UTC 24 | 92797864 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1458190901 | Sep 09 04:13:41 AM UTC 24 | Sep 09 04:13:57 AM UTC 24 | 688290248 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.439168524 | Sep 09 04:10:42 AM UTC 24 | Sep 09 04:14:04 AM UTC 24 | 22564969855 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2406367541 | Sep 09 04:13:11 AM UTC 24 | Sep 09 04:14:05 AM UTC 24 | 1469092196 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1139246389 | Sep 09 04:02:51 AM UTC 24 | Sep 09 04:14:06 AM UTC 24 | 186469591051 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.2235735516 | Sep 09 04:13:45 AM UTC 24 | Sep 09 04:14:08 AM UTC 24 | 743380795 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.687343794 | Sep 09 04:09:29 AM UTC 24 | Sep 09 04:14:08 AM UTC 24 | 35525987237 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.123062686 | Sep 09 04:11:05 AM UTC 24 | Sep 09 04:14:07 AM UTC 24 | 23385856134 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1585094628 | Sep 09 04:11:42 AM UTC 24 | Sep 09 04:14:08 AM UTC 24 | 12799174478 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.1987496658 | Sep 09 04:13:47 AM UTC 24 | Sep 09 04:14:08 AM UTC 24 | 1279068908 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1226691040 | Sep 09 04:13:38 AM UTC 24 | Sep 09 04:14:11 AM UTC 24 | 10753626576 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.4016863164 | Sep 09 04:13:35 AM UTC 24 | Sep 09 04:14:15 AM UTC 24 | 6977342343 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2942053775 | Sep 09 04:11:42 AM UTC 24 | Sep 09 04:14:16 AM UTC 24 | 24649835356 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.2527780417 | Sep 09 04:13:22 AM UTC 24 | Sep 09 04:14:19 AM UTC 24 | 631648704 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.300515002 | Sep 09 04:09:27 AM UTC 24 | Sep 09 04:14:19 AM UTC 24 | 94650012862 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.1289479236 | Sep 09 04:13:38 AM UTC 24 | Sep 09 04:14:19 AM UTC 24 | 1317372293 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.613328543 | Sep 09 04:13:41 AM UTC 24 | Sep 09 04:14:21 AM UTC 24 | 4353145685 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.197100363 | Sep 09 04:13:31 AM UTC 24 | Sep 09 04:14:23 AM UTC 24 | 962882933 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.2146910139 | Sep 09 04:12:36 AM UTC 24 | Sep 09 04:14:29 AM UTC 24 | 61708735842 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2400978926 | Sep 09 04:12:22 AM UTC 24 | Sep 09 04:14:40 AM UTC 24 | 469104412 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2160678580 | Sep 09 04:11:03 AM UTC 24 | Sep 09 04:14:47 AM UTC 24 | 95961199426 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3873839965 | Sep 09 04:00:53 AM UTC 24 | Sep 09 04:14:48 AM UTC 24 | 108692478181 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3033910646 | Sep 09 04:10:40 AM UTC 24 | Sep 09 04:14:51 AM UTC 24 | 84053595097 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1701711450 | Sep 09 04:12:22 AM UTC 24 | Sep 09 04:14:52 AM UTC 24 | 1055180798 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3828762737 | Sep 09 04:07:43 AM UTC 24 | Sep 09 04:14:56 AM UTC 24 | 110105922069 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.589546828 | Sep 09 04:12:20 AM UTC 24 | Sep 09 04:14:57 AM UTC 24 | 4941719048 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3234432981 | Sep 09 04:05:43 AM UTC 24 | Sep 09 04:15:03 AM UTC 24 | 57294416753 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2991640713 | Sep 09 04:13:51 AM UTC 24 | Sep 09 04:15:06 AM UTC 24 | 13199576401 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2702946357 | Sep 09 04:12:36 AM UTC 24 | Sep 09 04:15:07 AM UTC 24 | 38230943219 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1599032379 | Sep 09 04:08:56 AM UTC 24 | Sep 09 04:15:09 AM UTC 24 | 7455866055 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1138693343 | Sep 09 04:07:09 AM UTC 24 | Sep 09 04:15:09 AM UTC 24 | 77477846563 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3327139954 | Sep 09 04:10:03 AM UTC 24 | Sep 09 04:15:14 AM UTC 24 | 1323106946 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.1490238624 | Sep 09 04:12:50 AM UTC 24 | Sep 09 04:15:22 AM UTC 24 | 4390610482 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1545666447 | Sep 09 04:09:21 AM UTC 24 | Sep 09 04:15:22 AM UTC 24 | 2028098560 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1959919264 | Sep 09 04:13:49 AM UTC 24 | Sep 09 04:15:35 AM UTC 24 | 173074364 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3875134953 | Sep 09 04:13:06 AM UTC 24 | Sep 09 04:15:48 AM UTC 24 | 42314311174 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1006414723 | Sep 09 04:09:34 AM UTC 24 | Sep 09 04:15:57 AM UTC 24 | 982786987 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1387153617 | Sep 09 04:11:51 AM UTC 24 | Sep 09 04:16:07 AM UTC 24 | 4834603504 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.749071712 | Sep 09 04:12:20 AM UTC 24 | Sep 09 04:16:09 AM UTC 24 | 1081236256 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.3329657999 | Sep 09 04:13:05 AM UTC 24 | Sep 09 04:16:20 AM UTC 24 | 80158835887 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2359258904 | Sep 09 04:12:07 AM UTC 24 | Sep 09 04:16:26 AM UTC 24 | 35273115272 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.649883670 | Sep 09 04:12:53 AM UTC 24 | Sep 09 04:16:31 AM UTC 24 | 4629764556 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.4240042700 | Sep 09 04:13:40 AM UTC 24 | Sep 09 04:16:38 AM UTC 24 | 23782377138 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2550120658 | Sep 09 04:13:25 AM UTC 24 | Sep 09 04:16:41 AM UTC 24 | 4005422565 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2213458576 | Sep 09 04:13:27 AM UTC 24 | Sep 09 04:16:45 AM UTC 24 | 10500385394 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2072064996 | Sep 09 04:10:21 AM UTC 24 | Sep 09 04:16:47 AM UTC 24 | 5184867672 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.860703352 | Sep 09 04:09:08 AM UTC 24 | Sep 09 04:17:18 AM UTC 24 | 154775394166 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.930992460 | Sep 09 04:10:51 AM UTC 24 | Sep 09 04:17:28 AM UTC 24 | 1880504426 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.627695555 | Sep 09 04:13:40 AM UTC 24 | Sep 09 04:17:42 AM UTC 24 | 23933518574 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2876936433 | Sep 09 04:13:49 AM UTC 24 | Sep 09 04:17:57 AM UTC 24 | 9016398024 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3516284787 | Sep 09 04:12:10 AM UTC 24 | Sep 09 04:18:33 AM UTC 24 | 118966697658 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.4169237876 | Sep 09 04:11:29 AM UTC 24 | Sep 09 04:18:37 AM UTC 24 | 12336994472 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2715649458 | Sep 09 04:09:32 AM UTC 24 | Sep 09 04:19:08 AM UTC 24 | 95946026143 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1805824458 | Sep 09 04:08:13 AM UTC 24 | Sep 09 04:20:19 AM UTC 24 | 167982758651 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1670994315 | Sep 09 04:13:17 AM UTC 24 | Sep 09 04:20:41 AM UTC 24 | 50167701115 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.135000684 | Sep 09 04:12:42 AM UTC 24 | Sep 09 04:20:54 AM UTC 24 | 58879896027 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1869988810 | Sep 09 04:11:44 AM UTC 24 | Sep 09 04:21:50 AM UTC 24 | 73048496317 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.749303710 | Sep 09 04:10:11 AM UTC 24 | Sep 09 04:22:29 AM UTC 24 | 145224340191 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3242401032 | Sep 09 04:13:52 AM UTC 24 | Sep 09 04:22:32 AM UTC 24 | 4852073105 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1052562609 | Sep 09 04:09:59 AM UTC 24 | Sep 09 04:22:33 AM UTC 24 | 17605856508 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2597871110 | Sep 09 04:09:52 AM UTC 24 | Sep 09 04:22:51 AM UTC 24 | 155651823079 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2032737204 | Sep 09 04:13:41 AM UTC 24 | Sep 09 04:27:07 AM UTC 24 | 306797896181 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3344671195 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 342373093 ps |
| CPU time | 4.94 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:54:08 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344671195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3344671195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.190066552 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 54188504603 ps |
| CPU time | 459.82 seconds |
| Started | Sep 09 03:54:57 AM UTC 24 |
| Finished | Sep 09 04:02:42 AM UTC 24 |
| Peak memory | 221000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190066552 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.190066552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.848580869 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5550537472 ps |
| CPU time | 64.9 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:55:19 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848580869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.848580869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.708523561 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 64771241358 ps |
| CPU time | 600.97 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 04:04:21 AM UTC 24 |
| Peak memory | 222548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708523561 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.708523561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.1121424187 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1152446252 ps |
| CPU time | 40.04 seconds |
| Started | Sep 09 03:57:26 AM UTC 24 |
| Finished | Sep 09 03:58:07 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121424187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1121424187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.1396580149 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 21174788 ps |
| CPU time | 2.08 seconds |
| Started | Sep 09 03:53:59 AM UTC 24 |
| Finished | Sep 09 03:54:02 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396580149 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1396580149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.379412051 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 55694362907 ps |
| CPU time | 437.34 seconds |
| Started | Sep 09 03:55:34 AM UTC 24 |
| Finished | Sep 09 04:02:57 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379412051 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.379412051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3963953404 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13171525202 ps |
| CPU time | 160.79 seconds |
| Started | Sep 09 03:54:01 AM UTC 24 |
| Finished | Sep 09 03:56:56 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963953404 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.3963953404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.1066627381 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 106860075 ps |
| CPU time | 26.56 seconds |
| Started | Sep 09 03:53:53 AM UTC 24 |
| Finished | Sep 09 03:54:41 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066627381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.1066627381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.68964642 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 13197685880 ps |
| CPU time | 266.1 seconds |
| Started | Sep 09 03:55:18 AM UTC 24 |
| Finished | Sep 09 03:59:49 AM UTC 24 |
| Peak memory | 223352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68964642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.68964642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1629602439 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 5851899362 ps |
| CPU time | 28.54 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:54:29 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629602439 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1629602439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.299417025 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 349775792 ps |
| CPU time | 8.74 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:54:17 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299417025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.299417025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.2413848059 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1302185861 ps |
| CPU time | 43.88 seconds |
| Started | Sep 09 03:54:39 AM UTC 24 |
| Finished | Sep 09 03:55:25 AM UTC 24 |
| Peak memory | 218824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413848059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2413848059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3594159872 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 436762147 ps |
| CPU time | 156.07 seconds |
| Started | Sep 09 03:55:20 AM UTC 24 |
| Finished | Sep 09 03:57:59 AM UTC 24 |
| Peak memory | 221196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594159872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.3594159872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.1956012080 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2295355232 ps |
| CPU time | 30.73 seconds |
| Started | Sep 09 03:55:10 AM UTC 24 |
| Finished | Sep 09 03:55:42 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956012080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1956012080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3380311524 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 12361479569 ps |
| CPU time | 419.24 seconds |
| Started | Sep 09 03:54:30 AM UTC 24 |
| Finished | Sep 09 04:01:35 AM UTC 24 |
| Peak memory | 223308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380311524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.3380311524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.3720531295 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1583075172 ps |
| CPU time | 28.64 seconds |
| Started | Sep 09 03:54:28 AM UTC 24 |
| Finished | Sep 09 03:54:58 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720531295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3720531295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.4225191696 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1749333396 ps |
| CPU time | 207.91 seconds |
| Started | Sep 09 03:56:02 AM UTC 24 |
| Finished | Sep 09 03:59:33 AM UTC 24 |
| Peak memory | 222988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225191696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.4225191696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1019417712 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2247067793 ps |
| CPU time | 320.05 seconds |
| Started | Sep 09 04:02:34 AM UTC 24 |
| Finished | Sep 09 04:07:58 AM UTC 24 |
| Peak memory | 233656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019417712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.1019417712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1620222178 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 4568947563 ps |
| CPU time | 265.97 seconds |
| Started | Sep 09 04:09:18 AM UTC 24 |
| Finished | Sep 09 04:13:48 AM UTC 24 |
| Peak memory | 223048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620222178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.1620222178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.2317127779 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 172251069 ps |
| CPU time | 14.28 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:54:17 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317127779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2317127779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.943967803 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 812525588 ps |
| CPU time | 175.41 seconds |
| Started | Sep 09 03:57:37 AM UTC 24 |
| Finished | Sep 09 04:00:35 AM UTC 24 |
| Peak memory | 223284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943967803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.943967803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3228895044 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 118279371684 ps |
| CPU time | 811.18 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 04:07:42 AM UTC 24 |
| Peak memory | 222548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228895044 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.3228895044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.2372752318 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 487353046 ps |
| CPU time | 14.42 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:54:07 AM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372752318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2372752318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.4061627097 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1052980808 ps |
| CPU time | 61.81 seconds |
| Started | Sep 09 03:56:41 AM UTC 24 |
| Finished | Sep 09 03:57:45 AM UTC 24 |
| Peak memory | 220872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061627097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.4061627097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.215774693 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7461731565 ps |
| CPU time | 194.99 seconds |
| Started | Sep 09 03:58:44 AM UTC 24 |
| Finished | Sep 09 04:02:02 AM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215774693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.215774693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.661859303 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 249141593 ps |
| CPU time | 20.05 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:54:23 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661859303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.661859303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.29840919 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 848084614 ps |
| CPU time | 28.67 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:54:29 AM UTC 24 |
| Peak memory | 216952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29840919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.29840919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.1726566899 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 27548530558 ps |
| CPU time | 64.51 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:55:05 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726566899 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1726566899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1971791311 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 39965590886 ps |
| CPU time | 330.5 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:59:34 AM UTC 24 |
| Peak memory | 217284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971791311 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1971791311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.2175329679 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 494155574 ps |
| CPU time | 20.43 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:54:21 AM UTC 24 |
| Peak memory | 216704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175329679 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2175329679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.3594299596 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 256063886 ps |
| CPU time | 2.56 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:54:03 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594299596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3594299596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1292451376 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5122332905 ps |
| CPU time | 22.93 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:54:23 AM UTC 24 |
| Peak memory | 217044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292451376 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1292451376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2813927950 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 29650143 ps |
| CPU time | 2.16 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:54:02 AM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813927950 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2813927950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.1891656981 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 884788052 ps |
| CPU time | 121.23 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:56:06 AM UTC 24 |
| Peak memory | 220920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891656981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1891656981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3485027100 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1109976828 ps |
| CPU time | 27.31 seconds |
| Started | Sep 09 03:53:53 AM UTC 24 |
| Finished | Sep 09 03:54:42 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485027100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3485027100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.2231092501 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 101895763 ps |
| CPU time | 27.74 seconds |
| Started | Sep 09 03:53:53 AM UTC 24 |
| Finished | Sep 09 03:54:32 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231092501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.2231092501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.536796058 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 149547318 ps |
| CPU time | 24.37 seconds |
| Started | Sep 09 03:53:52 AM UTC 24 |
| Finished | Sep 09 03:54:28 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536796058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.536796058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1797748976 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 154052363 ps |
| CPU time | 16.06 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:54:24 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797748976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1797748976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.612853470 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 342095357 ps |
| CPU time | 12.19 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:54:26 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612853470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.612853470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.498824653 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 920019295 ps |
| CPU time | 32.05 seconds |
| Started | Sep 09 03:53:59 AM UTC 24 |
| Finished | Sep 09 03:54:32 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498824653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.498824653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.3027630497 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 12285205259 ps |
| CPU time | 67.66 seconds |
| Started | Sep 09 03:53:59 AM UTC 24 |
| Finished | Sep 09 03:55:08 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027630497 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3027630497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1477308068 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 40390058596 ps |
| CPU time | 113.11 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:56:08 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477308068 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1477308068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.3823924015 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 273564412 ps |
| CPU time | 17.89 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:54:32 AM UTC 24 |
| Peak memory | 216664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823924015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3823924015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.3212801033 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 173714951 ps |
| CPU time | 3.04 seconds |
| Started | Sep 09 03:53:54 AM UTC 24 |
| Finished | Sep 09 03:54:01 AM UTC 24 |
| Peak memory | 217132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212801033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3212801033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3321984878 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 30503132076 ps |
| CPU time | 44.19 seconds |
| Started | Sep 09 03:53:55 AM UTC 24 |
| Finished | Sep 09 03:54:44 AM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321984878 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3321984878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2929932001 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4236949177 ps |
| CPU time | 26.07 seconds |
| Started | Sep 09 03:53:57 AM UTC 24 |
| Finished | Sep 09 03:54:25 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929932001 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2929932001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3515717214 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 27277368 ps |
| CPU time | 1.87 seconds |
| Started | Sep 09 03:53:54 AM UTC 24 |
| Finished | Sep 09 03:54:00 AM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515717214 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3515717214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.343156937 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 9864004012 ps |
| CPU time | 194.49 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:57:25 AM UTC 24 |
| Peak memory | 220992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343156937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.343156937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1313477142 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 4319554084 ps |
| CPU time | 98.43 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:55:48 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313477142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1313477142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1747723677 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 650982970 ps |
| CPU time | 177.9 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:57:08 AM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747723677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.1747723677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2481032193 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 262438544 ps |
| CPU time | 56.9 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:55:06 AM UTC 24 |
| Peak memory | 218640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481032193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.2481032193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.318321337 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 534978587 ps |
| CPU time | 21.77 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:54:36 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318321337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.318321337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.3948051959 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 261478936 ps |
| CPU time | 29.62 seconds |
| Started | Sep 09 03:56:09 AM UTC 24 |
| Finished | Sep 09 03:56:40 AM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948051959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3948051959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.370683206 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 208138473088 ps |
| CPU time | 565.53 seconds |
| Started | Sep 09 03:56:09 AM UTC 24 |
| Finished | Sep 09 04:05:41 AM UTC 24 |
| Peak memory | 222616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370683206 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.370683206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2497668655 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 155924200 ps |
| CPU time | 17.3 seconds |
| Started | Sep 09 03:56:10 AM UTC 24 |
| Finished | Sep 09 03:56:29 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497668655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2497668655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.1957680995 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 769778558 ps |
| CPU time | 17.33 seconds |
| Started | Sep 09 03:56:09 AM UTC 24 |
| Finished | Sep 09 03:56:27 AM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957680995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1957680995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.3673102377 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 365432277 ps |
| CPU time | 26.65 seconds |
| Started | Sep 09 03:56:06 AM UTC 24 |
| Finished | Sep 09 03:56:34 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673102377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3673102377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.1511995865 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 44120294361 ps |
| CPU time | 258.66 seconds |
| Started | Sep 09 03:56:08 AM UTC 24 |
| Finished | Sep 09 04:00:30 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511995865 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1511995865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3705441614 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 74041874174 ps |
| CPU time | 279.74 seconds |
| Started | Sep 09 03:56:08 AM UTC 24 |
| Finished | Sep 09 04:00:51 AM UTC 24 |
| Peak memory | 217160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705441614 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3705441614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.3108461040 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 157299666 ps |
| CPU time | 19.86 seconds |
| Started | Sep 09 03:56:08 AM UTC 24 |
| Finished | Sep 09 03:56:29 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108461040 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3108461040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.2855087297 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 5116192383 ps |
| CPU time | 31.85 seconds |
| Started | Sep 09 03:56:09 AM UTC 24 |
| Finished | Sep 09 03:56:42 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855087297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2855087297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.1795755156 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 35287163 ps |
| CPU time | 3.15 seconds |
| Started | Sep 09 03:56:03 AM UTC 24 |
| Finished | Sep 09 03:56:07 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795755156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1795755156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3105305818 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 13395702701 ps |
| CPU time | 51.91 seconds |
| Started | Sep 09 03:56:05 AM UTC 24 |
| Finished | Sep 09 03:56:59 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105305818 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3105305818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3283288961 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3075973492 ps |
| CPU time | 23.53 seconds |
| Started | Sep 09 03:56:06 AM UTC 24 |
| Finished | Sep 09 03:56:31 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283288961 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3283288961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3965964957 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 24385966 ps |
| CPU time | 2.82 seconds |
| Started | Sep 09 03:56:04 AM UTC 24 |
| Finished | Sep 09 03:56:08 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965964957 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3965964957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.897703557 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4671414198 ps |
| CPU time | 149.71 seconds |
| Started | Sep 09 03:56:10 AM UTC 24 |
| Finished | Sep 09 03:58:43 AM UTC 24 |
| Peak memory | 223300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897703557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.897703557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.4116360766 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 8018738299 ps |
| CPU time | 242.35 seconds |
| Started | Sep 09 03:56:14 AM UTC 24 |
| Finished | Sep 09 04:00:21 AM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116360766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.4116360766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.964618140 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 5452487788 ps |
| CPU time | 91.21 seconds |
| Started | Sep 09 03:56:13 AM UTC 24 |
| Finished | Sep 09 03:57:47 AM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964618140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.964618140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.546083909 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 68870150 ps |
| CPU time | 35.1 seconds |
| Started | Sep 09 03:56:18 AM UTC 24 |
| Finished | Sep 09 03:56:54 AM UTC 24 |
| Peak memory | 219136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546083909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.546083909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.237238580 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 118107769 ps |
| CPU time | 10.52 seconds |
| Started | Sep 09 03:56:10 AM UTC 24 |
| Finished | Sep 09 03:56:22 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237238580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.237238580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.1086292743 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1770181100 ps |
| CPU time | 57.75 seconds |
| Started | Sep 09 03:56:29 AM UTC 24 |
| Finished | Sep 09 03:57:29 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086292743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1086292743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.12447846 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 53957838673 ps |
| CPU time | 422.99 seconds |
| Started | Sep 09 03:56:30 AM UTC 24 |
| Finished | Sep 09 04:03:38 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12447846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.12447846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2736592661 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 121783133 ps |
| CPU time | 20.24 seconds |
| Started | Sep 09 03:56:36 AM UTC 24 |
| Finished | Sep 09 03:56:58 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736592661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2736592661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.190442819 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 81990157 ps |
| CPU time | 6.41 seconds |
| Started | Sep 09 03:56:32 AM UTC 24 |
| Finished | Sep 09 03:56:39 AM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190442819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.190442819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.202310375 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 570889474 ps |
| CPU time | 13.69 seconds |
| Started | Sep 09 03:56:27 AM UTC 24 |
| Finished | Sep 09 03:56:42 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202310375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.202310375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.162320065 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 39705725873 ps |
| CPU time | 145.16 seconds |
| Started | Sep 09 03:56:28 AM UTC 24 |
| Finished | Sep 09 03:58:56 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162320065 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.162320065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.271798298 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 18306064631 ps |
| CPU time | 159.86 seconds |
| Started | Sep 09 03:56:29 AM UTC 24 |
| Finished | Sep 09 03:59:12 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271798298 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.271798298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.3475362549 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 109606166 ps |
| CPU time | 11.69 seconds |
| Started | Sep 09 03:56:27 AM UTC 24 |
| Finished | Sep 09 03:56:40 AM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475362549 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3475362549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.2710236166 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 16642262 ps |
| CPU time | 2.63 seconds |
| Started | Sep 09 03:56:32 AM UTC 24 |
| Finished | Sep 09 03:56:35 AM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710236166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2710236166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.753103512 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 303307828 ps |
| CPU time | 3.27 seconds |
| Started | Sep 09 03:56:22 AM UTC 24 |
| Finished | Sep 09 03:56:26 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753103512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.753103512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1606540197 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 10886938158 ps |
| CPU time | 42.02 seconds |
| Started | Sep 09 03:56:23 AM UTC 24 |
| Finished | Sep 09 03:57:06 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606540197 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1606540197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1218673927 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 13398884638 ps |
| CPU time | 66.34 seconds |
| Started | Sep 09 03:56:26 AM UTC 24 |
| Finished | Sep 09 03:57:34 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218673927 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1218673927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.485983209 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 42629988 ps |
| CPU time | 3.61 seconds |
| Started | Sep 09 03:56:22 AM UTC 24 |
| Finished | Sep 09 03:56:26 AM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485983209 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.485983209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.1055877550 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1387699013 ps |
| CPU time | 168.71 seconds |
| Started | Sep 09 03:56:40 AM UTC 24 |
| Finished | Sep 09 03:59:32 AM UTC 24 |
| Peak memory | 220868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055877550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1055877550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1832267870 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4554782774 ps |
| CPU time | 118.19 seconds |
| Started | Sep 09 03:56:41 AM UTC 24 |
| Finished | Sep 09 03:58:42 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832267870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1832267870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1387069895 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1518369163 ps |
| CPU time | 83.61 seconds |
| Started | Sep 09 03:56:40 AM UTC 24 |
| Finished | Sep 09 03:58:06 AM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387069895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.1387069895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.1142679868 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 220975977 ps |
| CPU time | 3.84 seconds |
| Started | Sep 09 03:56:35 AM UTC 24 |
| Finished | Sep 09 03:56:40 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142679868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1142679868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.1281117099 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 472816796 ps |
| CPU time | 36.25 seconds |
| Started | Sep 09 03:56:55 AM UTC 24 |
| Finished | Sep 09 03:57:32 AM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281117099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1281117099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3879823118 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 111813307281 ps |
| CPU time | 713.76 seconds |
| Started | Sep 09 03:56:56 AM UTC 24 |
| Finished | Sep 09 04:08:58 AM UTC 24 |
| Peak memory | 222548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879823118 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.3879823118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1072966109 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 506821075 ps |
| CPU time | 22.11 seconds |
| Started | Sep 09 03:57:00 AM UTC 24 |
| Finished | Sep 09 03:57:24 AM UTC 24 |
| Peak memory | 217100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072966109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1072966109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.1057063021 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1196594165 ps |
| CPU time | 19.13 seconds |
| Started | Sep 09 03:56:58 AM UTC 24 |
| Finished | Sep 09 03:57:18 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057063021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1057063021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.2682341295 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 5173814828 ps |
| CPU time | 40.44 seconds |
| Started | Sep 09 03:56:49 AM UTC 24 |
| Finished | Sep 09 03:57:31 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682341295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2682341295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.1298474641 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 37249862716 ps |
| CPU time | 196.46 seconds |
| Started | Sep 09 03:56:51 AM UTC 24 |
| Finished | Sep 09 04:00:11 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298474641 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1298474641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.4014656598 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 123597652969 ps |
| CPU time | 260.13 seconds |
| Started | Sep 09 03:56:51 AM UTC 24 |
| Finished | Sep 09 04:01:15 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014656598 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.4014656598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.3943920680 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 61098006 ps |
| CPU time | 9.81 seconds |
| Started | Sep 09 03:56:49 AM UTC 24 |
| Finished | Sep 09 03:57:00 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943920680 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3943920680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.2326550314 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 444572059 ps |
| CPU time | 22.16 seconds |
| Started | Sep 09 03:56:57 AM UTC 24 |
| Finished | Sep 09 03:57:20 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326550314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2326550314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.1097284566 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 176912805 ps |
| CPU time | 5.32 seconds |
| Started | Sep 09 03:56:43 AM UTC 24 |
| Finished | Sep 09 03:56:50 AM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097284566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1097284566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1182073693 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 4559391702 ps |
| CPU time | 22.2 seconds |
| Started | Sep 09 03:56:47 AM UTC 24 |
| Finished | Sep 09 03:57:10 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182073693 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1182073693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.903805442 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 9489832231 ps |
| CPU time | 46.32 seconds |
| Started | Sep 09 03:56:48 AM UTC 24 |
| Finished | Sep 09 03:57:36 AM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903805442 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.903805442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.1235650766 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 126773189 ps |
| CPU time | 3.13 seconds |
| Started | Sep 09 03:56:43 AM UTC 24 |
| Finished | Sep 09 03:56:48 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235650766 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1235650766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.3767710217 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 176079945 ps |
| CPU time | 27.88 seconds |
| Started | Sep 09 03:57:01 AM UTC 24 |
| Finished | Sep 09 03:57:30 AM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767710217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3767710217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3557681569 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 19360249588 ps |
| CPU time | 208.96 seconds |
| Started | Sep 09 03:57:07 AM UTC 24 |
| Finished | Sep 09 04:00:39 AM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557681569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3557681569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2199857814 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 25860200 ps |
| CPU time | 70.31 seconds |
| Started | Sep 09 03:57:05 AM UTC 24 |
| Finished | Sep 09 03:58:17 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199857814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2199857814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.635452964 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 569961332 ps |
| CPU time | 124.73 seconds |
| Started | Sep 09 03:57:09 AM UTC 24 |
| Finished | Sep 09 03:59:16 AM UTC 24 |
| Peak memory | 223108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635452964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.635452964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.3684182154 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 72897168 ps |
| CPU time | 10.65 seconds |
| Started | Sep 09 03:56:59 AM UTC 24 |
| Finished | Sep 09 03:57:11 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684182154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3684182154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.4032893172 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 5222716822 ps |
| CPU time | 29.18 seconds |
| Started | Sep 09 03:57:27 AM UTC 24 |
| Finished | Sep 09 03:57:57 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032893172 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.4032893172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2345782967 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 158961139 ps |
| CPU time | 8.06 seconds |
| Started | Sep 09 03:57:32 AM UTC 24 |
| Finished | Sep 09 03:57:41 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345782967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2345782967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.2986792602 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 747488901 ps |
| CPU time | 18.45 seconds |
| Started | Sep 09 03:57:30 AM UTC 24 |
| Finished | Sep 09 03:57:50 AM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986792602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2986792602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.2628562442 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 192987211 ps |
| CPU time | 29.18 seconds |
| Started | Sep 09 03:57:19 AM UTC 24 |
| Finished | Sep 09 03:57:50 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628562442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2628562442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.2353377363 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2883631587 ps |
| CPU time | 19.18 seconds |
| Started | Sep 09 03:57:23 AM UTC 24 |
| Finished | Sep 09 03:57:44 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353377363 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2353377363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.426726029 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3266025327 ps |
| CPU time | 35.61 seconds |
| Started | Sep 09 03:57:24 AM UTC 24 |
| Finished | Sep 09 03:58:01 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426726029 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.426726029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.4182468319 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 128411446 ps |
| CPU time | 9.44 seconds |
| Started | Sep 09 03:57:21 AM UTC 24 |
| Finished | Sep 09 03:57:32 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182468319 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.4182468319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1818194647 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1244969883 ps |
| CPU time | 15.55 seconds |
| Started | Sep 09 03:57:30 AM UTC 24 |
| Finished | Sep 09 03:57:47 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818194647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1818194647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.2408892319 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 63316138 ps |
| CPU time | 2.63 seconds |
| Started | Sep 09 03:57:11 AM UTC 24 |
| Finished | Sep 09 03:57:14 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408892319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2408892319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1946642777 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 9451084269 ps |
| CPU time | 54.16 seconds |
| Started | Sep 09 03:57:15 AM UTC 24 |
| Finished | Sep 09 03:58:11 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946642777 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1946642777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1512382879 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 6456797758 ps |
| CPU time | 25.88 seconds |
| Started | Sep 09 03:57:17 AM UTC 24 |
| Finished | Sep 09 03:57:44 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512382879 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1512382879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.286697808 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 32697988 ps |
| CPU time | 3.12 seconds |
| Started | Sep 09 03:57:12 AM UTC 24 |
| Finished | Sep 09 03:57:16 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286697808 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.286697808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.1762033455 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 6760227488 ps |
| CPU time | 197.12 seconds |
| Started | Sep 09 03:57:32 AM UTC 24 |
| Finished | Sep 09 04:00:52 AM UTC 24 |
| Peak memory | 222976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762033455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1762033455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.325105802 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 462284731 ps |
| CPU time | 28.76 seconds |
| Started | Sep 09 03:57:34 AM UTC 24 |
| Finished | Sep 09 03:58:05 AM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325105802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.325105802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1798770594 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1233188159 ps |
| CPU time | 468.59 seconds |
| Started | Sep 09 03:57:33 AM UTC 24 |
| Finished | Sep 09 04:05:29 AM UTC 24 |
| Peak memory | 223288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798770594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.1798770594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.687144685 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3262742395 ps |
| CPU time | 33 seconds |
| Started | Sep 09 03:57:31 AM UTC 24 |
| Finished | Sep 09 03:58:05 AM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687144685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.687144685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.1856522909 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 93570299 ps |
| CPU time | 16.88 seconds |
| Started | Sep 09 03:57:48 AM UTC 24 |
| Finished | Sep 09 03:58:06 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856522909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1856522909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1548154502 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 100284164992 ps |
| CPU time | 826.06 seconds |
| Started | Sep 09 03:57:48 AM UTC 24 |
| Finished | Sep 09 04:11:43 AM UTC 24 |
| Peak memory | 222548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548154502 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.1548154502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.864474891 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 429587814 ps |
| CPU time | 11.36 seconds |
| Started | Sep 09 03:57:51 AM UTC 24 |
| Finished | Sep 09 03:58:03 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864474891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.864474891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.2758031680 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 329426275 ps |
| CPU time | 9.74 seconds |
| Started | Sep 09 03:57:50 AM UTC 24 |
| Finished | Sep 09 03:58:01 AM UTC 24 |
| Peak memory | 217144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758031680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2758031680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.3624229750 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 174334042 ps |
| CPU time | 15.32 seconds |
| Started | Sep 09 03:57:45 AM UTC 24 |
| Finished | Sep 09 03:58:01 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624229750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3624229750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.3294698156 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 9181825051 ps |
| CPU time | 26.16 seconds |
| Started | Sep 09 03:57:46 AM UTC 24 |
| Finished | Sep 09 03:58:14 AM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294698156 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3294698156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1906638127 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 32024224626 ps |
| CPU time | 93 seconds |
| Started | Sep 09 03:57:46 AM UTC 24 |
| Finished | Sep 09 03:59:21 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906638127 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1906638127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.3753502031 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 92173836 ps |
| CPU time | 10.95 seconds |
| Started | Sep 09 03:57:45 AM UTC 24 |
| Finished | Sep 09 03:57:57 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753502031 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3753502031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.1409759861 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 176601409 ps |
| CPU time | 13.95 seconds |
| Started | Sep 09 03:57:48 AM UTC 24 |
| Finished | Sep 09 03:58:03 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409759861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1409759861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.4127735331 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 34744172 ps |
| CPU time | 3.46 seconds |
| Started | Sep 09 03:57:40 AM UTC 24 |
| Finished | Sep 09 03:57:44 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127735331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.4127735331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.4026062855 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 6493288708 ps |
| CPU time | 47.46 seconds |
| Started | Sep 09 03:57:43 AM UTC 24 |
| Finished | Sep 09 03:58:32 AM UTC 24 |
| Peak memory | 217204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026062855 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.4026062855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.1337836916 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2680490512 ps |
| CPU time | 31.45 seconds |
| Started | Sep 09 03:57:45 AM UTC 24 |
| Finished | Sep 09 03:58:18 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337836916 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1337836916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.4231415814 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 26206588 ps |
| CPU time | 2.82 seconds |
| Started | Sep 09 03:57:42 AM UTC 24 |
| Finished | Sep 09 03:57:46 AM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231415814 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.4231415814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.1421569531 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 214285112 ps |
| CPU time | 4.35 seconds |
| Started | Sep 09 03:57:58 AM UTC 24 |
| Finished | Sep 09 03:58:04 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421569531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1421569531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1701536778 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 929603866 ps |
| CPU time | 47.28 seconds |
| Started | Sep 09 03:58:00 AM UTC 24 |
| Finished | Sep 09 03:58:49 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701536778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1701536778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.90770333 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3587969570 ps |
| CPU time | 62.63 seconds |
| Started | Sep 09 03:57:58 AM UTC 24 |
| Finished | Sep 09 03:59:03 AM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90770333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.90770333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2471252518 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 835462372 ps |
| CPU time | 272.44 seconds |
| Started | Sep 09 03:58:00 AM UTC 24 |
| Finished | Sep 09 04:02:37 AM UTC 24 |
| Peak memory | 233592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471252518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.2471252518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.193826856 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 61097054 ps |
| CPU time | 11.11 seconds |
| Started | Sep 09 03:57:51 AM UTC 24 |
| Finished | Sep 09 03:58:03 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193826856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.193826856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.2487399130 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 267463840 ps |
| CPU time | 32.86 seconds |
| Started | Sep 09 03:58:06 AM UTC 24 |
| Finished | Sep 09 03:58:40 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487399130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2487399130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3906863189 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 100884124049 ps |
| CPU time | 626.42 seconds |
| Started | Sep 09 03:58:06 AM UTC 24 |
| Finished | Sep 09 04:08:40 AM UTC 24 |
| Peak memory | 222548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906863189 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.3906863189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.339828695 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 662755806 ps |
| CPU time | 29.88 seconds |
| Started | Sep 09 03:58:08 AM UTC 24 |
| Finished | Sep 09 03:58:39 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339828695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.339828695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.1877511154 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 727978339 ps |
| CPU time | 26.02 seconds |
| Started | Sep 09 03:58:08 AM UTC 24 |
| Finished | Sep 09 03:58:35 AM UTC 24 |
| Peak memory | 217076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877511154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1877511154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.2769581789 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 107869756 ps |
| CPU time | 4.04 seconds |
| Started | Sep 09 03:58:04 AM UTC 24 |
| Finished | Sep 09 03:58:09 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769581789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2769581789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.2971469928 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 18532489746 ps |
| CPU time | 135.47 seconds |
| Started | Sep 09 03:58:05 AM UTC 24 |
| Finished | Sep 09 04:00:23 AM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971469928 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2971469928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.797703991 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 14379790602 ps |
| CPU time | 52.1 seconds |
| Started | Sep 09 03:58:05 AM UTC 24 |
| Finished | Sep 09 03:58:59 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797703991 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.797703991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.2722807015 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 193240686 ps |
| CPU time | 25.28 seconds |
| Started | Sep 09 03:58:04 AM UTC 24 |
| Finished | Sep 09 03:58:30 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722807015 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2722807015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.2357240643 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1683558406 ps |
| CPU time | 27.2 seconds |
| Started | Sep 09 03:58:06 AM UTC 24 |
| Finished | Sep 09 03:58:35 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357240643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2357240643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.2027096025 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 100762497 ps |
| CPU time | 3.15 seconds |
| Started | Sep 09 03:58:01 AM UTC 24 |
| Finished | Sep 09 03:58:06 AM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027096025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2027096025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3181754197 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 16110397164 ps |
| CPU time | 23.88 seconds |
| Started | Sep 09 03:58:03 AM UTC 24 |
| Finished | Sep 09 03:58:28 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181754197 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3181754197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1083609712 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 9213359331 ps |
| CPU time | 34.84 seconds |
| Started | Sep 09 03:58:04 AM UTC 24 |
| Finished | Sep 09 03:58:40 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083609712 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1083609712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3965694119 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 32094378 ps |
| CPU time | 2.46 seconds |
| Started | Sep 09 03:58:03 AM UTC 24 |
| Finished | Sep 09 03:58:06 AM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965694119 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3965694119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.959550550 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 924559012 ps |
| CPU time | 84.66 seconds |
| Started | Sep 09 03:58:10 AM UTC 24 |
| Finished | Sep 09 03:59:36 AM UTC 24 |
| Peak memory | 219136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959550550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.959550550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3065777027 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1608604317 ps |
| CPU time | 142.45 seconds |
| Started | Sep 09 03:58:15 AM UTC 24 |
| Finished | Sep 09 04:00:40 AM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065777027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3065777027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2118616473 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 11528155496 ps |
| CPU time | 429.03 seconds |
| Started | Sep 09 03:58:12 AM UTC 24 |
| Finished | Sep 09 04:05:27 AM UTC 24 |
| Peak memory | 223420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118616473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.2118616473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2211835513 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 128692437 ps |
| CPU time | 32.4 seconds |
| Started | Sep 09 03:58:16 AM UTC 24 |
| Finished | Sep 09 03:58:50 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211835513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2211835513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.1498347943 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1485551255 ps |
| CPU time | 38.94 seconds |
| Started | Sep 09 03:58:08 AM UTC 24 |
| Finished | Sep 09 03:58:48 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498347943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1498347943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.253540170 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 310532718 ps |
| CPU time | 30.71 seconds |
| Started | Sep 09 03:58:34 AM UTC 24 |
| Finished | Sep 09 03:59:06 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253540170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.253540170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3714484945 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 4806865936 ps |
| CPU time | 37.46 seconds |
| Started | Sep 09 03:58:36 AM UTC 24 |
| Finished | Sep 09 03:59:15 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714484945 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.3714484945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.431123289 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 221975986 ps |
| CPU time | 24.02 seconds |
| Started | Sep 09 03:58:40 AM UTC 24 |
| Finished | Sep 09 03:59:06 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431123289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.431123289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.712336735 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1095198008 ps |
| CPU time | 28.99 seconds |
| Started | Sep 09 03:58:39 AM UTC 24 |
| Finished | Sep 09 03:59:10 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712336735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.712336735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.1484944402 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 117776687 ps |
| CPU time | 7.08 seconds |
| Started | Sep 09 03:58:25 AM UTC 24 |
| Finished | Sep 09 03:58:33 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484944402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1484944402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.3351952723 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 6369874699 ps |
| CPU time | 30.34 seconds |
| Started | Sep 09 03:58:32 AM UTC 24 |
| Finished | Sep 09 03:59:04 AM UTC 24 |
| Peak memory | 217216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351952723 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3351952723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2532538738 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 71119821721 ps |
| CPU time | 259.87 seconds |
| Started | Sep 09 03:58:33 AM UTC 24 |
| Finished | Sep 09 04:02:57 AM UTC 24 |
| Peak memory | 216968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532538738 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2532538738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.941552615 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 86265023 ps |
| CPU time | 8.32 seconds |
| Started | Sep 09 03:58:29 AM UTC 24 |
| Finished | Sep 09 03:58:38 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941552615 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.941552615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.3394093252 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1603159136 ps |
| CPU time | 36.5 seconds |
| Started | Sep 09 03:58:36 AM UTC 24 |
| Finished | Sep 09 03:59:14 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394093252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3394093252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.3567151632 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 159590240 ps |
| CPU time | 4.01 seconds |
| Started | Sep 09 03:58:18 AM UTC 24 |
| Finished | Sep 09 03:58:23 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567151632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3567151632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.346173793 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 7702747266 ps |
| CPU time | 53.21 seconds |
| Started | Sep 09 03:58:22 AM UTC 24 |
| Finished | Sep 09 03:59:18 AM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346173793 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.346173793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.3223375837 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 10775103000 ps |
| CPU time | 42.94 seconds |
| Started | Sep 09 03:58:25 AM UTC 24 |
| Finished | Sep 09 03:59:09 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223375837 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3223375837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.557094895 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 45687303 ps |
| CPU time | 2.64 seconds |
| Started | Sep 09 03:58:19 AM UTC 24 |
| Finished | Sep 09 03:58:23 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557094895 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.557094895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.4190711791 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 634561403 ps |
| CPU time | 77.85 seconds |
| Started | Sep 09 03:58:41 AM UTC 24 |
| Finished | Sep 09 04:00:01 AM UTC 24 |
| Peak memory | 220868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190711791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.4190711791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3602753412 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 121103864 ps |
| CPU time | 29.93 seconds |
| Started | Sep 09 03:58:44 AM UTC 24 |
| Finished | Sep 09 03:59:15 AM UTC 24 |
| Peak memory | 219016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602753412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.3602753412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3162669610 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 6679757680 ps |
| CPU time | 300.32 seconds |
| Started | Sep 09 03:58:49 AM UTC 24 |
| Finished | Sep 09 04:03:53 AM UTC 24 |
| Peak memory | 233656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162669610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.3162669610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.3138081783 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 311076128 ps |
| CPU time | 17.69 seconds |
| Started | Sep 09 03:58:39 AM UTC 24 |
| Finished | Sep 09 03:58:58 AM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138081783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3138081783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.1408026811 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 435445273 ps |
| CPU time | 46.63 seconds |
| Started | Sep 09 03:59:05 AM UTC 24 |
| Finished | Sep 09 03:59:53 AM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408026811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1408026811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1982563635 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 44584053442 ps |
| CPU time | 401.93 seconds |
| Started | Sep 09 03:59:07 AM UTC 24 |
| Finished | Sep 09 04:05:55 AM UTC 24 |
| Peak memory | 219016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982563635 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.1982563635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.451638513 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1255184947 ps |
| CPU time | 31.18 seconds |
| Started | Sep 09 03:59:10 AM UTC 24 |
| Finished | Sep 09 03:59:43 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451638513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.451638513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.2578191383 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 185127078 ps |
| CPU time | 19.15 seconds |
| Started | Sep 09 03:59:08 AM UTC 24 |
| Finished | Sep 09 03:59:28 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578191383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2578191383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.2837724197 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 695372175 ps |
| CPU time | 11.67 seconds |
| Started | Sep 09 03:58:56 AM UTC 24 |
| Finished | Sep 09 03:59:09 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837724197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2837724197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.2144760278 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 66270145159 ps |
| CPU time | 247.41 seconds |
| Started | Sep 09 03:59:00 AM UTC 24 |
| Finished | Sep 09 04:03:10 AM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144760278 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2144760278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1624978773 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 79484440699 ps |
| CPU time | 337.68 seconds |
| Started | Sep 09 03:59:04 AM UTC 24 |
| Finished | Sep 09 04:04:46 AM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624978773 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1624978773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.2291791501 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 89377435 ps |
| CPU time | 13.34 seconds |
| Started | Sep 09 03:58:59 AM UTC 24 |
| Finished | Sep 09 03:59:14 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291791501 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2291791501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.1569237751 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 157751093 ps |
| CPU time | 13.11 seconds |
| Started | Sep 09 03:59:07 AM UTC 24 |
| Finished | Sep 09 03:59:21 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569237751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1569237751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.1552647399 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 27111116 ps |
| CPU time | 2.84 seconds |
| Started | Sep 09 03:58:50 AM UTC 24 |
| Finished | Sep 09 03:58:54 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552647399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1552647399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1530040238 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4181905618 ps |
| CPU time | 35.99 seconds |
| Started | Sep 09 03:58:54 AM UTC 24 |
| Finished | Sep 09 03:59:32 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530040238 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1530040238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1648175644 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 28918413162 ps |
| CPU time | 63.44 seconds |
| Started | Sep 09 03:58:55 AM UTC 24 |
| Finished | Sep 09 04:00:00 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648175644 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1648175644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.744245660 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 41376939 ps |
| CPU time | 2.63 seconds |
| Started | Sep 09 03:58:51 AM UTC 24 |
| Finished | Sep 09 03:58:55 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744245660 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.744245660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.2580522724 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 8928728054 ps |
| CPU time | 108.03 seconds |
| Started | Sep 09 03:59:10 AM UTC 24 |
| Finished | Sep 09 04:01:01 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580522724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2580522724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2944278048 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1160370094 ps |
| CPU time | 128.57 seconds |
| Started | Sep 09 03:59:15 AM UTC 24 |
| Finished | Sep 09 04:01:26 AM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944278048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2944278048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3357816670 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 608227652 ps |
| CPU time | 262.59 seconds |
| Started | Sep 09 03:59:12 AM UTC 24 |
| Finished | Sep 09 04:03:39 AM UTC 24 |
| Peak memory | 222924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357816670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.3357816670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.939371803 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 517215118 ps |
| CPU time | 160.73 seconds |
| Started | Sep 09 03:59:15 AM UTC 24 |
| Finished | Sep 09 04:01:58 AM UTC 24 |
| Peak memory | 223232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939371803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.939371803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.2029120275 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1370863693 ps |
| CPU time | 16.8 seconds |
| Started | Sep 09 03:59:10 AM UTC 24 |
| Finished | Sep 09 03:59:28 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029120275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2029120275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.2254317334 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 883832967 ps |
| CPU time | 41.48 seconds |
| Started | Sep 09 03:59:23 AM UTC 24 |
| Finished | Sep 09 04:00:05 AM UTC 24 |
| Peak memory | 217032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254317334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2254317334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.760407043 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 50644711181 ps |
| CPU time | 411.1 seconds |
| Started | Sep 09 03:59:27 AM UTC 24 |
| Finished | Sep 09 04:06:23 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760407043 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.760407043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.69046665 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 110828790 ps |
| CPU time | 15.92 seconds |
| Started | Sep 09 03:59:33 AM UTC 24 |
| Finished | Sep 09 03:59:50 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69046665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.69046665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.610781704 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 723852446 ps |
| CPU time | 11.16 seconds |
| Started | Sep 09 03:59:29 AM UTC 24 |
| Finished | Sep 09 03:59:41 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610781704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.610781704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.2805674625 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 333382243 ps |
| CPU time | 24.23 seconds |
| Started | Sep 09 03:59:18 AM UTC 24 |
| Finished | Sep 09 03:59:44 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805674625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2805674625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.2648478766 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 31429719446 ps |
| CPU time | 204.99 seconds |
| Started | Sep 09 03:59:21 AM UTC 24 |
| Finished | Sep 09 04:02:49 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648478766 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2648478766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.4015096028 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 26507409367 ps |
| CPU time | 172.66 seconds |
| Started | Sep 09 03:59:23 AM UTC 24 |
| Finished | Sep 09 04:02:18 AM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015096028 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.4015096028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.290042399 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 637467124 ps |
| CPU time | 21.47 seconds |
| Started | Sep 09 03:59:19 AM UTC 24 |
| Finished | Sep 09 03:59:42 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290042399 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.290042399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.2068607871 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 918167782 ps |
| CPU time | 23.46 seconds |
| Started | Sep 09 03:59:29 AM UTC 24 |
| Finished | Sep 09 03:59:54 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068607871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2068607871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.428452898 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 203591514 ps |
| CPU time | 4.2 seconds |
| Started | Sep 09 03:59:16 AM UTC 24 |
| Finished | Sep 09 03:59:21 AM UTC 24 |
| Peak memory | 216492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428452898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.428452898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2626736237 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 4251615646 ps |
| CPU time | 29.89 seconds |
| Started | Sep 09 03:59:17 AM UTC 24 |
| Finished | Sep 09 03:59:48 AM UTC 24 |
| Peak memory | 217060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626736237 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2626736237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2169998059 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 12413921955 ps |
| CPU time | 69.25 seconds |
| Started | Sep 09 03:59:17 AM UTC 24 |
| Finished | Sep 09 04:00:28 AM UTC 24 |
| Peak memory | 217188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169998059 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2169998059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.490983973 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 23504389 ps |
| CPU time | 1.93 seconds |
| Started | Sep 09 03:59:16 AM UTC 24 |
| Finished | Sep 09 03:59:19 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490983973 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.490983973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.252125033 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1787301750 ps |
| CPU time | 116.01 seconds |
| Started | Sep 09 03:59:34 AM UTC 24 |
| Finished | Sep 09 04:01:33 AM UTC 24 |
| Peak memory | 220928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252125033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.252125033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1320840587 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 741566601 ps |
| CPU time | 34.41 seconds |
| Started | Sep 09 03:59:35 AM UTC 24 |
| Finished | Sep 09 04:00:11 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320840587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1320840587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1419712739 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4732496796 ps |
| CPU time | 368.11 seconds |
| Started | Sep 09 03:59:34 AM UTC 24 |
| Finished | Sep 09 04:05:47 AM UTC 24 |
| Peak memory | 223420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419712739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1419712739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.4083275443 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1600021427 ps |
| CPU time | 171.23 seconds |
| Started | Sep 09 03:59:38 AM UTC 24 |
| Finished | Sep 09 04:02:32 AM UTC 24 |
| Peak memory | 223548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083275443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.4083275443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.1467610083 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 191152296 ps |
| CPU time | 12.05 seconds |
| Started | Sep 09 03:59:32 AM UTC 24 |
| Finished | Sep 09 03:59:45 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467610083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1467610083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.2318733916 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 288213160 ps |
| CPU time | 9.52 seconds |
| Started | Sep 09 03:59:49 AM UTC 24 |
| Finished | Sep 09 04:00:00 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318733916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2318733916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2866266911 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 85042184351 ps |
| CPU time | 658.44 seconds |
| Started | Sep 09 03:59:51 AM UTC 24 |
| Finished | Sep 09 04:10:57 AM UTC 24 |
| Peak memory | 220564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866266911 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2866266911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2453818202 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 74088683 ps |
| CPU time | 4.29 seconds |
| Started | Sep 09 04:00:01 AM UTC 24 |
| Finished | Sep 09 04:00:10 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453818202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2453818202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1990545438 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 145488461 ps |
| CPU time | 12.34 seconds |
| Started | Sep 09 03:59:54 AM UTC 24 |
| Finished | Sep 09 04:00:07 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990545438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1990545438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.940248482 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 241812939 ps |
| CPU time | 26.44 seconds |
| Started | Sep 09 03:59:46 AM UTC 24 |
| Finished | Sep 09 04:00:14 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940248482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.940248482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.1541104146 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3635529470 ps |
| CPU time | 26.39 seconds |
| Started | Sep 09 03:59:47 AM UTC 24 |
| Finished | Sep 09 04:00:15 AM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541104146 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1541104146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1247201361 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 19139548363 ps |
| CPU time | 59.4 seconds |
| Started | Sep 09 03:59:49 AM UTC 24 |
| Finished | Sep 09 04:00:50 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247201361 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1247201361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.2939558547 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 46298790 ps |
| CPU time | 4.75 seconds |
| Started | Sep 09 03:59:46 AM UTC 24 |
| Finished | Sep 09 03:59:52 AM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939558547 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2939558547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.666221685 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2979863773 ps |
| CPU time | 38.92 seconds |
| Started | Sep 09 03:59:53 AM UTC 24 |
| Finished | Sep 09 04:00:33 AM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666221685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.666221685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.3571316648 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 39955876 ps |
| CPU time | 3.05 seconds |
| Started | Sep 09 03:59:42 AM UTC 24 |
| Finished | Sep 09 03:59:46 AM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571316648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3571316648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3382965587 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 9204415321 ps |
| CPU time | 36.67 seconds |
| Started | Sep 09 03:59:44 AM UTC 24 |
| Finished | Sep 09 04:00:22 AM UTC 24 |
| Peak memory | 216948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382965587 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3382965587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.516884710 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 10918535342 ps |
| CPU time | 67.23 seconds |
| Started | Sep 09 03:59:45 AM UTC 24 |
| Finished | Sep 09 04:00:54 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516884710 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.516884710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2588284285 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 29978813 ps |
| CPU time | 2.85 seconds |
| Started | Sep 09 03:59:43 AM UTC 24 |
| Finished | Sep 09 03:59:47 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588284285 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2588284285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.2242456688 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1402370642 ps |
| CPU time | 134.49 seconds |
| Started | Sep 09 04:00:01 AM UTC 24 |
| Finished | Sep 09 04:02:22 AM UTC 24 |
| Peak memory | 220928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242456688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2242456688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.500975169 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 5466007312 ps |
| CPU time | 98.36 seconds |
| Started | Sep 09 04:00:06 AM UTC 24 |
| Finished | Sep 09 04:01:47 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500975169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.500975169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1975266108 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 829408372 ps |
| CPU time | 282.58 seconds |
| Started | Sep 09 04:00:02 AM UTC 24 |
| Finished | Sep 09 04:04:52 AM UTC 24 |
| Peak memory | 221196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975266108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.1975266108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.604229404 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 385736849 ps |
| CPU time | 68.03 seconds |
| Started | Sep 09 04:00:06 AM UTC 24 |
| Finished | Sep 09 04:01:16 AM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604229404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.604229404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.3009210254 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 137959685 ps |
| CPU time | 18.72 seconds |
| Started | Sep 09 03:59:55 AM UTC 24 |
| Finished | Sep 09 04:00:15 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009210254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3009210254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.428376058 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 369108095 ps |
| CPU time | 7.72 seconds |
| Started | Sep 09 03:54:01 AM UTC 24 |
| Finished | Sep 09 03:54:11 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428376058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.428376058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1719752261 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 192494023 ps |
| CPU time | 9.83 seconds |
| Started | Sep 09 03:54:01 AM UTC 24 |
| Finished | Sep 09 03:54:23 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719752261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1719752261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.539452199 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 175514539 ps |
| CPU time | 5.72 seconds |
| Started | Sep 09 03:54:01 AM UTC 24 |
| Finished | Sep 09 03:54:19 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539452199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.539452199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.3808665164 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 18564837869 ps |
| CPU time | 93.97 seconds |
| Started | Sep 09 03:54:01 AM UTC 24 |
| Finished | Sep 09 03:55:38 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808665164 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3808665164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.4054104171 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 39196271069 ps |
| CPU time | 97.91 seconds |
| Started | Sep 09 03:54:01 AM UTC 24 |
| Finished | Sep 09 03:55:52 AM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054104171 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.4054104171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.3121103245 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 51442154 ps |
| CPU time | 5.54 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:54:14 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121103245 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3121103245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.1611465607 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1381354530 ps |
| CPU time | 29.79 seconds |
| Started | Sep 09 03:54:01 AM UTC 24 |
| Finished | Sep 09 03:54:43 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611465607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1611465607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.3566844807 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 127194340 ps |
| CPU time | 2.69 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:54:11 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566844807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3566844807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2263490521 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 4303550750 ps |
| CPU time | 27.8 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:54:36 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263490521 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2263490521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4080700636 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4433684835 ps |
| CPU time | 43.99 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:54:53 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080700636 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4080700636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3393766235 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 28719233 ps |
| CPU time | 2.14 seconds |
| Started | Sep 09 03:54:00 AM UTC 24 |
| Finished | Sep 09 03:54:10 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393766235 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3393766235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.1228585129 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1641038887 ps |
| CPU time | 206.14 seconds |
| Started | Sep 09 03:54:01 AM UTC 24 |
| Finished | Sep 09 03:57:42 AM UTC 24 |
| Peak memory | 223268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228585129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1228585129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3491611462 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1803578239 ps |
| CPU time | 36.22 seconds |
| Started | Sep 09 03:54:01 AM UTC 24 |
| Finished | Sep 09 03:54:50 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491611462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3491611462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2088584169 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1936352165 ps |
| CPU time | 151.64 seconds |
| Started | Sep 09 03:54:01 AM UTC 24 |
| Finished | Sep 09 03:56:47 AM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088584169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.2088584169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.594119624 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 343847636 ps |
| CPU time | 88.11 seconds |
| Started | Sep 09 03:54:03 AM UTC 24 |
| Finished | Sep 09 03:55:33 AM UTC 24 |
| Peak memory | 220940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594119624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.594119624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.2705081192 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 269614457 ps |
| CPU time | 18.01 seconds |
| Started | Sep 09 03:54:01 AM UTC 24 |
| Finished | Sep 09 03:54:32 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705081192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2705081192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.1181968867 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1340795662 ps |
| CPU time | 47.8 seconds |
| Started | Sep 09 04:00:17 AM UTC 24 |
| Finished | Sep 09 04:01:07 AM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181968867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1181968867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1680372546 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 52609566920 ps |
| CPU time | 568.22 seconds |
| Started | Sep 09 04:00:17 AM UTC 24 |
| Finished | Sep 09 04:09:53 AM UTC 24 |
| Peak memory | 219264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680372546 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.1680372546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.67150558 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 660731381 ps |
| CPU time | 19.78 seconds |
| Started | Sep 09 04:00:24 AM UTC 24 |
| Finished | Sep 09 04:00:45 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67150558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.67150558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.3923457640 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2347809822 ps |
| CPU time | 31.67 seconds |
| Started | Sep 09 04:00:22 AM UTC 24 |
| Finished | Sep 09 04:00:55 AM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923457640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3923457640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.617166702 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 833335111 ps |
| CPU time | 28.16 seconds |
| Started | Sep 09 04:00:15 AM UTC 24 |
| Finished | Sep 09 04:00:44 AM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617166702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.617166702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.2189135615 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 78693750894 ps |
| CPU time | 322.09 seconds |
| Started | Sep 09 04:00:16 AM UTC 24 |
| Finished | Sep 09 04:05:43 AM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189135615 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2189135615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.957409490 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3853679521 ps |
| CPU time | 43.32 seconds |
| Started | Sep 09 04:00:16 AM UTC 24 |
| Finished | Sep 09 04:01:01 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957409490 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.957409490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.1285347599 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 20226755 ps |
| CPU time | 2.62 seconds |
| Started | Sep 09 04:00:16 AM UTC 24 |
| Finished | Sep 09 04:00:20 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285347599 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1285347599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.238979794 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 776548468 ps |
| CPU time | 5.94 seconds |
| Started | Sep 09 04:00:21 AM UTC 24 |
| Finished | Sep 09 04:00:28 AM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238979794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.238979794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.2512330892 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 149373987 ps |
| CPU time | 4.76 seconds |
| Started | Sep 09 04:00:08 AM UTC 24 |
| Finished | Sep 09 04:00:15 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512330892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2512330892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.689300132 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 20174368801 ps |
| CPU time | 44.29 seconds |
| Started | Sep 09 04:00:12 AM UTC 24 |
| Finished | Sep 09 04:00:58 AM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689300132 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.689300132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.212268755 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 10001676624 ps |
| CPU time | 55.06 seconds |
| Started | Sep 09 04:00:12 AM UTC 24 |
| Finished | Sep 09 04:01:09 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212268755 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.212268755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.520725388 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 28988464 ps |
| CPU time | 3.32 seconds |
| Started | Sep 09 04:00:12 AM UTC 24 |
| Finished | Sep 09 04:00:16 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520725388 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.520725388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.4217761396 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1470787080 ps |
| CPU time | 114.86 seconds |
| Started | Sep 09 04:00:28 AM UTC 24 |
| Finished | Sep 09 04:02:25 AM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217761396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.4217761396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3468283916 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 22614947382 ps |
| CPU time | 118.05 seconds |
| Started | Sep 09 04:00:30 AM UTC 24 |
| Finished | Sep 09 04:02:31 AM UTC 24 |
| Peak memory | 219272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468283916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3468283916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1839053823 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3529806690 ps |
| CPU time | 473.76 seconds |
| Started | Sep 09 04:00:29 AM UTC 24 |
| Finished | Sep 09 04:08:29 AM UTC 24 |
| Peak memory | 237752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839053823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.1839053823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2635613083 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2004920843 ps |
| CPU time | 178.51 seconds |
| Started | Sep 09 04:00:34 AM UTC 24 |
| Finished | Sep 09 04:03:36 AM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635613083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.2635613083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.133422250 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 138985832 ps |
| CPU time | 26.26 seconds |
| Started | Sep 09 04:00:23 AM UTC 24 |
| Finished | Sep 09 04:00:51 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133422250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.133422250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.1411180161 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2436755728 ps |
| CPU time | 18.29 seconds |
| Started | Sep 09 04:00:52 AM UTC 24 |
| Finished | Sep 09 04:01:11 AM UTC 24 |
| Peak memory | 217160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411180161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1411180161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3873839965 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 108692478181 ps |
| CPU time | 825.53 seconds |
| Started | Sep 09 04:00:53 AM UTC 24 |
| Finished | Sep 09 04:14:48 AM UTC 24 |
| Peak memory | 222612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873839965 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3873839965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1731587186 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 164321436 ps |
| CPU time | 12.62 seconds |
| Started | Sep 09 04:00:58 AM UTC 24 |
| Finished | Sep 09 04:01:12 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731587186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1731587186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.3613365018 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 475219639 ps |
| CPU time | 14.26 seconds |
| Started | Sep 09 04:00:55 AM UTC 24 |
| Finished | Sep 09 04:01:10 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613365018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3613365018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.479394187 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 812210614 ps |
| CPU time | 21.66 seconds |
| Started | Sep 09 04:00:45 AM UTC 24 |
| Finished | Sep 09 04:01:08 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479394187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.479394187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.2789420378 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 32028905225 ps |
| CPU time | 131.25 seconds |
| Started | Sep 09 04:00:46 AM UTC 24 |
| Finished | Sep 09 04:03:00 AM UTC 24 |
| Peak memory | 217160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789420378 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2789420378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.455942898 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 6827845949 ps |
| CPU time | 33.75 seconds |
| Started | Sep 09 04:00:51 AM UTC 24 |
| Finished | Sep 09 04:01:27 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455942898 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.455942898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.783069615 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 445120624 ps |
| CPU time | 26.54 seconds |
| Started | Sep 09 04:00:46 AM UTC 24 |
| Finished | Sep 09 04:01:14 AM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783069615 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.783069615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.2838913996 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 759820669 ps |
| CPU time | 20.6 seconds |
| Started | Sep 09 04:00:54 AM UTC 24 |
| Finished | Sep 09 04:01:16 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838913996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2838913996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.1019570046 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 253753922 ps |
| CPU time | 5.16 seconds |
| Started | Sep 09 04:00:36 AM UTC 24 |
| Finished | Sep 09 04:00:42 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019570046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1019570046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1556225387 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 12354530233 ps |
| CPU time | 54.08 seconds |
| Started | Sep 09 04:00:41 AM UTC 24 |
| Finished | Sep 09 04:01:37 AM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556225387 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1556225387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1377146764 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 4583979097 ps |
| CPU time | 36.69 seconds |
| Started | Sep 09 04:00:43 AM UTC 24 |
| Finished | Sep 09 04:01:21 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377146764 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1377146764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3462781931 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 52995948 ps |
| CPU time | 3.27 seconds |
| Started | Sep 09 04:00:41 AM UTC 24 |
| Finished | Sep 09 04:00:45 AM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462781931 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3462781931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.4222788685 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 147723973 ps |
| CPU time | 12.68 seconds |
| Started | Sep 09 04:01:01 AM UTC 24 |
| Finished | Sep 09 04:01:15 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222788685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.4222788685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3235850227 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 33731426950 ps |
| CPU time | 234.41 seconds |
| Started | Sep 09 04:01:07 AM UTC 24 |
| Finished | Sep 09 04:05:05 AM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235850227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3235850227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2290754191 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 600146465 ps |
| CPU time | 273.24 seconds |
| Started | Sep 09 04:01:02 AM UTC 24 |
| Finished | Sep 09 04:05:40 AM UTC 24 |
| Peak memory | 220872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290754191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.2290754191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2631611435 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 5236828361 ps |
| CPU time | 135.01 seconds |
| Started | Sep 09 04:01:10 AM UTC 24 |
| Finished | Sep 09 04:03:27 AM UTC 24 |
| Peak memory | 223044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631611435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.2631611435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.2660422773 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 122431209 ps |
| CPU time | 20.6 seconds |
| Started | Sep 09 04:00:55 AM UTC 24 |
| Finished | Sep 09 04:01:17 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660422773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2660422773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.2109340584 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 557139862 ps |
| CPU time | 27.28 seconds |
| Started | Sep 09 04:01:16 AM UTC 24 |
| Finished | Sep 09 04:01:45 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109340584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2109340584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1114348996 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 67965697283 ps |
| CPU time | 604.72 seconds |
| Started | Sep 09 04:01:16 AM UTC 24 |
| Finished | Sep 09 04:11:28 AM UTC 24 |
| Peak memory | 219328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114348996 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.1114348996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.459593520 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1268343663 ps |
| CPU time | 27.18 seconds |
| Started | Sep 09 04:01:27 AM UTC 24 |
| Finished | Sep 09 04:01:55 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459593520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.459593520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.3627211284 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 770771056 ps |
| CPU time | 27.15 seconds |
| Started | Sep 09 04:01:18 AM UTC 24 |
| Finished | Sep 09 04:01:46 AM UTC 24 |
| Peak memory | 217144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627211284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3627211284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.451926749 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1409035665 ps |
| CPU time | 24.3 seconds |
| Started | Sep 09 04:01:15 AM UTC 24 |
| Finished | Sep 09 04:01:41 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451926749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.451926749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.3992773749 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 32288657983 ps |
| CPU time | 245.71 seconds |
| Started | Sep 09 04:01:16 AM UTC 24 |
| Finished | Sep 09 04:05:26 AM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992773749 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3992773749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3766940028 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 69899931799 ps |
| CPU time | 246.56 seconds |
| Started | Sep 09 04:01:16 AM UTC 24 |
| Finished | Sep 09 04:05:26 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766940028 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3766940028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.1419015245 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 180573428 ps |
| CPU time | 26.4 seconds |
| Started | Sep 09 04:01:15 AM UTC 24 |
| Finished | Sep 09 04:01:43 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419015245 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1419015245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.2241186391 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 418889873 ps |
| CPU time | 13.32 seconds |
| Started | Sep 09 04:01:17 AM UTC 24 |
| Finished | Sep 09 04:01:32 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241186391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2241186391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.3443602090 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 357124904 ps |
| CPU time | 5.14 seconds |
| Started | Sep 09 04:01:10 AM UTC 24 |
| Finished | Sep 09 04:01:16 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443602090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3443602090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2303793135 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3272339908 ps |
| CPU time | 26.69 seconds |
| Started | Sep 09 04:01:12 AM UTC 24 |
| Finished | Sep 09 04:01:40 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303793135 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2303793135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.854499760 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 20983845086 ps |
| CPU time | 55.27 seconds |
| Started | Sep 09 04:01:13 AM UTC 24 |
| Finished | Sep 09 04:02:10 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854499760 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.854499760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1294508520 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 41726399 ps |
| CPU time | 2.84 seconds |
| Started | Sep 09 04:01:11 AM UTC 24 |
| Finished | Sep 09 04:01:15 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294508520 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1294508520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.3677124571 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 918103458 ps |
| CPU time | 126.77 seconds |
| Started | Sep 09 04:01:28 AM UTC 24 |
| Finished | Sep 09 04:03:37 AM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677124571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3677124571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.894646138 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 11119387581 ps |
| CPU time | 101.68 seconds |
| Started | Sep 09 04:01:34 AM UTC 24 |
| Finished | Sep 09 04:03:18 AM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894646138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.894646138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1317860439 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 14156680817 ps |
| CPU time | 310.59 seconds |
| Started | Sep 09 04:01:33 AM UTC 24 |
| Finished | Sep 09 04:06:49 AM UTC 24 |
| Peak memory | 223048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317860439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.1317860439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1108334879 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 67880935 ps |
| CPU time | 34.8 seconds |
| Started | Sep 09 04:01:35 AM UTC 24 |
| Finished | Sep 09 04:02:12 AM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108334879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.1108334879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.4184144134 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 121999551 ps |
| CPU time | 22.87 seconds |
| Started | Sep 09 04:01:22 AM UTC 24 |
| Finished | Sep 09 04:01:46 AM UTC 24 |
| Peak memory | 218872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184144134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.4184144134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.402474892 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 22487022 ps |
| CPU time | 3.66 seconds |
| Started | Sep 09 04:01:47 AM UTC 24 |
| Finished | Sep 09 04:01:52 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402474892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.402474892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3477227668 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 23093702520 ps |
| CPU time | 231.1 seconds |
| Started | Sep 09 04:01:47 AM UTC 24 |
| Finished | Sep 09 04:05:42 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477227668 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.3477227668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.231646109 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1811736381 ps |
| CPU time | 17.29 seconds |
| Started | Sep 09 04:01:57 AM UTC 24 |
| Finished | Sep 09 04:02:15 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231646109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.231646109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.2408672263 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 3633292739 ps |
| CPU time | 36.85 seconds |
| Started | Sep 09 04:01:54 AM UTC 24 |
| Finished | Sep 09 04:02:32 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408672263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2408672263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.1894092270 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5482443769 ps |
| CPU time | 50.22 seconds |
| Started | Sep 09 04:01:43 AM UTC 24 |
| Finished | Sep 09 04:02:35 AM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894092270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1894092270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.2569422123 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 51411405955 ps |
| CPU time | 241.19 seconds |
| Started | Sep 09 04:01:45 AM UTC 24 |
| Finished | Sep 09 04:05:50 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569422123 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2569422123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1097072654 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 894619008 ps |
| CPU time | 14.73 seconds |
| Started | Sep 09 04:01:46 AM UTC 24 |
| Finished | Sep 09 04:02:02 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097072654 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1097072654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.2258311355 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 87837542 ps |
| CPU time | 10.92 seconds |
| Started | Sep 09 04:01:44 AM UTC 24 |
| Finished | Sep 09 04:01:56 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258311355 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2258311355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.3669251122 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 395178585 ps |
| CPU time | 9.02 seconds |
| Started | Sep 09 04:01:47 AM UTC 24 |
| Finished | Sep 09 04:01:58 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669251122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3669251122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.3851200193 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 178110034 ps |
| CPU time | 5.28 seconds |
| Started | Sep 09 04:01:38 AM UTC 24 |
| Finished | Sep 09 04:01:44 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851200193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3851200193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2186215887 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 10537101706 ps |
| CPU time | 55.1 seconds |
| Started | Sep 09 04:01:41 AM UTC 24 |
| Finished | Sep 09 04:02:37 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186215887 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2186215887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3412493658 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 4691625316 ps |
| CPU time | 33.24 seconds |
| Started | Sep 09 04:01:42 AM UTC 24 |
| Finished | Sep 09 04:02:16 AM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412493658 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3412493658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1212834366 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 49612047 ps |
| CPU time | 3.36 seconds |
| Started | Sep 09 04:01:38 AM UTC 24 |
| Finished | Sep 09 04:01:42 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212834366 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1212834366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.3932962586 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 6519456649 ps |
| CPU time | 108.34 seconds |
| Started | Sep 09 04:01:59 AM UTC 24 |
| Finished | Sep 09 04:03:50 AM UTC 24 |
| Peak memory | 220992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932962586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3932962586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2836221846 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 13280311116 ps |
| CPU time | 127.46 seconds |
| Started | Sep 09 04:02:02 AM UTC 24 |
| Finished | Sep 09 04:04:12 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836221846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2836221846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3113454181 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 225602981 ps |
| CPU time | 95.29 seconds |
| Started | Sep 09 04:01:59 AM UTC 24 |
| Finished | Sep 09 04:03:37 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113454181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.3113454181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3466251844 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 6983981327 ps |
| CPU time | 118.71 seconds |
| Started | Sep 09 04:02:03 AM UTC 24 |
| Finished | Sep 09 04:04:05 AM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466251844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3466251844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.1641717555 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 280173004 ps |
| CPU time | 15.53 seconds |
| Started | Sep 09 04:01:57 AM UTC 24 |
| Finished | Sep 09 04:02:13 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641717555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1641717555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.2141693899 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 208043018 ps |
| CPU time | 13.69 seconds |
| Started | Sep 09 04:02:19 AM UTC 24 |
| Finished | Sep 09 04:02:33 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141693899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2141693899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2171561843 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 67884793628 ps |
| CPU time | 617.83 seconds |
| Started | Sep 09 04:02:19 AM UTC 24 |
| Finished | Sep 09 04:12:44 AM UTC 24 |
| Peak memory | 222612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171561843 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.2171561843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.587689022 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 12770297 ps |
| CPU time | 2.52 seconds |
| Started | Sep 09 04:02:32 AM UTC 24 |
| Finished | Sep 09 04:02:36 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587689022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.587689022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.404530411 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 215363428 ps |
| CPU time | 8.56 seconds |
| Started | Sep 09 04:02:25 AM UTC 24 |
| Finished | Sep 09 04:02:35 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404530411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.404530411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.3677564333 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 231994214 ps |
| CPU time | 17.16 seconds |
| Started | Sep 09 04:02:17 AM UTC 24 |
| Finished | Sep 09 04:02:35 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677564333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3677564333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.937498007 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 16929302606 ps |
| CPU time | 65.64 seconds |
| Started | Sep 09 04:02:19 AM UTC 24 |
| Finished | Sep 09 04:03:26 AM UTC 24 |
| Peak memory | 216504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937498007 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.937498007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2496510350 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 40635769855 ps |
| CPU time | 195.86 seconds |
| Started | Sep 09 04:02:19 AM UTC 24 |
| Finished | Sep 09 04:05:37 AM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496510350 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2496510350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.1200299654 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 45293691 ps |
| CPU time | 5.81 seconds |
| Started | Sep 09 04:02:17 AM UTC 24 |
| Finished | Sep 09 04:02:24 AM UTC 24 |
| Peak memory | 216952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200299654 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1200299654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.2802396395 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 108600835 ps |
| CPU time | 8.82 seconds |
| Started | Sep 09 04:02:23 AM UTC 24 |
| Finished | Sep 09 04:02:33 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802396395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2802396395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.2179712705 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 263422423 ps |
| CPU time | 4.59 seconds |
| Started | Sep 09 04:02:10 AM UTC 24 |
| Finished | Sep 09 04:02:16 AM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179712705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2179712705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3524927587 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 6669414080 ps |
| CPU time | 35.29 seconds |
| Started | Sep 09 04:02:15 AM UTC 24 |
| Finished | Sep 09 04:02:51 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524927587 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3524927587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3434182668 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 10784125295 ps |
| CPU time | 41.18 seconds |
| Started | Sep 09 04:02:16 AM UTC 24 |
| Finished | Sep 09 04:02:58 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434182668 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3434182668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1364488312 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 41610898 ps |
| CPU time | 3.42 seconds |
| Started | Sep 09 04:02:13 AM UTC 24 |
| Finished | Sep 09 04:02:17 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364488312 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1364488312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.1367389152 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3828387688 ps |
| CPU time | 66.23 seconds |
| Started | Sep 09 04:02:34 AM UTC 24 |
| Finished | Sep 09 04:03:42 AM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367389152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1367389152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.880829610 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 850538448 ps |
| CPU time | 96.49 seconds |
| Started | Sep 09 04:02:34 AM UTC 24 |
| Finished | Sep 09 04:04:12 AM UTC 24 |
| Peak memory | 219148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880829610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.880829610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1455739082 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3832065301 ps |
| CPU time | 385.42 seconds |
| Started | Sep 09 04:02:34 AM UTC 24 |
| Finished | Sep 09 04:09:04 AM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455739082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.1455739082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.441720295 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 651558818 ps |
| CPU time | 28.44 seconds |
| Started | Sep 09 04:02:26 AM UTC 24 |
| Finished | Sep 09 04:02:56 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441720295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.441720295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.1013371645 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 599157648 ps |
| CPU time | 36.57 seconds |
| Started | Sep 09 04:02:43 AM UTC 24 |
| Finished | Sep 09 04:03:21 AM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013371645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1013371645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1139246389 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 186469591051 ps |
| CPU time | 667.57 seconds |
| Started | Sep 09 04:02:51 AM UTC 24 |
| Finished | Sep 09 04:14:06 AM UTC 24 |
| Peak memory | 220500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139246389 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1139246389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2829799885 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 4563111118 ps |
| CPU time | 32.34 seconds |
| Started | Sep 09 04:02:59 AM UTC 24 |
| Finished | Sep 09 04:03:32 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829799885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2829799885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.2192685514 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 178848976 ps |
| CPU time | 5.48 seconds |
| Started | Sep 09 04:02:56 AM UTC 24 |
| Finished | Sep 09 04:03:03 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192685514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2192685514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.3200911884 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 236922307 ps |
| CPU time | 20.92 seconds |
| Started | Sep 09 04:02:39 AM UTC 24 |
| Finished | Sep 09 04:03:01 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200911884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3200911884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.1288148462 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 6380996663 ps |
| CPU time | 43.96 seconds |
| Started | Sep 09 04:02:41 AM UTC 24 |
| Finished | Sep 09 04:03:26 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288148462 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1288148462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3378195683 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 8115135111 ps |
| CPU time | 55.9 seconds |
| Started | Sep 09 04:02:43 AM UTC 24 |
| Finished | Sep 09 04:03:40 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378195683 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3378195683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.3022646610 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 230194135 ps |
| CPU time | 35.83 seconds |
| Started | Sep 09 04:02:39 AM UTC 24 |
| Finished | Sep 09 04:03:16 AM UTC 24 |
| Peak memory | 219128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022646610 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3022646610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.2431842693 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 101141562 ps |
| CPU time | 7.66 seconds |
| Started | Sep 09 04:02:53 AM UTC 24 |
| Finished | Sep 09 04:03:02 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431842693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2431842693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.56340114 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 164661231 ps |
| CPU time | 5.18 seconds |
| Started | Sep 09 04:02:36 AM UTC 24 |
| Finished | Sep 09 04:02:42 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56340114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.56340114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.336058431 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 6130588921 ps |
| CPU time | 46.43 seconds |
| Started | Sep 09 04:02:36 AM UTC 24 |
| Finished | Sep 09 04:03:24 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336058431 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.336058431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1779027552 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 5113544638 ps |
| CPU time | 39.79 seconds |
| Started | Sep 09 04:02:39 AM UTC 24 |
| Finished | Sep 09 04:03:20 AM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779027552 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1779027552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1701377275 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 35643957 ps |
| CPU time | 2.84 seconds |
| Started | Sep 09 04:02:36 AM UTC 24 |
| Finished | Sep 09 04:02:40 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701377275 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1701377275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.3840425797 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 855705013 ps |
| CPU time | 10.77 seconds |
| Started | Sep 09 04:03:01 AM UTC 24 |
| Finished | Sep 09 04:03:13 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840425797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3840425797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2692112159 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1326386880 ps |
| CPU time | 78.04 seconds |
| Started | Sep 09 04:03:03 AM UTC 24 |
| Finished | Sep 09 04:04:23 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692112159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2692112159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3441289645 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 158764078 ps |
| CPU time | 63.55 seconds |
| Started | Sep 09 04:03:01 AM UTC 24 |
| Finished | Sep 09 04:04:06 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441289645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.3441289645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3689196079 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 132128086 ps |
| CPU time | 50.98 seconds |
| Started | Sep 09 04:03:03 AM UTC 24 |
| Finished | Sep 09 04:03:56 AM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689196079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3689196079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.1564347272 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1188961772 ps |
| CPU time | 26.4 seconds |
| Started | Sep 09 04:02:59 AM UTC 24 |
| Finished | Sep 09 04:03:26 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564347272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1564347272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.2472169714 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1199161213 ps |
| CPU time | 29.96 seconds |
| Started | Sep 09 04:03:21 AM UTC 24 |
| Finished | Sep 09 04:03:52 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472169714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2472169714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2650600028 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 13977788693 ps |
| CPU time | 127.56 seconds |
| Started | Sep 09 04:03:22 AM UTC 24 |
| Finished | Sep 09 04:05:32 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650600028 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.2650600028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.447673070 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 104832549 ps |
| CPU time | 9.33 seconds |
| Started | Sep 09 04:03:27 AM UTC 24 |
| Finished | Sep 09 04:03:38 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447673070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.447673070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.3239246859 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1769127554 ps |
| CPU time | 31.3 seconds |
| Started | Sep 09 04:03:27 AM UTC 24 |
| Finished | Sep 09 04:04:00 AM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239246859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3239246859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.4120637481 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 434913806 ps |
| CPU time | 15.99 seconds |
| Started | Sep 09 04:03:14 AM UTC 24 |
| Finished | Sep 09 04:03:32 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120637481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.4120637481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.1723484563 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 196868370151 ps |
| CPU time | 336.55 seconds |
| Started | Sep 09 04:03:17 AM UTC 24 |
| Finished | Sep 09 04:08:57 AM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723484563 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1723484563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2728728869 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1010994058 ps |
| CPU time | 11.53 seconds |
| Started | Sep 09 04:03:19 AM UTC 24 |
| Finished | Sep 09 04:03:31 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728728869 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2728728869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.944768496 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 853270091 ps |
| CPU time | 27.51 seconds |
| Started | Sep 09 04:03:17 AM UTC 24 |
| Finished | Sep 09 04:03:45 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944768496 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.944768496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.1419652170 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 25192406 ps |
| CPU time | 2.81 seconds |
| Started | Sep 09 04:03:25 AM UTC 24 |
| Finished | Sep 09 04:03:30 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419652170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1419652170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.2164645458 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 130722275 ps |
| CPU time | 4.69 seconds |
| Started | Sep 09 04:03:05 AM UTC 24 |
| Finished | Sep 09 04:03:11 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164645458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2164645458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3363866891 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 9234487310 ps |
| CPU time | 42.96 seconds |
| Started | Sep 09 04:03:11 AM UTC 24 |
| Finished | Sep 09 04:03:56 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363866891 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3363866891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.329092911 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 7443005103 ps |
| CPU time | 36.26 seconds |
| Started | Sep 09 04:03:13 AM UTC 24 |
| Finished | Sep 09 04:03:51 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329092911 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.329092911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2880782817 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 74993068 ps |
| CPU time | 3.32 seconds |
| Started | Sep 09 04:03:11 AM UTC 24 |
| Finished | Sep 09 04:03:16 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880782817 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2880782817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.344401758 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2561423795 ps |
| CPU time | 76.89 seconds |
| Started | Sep 09 04:03:28 AM UTC 24 |
| Finished | Sep 09 04:04:47 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344401758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.344401758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.674522287 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 121110135 ps |
| CPU time | 6.13 seconds |
| Started | Sep 09 04:03:31 AM UTC 24 |
| Finished | Sep 09 04:03:38 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674522287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.674522287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.270562058 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1753805450 ps |
| CPU time | 349.49 seconds |
| Started | Sep 09 04:03:30 AM UTC 24 |
| Finished | Sep 09 04:09:25 AM UTC 24 |
| Peak memory | 223164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270562058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.270562058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3195457509 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 2183640500 ps |
| CPU time | 327.82 seconds |
| Started | Sep 09 04:03:33 AM UTC 24 |
| Finished | Sep 09 04:09:05 AM UTC 24 |
| Peak memory | 233656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195457509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.3195457509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.872913449 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 439734458 ps |
| CPU time | 18.04 seconds |
| Started | Sep 09 04:03:27 AM UTC 24 |
| Finished | Sep 09 04:03:47 AM UTC 24 |
| Peak memory | 217028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872913449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.872913449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.2301584821 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 389387162 ps |
| CPU time | 33.71 seconds |
| Started | Sep 09 04:03:39 AM UTC 24 |
| Finished | Sep 09 04:04:14 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301584821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2301584821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2544190111 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 114166099057 ps |
| CPU time | 589.74 seconds |
| Started | Sep 09 04:03:40 AM UTC 24 |
| Finished | Sep 09 04:13:37 AM UTC 24 |
| Peak memory | 219588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544190111 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.2544190111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3992688495 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 56495311 ps |
| CPU time | 6.2 seconds |
| Started | Sep 09 04:03:42 AM UTC 24 |
| Finished | Sep 09 04:03:50 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992688495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3992688495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.1519145049 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 200723451 ps |
| CPU time | 17.83 seconds |
| Started | Sep 09 04:03:41 AM UTC 24 |
| Finished | Sep 09 04:04:01 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519145049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1519145049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.3945398772 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1534645901 ps |
| CPU time | 32.77 seconds |
| Started | Sep 09 04:03:37 AM UTC 24 |
| Finished | Sep 09 04:04:12 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945398772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3945398772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.4180542889 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 15804571476 ps |
| CPU time | 58.36 seconds |
| Started | Sep 09 04:03:39 AM UTC 24 |
| Finished | Sep 09 04:04:39 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180542889 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.4180542889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2904659407 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 6992484466 ps |
| CPU time | 33.21 seconds |
| Started | Sep 09 04:03:39 AM UTC 24 |
| Finished | Sep 09 04:04:14 AM UTC 24 |
| Peak memory | 217160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904659407 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2904659407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.1741870021 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 276396876 ps |
| CPU time | 23.76 seconds |
| Started | Sep 09 04:03:39 AM UTC 24 |
| Finished | Sep 09 04:04:04 AM UTC 24 |
| Peak memory | 217144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741870021 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1741870021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.3115125306 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1139656759 ps |
| CPU time | 12.82 seconds |
| Started | Sep 09 04:03:40 AM UTC 24 |
| Finished | Sep 09 04:03:54 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115125306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3115125306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.325689464 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 337707904 ps |
| CPU time | 5.44 seconds |
| Started | Sep 09 04:03:33 AM UTC 24 |
| Finished | Sep 09 04:03:39 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325689464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.325689464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1458708023 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 24853509596 ps |
| CPU time | 45.98 seconds |
| Started | Sep 09 04:03:37 AM UTC 24 |
| Finished | Sep 09 04:04:25 AM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458708023 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1458708023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2381404879 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 15572888050 ps |
| CPU time | 33.76 seconds |
| Started | Sep 09 04:03:37 AM UTC 24 |
| Finished | Sep 09 04:04:13 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381404879 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2381404879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2514781586 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 49076585 ps |
| CPU time | 2.72 seconds |
| Started | Sep 09 04:03:33 AM UTC 24 |
| Finished | Sep 09 04:03:37 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514781586 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2514781586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.1680058039 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 21498524301 ps |
| CPU time | 328.2 seconds |
| Started | Sep 09 04:03:46 AM UTC 24 |
| Finished | Sep 09 04:09:20 AM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680058039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1680058039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2650821307 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3143254121 ps |
| CPU time | 107.91 seconds |
| Started | Sep 09 04:03:48 AM UTC 24 |
| Finished | Sep 09 04:05:38 AM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650821307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2650821307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3575973333 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1818054480 ps |
| CPU time | 337.25 seconds |
| Started | Sep 09 04:03:47 AM UTC 24 |
| Finished | Sep 09 04:09:28 AM UTC 24 |
| Peak memory | 220940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575973333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.3575973333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.414375635 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 4478973265 ps |
| CPU time | 371.46 seconds |
| Started | Sep 09 04:03:51 AM UTC 24 |
| Finished | Sep 09 04:10:07 AM UTC 24 |
| Peak memory | 237748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414375635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.414375635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.1533817274 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 53864025 ps |
| CPU time | 2.98 seconds |
| Started | Sep 09 04:03:41 AM UTC 24 |
| Finished | Sep 09 04:03:46 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533817274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1533817274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.3390993810 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 130894932 ps |
| CPU time | 5.55 seconds |
| Started | Sep 09 04:03:57 AM UTC 24 |
| Finished | Sep 09 04:04:04 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390993810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3390993810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1913696628 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 124700473052 ps |
| CPU time | 362.82 seconds |
| Started | Sep 09 04:04:01 AM UTC 24 |
| Finished | Sep 09 04:10:09 AM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913696628 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.1913696628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3906931739 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1030848827 ps |
| CPU time | 23.62 seconds |
| Started | Sep 09 04:04:06 AM UTC 24 |
| Finished | Sep 09 04:04:30 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906931739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3906931739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.1831594722 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 98202681 ps |
| CPU time | 10.77 seconds |
| Started | Sep 09 04:04:04 AM UTC 24 |
| Finished | Sep 09 04:04:16 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831594722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1831594722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.180590765 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2817283446 ps |
| CPU time | 46.38 seconds |
| Started | Sep 09 04:03:56 AM UTC 24 |
| Finished | Sep 09 04:04:43 AM UTC 24 |
| Peak memory | 216960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180590765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.180590765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.4245938228 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 74454125489 ps |
| CPU time | 176 seconds |
| Started | Sep 09 04:03:57 AM UTC 24 |
| Finished | Sep 09 04:06:56 AM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245938228 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.4245938228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3202976149 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2552167102 ps |
| CPU time | 17.86 seconds |
| Started | Sep 09 04:03:57 AM UTC 24 |
| Finished | Sep 09 04:04:16 AM UTC 24 |
| Peak memory | 217024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202976149 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3202976149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.1345120320 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 121311202 ps |
| CPU time | 14.25 seconds |
| Started | Sep 09 04:03:56 AM UTC 24 |
| Finished | Sep 09 04:04:11 AM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345120320 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1345120320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.3203592646 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 774636626 ps |
| CPU time | 19.15 seconds |
| Started | Sep 09 04:04:01 AM UTC 24 |
| Finished | Sep 09 04:04:22 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203592646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3203592646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.1082145894 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 451995673 ps |
| CPU time | 3.09 seconds |
| Started | Sep 09 04:03:51 AM UTC 24 |
| Finished | Sep 09 04:03:55 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082145894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1082145894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3922374190 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 7781084135 ps |
| CPU time | 63.73 seconds |
| Started | Sep 09 04:03:53 AM UTC 24 |
| Finished | Sep 09 04:04:58 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922374190 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3922374190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2501918928 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2993202341 ps |
| CPU time | 26.9 seconds |
| Started | Sep 09 04:03:54 AM UTC 24 |
| Finished | Sep 09 04:04:23 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501918928 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2501918928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.311905614 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 82116352 ps |
| CPU time | 3.52 seconds |
| Started | Sep 09 04:03:52 AM UTC 24 |
| Finished | Sep 09 04:03:57 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311905614 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.311905614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.3856086150 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1351162622 ps |
| CPU time | 66.33 seconds |
| Started | Sep 09 04:04:07 AM UTC 24 |
| Finished | Sep 09 04:05:15 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856086150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3856086150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.376842388 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1768184566 ps |
| CPU time | 50.43 seconds |
| Started | Sep 09 04:04:13 AM UTC 24 |
| Finished | Sep 09 04:05:05 AM UTC 24 |
| Peak memory | 218824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376842388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.376842388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.4042318861 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 8527288695 ps |
| CPU time | 236.18 seconds |
| Started | Sep 09 04:04:12 AM UTC 24 |
| Finished | Sep 09 04:08:12 AM UTC 24 |
| Peak memory | 223052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042318861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.4042318861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.2635295008 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 60831635 ps |
| CPU time | 25.28 seconds |
| Started | Sep 09 04:04:13 AM UTC 24 |
| Finished | Sep 09 04:04:40 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635295008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.2635295008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.36298291 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 809852810 ps |
| CPU time | 33.02 seconds |
| Started | Sep 09 04:04:06 AM UTC 24 |
| Finished | Sep 09 04:04:40 AM UTC 24 |
| Peak memory | 219132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36298291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.36298291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.3588168280 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3502655512 ps |
| CPU time | 54.93 seconds |
| Started | Sep 09 04:04:22 AM UTC 24 |
| Finished | Sep 09 04:05:18 AM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588168280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3588168280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3114821939 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 58592847314 ps |
| CPU time | 452.05 seconds |
| Started | Sep 09 04:04:22 AM UTC 24 |
| Finished | Sep 09 04:12:00 AM UTC 24 |
| Peak memory | 221000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114821939 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.3114821939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1893208656 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 22153152 ps |
| CPU time | 2.1 seconds |
| Started | Sep 09 04:04:25 AM UTC 24 |
| Finished | Sep 09 04:04:29 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893208656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1893208656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.1693346799 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 6118975267 ps |
| CPU time | 41.77 seconds |
| Started | Sep 09 04:04:23 AM UTC 24 |
| Finished | Sep 09 04:05:06 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693346799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1693346799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.2088168552 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 69519227 ps |
| CPU time | 3.73 seconds |
| Started | Sep 09 04:04:17 AM UTC 24 |
| Finished | Sep 09 04:04:21 AM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088168552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2088168552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.3488983375 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 30992872156 ps |
| CPU time | 234.64 seconds |
| Started | Sep 09 04:04:18 AM UTC 24 |
| Finished | Sep 09 04:08:16 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488983375 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3488983375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1964709103 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 32921846281 ps |
| CPU time | 119.92 seconds |
| Started | Sep 09 04:04:19 AM UTC 24 |
| Finished | Sep 09 04:06:21 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964709103 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1964709103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.1320641792 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 129612328 ps |
| CPU time | 6.3 seconds |
| Started | Sep 09 04:04:18 AM UTC 24 |
| Finished | Sep 09 04:04:25 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320641792 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1320641792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.685784377 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 326221693 ps |
| CPU time | 21.73 seconds |
| Started | Sep 09 04:04:23 AM UTC 24 |
| Finished | Sep 09 04:04:46 AM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685784377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.685784377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.3641068397 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 411691947 ps |
| CPU time | 2.86 seconds |
| Started | Sep 09 04:04:13 AM UTC 24 |
| Finished | Sep 09 04:04:17 AM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641068397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3641068397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2063799209 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 9767612286 ps |
| CPU time | 58.18 seconds |
| Started | Sep 09 04:04:14 AM UTC 24 |
| Finished | Sep 09 04:05:14 AM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063799209 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2063799209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2042536203 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 4569814544 ps |
| CPU time | 30.64 seconds |
| Started | Sep 09 04:04:15 AM UTC 24 |
| Finished | Sep 09 04:04:47 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042536203 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2042536203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3663848364 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 48769718 ps |
| CPU time | 3.25 seconds |
| Started | Sep 09 04:04:13 AM UTC 24 |
| Finished | Sep 09 04:04:18 AM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663848364 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3663848364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.4259400595 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 18602759645 ps |
| CPU time | 276.46 seconds |
| Started | Sep 09 04:04:25 AM UTC 24 |
| Finished | Sep 09 04:09:06 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259400595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4259400595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.353461831 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 351669727 ps |
| CPU time | 33.28 seconds |
| Started | Sep 09 04:04:32 AM UTC 24 |
| Finished | Sep 09 04:05:06 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353461831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.353461831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2486802150 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 197505728 ps |
| CPU time | 133.68 seconds |
| Started | Sep 09 04:04:30 AM UTC 24 |
| Finished | Sep 09 04:06:46 AM UTC 24 |
| Peak memory | 221196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486802150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.2486802150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.599664734 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 583786358 ps |
| CPU time | 159.31 seconds |
| Started | Sep 09 04:04:40 AM UTC 24 |
| Finished | Sep 09 04:07:22 AM UTC 24 |
| Peak memory | 223256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599664734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.599664734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.3668447121 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 96120602 ps |
| CPU time | 17.84 seconds |
| Started | Sep 09 04:04:24 AM UTC 24 |
| Finished | Sep 09 04:04:43 AM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668447121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3668447121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.2094853446 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 291222839 ps |
| CPU time | 10.47 seconds |
| Started | Sep 09 03:54:09 AM UTC 24 |
| Finished | Sep 09 03:54:24 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094853446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2094853446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3417722738 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 58027576349 ps |
| CPU time | 549.37 seconds |
| Started | Sep 09 03:54:09 AM UTC 24 |
| Finished | Sep 09 04:03:28 AM UTC 24 |
| Peak memory | 222360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417722738 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.3417722738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1775135140 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1091015525 ps |
| CPU time | 11.7 seconds |
| Started | Sep 09 03:54:14 AM UTC 24 |
| Finished | Sep 09 03:54:27 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775135140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1775135140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.3944765316 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 862750119 ps |
| CPU time | 30.72 seconds |
| Started | Sep 09 03:54:12 AM UTC 24 |
| Finished | Sep 09 03:54:44 AM UTC 24 |
| Peak memory | 217144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944765316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3944765316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.718803538 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1200524380 ps |
| CPU time | 15.44 seconds |
| Started | Sep 09 03:54:07 AM UTC 24 |
| Finished | Sep 09 03:54:32 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718803538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.718803538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.2720058726 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 72302710938 ps |
| CPU time | 153.88 seconds |
| Started | Sep 09 03:54:08 AM UTC 24 |
| Finished | Sep 09 03:56:54 AM UTC 24 |
| Peak memory | 216488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720058726 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2720058726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.547521497 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 79064973896 ps |
| CPU time | 197.57 seconds |
| Started | Sep 09 03:54:08 AM UTC 24 |
| Finished | Sep 09 03:57:39 AM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547521497 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.547521497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.593842036 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 406623029 ps |
| CPU time | 12.97 seconds |
| Started | Sep 09 03:54:08 AM UTC 24 |
| Finished | Sep 09 03:54:32 AM UTC 24 |
| Peak memory | 216636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593842036 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.593842036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.2987198607 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1613673609 ps |
| CPU time | 32.98 seconds |
| Started | Sep 09 03:54:11 AM UTC 24 |
| Finished | Sep 09 03:54:46 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987198607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2987198607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.2910731647 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 156534628 ps |
| CPU time | 3.07 seconds |
| Started | Sep 09 03:54:03 AM UTC 24 |
| Finished | Sep 09 03:54:07 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910731647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2910731647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2581459561 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 15228110080 ps |
| CPU time | 41.14 seconds |
| Started | Sep 09 03:54:04 AM UTC 24 |
| Finished | Sep 09 03:54:56 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581459561 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2581459561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.4154583297 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3961334253 ps |
| CPU time | 28.06 seconds |
| Started | Sep 09 03:54:05 AM UTC 24 |
| Finished | Sep 09 03:54:47 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154583297 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.4154583297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3823763047 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 51887165 ps |
| CPU time | 2.17 seconds |
| Started | Sep 09 03:54:03 AM UTC 24 |
| Finished | Sep 09 03:54:06 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823763047 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3823763047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.1283734594 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1258473488 ps |
| CPU time | 150.69 seconds |
| Started | Sep 09 03:54:14 AM UTC 24 |
| Finished | Sep 09 03:56:48 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283734594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1283734594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1716642910 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1805480990 ps |
| CPU time | 49.36 seconds |
| Started | Sep 09 03:54:17 AM UTC 24 |
| Finished | Sep 09 03:55:08 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716642910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1716642910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3363122872 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 343274213 ps |
| CPU time | 129.66 seconds |
| Started | Sep 09 03:54:15 AM UTC 24 |
| Finished | Sep 09 03:56:31 AM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363122872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.3363122872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1881885554 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 508607229 ps |
| CPU time | 99.26 seconds |
| Started | Sep 09 03:54:19 AM UTC 24 |
| Finished | Sep 09 03:56:00 AM UTC 24 |
| Peak memory | 222916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881885554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.1881885554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.484804590 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1030507465 ps |
| CPU time | 14.18 seconds |
| Started | Sep 09 03:54:12 AM UTC 24 |
| Finished | Sep 09 03:54:28 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484804590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.484804590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.2646312520 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 189487956 ps |
| CPU time | 28.53 seconds |
| Started | Sep 09 04:04:48 AM UTC 24 |
| Finished | Sep 09 04:05:18 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646312520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2646312520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3600558177 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 19928247677 ps |
| CPU time | 252.75 seconds |
| Started | Sep 09 04:04:49 AM UTC 24 |
| Finished | Sep 09 04:09:05 AM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600558177 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.3600558177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.212110716 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 519143276 ps |
| CPU time | 16.43 seconds |
| Started | Sep 09 04:05:07 AM UTC 24 |
| Finished | Sep 09 04:05:24 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212110716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.212110716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.3422787293 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 3116355023 ps |
| CPU time | 41.74 seconds |
| Started | Sep 09 04:04:59 AM UTC 24 |
| Finished | Sep 09 04:05:43 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422787293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3422787293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.1233799104 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 4517796800 ps |
| CPU time | 38.93 seconds |
| Started | Sep 09 04:04:45 AM UTC 24 |
| Finished | Sep 09 04:05:26 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233799104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1233799104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.875948243 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 47075235682 ps |
| CPU time | 278.36 seconds |
| Started | Sep 09 04:04:47 AM UTC 24 |
| Finished | Sep 09 04:09:29 AM UTC 24 |
| Peak memory | 217160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875948243 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.875948243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.259772631 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 4158447776 ps |
| CPU time | 51.25 seconds |
| Started | Sep 09 04:04:47 AM UTC 24 |
| Finished | Sep 09 04:05:39 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259772631 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.259772631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.2051884333 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 152401054 ps |
| CPU time | 26.46 seconds |
| Started | Sep 09 04:04:47 AM UTC 24 |
| Finished | Sep 09 04:05:14 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051884333 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2051884333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.1901270289 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 210763050 ps |
| CPU time | 15.89 seconds |
| Started | Sep 09 04:04:53 AM UTC 24 |
| Finished | Sep 09 04:05:10 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901270289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1901270289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.788373989 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 71753974 ps |
| CPU time | 2.86 seconds |
| Started | Sep 09 04:04:41 AM UTC 24 |
| Finished | Sep 09 04:04:45 AM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788373989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.788373989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2013006091 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 9429474320 ps |
| CPU time | 40.6 seconds |
| Started | Sep 09 04:04:44 AM UTC 24 |
| Finished | Sep 09 04:05:26 AM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013006091 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2013006091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2675571381 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 10988677663 ps |
| CPU time | 38.83 seconds |
| Started | Sep 09 04:04:44 AM UTC 24 |
| Finished | Sep 09 04:05:24 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675571381 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2675571381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1576449100 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 51166784 ps |
| CPU time | 3.49 seconds |
| Started | Sep 09 04:04:41 AM UTC 24 |
| Finished | Sep 09 04:04:45 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576449100 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1576449100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.3067607848 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 28492437259 ps |
| CPU time | 137.02 seconds |
| Started | Sep 09 04:05:08 AM UTC 24 |
| Finished | Sep 09 04:07:28 AM UTC 24 |
| Peak memory | 220904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067607848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3067607848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1345139457 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2028037705 ps |
| CPU time | 43.62 seconds |
| Started | Sep 09 04:05:11 AM UTC 24 |
| Finished | Sep 09 04:05:56 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345139457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1345139457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.812936669 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 4323476380 ps |
| CPU time | 405.11 seconds |
| Started | Sep 09 04:05:08 AM UTC 24 |
| Finished | Sep 09 04:11:59 AM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812936669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.812936669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.667064925 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13946191996 ps |
| CPU time | 206.27 seconds |
| Started | Sep 09 04:05:15 AM UTC 24 |
| Finished | Sep 09 04:08:45 AM UTC 24 |
| Peak memory | 223044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667064925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.667064925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.1826030238 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 165181878 ps |
| CPU time | 24.27 seconds |
| Started | Sep 09 04:05:07 AM UTC 24 |
| Finished | Sep 09 04:05:32 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826030238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1826030238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.366901310 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1519147937 ps |
| CPU time | 48.06 seconds |
| Started | Sep 09 04:05:26 AM UTC 24 |
| Finished | Sep 09 04:06:15 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366901310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.366901310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.39129749 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 64848388094 ps |
| CPU time | 430.77 seconds |
| Started | Sep 09 04:05:27 AM UTC 24 |
| Finished | Sep 09 04:12:43 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39129749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.39129749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.738424126 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 362303314 ps |
| CPU time | 12.97 seconds |
| Started | Sep 09 04:05:28 AM UTC 24 |
| Finished | Sep 09 04:05:42 AM UTC 24 |
| Peak memory | 217160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738424126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.738424126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.1107010935 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 381036314 ps |
| CPU time | 13.31 seconds |
| Started | Sep 09 04:05:27 AM UTC 24 |
| Finished | Sep 09 04:05:41 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107010935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1107010935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.2747218053 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 53845016 ps |
| CPU time | 3.81 seconds |
| Started | Sep 09 04:05:20 AM UTC 24 |
| Finished | Sep 09 04:05:25 AM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747218053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2747218053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.3150381612 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 27779680429 ps |
| CPU time | 179.73 seconds |
| Started | Sep 09 04:05:25 AM UTC 24 |
| Finished | Sep 09 04:08:27 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150381612 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3150381612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.324726988 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 31418570253 ps |
| CPU time | 286.73 seconds |
| Started | Sep 09 04:05:26 AM UTC 24 |
| Finished | Sep 09 04:10:16 AM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324726988 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.324726988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.3875900545 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 176222625 ps |
| CPU time | 9.58 seconds |
| Started | Sep 09 04:05:22 AM UTC 24 |
| Finished | Sep 09 04:05:32 AM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875900545 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3875900545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.892005061 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 887799339 ps |
| CPU time | 20.42 seconds |
| Started | Sep 09 04:05:27 AM UTC 24 |
| Finished | Sep 09 04:05:49 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892005061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.892005061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.1275044976 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 24671356 ps |
| CPU time | 3.05 seconds |
| Started | Sep 09 04:05:15 AM UTC 24 |
| Finished | Sep 09 04:05:19 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275044976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1275044976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.4271350503 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 8675994782 ps |
| CPU time | 40.82 seconds |
| Started | Sep 09 04:05:18 AM UTC 24 |
| Finished | Sep 09 04:06:00 AM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271350503 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.4271350503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.244177525 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 2575509529 ps |
| CPU time | 25.81 seconds |
| Started | Sep 09 04:05:19 AM UTC 24 |
| Finished | Sep 09 04:05:46 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244177525 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.244177525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3590641044 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 38790360 ps |
| CPU time | 3.14 seconds |
| Started | Sep 09 04:05:16 AM UTC 24 |
| Finished | Sep 09 04:05:20 AM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590641044 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3590641044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.2865332882 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 652985945 ps |
| CPU time | 79.85 seconds |
| Started | Sep 09 04:05:30 AM UTC 24 |
| Finished | Sep 09 04:06:51 AM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865332882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2865332882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3894556282 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 6091366270 ps |
| CPU time | 101.25 seconds |
| Started | Sep 09 04:05:33 AM UTC 24 |
| Finished | Sep 09 04:07:16 AM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894556282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3894556282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2806452260 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 322835802 ps |
| CPU time | 134.79 seconds |
| Started | Sep 09 04:05:33 AM UTC 24 |
| Finished | Sep 09 04:07:50 AM UTC 24 |
| Peak memory | 221196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806452260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.2806452260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2969986031 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 84086936 ps |
| CPU time | 10.16 seconds |
| Started | Sep 09 04:05:33 AM UTC 24 |
| Finished | Sep 09 04:05:44 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969986031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.2969986031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.1228579641 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 932581489 ps |
| CPU time | 13.43 seconds |
| Started | Sep 09 04:05:27 AM UTC 24 |
| Finished | Sep 09 04:05:42 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228579641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1228579641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.2965536624 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 442771768 ps |
| CPU time | 23.63 seconds |
| Started | Sep 09 04:05:43 AM UTC 24 |
| Finished | Sep 09 04:06:08 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965536624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2965536624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3234432981 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 57294416753 ps |
| CPU time | 552.71 seconds |
| Started | Sep 09 04:05:43 AM UTC 24 |
| Finished | Sep 09 04:15:03 AM UTC 24 |
| Peak memory | 220500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234432981 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.3234432981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1968525144 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 89407563 ps |
| CPU time | 8.59 seconds |
| Started | Sep 09 04:05:46 AM UTC 24 |
| Finished | Sep 09 04:05:55 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968525144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1968525144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.1348888867 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 5644835336 ps |
| CPU time | 43.26 seconds |
| Started | Sep 09 04:05:43 AM UTC 24 |
| Finished | Sep 09 04:06:28 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348888867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1348888867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.2316041037 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 85129864 ps |
| CPU time | 12.51 seconds |
| Started | Sep 09 04:05:42 AM UTC 24 |
| Finished | Sep 09 04:05:56 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316041037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2316041037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.499700945 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 18970719484 ps |
| CPU time | 101.12 seconds |
| Started | Sep 09 04:05:42 AM UTC 24 |
| Finished | Sep 09 04:07:25 AM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499700945 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.499700945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.392564095 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 32483196512 ps |
| CPU time | 278.09 seconds |
| Started | Sep 09 04:05:43 AM UTC 24 |
| Finished | Sep 09 04:10:25 AM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392564095 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.392564095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.3213906350 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 278147318 ps |
| CPU time | 14.6 seconds |
| Started | Sep 09 04:05:42 AM UTC 24 |
| Finished | Sep 09 04:05:58 AM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213906350 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3213906350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.157607691 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2053583399 ps |
| CPU time | 22.4 seconds |
| Started | Sep 09 04:05:43 AM UTC 24 |
| Finished | Sep 09 04:06:07 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157607691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.157607691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.1652275234 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 396292624 ps |
| CPU time | 3.94 seconds |
| Started | Sep 09 04:05:38 AM UTC 24 |
| Finished | Sep 09 04:05:43 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652275234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1652275234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.676594568 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 5066571447 ps |
| CPU time | 24.45 seconds |
| Started | Sep 09 04:05:41 AM UTC 24 |
| Finished | Sep 09 04:06:06 AM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676594568 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.676594568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2859221637 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 3327533263 ps |
| CPU time | 38.66 seconds |
| Started | Sep 09 04:05:41 AM UTC 24 |
| Finished | Sep 09 04:06:21 AM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859221637 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2859221637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.40761817 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 121390809 ps |
| CPU time | 2.41 seconds |
| Started | Sep 09 04:05:38 AM UTC 24 |
| Finished | Sep 09 04:05:42 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40761817 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.40761817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.2163927193 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2533110146 ps |
| CPU time | 53.69 seconds |
| Started | Sep 09 04:05:47 AM UTC 24 |
| Finished | Sep 09 04:06:42 AM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163927193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2163927193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3830581935 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1123108424 ps |
| CPU time | 27.49 seconds |
| Started | Sep 09 04:05:50 AM UTC 24 |
| Finished | Sep 09 04:06:19 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830581935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3830581935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2420410948 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 8565874194 ps |
| CPU time | 259.13 seconds |
| Started | Sep 09 04:05:49 AM UTC 24 |
| Finished | Sep 09 04:10:12 AM UTC 24 |
| Peak memory | 223116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420410948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.2420410948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3713356471 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1638441463 ps |
| CPU time | 132.4 seconds |
| Started | Sep 09 04:05:51 AM UTC 24 |
| Finished | Sep 09 04:08:06 AM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713356471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.3713356471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.878022568 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 967115479 ps |
| CPU time | 27.62 seconds |
| Started | Sep 09 04:05:44 AM UTC 24 |
| Finished | Sep 09 04:06:13 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878022568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.878022568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.1054215734 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1413603863 ps |
| CPU time | 57.95 seconds |
| Started | Sep 09 04:06:07 AM UTC 24 |
| Finished | Sep 09 04:07:07 AM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054215734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1054215734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2123520941 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 55203306678 ps |
| CPU time | 179.68 seconds |
| Started | Sep 09 04:06:08 AM UTC 24 |
| Finished | Sep 09 04:09:11 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123520941 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.2123520941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.84861090 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 1151304024 ps |
| CPU time | 28.68 seconds |
| Started | Sep 09 04:06:16 AM UTC 24 |
| Finished | Sep 09 04:06:47 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84861090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.84861090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.3057166380 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2278290154 ps |
| CPU time | 21.28 seconds |
| Started | Sep 09 04:06:14 AM UTC 24 |
| Finished | Sep 09 04:06:37 AM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057166380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3057166380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.3110736853 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 164610619 ps |
| CPU time | 13.44 seconds |
| Started | Sep 09 04:05:59 AM UTC 24 |
| Finished | Sep 09 04:06:13 AM UTC 24 |
| Peak memory | 217028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110736853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3110736853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.2460520835 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4148823216 ps |
| CPU time | 21.47 seconds |
| Started | Sep 09 04:06:02 AM UTC 24 |
| Finished | Sep 09 04:06:24 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460520835 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2460520835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.738540247 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 15087113763 ps |
| CPU time | 127.34 seconds |
| Started | Sep 09 04:06:02 AM UTC 24 |
| Finished | Sep 09 04:08:11 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738540247 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.738540247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.1579467481 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 179520726 ps |
| CPU time | 20.6 seconds |
| Started | Sep 09 04:06:01 AM UTC 24 |
| Finished | Sep 09 04:06:23 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579467481 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1579467481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.545549298 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 512784082 ps |
| CPU time | 20.01 seconds |
| Started | Sep 09 04:06:09 AM UTC 24 |
| Finished | Sep 09 04:06:30 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545549298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.545549298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.1016598722 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 222023910 ps |
| CPU time | 4.04 seconds |
| Started | Sep 09 04:05:55 AM UTC 24 |
| Finished | Sep 09 04:06:00 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016598722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1016598722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1251268255 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 5512328556 ps |
| CPU time | 30.69 seconds |
| Started | Sep 09 04:05:56 AM UTC 24 |
| Finished | Sep 09 04:06:28 AM UTC 24 |
| Peak memory | 216192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251268255 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1251268255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.4210191039 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 6917555358 ps |
| CPU time | 33.44 seconds |
| Started | Sep 09 04:05:58 AM UTC 24 |
| Finished | Sep 09 04:06:32 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210191039 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.4210191039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.97573607 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 124540068 ps |
| CPU time | 3.17 seconds |
| Started | Sep 09 04:05:56 AM UTC 24 |
| Finished | Sep 09 04:06:01 AM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97573607 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.97573607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.3060119476 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 2349965048 ps |
| CPU time | 89.11 seconds |
| Started | Sep 09 04:06:20 AM UTC 24 |
| Finished | Sep 09 04:07:51 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060119476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3060119476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2146322979 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1057169729 ps |
| CPU time | 139.34 seconds |
| Started | Sep 09 04:06:22 AM UTC 24 |
| Finished | Sep 09 04:08:44 AM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146322979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2146322979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3244361598 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 77176674 ps |
| CPU time | 5.23 seconds |
| Started | Sep 09 04:06:22 AM UTC 24 |
| Finished | Sep 09 04:06:29 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244361598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.3244361598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.482328414 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 3079499717 ps |
| CPU time | 300.84 seconds |
| Started | Sep 09 04:06:23 AM UTC 24 |
| Finished | Sep 09 04:11:28 AM UTC 24 |
| Peak memory | 223412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482328414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.482328414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.1898303018 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 4914372207 ps |
| CPU time | 29.09 seconds |
| Started | Sep 09 04:06:14 AM UTC 24 |
| Finished | Sep 09 04:06:45 AM UTC 24 |
| Peak memory | 218940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898303018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1898303018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.1327589409 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 800665540 ps |
| CPU time | 29.9 seconds |
| Started | Sep 09 04:06:33 AM UTC 24 |
| Finished | Sep 09 04:07:04 AM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327589409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1327589409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3562752218 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 33473732519 ps |
| CPU time | 171.11 seconds |
| Started | Sep 09 04:06:38 AM UTC 24 |
| Finished | Sep 09 04:09:32 AM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562752218 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.3562752218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.331121491 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 496580340 ps |
| CPU time | 18.98 seconds |
| Started | Sep 09 04:06:47 AM UTC 24 |
| Finished | Sep 09 04:07:08 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331121491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.331121491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.983495283 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 34781845 ps |
| CPU time | 4.63 seconds |
| Started | Sep 09 04:06:43 AM UTC 24 |
| Finished | Sep 09 04:06:49 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983495283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.983495283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.1688058098 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 67076678 ps |
| CPU time | 8.84 seconds |
| Started | Sep 09 04:06:29 AM UTC 24 |
| Finished | Sep 09 04:06:39 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688058098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.1688058098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.2711637994 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 40253148495 ps |
| CPU time | 88.06 seconds |
| Started | Sep 09 04:06:31 AM UTC 24 |
| Finished | Sep 09 04:08:01 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711637994 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2711637994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3205365179 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 5662425611 ps |
| CPU time | 54.68 seconds |
| Started | Sep 09 04:06:32 AM UTC 24 |
| Finished | Sep 09 04:07:28 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205365179 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3205365179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.1568535382 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 81471416 ps |
| CPU time | 16.44 seconds |
| Started | Sep 09 04:06:29 AM UTC 24 |
| Finished | Sep 09 04:06:47 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568535382 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1568535382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.16811511 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 5657528808 ps |
| CPU time | 29.11 seconds |
| Started | Sep 09 04:06:41 AM UTC 24 |
| Finished | Sep 09 04:07:12 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16811511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.16811511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.655845466 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 174333973 ps |
| CPU time | 3.42 seconds |
| Started | Sep 09 04:06:24 AM UTC 24 |
| Finished | Sep 09 04:06:29 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655845466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.655845466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1596325590 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 14776329132 ps |
| CPU time | 35.33 seconds |
| Started | Sep 09 04:06:29 AM UTC 24 |
| Finished | Sep 09 04:07:06 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596325590 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1596325590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1672731874 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 5202124027 ps |
| CPU time | 39.38 seconds |
| Started | Sep 09 04:06:29 AM UTC 24 |
| Finished | Sep 09 04:07:10 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672731874 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1672731874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3842656842 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 43448165 ps |
| CPU time | 3.14 seconds |
| Started | Sep 09 04:06:25 AM UTC 24 |
| Finished | Sep 09 04:06:29 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842656842 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3842656842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.1921902705 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1308876511 ps |
| CPU time | 154.37 seconds |
| Started | Sep 09 04:06:47 AM UTC 24 |
| Finished | Sep 09 04:09:25 AM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921902705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1921902705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3346285282 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 539208665 ps |
| CPU time | 56.95 seconds |
| Started | Sep 09 04:06:50 AM UTC 24 |
| Finished | Sep 09 04:07:48 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346285282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3346285282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.173033703 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 5022500822 ps |
| CPU time | 142.54 seconds |
| Started | Sep 09 04:06:49 AM UTC 24 |
| Finished | Sep 09 04:09:14 AM UTC 24 |
| Peak memory | 220992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173033703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.173033703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3404392257 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 369708514 ps |
| CPU time | 115.8 seconds |
| Started | Sep 09 04:06:50 AM UTC 24 |
| Finished | Sep 09 04:08:48 AM UTC 24 |
| Peak memory | 220940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404392257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.3404392257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.189939176 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 302423385 ps |
| CPU time | 10.92 seconds |
| Started | Sep 09 04:06:45 AM UTC 24 |
| Finished | Sep 09 04:06:57 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189939176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.189939176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.3524839834 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 4536458607 ps |
| CPU time | 34.5 seconds |
| Started | Sep 09 04:07:08 AM UTC 24 |
| Finished | Sep 09 04:07:44 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524839834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3524839834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1138693343 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 77477846563 ps |
| CPU time | 474.41 seconds |
| Started | Sep 09 04:07:09 AM UTC 24 |
| Finished | Sep 09 04:15:09 AM UTC 24 |
| Peak memory | 219264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138693343 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.1138693343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1285290355 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 256001301 ps |
| CPU time | 10.86 seconds |
| Started | Sep 09 04:07:18 AM UTC 24 |
| Finished | Sep 09 04:07:30 AM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285290355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1285290355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.3211089873 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 203832559 ps |
| CPU time | 9.89 seconds |
| Started | Sep 09 04:07:13 AM UTC 24 |
| Finished | Sep 09 04:07:24 AM UTC 24 |
| Peak memory | 217076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211089873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3211089873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.2468393046 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 405384255 ps |
| CPU time | 17.87 seconds |
| Started | Sep 09 04:06:58 AM UTC 24 |
| Finished | Sep 09 04:07:17 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468393046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2468393046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.78687266 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 41946340801 ps |
| CPU time | 125.66 seconds |
| Started | Sep 09 04:07:06 AM UTC 24 |
| Finished | Sep 09 04:09:14 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78687266 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.78687266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2206254010 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 17707679529 ps |
| CPU time | 122.05 seconds |
| Started | Sep 09 04:07:07 AM UTC 24 |
| Finished | Sep 09 04:09:11 AM UTC 24 |
| Peak memory | 217032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206254010 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2206254010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.3408558768 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 127328693 ps |
| CPU time | 27.31 seconds |
| Started | Sep 09 04:07:01 AM UTC 24 |
| Finished | Sep 09 04:07:30 AM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408558768 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3408558768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.611597390 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 623899390 ps |
| CPU time | 14.97 seconds |
| Started | Sep 09 04:07:11 AM UTC 24 |
| Finished | Sep 09 04:07:27 AM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611597390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.611597390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.2898846619 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 496502765 ps |
| CPU time | 5.06 seconds |
| Started | Sep 09 04:06:52 AM UTC 24 |
| Finished | Sep 09 04:06:58 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898846619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2898846619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2413610430 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 8024677789 ps |
| CPU time | 37.06 seconds |
| Started | Sep 09 04:06:57 AM UTC 24 |
| Finished | Sep 09 04:07:36 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413610430 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2413610430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.507010952 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 3323990589 ps |
| CPU time | 33.74 seconds |
| Started | Sep 09 04:06:58 AM UTC 24 |
| Finished | Sep 09 04:07:33 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507010952 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.507010952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3213299817 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 171359614 ps |
| CPU time | 3.7 seconds |
| Started | Sep 09 04:06:56 AM UTC 24 |
| Finished | Sep 09 04:07:01 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213299817 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3213299817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2449789059 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1825907101 ps |
| CPU time | 37.9 seconds |
| Started | Sep 09 04:07:23 AM UTC 24 |
| Finished | Sep 09 04:08:02 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449789059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2449789059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.905443907 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1243083684 ps |
| CPU time | 148.91 seconds |
| Started | Sep 09 04:07:26 AM UTC 24 |
| Finished | Sep 09 04:09:57 AM UTC 24 |
| Peak memory | 223244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905443907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.905443907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3161293719 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 140242682 ps |
| CPU time | 60.23 seconds |
| Started | Sep 09 04:07:25 AM UTC 24 |
| Finished | Sep 09 04:08:27 AM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161293719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.3161293719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3823183552 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4138212988 ps |
| CPU time | 204.38 seconds |
| Started | Sep 09 04:07:28 AM UTC 24 |
| Finished | Sep 09 04:10:56 AM UTC 24 |
| Peak memory | 223048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823183552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.3823183552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.177575447 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 697035287 ps |
| CPU time | 23.58 seconds |
| Started | Sep 09 04:07:17 AM UTC 24 |
| Finished | Sep 09 04:07:42 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177575447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.177575447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.2183856967 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 3562636621 ps |
| CPU time | 51.07 seconds |
| Started | Sep 09 04:07:43 AM UTC 24 |
| Finished | Sep 09 04:08:36 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183856967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2183856967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3828762737 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 110105922069 ps |
| CPU time | 427.65 seconds |
| Started | Sep 09 04:07:43 AM UTC 24 |
| Finished | Sep 09 04:14:56 AM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828762737 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.3828762737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3265218149 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 841871639 ps |
| CPU time | 12.13 seconds |
| Started | Sep 09 04:07:51 AM UTC 24 |
| Finished | Sep 09 04:08:05 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265218149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3265218149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.2028237751 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 268414823 ps |
| CPU time | 24.71 seconds |
| Started | Sep 09 04:07:49 AM UTC 24 |
| Finished | Sep 09 04:08:15 AM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028237751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2028237751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.1984836418 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 512925791 ps |
| CPU time | 14.37 seconds |
| Started | Sep 09 04:07:35 AM UTC 24 |
| Finished | Sep 09 04:07:50 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984836418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1984836418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.3019244847 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 17272764071 ps |
| CPU time | 62.88 seconds |
| Started | Sep 09 04:07:36 AM UTC 24 |
| Finished | Sep 09 04:08:40 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019244847 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3019244847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1702280727 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 32059713095 ps |
| CPU time | 282.35 seconds |
| Started | Sep 09 04:07:37 AM UTC 24 |
| Finished | Sep 09 04:12:23 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702280727 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1702280727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.398230339 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 222699251 ps |
| CPU time | 33.12 seconds |
| Started | Sep 09 04:07:35 AM UTC 24 |
| Finished | Sep 09 04:08:09 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398230339 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.398230339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.3958839184 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 211172700 ps |
| CPU time | 20.75 seconds |
| Started | Sep 09 04:07:45 AM UTC 24 |
| Finished | Sep 09 04:08:07 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958839184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3958839184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.1636275860 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 620667380 ps |
| CPU time | 5.72 seconds |
| Started | Sep 09 04:07:28 AM UTC 24 |
| Finished | Sep 09 04:07:35 AM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636275860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1636275860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3493809549 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 7513659539 ps |
| CPU time | 34.57 seconds |
| Started | Sep 09 04:07:31 AM UTC 24 |
| Finished | Sep 09 04:08:07 AM UTC 24 |
| Peak memory | 216948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493809549 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3493809549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2874963987 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2919030254 ps |
| CPU time | 35.28 seconds |
| Started | Sep 09 04:07:31 AM UTC 24 |
| Finished | Sep 09 04:08:08 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874963987 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2874963987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3621625611 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 30368525 ps |
| CPU time | 3.15 seconds |
| Started | Sep 09 04:07:29 AM UTC 24 |
| Finished | Sep 09 04:07:33 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621625611 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3621625611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.2949683539 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 651392626 ps |
| CPU time | 89.12 seconds |
| Started | Sep 09 04:07:51 AM UTC 24 |
| Finished | Sep 09 04:09:23 AM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949683539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2949683539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2353705476 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1554014173 ps |
| CPU time | 36.29 seconds |
| Started | Sep 09 04:08:01 AM UTC 24 |
| Finished | Sep 09 04:08:39 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353705476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2353705476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1908832822 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1281692577 ps |
| CPU time | 345.76 seconds |
| Started | Sep 09 04:08:00 AM UTC 24 |
| Finished | Sep 09 04:13:50 AM UTC 24 |
| Peak memory | 223244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908832822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.1908832822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.608418460 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 477446959 ps |
| CPU time | 84.09 seconds |
| Started | Sep 09 04:08:03 AM UTC 24 |
| Finished | Sep 09 04:09:30 AM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608418460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.608418460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.3335325228 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 88363210 ps |
| CPU time | 12.88 seconds |
| Started | Sep 09 04:07:51 AM UTC 24 |
| Finished | Sep 09 04:08:05 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335325228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3335325228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.777881869 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 46684949 ps |
| CPU time | 7.05 seconds |
| Started | Sep 09 04:08:13 AM UTC 24 |
| Finished | Sep 09 04:08:21 AM UTC 24 |
| Peak memory | 217028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777881869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.777881869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1805824458 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 167982758651 ps |
| CPU time | 717.63 seconds |
| Started | Sep 09 04:08:13 AM UTC 24 |
| Finished | Sep 09 04:20:19 AM UTC 24 |
| Peak memory | 222612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805824458 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.1805824458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.4073221537 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 717874799 ps |
| CPU time | 18.09 seconds |
| Started | Sep 09 04:08:19 AM UTC 24 |
| Finished | Sep 09 04:08:38 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073221537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.4073221537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.2209300768 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1752011124 ps |
| CPU time | 31.47 seconds |
| Started | Sep 09 04:08:16 AM UTC 24 |
| Finished | Sep 09 04:08:49 AM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209300768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2209300768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1372302370 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 403419620 ps |
| CPU time | 8.17 seconds |
| Started | Sep 09 04:08:09 AM UTC 24 |
| Finished | Sep 09 04:08:18 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372302370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1372302370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2295779385 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 39761070425 ps |
| CPU time | 236.41 seconds |
| Started | Sep 09 04:08:10 AM UTC 24 |
| Finished | Sep 09 04:12:10 AM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295779385 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2295779385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3627484788 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 77533620859 ps |
| CPU time | 272.58 seconds |
| Started | Sep 09 04:08:11 AM UTC 24 |
| Finished | Sep 09 04:12:48 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627484788 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3627484788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.3560720989 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 129182547 ps |
| CPU time | 16.45 seconds |
| Started | Sep 09 04:08:09 AM UTC 24 |
| Finished | Sep 09 04:08:26 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560720989 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3560720989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.2213309330 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 734292513 ps |
| CPU time | 12.04 seconds |
| Started | Sep 09 04:08:13 AM UTC 24 |
| Finished | Sep 09 04:08:26 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213309330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2213309330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.247842110 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 163502183 ps |
| CPU time | 3.61 seconds |
| Started | Sep 09 04:08:06 AM UTC 24 |
| Finished | Sep 09 04:08:10 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247842110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.247842110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.4130538031 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 5578971452 ps |
| CPU time | 43.56 seconds |
| Started | Sep 09 04:08:07 AM UTC 24 |
| Finished | Sep 09 04:08:52 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130538031 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.4130538031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3512657536 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 19098968605 ps |
| CPU time | 42.48 seconds |
| Started | Sep 09 04:08:07 AM UTC 24 |
| Finished | Sep 09 04:08:51 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512657536 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3512657536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3478309896 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 26814069 ps |
| CPU time | 3.22 seconds |
| Started | Sep 09 04:08:07 AM UTC 24 |
| Finished | Sep 09 04:08:12 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478309896 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3478309896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.874808634 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 9567842819 ps |
| CPU time | 99.74 seconds |
| Started | Sep 09 04:08:22 AM UTC 24 |
| Finished | Sep 09 04:10:04 AM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874808634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.874808634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.373018186 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 122213278 ps |
| CPU time | 20.5 seconds |
| Started | Sep 09 04:08:27 AM UTC 24 |
| Finished | Sep 09 04:08:49 AM UTC 24 |
| Peak memory | 217100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373018186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.373018186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.911200907 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 165806170 ps |
| CPU time | 100.14 seconds |
| Started | Sep 09 04:08:27 AM UTC 24 |
| Finished | Sep 09 04:10:09 AM UTC 24 |
| Peak memory | 221184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911200907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.911200907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3185033238 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 413176974 ps |
| CPU time | 92.9 seconds |
| Started | Sep 09 04:08:29 AM UTC 24 |
| Finished | Sep 09 04:10:03 AM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185033238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3185033238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.442903463 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 189959616 ps |
| CPU time | 28.88 seconds |
| Started | Sep 09 04:08:17 AM UTC 24 |
| Finished | Sep 09 04:08:48 AM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442903463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.442903463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.2612268935 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 259662608 ps |
| CPU time | 37.85 seconds |
| Started | Sep 09 04:08:41 AM UTC 24 |
| Finished | Sep 09 04:09:20 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612268935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2612268935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1991391865 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 29591886507 ps |
| CPU time | 180.26 seconds |
| Started | Sep 09 04:08:46 AM UTC 24 |
| Finished | Sep 09 04:11:49 AM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991391865 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.1991391865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1030479981 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 156163018 ps |
| CPU time | 5.29 seconds |
| Started | Sep 09 04:08:50 AM UTC 24 |
| Finished | Sep 09 04:08:56 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030479981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1030479981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.3888477687 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 579663651 ps |
| CPU time | 22.58 seconds |
| Started | Sep 09 04:08:50 AM UTC 24 |
| Finished | Sep 09 04:09:13 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888477687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3888477687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.1243482369 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 273499114 ps |
| CPU time | 18.64 seconds |
| Started | Sep 09 04:08:37 AM UTC 24 |
| Finished | Sep 09 04:08:56 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243482369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1243482369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.199935097 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 14013071568 ps |
| CPU time | 71.13 seconds |
| Started | Sep 09 04:08:40 AM UTC 24 |
| Finished | Sep 09 04:09:53 AM UTC 24 |
| Peak memory | 217220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199935097 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.199935097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.740334451 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 24020346492 ps |
| CPU time | 258.46 seconds |
| Started | Sep 09 04:08:41 AM UTC 24 |
| Finished | Sep 09 04:13:03 AM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740334451 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.740334451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.493919532 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 636444565 ps |
| CPU time | 26.33 seconds |
| Started | Sep 09 04:08:39 AM UTC 24 |
| Finished | Sep 09 04:09:07 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493919532 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.493919532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.574452173 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2077829413 ps |
| CPU time | 30.16 seconds |
| Started | Sep 09 04:08:46 AM UTC 24 |
| Finished | Sep 09 04:09:17 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574452173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.574452173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.921589915 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 130513393 ps |
| CPU time | 5.02 seconds |
| Started | Sep 09 04:08:29 AM UTC 24 |
| Finished | Sep 09 04:08:35 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921589915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.921589915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2770829919 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 6179493138 ps |
| CPU time | 48.32 seconds |
| Started | Sep 09 04:08:35 AM UTC 24 |
| Finished | Sep 09 04:09:25 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770829919 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2770829919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.980138888 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 28544159685 ps |
| CPU time | 67.35 seconds |
| Started | Sep 09 04:08:35 AM UTC 24 |
| Finished | Sep 09 04:09:44 AM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980138888 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.980138888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2167129963 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 50157236 ps |
| CPU time | 3.14 seconds |
| Started | Sep 09 04:08:30 AM UTC 24 |
| Finished | Sep 09 04:08:34 AM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167129963 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2167129963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.3375367868 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5784090916 ps |
| CPU time | 138.35 seconds |
| Started | Sep 09 04:08:51 AM UTC 24 |
| Finished | Sep 09 04:11:12 AM UTC 24 |
| Peak memory | 218944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375367868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3375367868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2010307925 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 16754117250 ps |
| CPU time | 230.48 seconds |
| Started | Sep 09 04:08:53 AM UTC 24 |
| Finished | Sep 09 04:12:47 AM UTC 24 |
| Peak memory | 223308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010307925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2010307925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3337674586 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 191523866 ps |
| CPU time | 87.48 seconds |
| Started | Sep 09 04:08:52 AM UTC 24 |
| Finished | Sep 09 04:10:21 AM UTC 24 |
| Peak memory | 220872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337674586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.3337674586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1599032379 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 7455866055 ps |
| CPU time | 367.9 seconds |
| Started | Sep 09 04:08:56 AM UTC 24 |
| Finished | Sep 09 04:15:09 AM UTC 24 |
| Peak memory | 233592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599032379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.1599032379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.117088314 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 903281957 ps |
| CPU time | 34.4 seconds |
| Started | Sep 09 04:08:50 AM UTC 24 |
| Finished | Sep 09 04:09:25 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117088314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.117088314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.596231872 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 7330157540 ps |
| CPU time | 59.98 seconds |
| Started | Sep 09 04:09:08 AM UTC 24 |
| Finished | Sep 09 04:10:09 AM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596231872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.596231872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.860703352 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 154775394166 ps |
| CPU time | 484.47 seconds |
| Started | Sep 09 04:09:08 AM UTC 24 |
| Finished | Sep 09 04:17:18 AM UTC 24 |
| Peak memory | 220436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860703352 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.860703352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3601134510 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 140842745 ps |
| CPU time | 19.86 seconds |
| Started | Sep 09 04:09:15 AM UTC 24 |
| Finished | Sep 09 04:09:36 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601134510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3601134510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.1924323945 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 140469446 ps |
| CPU time | 17.82 seconds |
| Started | Sep 09 04:09:12 AM UTC 24 |
| Finished | Sep 09 04:09:31 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924323945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1924323945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.1928925595 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1712131096 ps |
| CPU time | 24.02 seconds |
| Started | Sep 09 04:09:06 AM UTC 24 |
| Finished | Sep 09 04:09:31 AM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928925595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1928925595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.1122234998 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 30980034730 ps |
| CPU time | 170.61 seconds |
| Started | Sep 09 04:09:08 AM UTC 24 |
| Finished | Sep 09 04:12:01 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122234998 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1122234998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.4132621612 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 31613318980 ps |
| CPU time | 150.65 seconds |
| Started | Sep 09 04:09:08 AM UTC 24 |
| Finished | Sep 09 04:11:41 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132621612 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4132621612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.2263016673 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 300769759 ps |
| CPU time | 27.64 seconds |
| Started | Sep 09 04:09:06 AM UTC 24 |
| Finished | Sep 09 04:09:35 AM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263016673 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2263016673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.3414133369 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 490906357 ps |
| CPU time | 11.5 seconds |
| Started | Sep 09 04:09:12 AM UTC 24 |
| Finished | Sep 09 04:09:25 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414133369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3414133369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.1405246441 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 523512929 ps |
| CPU time | 6.09 seconds |
| Started | Sep 09 04:08:58 AM UTC 24 |
| Finished | Sep 09 04:09:05 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405246441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1405246441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3373506624 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 10008440109 ps |
| CPU time | 56.95 seconds |
| Started | Sep 09 04:08:59 AM UTC 24 |
| Finished | Sep 09 04:09:58 AM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373506624 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3373506624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2979976497 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 17005113319 ps |
| CPU time | 44.82 seconds |
| Started | Sep 09 04:09:04 AM UTC 24 |
| Finished | Sep 09 04:09:51 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979976497 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2979976497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1350869814 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 79067578 ps |
| CPU time | 3.07 seconds |
| Started | Sep 09 04:08:59 AM UTC 24 |
| Finished | Sep 09 04:09:03 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350869814 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1350869814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.757209511 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1199618031 ps |
| CPU time | 214.24 seconds |
| Started | Sep 09 04:09:15 AM UTC 24 |
| Finished | Sep 09 04:12:52 AM UTC 24 |
| Peak memory | 221184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757209511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.757209511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.711244628 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 176565769 ps |
| CPU time | 7.34 seconds |
| Started | Sep 09 04:09:20 AM UTC 24 |
| Finished | Sep 09 04:09:28 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711244628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.711244628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1545666447 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2028098560 ps |
| CPU time | 355.89 seconds |
| Started | Sep 09 04:09:21 AM UTC 24 |
| Finished | Sep 09 04:15:22 AM UTC 24 |
| Peak memory | 233596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545666447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.1545666447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.332790106 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 702900625 ps |
| CPU time | 20.05 seconds |
| Started | Sep 09 04:09:15 AM UTC 24 |
| Finished | Sep 09 04:09:36 AM UTC 24 |
| Peak memory | 219136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332790106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.332790106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.3774284714 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 354631275 ps |
| CPU time | 16.91 seconds |
| Started | Sep 09 03:54:25 AM UTC 24 |
| Finished | Sep 09 03:54:43 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774284714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3774284714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1593868926 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 135683151415 ps |
| CPU time | 740.47 seconds |
| Started | Sep 09 03:54:26 AM UTC 24 |
| Finished | Sep 09 04:06:57 AM UTC 24 |
| Peak memory | 222548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593868926 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.1593868926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.49356977 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1053248273 ps |
| CPU time | 25.31 seconds |
| Started | Sep 09 03:54:29 AM UTC 24 |
| Finished | Sep 09 03:54:56 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49356977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.49356977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.293190757 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 601332788 ps |
| CPU time | 16.41 seconds |
| Started | Sep 09 03:54:27 AM UTC 24 |
| Finished | Sep 09 03:54:45 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293190757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.293190757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.1601525026 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 184325425 ps |
| CPU time | 13.04 seconds |
| Started | Sep 09 03:54:24 AM UTC 24 |
| Finished | Sep 09 03:54:38 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601525026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1601525026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.785343564 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 55962833309 ps |
| CPU time | 197.91 seconds |
| Started | Sep 09 03:54:25 AM UTC 24 |
| Finished | Sep 09 03:57:46 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785343564 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.785343564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2746305692 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 40023496236 ps |
| CPU time | 211.39 seconds |
| Started | Sep 09 03:54:25 AM UTC 24 |
| Finished | Sep 09 03:58:00 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746305692 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2746305692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.1239242047 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 242783244 ps |
| CPU time | 13.39 seconds |
| Started | Sep 09 03:54:24 AM UTC 24 |
| Finished | Sep 09 03:54:39 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239242047 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1239242047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.3622614513 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 129305277 ps |
| CPU time | 15.8 seconds |
| Started | Sep 09 03:54:26 AM UTC 24 |
| Finished | Sep 09 03:54:43 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622614513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3622614513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.3418088956 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 65957660 ps |
| CPU time | 3.62 seconds |
| Started | Sep 09 03:54:20 AM UTC 24 |
| Finished | Sep 09 03:54:24 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418088956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3418088956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1634001608 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 16759129727 ps |
| CPU time | 60.61 seconds |
| Started | Sep 09 03:54:24 AM UTC 24 |
| Finished | Sep 09 03:55:26 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634001608 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1634001608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.67876398 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3582846468 ps |
| CPU time | 31.64 seconds |
| Started | Sep 09 03:54:24 AM UTC 24 |
| Finished | Sep 09 03:54:57 AM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67876398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.67876398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3254704377 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26292887 ps |
| CPU time | 2.99 seconds |
| Started | Sep 09 03:54:22 AM UTC 24 |
| Finished | Sep 09 03:54:26 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254704377 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3254704377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.666645006 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 10321563372 ps |
| CPU time | 229.2 seconds |
| Started | Sep 09 03:54:29 AM UTC 24 |
| Finished | Sep 09 03:58:21 AM UTC 24 |
| Peak memory | 221124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666645006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.666645006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1437696958 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2796840672 ps |
| CPU time | 82.47 seconds |
| Started | Sep 09 03:54:30 AM UTC 24 |
| Finished | Sep 09 03:55:54 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437696958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1437696958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.4239980900 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 779809757 ps |
| CPU time | 136.04 seconds |
| Started | Sep 09 03:54:32 AM UTC 24 |
| Finished | Sep 09 03:56:50 AM UTC 24 |
| Peak memory | 223116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239980900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.4239980900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.2646006190 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 303892064 ps |
| CPU time | 34.84 seconds |
| Started | Sep 09 04:09:32 AM UTC 24 |
| Finished | Sep 09 04:10:08 AM UTC 24 |
| Peak memory | 218716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646006190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.2646006190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2715649458 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 95946026143 ps |
| CPU time | 569.09 seconds |
| Started | Sep 09 04:09:32 AM UTC 24 |
| Finished | Sep 09 04:19:08 AM UTC 24 |
| Peak memory | 220500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715649458 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.2715649458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3315240819 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 659617943 ps |
| CPU time | 23.6 seconds |
| Started | Sep 09 04:09:34 AM UTC 24 |
| Finished | Sep 09 04:09:59 AM UTC 24 |
| Peak memory | 217160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315240819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3315240819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.2027446330 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 534194556 ps |
| CPU time | 19.69 seconds |
| Started | Sep 09 04:09:32 AM UTC 24 |
| Finished | Sep 09 04:09:53 AM UTC 24 |
| Peak memory | 217084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027446330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2027446330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.3847549862 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 281181440 ps |
| CPU time | 21.35 seconds |
| Started | Sep 09 04:09:27 AM UTC 24 |
| Finished | Sep 09 04:09:50 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847549862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3847549862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.300515002 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 94650012862 ps |
| CPU time | 287.35 seconds |
| Started | Sep 09 04:09:27 AM UTC 24 |
| Finished | Sep 09 04:14:19 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300515002 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.300515002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.687343794 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 35525987237 ps |
| CPU time | 274.8 seconds |
| Started | Sep 09 04:09:29 AM UTC 24 |
| Finished | Sep 09 04:14:08 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687343794 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.687343794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.1492672472 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 136238503 ps |
| CPU time | 20.25 seconds |
| Started | Sep 09 04:09:27 AM UTC 24 |
| Finished | Sep 09 04:09:49 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492672472 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1492672472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.1520375612 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 636460536 ps |
| CPU time | 11.9 seconds |
| Started | Sep 09 04:09:32 AM UTC 24 |
| Finished | Sep 09 04:09:45 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520375612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1520375612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.3168432303 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 247015316 ps |
| CPU time | 4.83 seconds |
| Started | Sep 09 04:09:24 AM UTC 24 |
| Finished | Sep 09 04:09:30 AM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168432303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3168432303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1109475892 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 9787228004 ps |
| CPU time | 36.96 seconds |
| Started | Sep 09 04:09:27 AM UTC 24 |
| Finished | Sep 09 04:10:05 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109475892 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1109475892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3101551163 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 4904294635 ps |
| CPU time | 28.54 seconds |
| Started | Sep 09 04:09:27 AM UTC 24 |
| Finished | Sep 09 04:09:57 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101551163 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3101551163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1353744111 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 51821857 ps |
| CPU time | 2.6 seconds |
| Started | Sep 09 04:09:24 AM UTC 24 |
| Finished | Sep 09 04:09:27 AM UTC 24 |
| Peak memory | 217128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353744111 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1353744111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.2861526022 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 193916662 ps |
| CPU time | 15.31 seconds |
| Started | Sep 09 04:09:34 AM UTC 24 |
| Finished | Sep 09 04:09:51 AM UTC 24 |
| Peak memory | 219008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861526022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2861526022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.4136435457 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 2862971565 ps |
| CPU time | 54.88 seconds |
| Started | Sep 09 04:09:37 AM UTC 24 |
| Finished | Sep 09 04:10:34 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136435457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.4136435457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1006414723 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 982786987 ps |
| CPU time | 377.38 seconds |
| Started | Sep 09 04:09:34 AM UTC 24 |
| Finished | Sep 09 04:15:57 AM UTC 24 |
| Peak memory | 222900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006414723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.1006414723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1380535695 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 430029501 ps |
| CPU time | 67.39 seconds |
| Started | Sep 09 04:09:37 AM UTC 24 |
| Finished | Sep 09 04:10:46 AM UTC 24 |
| Peak memory | 220848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380535695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.1380535695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.3906327868 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 180482989 ps |
| CPU time | 4.22 seconds |
| Started | Sep 09 04:09:32 AM UTC 24 |
| Finished | Sep 09 04:09:37 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906327868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3906327868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.1821314139 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3399717261 ps |
| CPU time | 49.66 seconds |
| Started | Sep 09 04:09:52 AM UTC 24 |
| Finished | Sep 09 04:10:43 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821314139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1821314139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2597871110 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 155651823079 ps |
| CPU time | 770.34 seconds |
| Started | Sep 09 04:09:52 AM UTC 24 |
| Finished | Sep 09 04:22:51 AM UTC 24 |
| Peak memory | 220500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597871110 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.2597871110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.550863563 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 723878931 ps |
| CPU time | 20.77 seconds |
| Started | Sep 09 04:09:58 AM UTC 24 |
| Finished | Sep 09 04:10:20 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550863563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.550863563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.88168977 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 208318856 ps |
| CPU time | 8.95 seconds |
| Started | Sep 09 04:09:54 AM UTC 24 |
| Finished | Sep 09 04:10:05 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88168977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.88168977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.100876574 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1430141244 ps |
| CPU time | 33.05 seconds |
| Started | Sep 09 04:09:47 AM UTC 24 |
| Finished | Sep 09 04:10:21 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100876574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.100876574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.2226206538 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 75098699509 ps |
| CPU time | 207.32 seconds |
| Started | Sep 09 04:09:50 AM UTC 24 |
| Finished | Sep 09 04:13:20 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226206538 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2226206538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1271929458 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 42295174797 ps |
| CPU time | 201.04 seconds |
| Started | Sep 09 04:09:52 AM UTC 24 |
| Finished | Sep 09 04:13:16 AM UTC 24 |
| Peak memory | 217220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271929458 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1271929458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.375368918 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 145841575 ps |
| CPU time | 14.43 seconds |
| Started | Sep 09 04:09:47 AM UTC 24 |
| Finished | Sep 09 04:10:02 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375368918 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.375368918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.2804543298 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1575114895 ps |
| CPU time | 44.34 seconds |
| Started | Sep 09 04:09:54 AM UTC 24 |
| Finished | Sep 09 04:10:41 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804543298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2804543298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.969518424 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 147458016 ps |
| CPU time | 4.85 seconds |
| Started | Sep 09 04:09:37 AM UTC 24 |
| Finished | Sep 09 04:09:43 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969518424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.969518424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1875151625 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 18741301610 ps |
| CPU time | 61.76 seconds |
| Started | Sep 09 04:09:45 AM UTC 24 |
| Finished | Sep 09 04:10:49 AM UTC 24 |
| Peak memory | 217204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875151625 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1875151625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.688295763 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 4827519691 ps |
| CPU time | 29.33 seconds |
| Started | Sep 09 04:09:45 AM UTC 24 |
| Finished | Sep 09 04:10:16 AM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688295763 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.688295763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3872229026 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 63503292 ps |
| CPU time | 3.38 seconds |
| Started | Sep 09 04:09:38 AM UTC 24 |
| Finished | Sep 09 04:09:44 AM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872229026 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3872229026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.1969915273 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 7010726402 ps |
| CPU time | 213.14 seconds |
| Started | Sep 09 04:09:59 AM UTC 24 |
| Finished | Sep 09 04:13:36 AM UTC 24 |
| Peak memory | 220928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969915273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1969915273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2571697480 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 7786792847 ps |
| CPU time | 158.93 seconds |
| Started | Sep 09 04:10:01 AM UTC 24 |
| Finished | Sep 09 04:12:42 AM UTC 24 |
| Peak memory | 223048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571697480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2571697480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1052562609 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 17605856508 ps |
| CPU time | 745.04 seconds |
| Started | Sep 09 04:09:59 AM UTC 24 |
| Finished | Sep 09 04:22:33 AM UTC 24 |
| Peak memory | 224600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052562609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.1052562609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3327139954 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 1323106946 ps |
| CPU time | 306.63 seconds |
| Started | Sep 09 04:10:03 AM UTC 24 |
| Finished | Sep 09 04:15:14 AM UTC 24 |
| Peak memory | 233528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327139954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.3327139954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.3742834632 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1149283473 ps |
| CPU time | 9.61 seconds |
| Started | Sep 09 04:09:54 AM UTC 24 |
| Finished | Sep 09 04:10:05 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742834632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3742834632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.2000501411 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1222974379 ps |
| CPU time | 37.15 seconds |
| Started | Sep 09 04:10:11 AM UTC 24 |
| Finished | Sep 09 04:10:50 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000501411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2000501411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.749303710 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 145224340191 ps |
| CPU time | 729.01 seconds |
| Started | Sep 09 04:10:11 AM UTC 24 |
| Finished | Sep 09 04:22:29 AM UTC 24 |
| Peak memory | 220500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749303710 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.749303710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2777348768 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 2676621949 ps |
| CPU time | 20.18 seconds |
| Started | Sep 09 04:10:17 AM UTC 24 |
| Finished | Sep 09 04:10:39 AM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777348768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2777348768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.491430510 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 434971958 ps |
| CPU time | 11.64 seconds |
| Started | Sep 09 04:10:11 AM UTC 24 |
| Finished | Sep 09 04:10:24 AM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491430510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.491430510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.2372699268 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 344713431 ps |
| CPU time | 32.01 seconds |
| Started | Sep 09 04:10:07 AM UTC 24 |
| Finished | Sep 09 04:10:40 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372699268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2372699268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.4034701510 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 41683364635 ps |
| CPU time | 183.4 seconds |
| Started | Sep 09 04:10:09 AM UTC 24 |
| Finished | Sep 09 04:13:15 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034701510 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.4034701510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1374848673 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 6112813172 ps |
| CPU time | 67.17 seconds |
| Started | Sep 09 04:10:11 AM UTC 24 |
| Finished | Sep 09 04:11:20 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374848673 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1374848673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.59093709 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 116265648 ps |
| CPU time | 16.48 seconds |
| Started | Sep 09 04:10:09 AM UTC 24 |
| Finished | Sep 09 04:10:26 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59093709 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.59093709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.1697811969 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2276690668 ps |
| CPU time | 34.63 seconds |
| Started | Sep 09 04:10:11 AM UTC 24 |
| Finished | Sep 09 04:10:47 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697811969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1697811969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.3218565602 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 103244168 ps |
| CPU time | 3.25 seconds |
| Started | Sep 09 04:10:05 AM UTC 24 |
| Finished | Sep 09 04:10:09 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218565602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3218565602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2164949512 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 22538768933 ps |
| CPU time | 44.66 seconds |
| Started | Sep 09 04:10:07 AM UTC 24 |
| Finished | Sep 09 04:10:53 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164949512 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2164949512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1377605498 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3668368415 ps |
| CPU time | 41.28 seconds |
| Started | Sep 09 04:10:07 AM UTC 24 |
| Finished | Sep 09 04:10:50 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377605498 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1377605498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2463895848 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 90035212 ps |
| CPU time | 3.36 seconds |
| Started | Sep 09 04:10:05 AM UTC 24 |
| Finished | Sep 09 04:10:09 AM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463895848 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2463895848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.1728211894 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 3237687224 ps |
| CPU time | 205.51 seconds |
| Started | Sep 09 04:10:18 AM UTC 24 |
| Finished | Sep 09 04:13:47 AM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728211894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1728211894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3767762205 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 5420133961 ps |
| CPU time | 103.37 seconds |
| Started | Sep 09 04:10:22 AM UTC 24 |
| Finished | Sep 09 04:12:08 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767762205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3767762205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2072064996 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 5184867672 ps |
| CPU time | 380.54 seconds |
| Started | Sep 09 04:10:21 AM UTC 24 |
| Finished | Sep 09 04:16:47 AM UTC 24 |
| Peak memory | 233920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072064996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.2072064996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2980680604 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 695475085 ps |
| CPU time | 93.71 seconds |
| Started | Sep 09 04:10:22 AM UTC 24 |
| Finished | Sep 09 04:11:58 AM UTC 24 |
| Peak memory | 222920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980680604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.2980680604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.3067039051 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 141198291 ps |
| CPU time | 14.92 seconds |
| Started | Sep 09 04:10:13 AM UTC 24 |
| Finished | Sep 09 04:10:29 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067039051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3067039051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.1238309737 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 299989618 ps |
| CPU time | 21.04 seconds |
| Started | Sep 09 04:10:42 AM UTC 24 |
| Finished | Sep 09 04:11:04 AM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238309737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1238309737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.439168524 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 22564969855 ps |
| CPU time | 199.02 seconds |
| Started | Sep 09 04:10:42 AM UTC 24 |
| Finished | Sep 09 04:14:04 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439168524 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.439168524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2180567262 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 750945449 ps |
| CPU time | 13.59 seconds |
| Started | Sep 09 04:10:48 AM UTC 24 |
| Finished | Sep 09 04:11:03 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180567262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2180567262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.478298428 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 1785449588 ps |
| CPU time | 29.46 seconds |
| Started | Sep 09 04:10:44 AM UTC 24 |
| Finished | Sep 09 04:11:15 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478298428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.478298428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.1636980633 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 952384613 ps |
| CPU time | 28.16 seconds |
| Started | Sep 09 04:10:31 AM UTC 24 |
| Finished | Sep 09 04:11:01 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636980633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1636980633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.317014112 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4389183757 ps |
| CPU time | 23.05 seconds |
| Started | Sep 09 04:10:35 AM UTC 24 |
| Finished | Sep 09 04:10:59 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317014112 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.317014112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3033910646 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 84053595097 ps |
| CPU time | 247.04 seconds |
| Started | Sep 09 04:10:40 AM UTC 24 |
| Finished | Sep 09 04:14:51 AM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033910646 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3033910646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.3731387406 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 62636981 ps |
| CPU time | 11.22 seconds |
| Started | Sep 09 04:10:31 AM UTC 24 |
| Finished | Sep 09 04:10:44 AM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731387406 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3731387406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.4267585252 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 2178531532 ps |
| CPU time | 31.71 seconds |
| Started | Sep 09 04:10:44 AM UTC 24 |
| Finished | Sep 09 04:11:17 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267585252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.4267585252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.2529136320 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 27745141 ps |
| CPU time | 3.43 seconds |
| Started | Sep 09 04:10:25 AM UTC 24 |
| Finished | Sep 09 04:10:29 AM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529136320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2529136320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2906363887 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 11733067385 ps |
| CPU time | 51.43 seconds |
| Started | Sep 09 04:10:27 AM UTC 24 |
| Finished | Sep 09 04:11:20 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906363887 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2906363887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2715711750 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3669029450 ps |
| CPU time | 32.95 seconds |
| Started | Sep 09 04:10:30 AM UTC 24 |
| Finished | Sep 09 04:11:04 AM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715711750 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2715711750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1878997009 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 97149617 ps |
| CPU time | 3.28 seconds |
| Started | Sep 09 04:10:26 AM UTC 24 |
| Finished | Sep 09 04:10:30 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878997009 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1878997009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.1655471850 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1209942887 ps |
| CPU time | 23.62 seconds |
| Started | Sep 09 04:10:49 AM UTC 24 |
| Finished | Sep 09 04:11:14 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655471850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1655471850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2174561768 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 648382050 ps |
| CPU time | 28.45 seconds |
| Started | Sep 09 04:10:51 AM UTC 24 |
| Finished | Sep 09 04:11:21 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174561768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2174561768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.930992460 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 1880504426 ps |
| CPU time | 392.24 seconds |
| Started | Sep 09 04:10:51 AM UTC 24 |
| Finished | Sep 09 04:17:28 AM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930992460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.930992460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.93915503 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 157244691 ps |
| CPU time | 46.92 seconds |
| Started | Sep 09 04:10:54 AM UTC 24 |
| Finished | Sep 09 04:11:42 AM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93915503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.93915503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.4072664326 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 211983936 ps |
| CPU time | 6.62 seconds |
| Started | Sep 09 04:10:48 AM UTC 24 |
| Finished | Sep 09 04:10:56 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072664326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.4072664326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.29886243 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 304393911 ps |
| CPU time | 31.55 seconds |
| Started | Sep 09 04:11:05 AM UTC 24 |
| Finished | Sep 09 04:11:38 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29886243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.29886243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3234520666 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 24427768731 ps |
| CPU time | 93.25 seconds |
| Started | Sep 09 04:11:05 AM UTC 24 |
| Finished | Sep 09 04:12:40 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234520666 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.3234520666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2140989837 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 150273433 ps |
| CPU time | 19.65 seconds |
| Started | Sep 09 04:11:19 AM UTC 24 |
| Finished | Sep 09 04:11:40 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140989837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2140989837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2062927646 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1124636618 ps |
| CPU time | 35.65 seconds |
| Started | Sep 09 04:11:15 AM UTC 24 |
| Finished | Sep 09 04:11:52 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062927646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2062927646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.4134946555 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2951371340 ps |
| CPU time | 44.46 seconds |
| Started | Sep 09 04:11:02 AM UTC 24 |
| Finished | Sep 09 04:11:48 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134946555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.4134946555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2160678580 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 95961199426 ps |
| CPU time | 220.46 seconds |
| Started | Sep 09 04:11:03 AM UTC 24 |
| Finished | Sep 09 04:14:47 AM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160678580 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2160678580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.123062686 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 23385856134 ps |
| CPU time | 178.99 seconds |
| Started | Sep 09 04:11:05 AM UTC 24 |
| Finished | Sep 09 04:14:07 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123062686 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.123062686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.3348463151 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 595572769 ps |
| CPU time | 32.34 seconds |
| Started | Sep 09 04:11:03 AM UTC 24 |
| Finished | Sep 09 04:11:37 AM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348463151 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3348463151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3274983982 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 3289370440 ps |
| CPU time | 33.22 seconds |
| Started | Sep 09 04:11:13 AM UTC 24 |
| Finished | Sep 09 04:11:47 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274983982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3274983982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.1682134395 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 111429037 ps |
| CPU time | 3.12 seconds |
| Started | Sep 09 04:10:58 AM UTC 24 |
| Finished | Sep 09 04:11:02 AM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682134395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1682134395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1274588858 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 37004758300 ps |
| CPU time | 48.27 seconds |
| Started | Sep 09 04:10:58 AM UTC 24 |
| Finished | Sep 09 04:11:48 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274588858 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1274588858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.44308429 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 3759524447 ps |
| CPU time | 29.13 seconds |
| Started | Sep 09 04:11:00 AM UTC 24 |
| Finished | Sep 09 04:11:31 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44308429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.44308429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1873402488 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 43538018 ps |
| CPU time | 3.63 seconds |
| Started | Sep 09 04:10:58 AM UTC 24 |
| Finished | Sep 09 04:11:03 AM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873402488 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1873402488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.3655890741 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 4319872962 ps |
| CPU time | 114.56 seconds |
| Started | Sep 09 04:11:21 AM UTC 24 |
| Finished | Sep 09 04:13:18 AM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655890741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3655890741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1379078014 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 10246056882 ps |
| CPU time | 128.39 seconds |
| Started | Sep 09 04:11:22 AM UTC 24 |
| Finished | Sep 09 04:13:33 AM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379078014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1379078014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2052175514 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 212522057 ps |
| CPU time | 97.29 seconds |
| Started | Sep 09 04:11:21 AM UTC 24 |
| Finished | Sep 09 04:13:01 AM UTC 24 |
| Peak memory | 220940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052175514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.2052175514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.4169237876 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 12336994472 ps |
| CPU time | 421.14 seconds |
| Started | Sep 09 04:11:29 AM UTC 24 |
| Finished | Sep 09 04:18:37 AM UTC 24 |
| Peak memory | 233984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169237876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.4169237876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.4235337832 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 121110308 ps |
| CPU time | 22.72 seconds |
| Started | Sep 09 04:11:16 AM UTC 24 |
| Finished | Sep 09 04:11:40 AM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235337832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.4235337832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.260778529 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 502561242 ps |
| CPU time | 41.62 seconds |
| Started | Sep 09 04:11:42 AM UTC 24 |
| Finished | Sep 09 04:12:25 AM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260778529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.260778529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1869988810 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 73048496317 ps |
| CPU time | 599.21 seconds |
| Started | Sep 09 04:11:44 AM UTC 24 |
| Finished | Sep 09 04:21:50 AM UTC 24 |
| Peak memory | 222612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869988810 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.1869988810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1715894663 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 68025426 ps |
| CPU time | 4 seconds |
| Started | Sep 09 04:11:49 AM UTC 24 |
| Finished | Sep 09 04:11:54 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715894663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1715894663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3786161530 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 2671962512 ps |
| CPU time | 26.83 seconds |
| Started | Sep 09 04:11:49 AM UTC 24 |
| Finished | Sep 09 04:12:17 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786161530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3786161530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1241474748 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 209193425 ps |
| CPU time | 19.92 seconds |
| Started | Sep 09 04:11:38 AM UTC 24 |
| Finished | Sep 09 04:11:59 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241474748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1241474748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2942053775 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 24649835356 ps |
| CPU time | 151.49 seconds |
| Started | Sep 09 04:11:42 AM UTC 24 |
| Finished | Sep 09 04:14:16 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942053775 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2942053775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1585094628 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 12799174478 ps |
| CPU time | 143.41 seconds |
| Started | Sep 09 04:11:42 AM UTC 24 |
| Finished | Sep 09 04:14:08 AM UTC 24 |
| Peak memory | 216628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585094628 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1585094628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.382389741 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 363624492 ps |
| CPU time | 22.79 seconds |
| Started | Sep 09 04:11:39 AM UTC 24 |
| Finished | Sep 09 04:12:03 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382389741 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.382389741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1175895193 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 34128815 ps |
| CPU time | 3.21 seconds |
| Started | Sep 09 04:11:44 AM UTC 24 |
| Finished | Sep 09 04:11:48 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175895193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1175895193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.4206101405 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 55856598 ps |
| CPU time | 3 seconds |
| Started | Sep 09 04:11:30 AM UTC 24 |
| Finished | Sep 09 04:11:34 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206101405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4206101405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.678064414 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 4750050799 ps |
| CPU time | 36.75 seconds |
| Started | Sep 09 04:11:35 AM UTC 24 |
| Finished | Sep 09 04:12:13 AM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678064414 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.678064414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.4197540230 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 4540605287 ps |
| CPU time | 34.55 seconds |
| Started | Sep 09 04:11:36 AM UTC 24 |
| Finished | Sep 09 04:12:12 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197540230 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.4197540230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1077435509 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 85662988 ps |
| CPU time | 2.96 seconds |
| Started | Sep 09 04:11:32 AM UTC 24 |
| Finished | Sep 09 04:11:36 AM UTC 24 |
| Peak memory | 216804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077435509 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1077435509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3129757242 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1202803261 ps |
| CPU time | 93.42 seconds |
| Started | Sep 09 04:11:49 AM UTC 24 |
| Finished | Sep 09 04:13:25 AM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129757242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3129757242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3736401387 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2089121727 ps |
| CPU time | 85.48 seconds |
| Started | Sep 09 04:11:53 AM UTC 24 |
| Finished | Sep 09 04:13:20 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736401387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3736401387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1387153617 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 4834603504 ps |
| CPU time | 252.6 seconds |
| Started | Sep 09 04:11:51 AM UTC 24 |
| Finished | Sep 09 04:16:07 AM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387153617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.1387153617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.267417073 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 180811518 ps |
| CPU time | 105.72 seconds |
| Started | Sep 09 04:11:56 AM UTC 24 |
| Finished | Sep 09 04:13:44 AM UTC 24 |
| Peak memory | 222976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267417073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.267417073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.4131696138 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 73758646 ps |
| CPU time | 14.45 seconds |
| Started | Sep 09 04:11:49 AM UTC 24 |
| Finished | Sep 09 04:12:05 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131696138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.4131696138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.1753177176 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1176142311 ps |
| CPU time | 43.11 seconds |
| Started | Sep 09 04:12:07 AM UTC 24 |
| Finished | Sep 09 04:12:52 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753177176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1753177176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3516284787 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 118966697658 ps |
| CPU time | 378.76 seconds |
| Started | Sep 09 04:12:10 AM UTC 24 |
| Finished | Sep 09 04:18:33 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516284787 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.3516284787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3689747271 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 64220334 ps |
| CPU time | 3.36 seconds |
| Started | Sep 09 04:12:18 AM UTC 24 |
| Finished | Sep 09 04:12:23 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689747271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3689747271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1270651642 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 139145574 ps |
| CPU time | 6.06 seconds |
| Started | Sep 09 04:12:13 AM UTC 24 |
| Finished | Sep 09 04:12:20 AM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270651642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1270651642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.643446400 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 530942980 ps |
| CPU time | 31.78 seconds |
| Started | Sep 09 04:12:02 AM UTC 24 |
| Finished | Sep 09 04:12:35 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643446400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.643446400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.2732606283 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 3589951577 ps |
| CPU time | 25.83 seconds |
| Started | Sep 09 04:12:05 AM UTC 24 |
| Finished | Sep 09 04:12:32 AM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732606283 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2732606283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2359258904 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 35273115272 ps |
| CPU time | 255.49 seconds |
| Started | Sep 09 04:12:07 AM UTC 24 |
| Finished | Sep 09 04:16:26 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359258904 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2359258904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.1325967421 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 128880631 ps |
| CPU time | 12.92 seconds |
| Started | Sep 09 04:12:04 AM UTC 24 |
| Finished | Sep 09 04:12:18 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325967421 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1325967421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.2409875912 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 72058419 ps |
| CPU time | 6.82 seconds |
| Started | Sep 09 04:12:11 AM UTC 24 |
| Finished | Sep 09 04:12:19 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409875912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2409875912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.2106592360 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 46322178 ps |
| CPU time | 3.62 seconds |
| Started | Sep 09 04:11:59 AM UTC 24 |
| Finished | Sep 09 04:12:04 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106592360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2106592360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3627083239 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 7652740586 ps |
| CPU time | 31.03 seconds |
| Started | Sep 09 04:12:02 AM UTC 24 |
| Finished | Sep 09 04:12:34 AM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627083239 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3627083239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3209720257 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 3833176068 ps |
| CPU time | 34.76 seconds |
| Started | Sep 09 04:12:02 AM UTC 24 |
| Finished | Sep 09 04:12:38 AM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209720257 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3209720257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1125694248 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 41562306 ps |
| CPU time | 2.88 seconds |
| Started | Sep 09 04:12:02 AM UTC 24 |
| Finished | Sep 09 04:12:05 AM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125694248 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1125694248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.589546828 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 4941719048 ps |
| CPU time | 154.69 seconds |
| Started | Sep 09 04:12:20 AM UTC 24 |
| Finished | Sep 09 04:14:57 AM UTC 24 |
| Peak memory | 220928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589546828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.589546828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1701711450 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 1055180798 ps |
| CPU time | 146.43 seconds |
| Started | Sep 09 04:12:22 AM UTC 24 |
| Finished | Sep 09 04:14:52 AM UTC 24 |
| Peak memory | 218968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701711450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1701711450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.749071712 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1081236256 ps |
| CPU time | 225.36 seconds |
| Started | Sep 09 04:12:20 AM UTC 24 |
| Finished | Sep 09 04:16:09 AM UTC 24 |
| Peak memory | 233588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749071712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.749071712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2400978926 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 469104412 ps |
| CPU time | 135.22 seconds |
| Started | Sep 09 04:12:22 AM UTC 24 |
| Finished | Sep 09 04:14:40 AM UTC 24 |
| Peak memory | 222852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400978926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.2400978926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.1684208427 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 95667623 ps |
| CPU time | 5.01 seconds |
| Started | Sep 09 04:12:15 AM UTC 24 |
| Finished | Sep 09 04:12:21 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684208427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1684208427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.832735125 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 497808368 ps |
| CPU time | 48.05 seconds |
| Started | Sep 09 04:12:39 AM UTC 24 |
| Finished | Sep 09 04:13:29 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832735125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.832735125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.135000684 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 58879896027 ps |
| CPU time | 486.12 seconds |
| Started | Sep 09 04:12:42 AM UTC 24 |
| Finished | Sep 09 04:20:54 AM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135000684 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.135000684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3538490635 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 24430994 ps |
| CPU time | 3.52 seconds |
| Started | Sep 09 04:12:48 AM UTC 24 |
| Finished | Sep 09 04:12:53 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538490635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3538490635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.644950286 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 92653340 ps |
| CPU time | 12.8 seconds |
| Started | Sep 09 04:12:44 AM UTC 24 |
| Finished | Sep 09 04:12:58 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644950286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.644950286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.86897046 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 199186721 ps |
| CPU time | 24.29 seconds |
| Started | Sep 09 04:12:30 AM UTC 24 |
| Finished | Sep 09 04:12:56 AM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86897046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.86897046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.2146910139 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 61708735842 ps |
| CPU time | 111.01 seconds |
| Started | Sep 09 04:12:36 AM UTC 24 |
| Finished | Sep 09 04:14:29 AM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146910139 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2146910139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2702946357 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 38230943219 ps |
| CPU time | 148.33 seconds |
| Started | Sep 09 04:12:36 AM UTC 24 |
| Finished | Sep 09 04:15:07 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702946357 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2702946357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2770709959 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 192267629 ps |
| CPU time | 34.01 seconds |
| Started | Sep 09 04:12:34 AM UTC 24 |
| Finished | Sep 09 04:13:09 AM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770709959 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2770709959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.621422895 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 942736417 ps |
| CPU time | 16.2 seconds |
| Started | Sep 09 04:12:43 AM UTC 24 |
| Finished | Sep 09 04:13:00 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621422895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.621422895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.3670027439 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 160768517 ps |
| CPU time | 4.3 seconds |
| Started | Sep 09 04:12:24 AM UTC 24 |
| Finished | Sep 09 04:12:29 AM UTC 24 |
| Peak memory | 217076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670027439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3670027439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.4050618498 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 27612995301 ps |
| CPU time | 67.76 seconds |
| Started | Sep 09 04:12:26 AM UTC 24 |
| Finished | Sep 09 04:13:36 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050618498 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.4050618498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3141780177 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 2931093031 ps |
| CPU time | 27.4 seconds |
| Started | Sep 09 04:12:30 AM UTC 24 |
| Finished | Sep 09 04:12:59 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141780177 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3141780177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.617977237 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 37633351 ps |
| CPU time | 3.09 seconds |
| Started | Sep 09 04:12:25 AM UTC 24 |
| Finished | Sep 09 04:12:29 AM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617977237 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.617977237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.1490238624 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 4390610482 ps |
| CPU time | 148.53 seconds |
| Started | Sep 09 04:12:50 AM UTC 24 |
| Finished | Sep 09 04:15:22 AM UTC 24 |
| Peak memory | 221252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490238624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1490238624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1681412849 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 391043577 ps |
| CPU time | 40.66 seconds |
| Started | Sep 09 04:12:55 AM UTC 24 |
| Finished | Sep 09 04:13:37 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681412849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1681412849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.649883670 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4629764556 ps |
| CPU time | 214.86 seconds |
| Started | Sep 09 04:12:53 AM UTC 24 |
| Finished | Sep 09 04:16:31 AM UTC 24 |
| Peak memory | 220992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649883670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.649883670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.117242890 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 105616950 ps |
| CPU time | 28.13 seconds |
| Started | Sep 09 04:12:55 AM UTC 24 |
| Finished | Sep 09 04:13:24 AM UTC 24 |
| Peak memory | 218816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117242890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.117242890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.207480850 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 669062913 ps |
| CPU time | 28.52 seconds |
| Started | Sep 09 04:12:46 AM UTC 24 |
| Finished | Sep 09 04:13:16 AM UTC 24 |
| Peak memory | 219132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207480850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.207480850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2406367541 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1469092196 ps |
| CPU time | 51.76 seconds |
| Started | Sep 09 04:13:11 AM UTC 24 |
| Finished | Sep 09 04:14:05 AM UTC 24 |
| Peak memory | 219148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406367541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2406367541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1670994315 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 50167701115 ps |
| CPU time | 438.41 seconds |
| Started | Sep 09 04:13:17 AM UTC 24 |
| Finished | Sep 09 04:20:41 AM UTC 24 |
| Peak memory | 218948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670994315 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.1670994315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2715279864 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1425386144 ps |
| CPU time | 27.19 seconds |
| Started | Sep 09 04:13:21 AM UTC 24 |
| Finished | Sep 09 04:13:50 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715279864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2715279864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.344961237 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2001945941 ps |
| CPU time | 25.96 seconds |
| Started | Sep 09 04:13:18 AM UTC 24 |
| Finished | Sep 09 04:13:46 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344961237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.344961237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2703741173 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1321559013 ps |
| CPU time | 30.5 seconds |
| Started | Sep 09 04:13:03 AM UTC 24 |
| Finished | Sep 09 04:13:35 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703741173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2703741173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.3329657999 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 80158835887 ps |
| CPU time | 192.86 seconds |
| Started | Sep 09 04:13:05 AM UTC 24 |
| Finished | Sep 09 04:16:20 AM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329657999 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3329657999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3875134953 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 42314311174 ps |
| CPU time | 159.36 seconds |
| Started | Sep 09 04:13:06 AM UTC 24 |
| Finished | Sep 09 04:15:48 AM UTC 24 |
| Peak memory | 217156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875134953 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3875134953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.3894508690 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 175727109 ps |
| CPU time | 22.77 seconds |
| Started | Sep 09 04:13:05 AM UTC 24 |
| Finished | Sep 09 04:13:29 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894508690 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3894508690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.2021478550 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 191772018 ps |
| CPU time | 13.24 seconds |
| Started | Sep 09 04:13:17 AM UTC 24 |
| Finished | Sep 09 04:13:31 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021478550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2021478550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1692071831 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 194484610 ps |
| CPU time | 4.97 seconds |
| Started | Sep 09 04:12:57 AM UTC 24 |
| Finished | Sep 09 04:13:04 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692071831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1692071831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.368734351 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 4130986809 ps |
| CPU time | 44.22 seconds |
| Started | Sep 09 04:13:01 AM UTC 24 |
| Finished | Sep 09 04:13:47 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368734351 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.368734351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1397907962 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 11890315001 ps |
| CPU time | 43.71 seconds |
| Started | Sep 09 04:13:02 AM UTC 24 |
| Finished | Sep 09 04:13:47 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397907962 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1397907962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2051694172 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 46615251 ps |
| CPU time | 3.68 seconds |
| Started | Sep 09 04:13:00 AM UTC 24 |
| Finished | Sep 09 04:13:05 AM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051694172 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2051694172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.2527780417 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 631648704 ps |
| CPU time | 55.47 seconds |
| Started | Sep 09 04:13:22 AM UTC 24 |
| Finished | Sep 09 04:14:19 AM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527780417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2527780417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2213458576 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 10500385394 ps |
| CPU time | 194.85 seconds |
| Started | Sep 09 04:13:27 AM UTC 24 |
| Finished | Sep 09 04:16:45 AM UTC 24 |
| Peak memory | 222980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213458576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2213458576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2550120658 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 4005422565 ps |
| CPU time | 192.49 seconds |
| Started | Sep 09 04:13:25 AM UTC 24 |
| Finished | Sep 09 04:16:41 AM UTC 24 |
| Peak memory | 221000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550120658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.2550120658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.197100363 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 962882933 ps |
| CPU time | 50.96 seconds |
| Started | Sep 09 04:13:31 AM UTC 24 |
| Finished | Sep 09 04:14:23 AM UTC 24 |
| Peak memory | 220928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197100363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.197100363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.106332560 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 183073059 ps |
| CPU time | 15.62 seconds |
| Started | Sep 09 04:13:20 AM UTC 24 |
| Finished | Sep 09 04:13:37 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106332560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.106332560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.613328543 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 4353145685 ps |
| CPU time | 39 seconds |
| Started | Sep 09 04:13:41 AM UTC 24 |
| Finished | Sep 09 04:14:21 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613328543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.613328543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2032737204 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 306797896181 ps |
| CPU time | 797.39 seconds |
| Started | Sep 09 04:13:41 AM UTC 24 |
| Finished | Sep 09 04:27:07 AM UTC 24 |
| Peak memory | 222548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032737204 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.2032737204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3634155930 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 92797864 ps |
| CPU time | 4.35 seconds |
| Started | Sep 09 04:13:49 AM UTC 24 |
| Finished | Sep 09 04:13:55 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634155930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3634155930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.2235735516 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 743380795 ps |
| CPU time | 21.1 seconds |
| Started | Sep 09 04:13:45 AM UTC 24 |
| Finished | Sep 09 04:14:08 AM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235735516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2235735516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.1289479236 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1317372293 ps |
| CPU time | 39.2 seconds |
| Started | Sep 09 04:13:38 AM UTC 24 |
| Finished | Sep 09 04:14:19 AM UTC 24 |
| Peak memory | 219140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289479236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1289479236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.4240042700 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 23782377138 ps |
| CPU time | 174.68 seconds |
| Started | Sep 09 04:13:40 AM UTC 24 |
| Finished | Sep 09 04:16:38 AM UTC 24 |
| Peak memory | 216900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240042700 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.4240042700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.627695555 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 23933518574 ps |
| CPU time | 237.96 seconds |
| Started | Sep 09 04:13:40 AM UTC 24 |
| Finished | Sep 09 04:17:42 AM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627695555 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.627695555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2565675271 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 150524627 ps |
| CPU time | 13.38 seconds |
| Started | Sep 09 04:13:38 AM UTC 24 |
| Finished | Sep 09 04:13:53 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565675271 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2565675271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1458190901 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 688290248 ps |
| CPU time | 15.56 seconds |
| Started | Sep 09 04:13:41 AM UTC 24 |
| Finished | Sep 09 04:13:57 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458190901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1458190901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.744311125 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 34572935 ps |
| CPU time | 3.22 seconds |
| Started | Sep 09 04:13:31 AM UTC 24 |
| Finished | Sep 09 04:13:35 AM UTC 24 |
| Peak memory | 217132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744311125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.744311125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.4016863164 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 6977342343 ps |
| CPU time | 39.24 seconds |
| Started | Sep 09 04:13:35 AM UTC 24 |
| Finished | Sep 09 04:14:15 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016863164 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.4016863164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1226691040 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 10753626576 ps |
| CPU time | 32.1 seconds |
| Started | Sep 09 04:13:38 AM UTC 24 |
| Finished | Sep 09 04:14:11 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226691040 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1226691040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.133292408 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 31783940 ps |
| CPU time | 2.78 seconds |
| Started | Sep 09 04:13:33 AM UTC 24 |
| Finished | Sep 09 04:13:37 AM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133292408 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.133292408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2876936433 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 9016398024 ps |
| CPU time | 244.36 seconds |
| Started | Sep 09 04:13:49 AM UTC 24 |
| Finished | Sep 09 04:17:57 AM UTC 24 |
| Peak memory | 223040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876936433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2876936433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2991640713 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 13199576401 ps |
| CPU time | 72.75 seconds |
| Started | Sep 09 04:13:51 AM UTC 24 |
| Finished | Sep 09 04:15:06 AM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991640713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2991640713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1959919264 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 173074364 ps |
| CPU time | 103.24 seconds |
| Started | Sep 09 04:13:49 AM UTC 24 |
| Finished | Sep 09 04:15:35 AM UTC 24 |
| Peak memory | 220872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959919264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.1959919264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3242401032 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 4852073105 ps |
| CPU time | 514.12 seconds |
| Started | Sep 09 04:13:52 AM UTC 24 |
| Finished | Sep 09 04:22:32 AM UTC 24 |
| Peak memory | 240224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242401032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.3242401032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.1987496658 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1279068908 ps |
| CPU time | 20.36 seconds |
| Started | Sep 09 04:13:47 AM UTC 24 |
| Finished | Sep 09 04:14:08 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987496658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1987496658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.786730821 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 54299963015 ps |
| CPU time | 530.32 seconds |
| Started | Sep 09 03:54:39 AM UTC 24 |
| Finished | Sep 09 04:03:36 AM UTC 24 |
| Peak memory | 221380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786730821 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.786730821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.3011837304 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 36892112 ps |
| CPU time | 6.73 seconds |
| Started | Sep 09 03:54:43 AM UTC 24 |
| Finished | Sep 09 03:54:51 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011837304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.3011837304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.2937804662 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1223098149 ps |
| CPU time | 17.94 seconds |
| Started | Sep 09 03:54:42 AM UTC 24 |
| Finished | Sep 09 03:55:01 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937804662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2937804662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.965006993 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 957884156 ps |
| CPU time | 34.94 seconds |
| Started | Sep 09 03:54:34 AM UTC 24 |
| Finished | Sep 09 03:55:10 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965006993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.965006993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.3608341917 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 18468626786 ps |
| CPU time | 86.16 seconds |
| Started | Sep 09 03:54:37 AM UTC 24 |
| Finished | Sep 09 03:56:05 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608341917 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3608341917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.4289588732 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 15236711139 ps |
| CPU time | 144.32 seconds |
| Started | Sep 09 03:54:38 AM UTC 24 |
| Finished | Sep 09 03:57:05 AM UTC 24 |
| Peak memory | 217216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289588732 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4289588732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.4192269638 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 207527196 ps |
| CPU time | 27.44 seconds |
| Started | Sep 09 03:54:37 AM UTC 24 |
| Finished | Sep 09 03:55:05 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192269638 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.4192269638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.489744449 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2122905362 ps |
| CPU time | 20.53 seconds |
| Started | Sep 09 03:54:40 AM UTC 24 |
| Finished | Sep 09 03:55:02 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489744449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.489744449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.2111873912 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 35663106 ps |
| CPU time | 3.01 seconds |
| Started | Sep 09 03:54:33 AM UTC 24 |
| Finished | Sep 09 03:54:37 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111873912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2111873912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2457953097 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 33506423073 ps |
| CPU time | 71.64 seconds |
| Started | Sep 09 03:54:33 AM UTC 24 |
| Finished | Sep 09 03:55:47 AM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457953097 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2457953097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2755467107 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3858930379 ps |
| CPU time | 27.15 seconds |
| Started | Sep 09 03:54:33 AM UTC 24 |
| Finished | Sep 09 03:55:02 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755467107 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2755467107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3082887412 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 40222595 ps |
| CPU time | 3.21 seconds |
| Started | Sep 09 03:54:33 AM UTC 24 |
| Finished | Sep 09 03:54:38 AM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082887412 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3082887412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.4164762352 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 28442650001 ps |
| CPU time | 158.5 seconds |
| Started | Sep 09 03:54:45 AM UTC 24 |
| Finished | Sep 09 03:57:26 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164762352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.4164762352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3023424837 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1278022885 ps |
| CPU time | 30.46 seconds |
| Started | Sep 09 03:54:45 AM UTC 24 |
| Finished | Sep 09 03:55:17 AM UTC 24 |
| Peak memory | 216760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023424837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3023424837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.4103075550 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 691825300 ps |
| CPU time | 267.02 seconds |
| Started | Sep 09 03:54:45 AM UTC 24 |
| Finished | Sep 09 03:59:16 AM UTC 24 |
| Peak memory | 220936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103075550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.4103075550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1090755790 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5008802388 ps |
| CPU time | 161.28 seconds |
| Started | Sep 09 03:54:45 AM UTC 24 |
| Finished | Sep 09 03:57:29 AM UTC 24 |
| Peak memory | 223052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090755790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.1090755790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.1618205330 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 609307795 ps |
| CPU time | 28.86 seconds |
| Started | Sep 09 03:54:43 AM UTC 24 |
| Finished | Sep 09 03:55:14 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618205330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1618205330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.3319704340 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1190480074 ps |
| CPU time | 39.36 seconds |
| Started | Sep 09 03:54:54 AM UTC 24 |
| Finished | Sep 09 03:55:34 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319704340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3319704340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2308618132 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 532299475 ps |
| CPU time | 17.21 seconds |
| Started | Sep 09 03:54:59 AM UTC 24 |
| Finished | Sep 09 03:55:18 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308618132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2308618132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.2102655007 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 5012766526 ps |
| CPU time | 41.75 seconds |
| Started | Sep 09 03:54:58 AM UTC 24 |
| Finished | Sep 09 03:55:42 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102655007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2102655007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.629153463 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 316647951 ps |
| CPU time | 12.43 seconds |
| Started | Sep 09 03:54:50 AM UTC 24 |
| Finished | Sep 09 03:55:04 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629153463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.629153463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.2081630532 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 5415426588 ps |
| CPU time | 20.74 seconds |
| Started | Sep 09 03:54:51 AM UTC 24 |
| Finished | Sep 09 03:55:13 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081630532 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2081630532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3075816767 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1565854741 ps |
| CPU time | 15.24 seconds |
| Started | Sep 09 03:54:53 AM UTC 24 |
| Finished | Sep 09 03:55:09 AM UTC 24 |
| Peak memory | 216824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075816767 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3075816767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.3928326829 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 34028376 ps |
| CPU time | 5.07 seconds |
| Started | Sep 09 03:54:51 AM UTC 24 |
| Finished | Sep 09 03:54:58 AM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928326829 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3928326829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.3134721878 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 269418379 ps |
| CPU time | 8.37 seconds |
| Started | Sep 09 03:54:57 AM UTC 24 |
| Finished | Sep 09 03:55:06 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134721878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3134721878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2552997270 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 47296047 ps |
| CPU time | 3.43 seconds |
| Started | Sep 09 03:54:45 AM UTC 24 |
| Finished | Sep 09 03:54:49 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552997270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2552997270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.385151149 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 17197038594 ps |
| CPU time | 58.91 seconds |
| Started | Sep 09 03:54:47 AM UTC 24 |
| Finished | Sep 09 03:55:48 AM UTC 24 |
| Peak memory | 216820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385151149 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.385151149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2706551395 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 9981990431 ps |
| CPU time | 43.56 seconds |
| Started | Sep 09 03:54:48 AM UTC 24 |
| Finished | Sep 09 03:55:33 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706551395 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2706551395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2724053796 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 48845627 ps |
| CPU time | 3.36 seconds |
| Started | Sep 09 03:54:46 AM UTC 24 |
| Finished | Sep 09 03:54:50 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724053796 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2724053796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.2111612086 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 356883167 ps |
| CPU time | 14.89 seconds |
| Started | Sep 09 03:55:02 AM UTC 24 |
| Finished | Sep 09 03:55:19 AM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111612086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2111612086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.541410042 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 817715531 ps |
| CPU time | 46.53 seconds |
| Started | Sep 09 03:55:02 AM UTC 24 |
| Finished | Sep 09 03:55:51 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541410042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.541410042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2053178608 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2713252272 ps |
| CPU time | 428.4 seconds |
| Started | Sep 09 03:55:02 AM UTC 24 |
| Finished | Sep 09 04:02:17 AM UTC 24 |
| Peak memory | 223292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053178608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.2053178608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2792682765 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 144205109 ps |
| CPU time | 32.87 seconds |
| Started | Sep 09 03:55:04 AM UTC 24 |
| Finished | Sep 09 03:55:39 AM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792682765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.2792682765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.374826774 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 764546432 ps |
| CPU time | 21.08 seconds |
| Started | Sep 09 03:54:58 AM UTC 24 |
| Finished | Sep 09 03:55:21 AM UTC 24 |
| Peak memory | 216764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374826774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.374826774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3408193660 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 322267094468 ps |
| CPU time | 841.98 seconds |
| Started | Sep 09 03:55:11 AM UTC 24 |
| Finished | Sep 09 04:09:23 AM UTC 24 |
| Peak memory | 222548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408193660 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.3408193660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1473897645 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 140325088 ps |
| CPU time | 7.32 seconds |
| Started | Sep 09 03:55:18 AM UTC 24 |
| Finished | Sep 09 03:55:27 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473897645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1473897645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.950664521 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 108112988 ps |
| CPU time | 14.61 seconds |
| Started | Sep 09 03:55:15 AM UTC 24 |
| Finished | Sep 09 03:55:31 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950664521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.950664521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.1677201144 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 769522970 ps |
| CPU time | 27.48 seconds |
| Started | Sep 09 03:55:09 AM UTC 24 |
| Finished | Sep 09 03:55:38 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677201144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1677201144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.4037552391 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 47704219090 ps |
| CPU time | 259.89 seconds |
| Started | Sep 09 03:55:10 AM UTC 24 |
| Finished | Sep 09 03:59:34 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037552391 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.4037552391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2309294982 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 59747153849 ps |
| CPU time | 233.3 seconds |
| Started | Sep 09 03:55:10 AM UTC 24 |
| Finished | Sep 09 03:59:07 AM UTC 24 |
| Peak memory | 219076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309294982 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2309294982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.4094252637 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 210947720 ps |
| CPU time | 31.29 seconds |
| Started | Sep 09 03:55:09 AM UTC 24 |
| Finished | Sep 09 03:55:42 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094252637 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.4094252637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.663056715 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 165548379 ps |
| CPU time | 9.23 seconds |
| Started | Sep 09 03:55:15 AM UTC 24 |
| Finished | Sep 09 03:55:25 AM UTC 24 |
| Peak memory | 217088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663056715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.663056715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.394017873 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 185658060 ps |
| CPU time | 5.2 seconds |
| Started | Sep 09 03:55:07 AM UTC 24 |
| Finished | Sep 09 03:55:13 AM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394017873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.394017873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3721998621 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4094278335 ps |
| CPU time | 24.19 seconds |
| Started | Sep 09 03:55:07 AM UTC 24 |
| Finished | Sep 09 03:55:32 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721998621 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3721998621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.4100287322 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3545487442 ps |
| CPU time | 32.84 seconds |
| Started | Sep 09 03:55:08 AM UTC 24 |
| Finished | Sep 09 03:55:42 AM UTC 24 |
| Peak memory | 217200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100287322 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.4100287322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2698114098 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 28199408 ps |
| CPU time | 2.82 seconds |
| Started | Sep 09 03:55:07 AM UTC 24 |
| Finished | Sep 09 03:55:11 AM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698114098 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2698114098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.410104193 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 7730072517 ps |
| CPU time | 119.59 seconds |
| Started | Sep 09 03:55:20 AM UTC 24 |
| Finished | Sep 09 03:57:23 AM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410104193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.410104193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1002921451 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 8827701 ps |
| CPU time | 12.28 seconds |
| Started | Sep 09 03:55:21 AM UTC 24 |
| Finished | Sep 09 03:55:35 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002921451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.1002921451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.4091300849 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2528292394 ps |
| CPU time | 16.96 seconds |
| Started | Sep 09 03:55:15 AM UTC 24 |
| Finished | Sep 09 03:55:33 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091300849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.4091300849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.1387941037 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1142165340 ps |
| CPU time | 28.68 seconds |
| Started | Sep 09 03:55:33 AM UTC 24 |
| Finished | Sep 09 03:56:03 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387941037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1387941037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.4155738911 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 247929726 ps |
| CPU time | 18 seconds |
| Started | Sep 09 03:55:38 AM UTC 24 |
| Finished | Sep 09 03:55:57 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155738911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.4155738911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.400871523 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 47246935 ps |
| CPU time | 4.75 seconds |
| Started | Sep 09 03:55:36 AM UTC 24 |
| Finished | Sep 09 03:55:41 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400871523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.400871523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.59742658 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 167858468 ps |
| CPU time | 28.98 seconds |
| Started | Sep 09 03:55:31 AM UTC 24 |
| Finished | Sep 09 03:56:01 AM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59742658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.59742658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.597754940 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 46019636819 ps |
| CPU time | 280.08 seconds |
| Started | Sep 09 03:55:32 AM UTC 24 |
| Finished | Sep 09 04:00:16 AM UTC 24 |
| Peak memory | 217160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597754940 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.597754940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1225540312 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 15503863018 ps |
| CPU time | 45.99 seconds |
| Started | Sep 09 03:55:33 AM UTC 24 |
| Finished | Sep 09 03:56:21 AM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225540312 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1225540312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.651569720 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 56065973 ps |
| CPU time | 5.06 seconds |
| Started | Sep 09 03:55:31 AM UTC 24 |
| Finished | Sep 09 03:55:37 AM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651569720 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.651569720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.3334078295 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1859533503 ps |
| CPU time | 26.82 seconds |
| Started | Sep 09 03:55:34 AM UTC 24 |
| Finished | Sep 09 03:56:02 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334078295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3334078295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.2481125553 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 48820346 ps |
| CPU time | 3.04 seconds |
| Started | Sep 09 03:55:25 AM UTC 24 |
| Finished | Sep 09 03:55:30 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481125553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2481125553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.49745668 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 10327646652 ps |
| CPU time | 43.03 seconds |
| Started | Sep 09 03:55:28 AM UTC 24 |
| Finished | Sep 09 03:56:12 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49745668 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.49745668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.141580981 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9743193503 ps |
| CPU time | 51.4 seconds |
| Started | Sep 09 03:55:28 AM UTC 24 |
| Finished | Sep 09 03:56:21 AM UTC 24 |
| Peak memory | 216872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141580981 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.141580981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1163831668 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 27026567 ps |
| CPU time | 2.72 seconds |
| Started | Sep 09 03:55:26 AM UTC 24 |
| Finished | Sep 09 03:55:30 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163831668 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1163831668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.1196416401 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1212664897 ps |
| CPU time | 29.5 seconds |
| Started | Sep 09 03:55:39 AM UTC 24 |
| Finished | Sep 09 03:56:10 AM UTC 24 |
| Peak memory | 219004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196416401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1196416401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.123054480 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 398482901 ps |
| CPU time | 15.86 seconds |
| Started | Sep 09 03:55:40 AM UTC 24 |
| Finished | Sep 09 03:55:57 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123054480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.123054480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1929949630 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 46645119 ps |
| CPU time | 28.87 seconds |
| Started | Sep 09 03:55:39 AM UTC 24 |
| Finished | Sep 09 03:56:09 AM UTC 24 |
| Peak memory | 219216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929949630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.1929949630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1988307530 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 216113038 ps |
| CPU time | 72.93 seconds |
| Started | Sep 09 03:55:42 AM UTC 24 |
| Finished | Sep 09 03:56:57 AM UTC 24 |
| Peak memory | 220868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988307530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.1988307530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.2223287448 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 358674360 ps |
| CPU time | 30.78 seconds |
| Started | Sep 09 03:55:36 AM UTC 24 |
| Finished | Sep 09 03:56:08 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223287448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2223287448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.3313051374 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1719492059 ps |
| CPU time | 39.28 seconds |
| Started | Sep 09 03:55:49 AM UTC 24 |
| Finished | Sep 09 03:56:30 AM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313051374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3313051374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3555109842 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 38741494790 ps |
| CPU time | 250.05 seconds |
| Started | Sep 09 03:55:52 AM UTC 24 |
| Finished | Sep 09 04:00:06 AM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555109842 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.3555109842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3811705667 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 109665943 ps |
| CPU time | 11.44 seconds |
| Started | Sep 09 03:55:56 AM UTC 24 |
| Finished | Sep 09 03:56:09 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811705667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3811705667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.3709414342 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 277829956 ps |
| CPU time | 11.42 seconds |
| Started | Sep 09 03:55:53 AM UTC 24 |
| Finished | Sep 09 03:56:06 AM UTC 24 |
| Peak memory | 216756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709414342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3709414342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.2031911610 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 365808285 ps |
| CPU time | 6.84 seconds |
| Started | Sep 09 03:55:48 AM UTC 24 |
| Finished | Sep 09 03:55:55 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031911610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2031911610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.1170920200 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 84736071230 ps |
| CPU time | 344.93 seconds |
| Started | Sep 09 03:55:48 AM UTC 24 |
| Finished | Sep 09 04:01:37 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170920200 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1170920200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.4210208855 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 27934175238 ps |
| CPU time | 144.09 seconds |
| Started | Sep 09 03:55:49 AM UTC 24 |
| Finished | Sep 09 03:58:15 AM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210208855 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.4210208855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.424400063 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 170126803 ps |
| CPU time | 24.99 seconds |
| Started | Sep 09 03:55:48 AM UTC 24 |
| Finished | Sep 09 03:56:14 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424400063 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.424400063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.2087861925 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 195345284 ps |
| CPU time | 13.74 seconds |
| Started | Sep 09 03:55:52 AM UTC 24 |
| Finished | Sep 09 03:56:07 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087861925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2087861925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.579419679 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 40739812 ps |
| CPU time | 3.39 seconds |
| Started | Sep 09 03:55:42 AM UTC 24 |
| Finished | Sep 09 03:55:46 AM UTC 24 |
| Peak memory | 217076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579419679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.579419679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1249015493 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 17274363811 ps |
| CPU time | 39.99 seconds |
| Started | Sep 09 03:55:43 AM UTC 24 |
| Finished | Sep 09 03:56:25 AM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249015493 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1249015493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.840499278 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2354705911 ps |
| CPU time | 23.81 seconds |
| Started | Sep 09 03:55:43 AM UTC 24 |
| Finished | Sep 09 03:56:08 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840499278 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.840499278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1076591972 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 73949769 ps |
| CPU time | 3.38 seconds |
| Started | Sep 09 03:55:42 AM UTC 24 |
| Finished | Sep 09 03:55:47 AM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076591972 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1076591972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.4000751271 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 7221980114 ps |
| CPU time | 204.55 seconds |
| Started | Sep 09 03:55:58 AM UTC 24 |
| Finished | Sep 09 03:59:25 AM UTC 24 |
| Peak memory | 222976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000751271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4000751271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2083401746 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 1708900752 ps |
| CPU time | 105.73 seconds |
| Started | Sep 09 03:56:01 AM UTC 24 |
| Finished | Sep 09 03:57:49 AM UTC 24 |
| Peak memory | 220924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083401746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2083401746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1419798323 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 152749543 ps |
| CPU time | 46.49 seconds |
| Started | Sep 09 03:55:58 AM UTC 24 |
| Finished | Sep 09 03:56:45 AM UTC 24 |
| Peak memory | 219144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419798323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.1419798323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.3618644521 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 328677486 ps |
| CPU time | 10.11 seconds |
| Started | Sep 09 03:55:55 AM UTC 24 |
| Finished | Sep 09 03:56:07 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618644521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3618644521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest |
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