Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	24	0	24	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	24	0	24	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	441	1			T10	1		T26	4		T22	1
all_values[1]	458	1			T26	2		T30	1		T41	2
all_values[2]	488	1			T21	1		T41	3		T199	2
all_values[3]	477	1			T26	3		T30	1		T41	4
all_values[4]	444	1			T21	1		T30	1		T41	1
all_values[5]	476	1			T22	4		T41	3		T195	1
all_values[6]	447	1			T26	1		T30	2		T41	1
all_values[7]	481	1			T10	1		T22	1		T41	1
all_values[8]	440	1			T26	1		T21	1		T22	1
all_values[9]	433	1			T26	2		T30	2		T195	2
all_values[10]	443	1			T22	1		T30	1		T41	1
all_values[11]	451	1			T26	2		T22	2		T31	1
all_values[12]	420	1			T22	1		T41	1		T199	3
all_values[13]	498	1			T26	1		T21	2		T22	1
all_values[14]	465	1			T10	2		T21	1		T30	1
all_values[15]	447	1			T21	1		T48	1		T195	2
all_values[16]	489	1			T26	1		T22	1		T30	1
all_values[17]	411	1			T26	2		T198	1		T87	1
all_values[18]	481	1			T10	4		T22	1		T41	1
all_values[19]	462	1			T26	1		T21	1		T41	1
all_values[20]	421	1			T22	1		T31	1		T30	1
all_values[21]	440	1			T26	1		T21	1		T41	2
all_values[22]	487	1			T26	2		T22	1		T48	1
all_values[23]	483	1			T22	1		T31	1		T41	1