Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1776	1			T9	1		T38	1		T19	5
all_values[1]	1780	1			T9	1		T38	1		T19	5
all_values[2]	1733	1			T9	2		T38	1		T19	6
all_values[3]	1783	1			T9	3		T38	1		T19	3
all_values[4]	1804	1			T9	6		T38	2		T19	9
all_values[5]	1741	1			T9	3		T38	1		T19	4
all_values[6]	1768	1			T9	3		T38	2		T19	7
all_values[7]	1723	1			T9	4		T38	2		T19	4
all_values[8]	1738	1			T9	2		T38	2		T19	6
all_values[9]	1761	1			T9	3		T19	10		T22	1
all_values[10]	1806	1			T9	1		T19	7		T22	4
all_values[11]	1731	1			T9	1		T38	1		T19	6
all_values[12]	1772	1			T9	2		T38	2		T19	4
all_values[13]	1738	1			T9	2		T38	2		T19	9
all_values[14]	1713	1			T9	3		T38	1		T19	4
all_values[15]	1750	1			T9	3		T38	2		T19	6
all_values[16]	1735	1			T9	5		T38	2		T19	6
all_values[17]	1749	1			T9	3		T38	2		T19	3
all_values[18]	1822	1			T9	1		T19	6		T22	6
all_values[19]	1686	1			T9	1		T38	1		T19	4
all_values[20]	1719	1			T19	8		T22	1		T56	3
all_values[21]	1716	1			T9	7		T38	5		T19	4
all_values[22]	1756	1			T9	2		T38	3		T19	8
all_values[23]	1710	1			T9	3		T38	1		T19	8
all_values[24]	1634	1			T9	2		T38	2		T19	5
all_values[25]	1760	1			T9	3		T38	1		T19	6
all_values[26]	1755	1			T38	2		T19	8		T22	5
all_values[27]	1754	1			T9	2		T38	1		T19	4
all_values[28]	1659	1			T9	2		T38	3		T19	6
all_values[29]	1804	1			T9	2		T19	3		T22	6
all_values[30]	1734	1			T9	3		T38	1		T19	8
all_values[31]	1755	1			T9	3		T38	2		T19	7
all_values[32]	1780	1			T9	1		T38	1		T19	7
all_values[33]	1775	1			T9	7		T19	5		T22	4
all_values[34]	1743	1			T9	3		T19	8		T22	2
all_values[35]	1683	1			T9	3		T38	6		T19	3
all_values[36]	1698	1			T9	5		T38	4		T19	6
all_values[37]	1685	1			T9	1		T19	8		T22	2
all_values[38]	1708	1			T9	4		T38	3		T19	8
all_values[39]	1714	1			T9	2		T38	1		T19	7
all_values[40]	1625	1			T9	1		T38	2		T19	7
all_values[41]	1738	1			T9	1		T19	5		T22	1
all_values[42]	1781	1			T9	5		T38	1		T19	6
all_values[43]	1768	1			T9	1		T19	6		T22	2
all_values[44]	1782	1			T9	1		T38	2		T19	4
all_values[45]	1712	1			T9	2		T38	2		T19	3
all_values[46]	1789	1			T9	2		T19	2		T22	2
all_values[47]	1748	1			T9	1		T38	2		T19	3
all_values[48]	1794	1			T9	3		T38	1		T19	9
all_values[49]	1770	1			T9	1		T38	2		T19	7
all_values[50]	1808	1			T9	3		T38	1		T19	6
all_values[51]	1802	1			T9	2		T38	3		T19	5
all_values[52]	1687	1			T38	3		T19	9		T22	2
all_values[53]	1622	1			T9	1		T38	2		T19	12
all_values[54]	1800	1			T9	4		T38	4		T19	7
all_values[55]	1789	1			T9	1		T19	5		T22	4
all_values[56]	1775	1			T9	3		T38	1		T19	5
all_values[57]	1688	1			T9	3		T38	2		T19	3
all_values[58]	1722	1			T9	2		T38	1		T19	7
all_values[59]	1793	1			T9	1		T38	3		T19	9
all_values[60]	1761	1			T9	5		T19	5		T22	3
all_values[61]	1730	1			T9	2		T38	3		T19	10
all_values[62]	1726	1			T9	2		T38	1		T19	8
all_values[63]	1740	1			T9	3		T38	3		T19	3