Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	24	0	24	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	24	0	24	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	453	1			T154	1		T33	1		T34	2
all_values[1]	438	1			T52	1		T33	1		T87	1
all_values[2]	468	1			T15	1		T52	1		T87	1
all_values[3]	491	1			T51	1		T82	1		T52	2
all_values[4]	449	1			T33	1		T87	1		T223	1
all_values[5]	397	1			T15	1		T51	1		T52	3
all_values[6]	482	1			T82	1		T52	3		T154	1
all_values[7]	404	1			T82	1		T52	1		T154	1
all_values[8]	417	1			T82	3		T52	2		T33	2
all_values[9]	448	1			T82	2		T52	1		T87	1
all_values[10]	453	1			T52	6		T33	2		T34	1
all_values[11]	441	1			T15	3		T52	2		T223	1
all_values[12]	443	1			T15	1		T82	2		T33	1
all_values[13]	458	1			T51	1		T52	2		T87	2
all_values[14]	448	1			T52	2		T34	1		T89	1
all_values[15]	432	1			T15	1		T86	1		T82	2
all_values[16]	449	1			T15	1		T52	2		T88	2
all_values[17]	454	1			T15	1		T52	1		T154	1
all_values[18]	456	1			T15	1		T52	2		T229	1
all_values[19]	472	1			T82	1		T154	1		T34	2
all_values[20]	425	1			T51	1		T82	1		T52	4
all_values[21]	445	1			T82	1		T52	2		T33	1
all_values[22]	427	1			T52	2		T154	1		T33	2
all_values[23]	427	1			T52	2		T33	1		T223	1