Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1541	1			T54	3		T21	1		T39	1
all_values[1]	1570	1			T18	1		T54	3		T21	9
all_values[2]	1630	1			T54	2		T21	2		T51	2
all_values[3]	1558	1			T54	2		T21	4		T57	2
all_values[4]	1556	1			T54	4		T21	1		T51	2
all_values[5]	1521	1			T54	1		T21	2		T51	1
all_values[6]	1558	1			T18	1		T54	3		T21	4
all_values[7]	1518	1			T54	4		T21	5		T51	3
all_values[8]	1528	1			T54	2		T21	1		T51	3
all_values[9]	1590	1			T54	2		T21	3		T51	2
all_values[10]	1611	1			T54	5		T21	5		T51	2
all_values[11]	1597	1			T54	4		T21	3		T51	3
all_values[12]	1553	1			T54	2		T21	2		T51	2
all_values[13]	1603	1			T18	3		T54	1		T21	4
all_values[14]	1494	1			T54	2		T21	7		T51	3
all_values[15]	1558	1			T54	2		T21	1		T51	2
all_values[16]	1577	1			T18	1		T54	2		T21	1
all_values[17]	1508	1			T18	1		T54	3		T21	4
all_values[18]	1586	1			T18	2		T54	3		T21	3
all_values[19]	1647	1			T54	3		T21	4		T51	1
all_values[20]	1604	1			T18	2		T54	1		T21	2
all_values[21]	1573	1			T54	2		T21	6		T51	6
all_values[22]	1573	1			T54	3		T21	2		T51	2
all_values[23]	1581	1			T18	1		T54	3		T21	2
all_values[24]	1550	1			T54	3		T21	2		T51	1
all_values[25]	1542	1			T54	1		T21	5		T51	1
all_values[26]	1520	1			T18	1		T54	2		T21	5
all_values[27]	1596	1			T18	1		T54	4		T21	2
all_values[28]	1573	1			T54	4		T21	4		T51	2
all_values[29]	1554	1			T18	1		T54	2		T21	4
all_values[30]	1575	1			T18	1		T54	2		T21	4
all_values[31]	1548	1			T54	2		T21	6		T51	2
all_values[32]	1561	1			T18	2		T54	2		T51	2
all_values[33]	1504	1			T54	2		T21	3		T51	3
all_values[34]	1608	1			T54	2		T21	3		T51	3
all_values[35]	1529	1			T54	5		T21	1		T51	3
all_values[36]	1607	1			T18	3		T54	3		T21	2
all_values[37]	1591	1			T18	1		T54	2		T51	3
all_values[38]	1605	1			T54	2		T21	6		T57	1
all_values[39]	1603	1			T18	1		T54	1		T21	3
all_values[40]	1536	1			T54	2		T21	6		T57	1
all_values[41]	1641	1			T54	5		T21	1		T57	1
all_values[42]	1560	1			T18	1		T54	1		T21	1
all_values[43]	1572	1			T54	1		T21	4		T51	1
all_values[44]	1547	1			T18	1		T54	2		T21	2
all_values[45]	1637	1			T18	1		T54	4		T21	1
all_values[46]	1538	1			T18	1		T54	3		T21	1
all_values[47]	1544	1			T18	2		T54	2		T21	1
all_values[48]	1570	1			T54	2		T21	4		T51	1
all_values[49]	1664	1			T18	3		T54	1		T21	6
all_values[50]	1509	1			T54	4		T21	1		T51	1
all_values[51]	1543	1			T18	1		T54	3		T21	4
all_values[52]	1517	1			T54	4		T21	4		T51	3
all_values[53]	1539	1			T54	2		T21	4		T51	3
all_values[54]	1530	1			T54	2		T21	2		T51	3
all_values[55]	1562	1			T18	1		T54	3		T21	2
all_values[56]	1607	1			T54	2		T21	4		T51	2
all_values[57]	1607	1			T18	1		T54	2		T21	3
all_values[58]	1500	1			T54	1		T21	1		T51	2
all_values[59]	1622	1			T54	4		T21	1		T51	2
all_values[60]	1466	1			T18	2		T21	1		T51	3
all_values[61]	1554	1			T54	3		T51	5		T52	8
all_values[62]	1545	1			T18	2		T54	5		T21	2
all_values[63]	1608	1			T18	1		T21	1		T51	3