Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.02	99.26	88.89	98.80		95.88	99.28	100.00

Total test records in report: 900

T772	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3861176344	Sep 18 06:06:10 AM UTC 24	Sep 18 06:06:41 AM UTC 24	1804550307 ps
T247	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.2601439038	Sep 18 06:06:10 AM UTC 24	Sep 18 06:06:42 AM UTC 24	945203542 ps
T773	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.10956526	Sep 18 06:06:22 AM UTC 24	Sep 18 06:06:43 AM UTC 24	825980623 ps
T774	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.430842078	Sep 18 06:06:44 AM UTC 24	Sep 18 06:06:47 AM UTC 24	26346115 ps
T775	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1196823796	Sep 18 06:06:44 AM UTC 24	Sep 18 06:06:49 AM UTC 24	37027447 ps
T776	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1147549362	Sep 18 06:06:39 AM UTC 24	Sep 18 06:06:50 AM UTC 24	154352369 ps
T777	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.2067463221	Sep 18 06:06:03 AM UTC 24	Sep 18 06:06:51 AM UTC 24	5520247315 ps
T778	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3428741404	Sep 18 06:01:23 AM UTC 24	Sep 18 06:06:53 AM UTC 24	62366709425 ps
T779	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.177519220	Sep 18 06:06:36 AM UTC 24	Sep 18 06:06:53 AM UTC 24	70390132 ps
T780	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3058444667	Sep 18 06:04:32 AM UTC 24	Sep 18 06:06:55 AM UTC 24	161863770 ps
T781	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.3562770326	Sep 18 06:06:50 AM UTC 24	Sep 18 06:06:57 AM UTC 24	214893787 ps
T782	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2090316117	Sep 18 06:06:39 AM UTC 24	Sep 18 06:07:04 AM UTC 24	252782656 ps
T783	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2584750498	Sep 18 06:06:52 AM UTC 24	Sep 18 06:07:04 AM UTC 24	456533716 ps
T784	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.3055217418	Sep 18 06:06:54 AM UTC 24	Sep 18 06:07:09 AM UTC 24	390813799 ps
T785	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3549003461	Sep 18 06:06:22 AM UTC 24	Sep 18 06:07:10 AM UTC 24	27721293856 ps
T255	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.124211633	Sep 18 06:03:25 AM UTC 24	Sep 18 06:07:14 AM UTC 24	64618875517 ps
T786	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3447995154	Sep 18 06:04:10 AM UTC 24	Sep 18 06:07:15 AM UTC 24	10189248133 ps
T787	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1864990873	Sep 18 06:07:10 AM UTC 24	Sep 18 06:07:16 AM UTC 24	174787895 ps
T788	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.3538856490	Sep 18 06:06:58 AM UTC 24	Sep 18 06:07:17 AM UTC 24	447513775 ps
T789	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.2832115644	Sep 18 06:06:28 AM UTC 24	Sep 18 06:07:18 AM UTC 24	1794847446 ps
T790	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.315861352	Sep 18 06:05:52 AM UTC 24	Sep 18 06:07:19 AM UTC 24	3274665843 ps
T791	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.933740774	Sep 18 06:06:22 AM UTC 24	Sep 18 06:07:22 AM UTC 24	7508294346 ps
T792	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1824471505	Sep 18 06:07:20 AM UTC 24	Sep 18 06:07:24 AM UTC 24	79350692 ps
T793	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1670156416	Sep 18 06:06:35 AM UTC 24	Sep 18 06:07:25 AM UTC 24	1021918649 ps
T794	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.2852139674	Sep 18 06:07:05 AM UTC 24	Sep 18 06:07:25 AM UTC 24	863751707 ps
T795	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.4181322785	Sep 18 06:07:18 AM UTC 24	Sep 18 06:07:26 AM UTC 24	740875577 ps
T219	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.876436887	Sep 18 06:02:03 AM UTC 24	Sep 18 06:07:27 AM UTC 24	1956705533 ps
T796	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3493392918	Sep 18 06:05:18 AM UTC 24	Sep 18 06:07:29 AM UTC 24	37425015287 ps
T797	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.60669993	Sep 18 06:06:44 AM UTC 24	Sep 18 06:07:30 AM UTC 24	5196815537 ps
T75	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.683891394	Sep 18 06:06:48 AM UTC 24	Sep 18 06:07:31 AM UTC 24	3077543845 ps
T798	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2561146871	Sep 18 06:07:05 AM UTC 24	Sep 18 06:07:33 AM UTC 24	891736896 ps
T210	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.3716757800	Sep 18 06:05:52 AM UTC 24	Sep 18 06:07:36 AM UTC 24	916474151 ps
T799	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.4017542204	Sep 18 06:06:12 AM UTC 24	Sep 18 06:07:37 AM UTC 24	5470637888 ps
T800	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1859713919	Sep 18 06:07:12 AM UTC 24	Sep 18 06:07:37 AM UTC 24	143544731 ps
T236	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.871967085	Sep 18 06:07:28 AM UTC 24	Sep 18 06:07:42 AM UTC 24	164948671 ps
T801	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2648176916	Sep 18 06:05:25 AM UTC 24	Sep 18 06:07:45 AM UTC 24	5834928239 ps
T802	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.2622636281	Sep 18 06:05:16 AM UTC 24	Sep 18 06:07:46 AM UTC 24	40964636049 ps
T803	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1316746652	Sep 18 06:04:23 AM UTC 24	Sep 18 06:07:46 AM UTC 24	28393531116 ps
T804	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.3270527953	Sep 18 06:07:25 AM UTC 24	Sep 18 06:07:46 AM UTC 24	419591982 ps
T805	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.503013356	Sep 18 06:07:27 AM UTC 24	Sep 18 06:07:47 AM UTC 24	179379446 ps
T806	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.494221969	Sep 18 06:07:32 AM UTC 24	Sep 18 06:07:50 AM UTC 24	212795825 ps
T807	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.984361861	Sep 18 06:07:39 AM UTC 24	Sep 18 06:07:52 AM UTC 24	104275081 ps
T808	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.4153051721	Sep 18 06:07:48 AM UTC 24	Sep 18 06:07:52 AM UTC 24	31784095 ps
T809	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.2006159624	Sep 18 06:07:34 AM UTC 24	Sep 18 06:07:54 AM UTC 24	179708395 ps
T293	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.4247566425	Sep 18 06:07:48 AM UTC 24	Sep 18 06:07:54 AM UTC 24	754105484 ps
T810	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1970351431	Sep 18 06:07:32 AM UTC 24	Sep 18 06:07:57 AM UTC 24	1074650474 ps
T811	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.286363088	Sep 18 05:58:18 AM UTC 24	Sep 18 06:07:57 AM UTC 24	71357082099 ps
T812	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.452120805	Sep 18 06:06:56 AM UTC 24	Sep 18 06:08:06 AM UTC 24	9546993682 ps
T142	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2002748305	Sep 18 06:01:54 AM UTC 24	Sep 18 06:08:07 AM UTC 24	51374723400 ps
T813	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2973745134	Sep 18 06:07:24 AM UTC 24	Sep 18 06:08:07 AM UTC 24	6704454607 ps
T814	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.487118516	Sep 18 06:07:27 AM UTC 24	Sep 18 06:08:09 AM UTC 24	10890697563 ps
T815	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1487463604	Sep 18 05:56:26 AM UTC 24	Sep 18 06:08:10 AM UTC 24	78757920232 ps
T816	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3243314744	Sep 18 05:53:50 AM UTC 24	Sep 18 06:08:13 AM UTC 24	78174689467 ps
T817	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3049151430	Sep 18 06:08:08 AM UTC 24	Sep 18 06:08:13 AM UTC 24	19624450 ps
T76	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.1410855508	Sep 18 06:07:51 AM UTC 24	Sep 18 06:08:15 AM UTC 24	527528297 ps
T143	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.566096116	Sep 18 06:03:09 AM UTC 24	Sep 18 06:08:16 AM UTC 24	5193659374 ps
T818	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2321004233	Sep 18 06:07:53 AM UTC 24	Sep 18 06:08:16 AM UTC 24	221376749 ps
T819	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.578048639	Sep 18 06:08:07 AM UTC 24	Sep 18 06:08:16 AM UTC 24	64926872 ps
T820	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.1481060861	Sep 18 06:07:56 AM UTC 24	Sep 18 06:08:16 AM UTC 24	238754808 ps
T821	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.8948010	Sep 18 06:08:08 AM UTC 24	Sep 18 06:08:19 AM UTC 24	668522151 ps
T822	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.686644987	Sep 18 06:05:22 AM UTC 24	Sep 18 06:08:21 AM UTC 24	7287757525 ps
T823	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3449728047	Sep 18 06:08:18 AM UTC 24	Sep 18 06:08:22 AM UTC 24	52451504 ps
T824	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2815021195	Sep 18 06:07:49 AM UTC 24	Sep 18 06:08:24 AM UTC 24	10561001892 ps
T825	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.3876567563	Sep 18 06:08:18 AM UTC 24	Sep 18 06:08:24 AM UTC 24	137873133 ps
T826	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2607266364	Sep 18 06:07:20 AM UTC 24	Sep 18 06:08:30 AM UTC 24	21379152686 ps
T144	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2552453289	Sep 18 06:03:23 AM UTC 24	Sep 18 06:08:30 AM UTC 24	43127035450 ps
T47	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.1318128629	Sep 18 06:07:58 AM UTC 24	Sep 18 06:08:30 AM UTC 24	1923133212 ps
T827	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.1285131602	Sep 18 06:07:39 AM UTC 24	Sep 18 06:08:32 AM UTC 24	491901300 ps
T828	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1547644876	Sep 18 06:07:58 AM UTC 24	Sep 18 06:08:37 AM UTC 24	6465719408 ps
T829	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1247967653	Sep 18 06:07:16 AM UTC 24	Sep 18 06:08:38 AM UTC 24	530066322 ps
T830	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3444157412	Sep 18 06:08:32 AM UTC 24	Sep 18 06:08:39 AM UTC 24	92935034 ps
T831	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3988335740	Sep 18 06:03:24 AM UTC 24	Sep 18 06:08:40 AM UTC 24	28177765902 ps
T832	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.349429467	Sep 18 06:05:04 AM UTC 24	Sep 18 06:08:41 AM UTC 24	10047173506 ps
T833	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.730737483	Sep 18 06:08:20 AM UTC 24	Sep 18 06:08:47 AM UTC 24	283930129 ps
T834	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3929475127	Sep 18 06:08:14 AM UTC 24	Sep 18 06:08:48 AM UTC 24	1243318928 ps
T835	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.907707027	Sep 18 06:08:42 AM UTC 24	Sep 18 06:08:48 AM UTC 24	648169124 ps
T836	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1472892960	Sep 18 06:05:46 AM UTC 24	Sep 18 06:08:49 AM UTC 24	31197472805 ps
T837	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2357450561	Sep 18 06:08:18 AM UTC 24	Sep 18 06:08:50 AM UTC 24	7682847875 ps
T838	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2336722220	Sep 18 06:07:48 AM UTC 24	Sep 18 06:08:51 AM UTC 24	5504338652 ps
T839	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1248414306	Sep 18 06:08:48 AM UTC 24	Sep 18 06:08:52 AM UTC 24	24655391 ps
T840	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2650015685	Sep 18 06:08:20 AM UTC 24	Sep 18 06:08:56 AM UTC 24	847572111 ps
T841	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3960519843	Sep 18 06:08:42 AM UTC 24	Sep 18 06:08:56 AM UTC 24	44233092 ps
T145	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3704592013	Sep 18 06:03:52 AM UTC 24	Sep 18 06:08:58 AM UTC 24	71218491348 ps
T842	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.113432913	Sep 18 06:08:33 AM UTC 24	Sep 18 06:08:58 AM UTC 24	136035670 ps
T843	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.219656007	Sep 18 06:05:46 AM UTC 24	Sep 18 06:08:59 AM UTC 24	26536555916 ps
T844	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2934620027	Sep 18 06:08:26 AM UTC 24	Sep 18 06:08:59 AM UTC 24	537275944 ps
T845	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.2509766855	Sep 18 06:08:32 AM UTC 24	Sep 18 06:09:00 AM UTC 24	5822961559 ps
T846	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3874067371	Sep 18 06:08:18 AM UTC 24	Sep 18 06:09:00 AM UTC 24	3697924158 ps
T847	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.4099732327	Sep 18 06:08:53 AM UTC 24	Sep 18 06:09:01 AM UTC 24	34297299 ps
T848	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.3890940944	Sep 18 06:08:58 AM UTC 24	Sep 18 06:09:03 AM UTC 24	37382941 ps
T849	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.35470165	Sep 18 06:06:13 AM UTC 24	Sep 18 06:09:04 AM UTC 24	27122100480 ps
T850	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3059700282	Sep 18 06:08:11 AM UTC 24	Sep 18 06:09:05 AM UTC 24	214011371 ps
T851	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.3178518567	Sep 18 06:06:02 AM UTC 24	Sep 18 06:09:07 AM UTC 24	74296331919 ps
T852	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3305858638	Sep 18 06:09:00 AM UTC 24	Sep 18 06:09:09 AM UTC 24	71069009 ps
T853	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.197145242	Sep 18 06:09:00 AM UTC 24	Sep 18 06:09:10 AM UTC 24	310804156 ps
T854	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2592750243	Sep 18 06:08:32 AM UTC 24	Sep 18 06:09:10 AM UTC 24	887568052 ps
T198	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3151510565	Sep 18 06:04:50 AM UTC 24	Sep 18 06:09:11 AM UTC 24	29977824899 ps
T855	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2386415197	Sep 18 06:09:00 AM UTC 24	Sep 18 06:09:11 AM UTC 24	682088335 ps
T856	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.316442001	Sep 18 06:04:48 AM UTC 24	Sep 18 06:09:13 AM UTC 24	37030156314 ps
T857	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.404150292	Sep 18 06:08:50 AM UTC 24	Sep 18 06:09:18 AM UTC 24	2968721337 ps
T858	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.490593177	Sep 18 06:07:14 AM UTC 24	Sep 18 06:09:19 AM UTC 24	4519874645 ps
T859	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2701876976	Sep 18 06:08:53 AM UTC 24	Sep 18 06:09:19 AM UTC 24	3665516022 ps
T860	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2359775108	Sep 18 06:05:25 AM UTC 24	Sep 18 06:09:21 AM UTC 24	5384986285 ps
T861	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2267412608	Sep 18 05:55:16 AM UTC 24	Sep 18 06:09:33 AM UTC 24	204671563159 ps
T40	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3256388188	Sep 18 06:05:00 AM UTC 24	Sep 18 06:09:34 AM UTC 24	1658786580 ps
T862	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.4251269562	Sep 18 06:09:00 AM UTC 24	Sep 18 06:09:36 AM UTC 24	3409444966 ps
T863	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.4257497281	Sep 18 06:08:40 AM UTC 24	Sep 18 06:09:37 AM UTC 24	3735624734 ps
T864	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2711627768	Sep 18 06:06:02 AM UTC 24	Sep 18 06:09:40 AM UTC 24	30174218041 ps
T865	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.4184145149	Sep 18 06:08:50 AM UTC 24	Sep 18 06:09:43 AM UTC 24	8482209761 ps
T866	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.4189217854	Sep 18 06:09:04 AM UTC 24	Sep 18 06:09:44 AM UTC 24	172701779 ps
T867	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3407506446	Sep 18 06:02:26 AM UTC 24	Sep 18 06:09:47 AM UTC 24	3997754553 ps
T868	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.1442917291	Sep 18 06:06:52 AM UTC 24	Sep 18 06:09:59 AM UTC 24	74943122072 ps
T869	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.828190072	Sep 18 06:08:53 AM UTC 24	Sep 18 06:10:03 AM UTC 24	11551772978 ps
T870	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2948768290	Sep 18 06:08:10 AM UTC 24	Sep 18 06:10:03 AM UTC 24	4535081946 ps
T871	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2719653417	Sep 18 06:06:42 AM UTC 24	Sep 18 06:10:05 AM UTC 24	11882336748 ps
T872	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.723315208	Sep 18 06:07:43 AM UTC 24	Sep 18 06:10:06 AM UTC 24	1931591849 ps
T873	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.2723528406	Sep 18 06:03:47 AM UTC 24	Sep 18 06:10:11 AM UTC 24	198876020955 ps
T874	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3888155705	Sep 18 06:09:02 AM UTC 24	Sep 18 06:10:15 AM UTC 24	2659856841 ps
T875	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2316770891	Sep 18 06:06:54 AM UTC 24	Sep 18 06:10:19 AM UTC 24	25641285086 ps
T876	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2911949620	Sep 18 06:09:02 AM UTC 24	Sep 18 06:10:23 AM UTC 24	375809010 ps
T152	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.4189668175	Sep 18 06:08:38 AM UTC 24	Sep 18 06:10:41 AM UTC 24	7834759431 ps
T877	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3416675290	Sep 18 06:08:24 AM UTC 24	Sep 18 06:10:41 AM UTC 24	15257296285 ps
T878	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2273082799	Sep 18 06:08:40 AM UTC 24	Sep 18 06:10:43 AM UTC 24	864100771 ps
T879	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1767914598	Sep 18 06:07:39 AM UTC 24	Sep 18 06:10:47 AM UTC 24	408124310 ps
T880	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2412327124	Sep 18 06:06:25 AM UTC 24	Sep 18 06:11:02 AM UTC 24	56409607706 ps
T146	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1907203270	Sep 18 06:06:03 AM UTC 24	Sep 18 06:11:11 AM UTC 24	46851790845 ps
T881	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3536843186	Sep 18 06:06:42 AM UTC 24	Sep 18 06:11:12 AM UTC 24	18230953567 ps
T882	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3823739757	Sep 18 06:07:27 AM UTC 24	Sep 18 06:11:13 AM UTC 24	24682010715 ps
T883	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1252181998	Sep 18 06:07:56 AM UTC 24	Sep 18 06:11:24 AM UTC 24	50152648724 ps
T884	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.3882449710	Sep 18 06:08:23 AM UTC 24	Sep 18 06:11:36 AM UTC 24	46842140181 ps
T29	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1273567685	Sep 18 06:07:17 AM UTC 24	Sep 18 06:11:39 AM UTC 24	10767720330 ps
T885	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.643129461	Sep 18 05:58:41 AM UTC 24	Sep 18 06:11:41 AM UTC 24	153825091875 ps
T886	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3419925479	Sep 18 06:09:02 AM UTC 24	Sep 18 06:11:43 AM UTC 24	19209549623 ps
T887	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1743246592	Sep 18 06:05:52 AM UTC 24	Sep 18 06:11:43 AM UTC 24	1395396912 ps
T888	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2382699814	Sep 18 06:06:39 AM UTC 24	Sep 18 06:11:51 AM UTC 24	5396063957 ps
T889	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3186816633	Sep 18 06:08:26 AM UTC 24	Sep 18 06:12:02 AM UTC 24	112591544910 ps
T890	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3506972024	Sep 18 06:01:04 AM UTC 24	Sep 18 06:12:04 AM UTC 24	82066487272 ps
T891	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3810087142	Sep 18 06:07:53 AM UTC 24	Sep 18 06:12:07 AM UTC 24	47276758898 ps
T149	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.745728597	Sep 18 06:07:32 AM UTC 24	Sep 18 06:12:09 AM UTC 24	114459306311 ps
T892	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1920969903	Sep 18 06:06:12 AM UTC 24	Sep 18 06:12:33 AM UTC 24	2650000113 ps
T893	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3696903916	Sep 18 06:08:53 AM UTC 24	Sep 18 06:12:41 AM UTC 24	75778529625 ps
T894	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1724941873	Sep 18 06:05:46 AM UTC 24	Sep 18 06:12:44 AM UTC 24	183391562751 ps
T895	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3565401062	Sep 18 06:08:58 AM UTC 24	Sep 18 06:12:54 AM UTC 24	74582562037 ps
T896	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.396694430	Sep 18 06:02:42 AM UTC 24	Sep 18 06:12:56 AM UTC 24	141234646039 ps
T150	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.192674309	Sep 18 06:02:15 AM UTC 24	Sep 18 06:13:09 AM UTC 24	198349717339 ps
T151	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.15773294	Sep 18 06:03:04 AM UTC 24	Sep 18 06:13:17 AM UTC 24	79077713849 ps
T897	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3503908366	Sep 18 06:05:18 AM UTC 24	Sep 18 06:13:45 AM UTC 24	74227638846 ps
T898	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3375149601	Sep 18 06:08:14 AM UTC 24	Sep 18 06:13:47 AM UTC 24	10158794610 ps
T899	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3200743658	Sep 18 06:07:48 AM UTC 24	Sep 18 06:13:49 AM UTC 24	3771470992 ps
T900	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.112962063	Sep 18 06:06:33 AM UTC 24	Sep 18 06:14:42 AM UTC 24	57068716057 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.425160823
Short name	T11
Test name
Test status
Simulation time	671960789 ps
CPU time	19.41 seconds
Started	Sep 18 05:47:06 AM UTC 24
Finished	Sep 18 05:47:27 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425160823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.425160823
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.2956151353
Short name	T91
Test name
Test status
Simulation time	5978397793 ps
CPU time	72.64 seconds
Started	Sep 18 05:48:47 AM UTC 24
Finished	Sep 18 05:50:02 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956151353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2956151353
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.100541854
Short name	T115
Test name
Test status
Simulation time	53704721244 ps
CPU time	389.46 seconds
Started	Sep 18 05:48:10 AM UTC 24
Finished	Sep 18 05:54:44 AM UTC 24
Peak memory	219492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100541854 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.100541854
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3449965225
Short name	T147
Test name
Test status
Simulation time	80427917700 ps
CPU time	608.61 seconds
Started	Sep 18 05:49:24 AM UTC 24
Finished	Sep 18 05:59:39 AM UTC 24
Peak memory	221544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449965225 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.3449965225
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.3086305001
Short name	T6
Test name
Test status
Simulation time	5729301989 ps
CPU time	122.04 seconds
Started	Sep 18 05:47:55 AM UTC 24
Finished	Sep 18 05:49:59 AM UTC 24
Peak memory	220136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086305001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3086305001
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.1923327251
Short name	T33
Test name
Test status
Simulation time	2084942634 ps
CPU time	62.68 seconds
Started	Sep 18 05:47:42 AM UTC 24
Finished	Sep 18 05:48:47 AM UTC 24
Peak memory	218024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923327251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1923327251
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.2031956432
Short name	T14
Test name
Test status
Simulation time	628543694 ps
CPU time	25.59 seconds
Started	Sep 18 05:47:08 AM UTC 24
Finished	Sep 18 05:47:35 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031956432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2031956432
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.553081080
Short name	T89
Test name
Test status
Simulation time	4997877708 ps
CPU time	145.16 seconds
Started	Sep 18 05:47:10 AM UTC 24
Finished	Sep 18 05:49:38 AM UTC 24
Peak memory	219940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553081080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.553081080
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.3839143201
Short name	T87
Test name
Test status
Simulation time	878446690 ps
CPU time	35.52 seconds
Started	Sep 18 05:48:14 AM UTC 24
Finished	Sep 18 05:48:51 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839143201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3839143201
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.395924290
Short name	T18
Test name
Test status
Simulation time	281091914 ps
CPU time	6.12 seconds
Started	Sep 18 05:47:32 AM UTC 24
Finished	Sep 18 05:47:39 AM UTC 24
Peak memory	216028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395924290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.395924290
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2162647975
Short name	T55
Test name
Test status
Simulation time	4884433438 ps
CPU time	29.15 seconds
Started	Sep 18 05:47:19 AM UTC 24
Finished	Sep 18 05:47:50 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162647975 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2162647975
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.334348721
Short name	T82
Test name
Test status
Simulation time	1350826574 ps
CPU time	52.85 seconds
Started	Sep 18 05:47:25 AM UTC 24
Finished	Sep 18 05:48:20 AM UTC 24
Peak memory	215616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334348721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.334348721
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.293502793
Short name	T30
Test name
Test status
Simulation time	802598074 ps
CPU time	262.5 seconds
Started	Sep 18 05:47:13 AM UTC 24
Finished	Sep 18 05:51:39 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293502793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.293502793
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.3852746482
Short name	T92
Test name
Test status
Simulation time	2128347742 ps
CPU time	60.99 seconds
Started	Sep 18 05:50:22 AM UTC 24
Finished	Sep 18 05:51:25 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852746482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3852746482
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1473962948
Short name	T49
Test name
Test status
Simulation time	5498027728 ps
CPU time	215.84 seconds
Started	Sep 18 05:56:14 AM UTC 24
Finished	Sep 18 05:59:54 AM UTC 24
Peak memory	220204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473962948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.1473962948
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.4147947242
Short name	T53
Test name
Test status
Simulation time	3268228740 ps
CPU time	68.82 seconds
Started	Sep 18 05:47:29 AM UTC 24
Finished	Sep 18 05:48:40 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147947242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.4147947242
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.247496476
Short name	T28
Test name
Test status
Simulation time	703082582 ps
CPU time	225.06 seconds
Started	Sep 18 05:57:06 AM UTC 24
Finished	Sep 18 06:00:55 AM UTC 24
Peak memory	222124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247496476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.247496476
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.1473992284
Short name	T23
Test name
Test status
Simulation time	245863727 ps
CPU time	7.63 seconds
Started	Sep 18 05:47:22 AM UTC 24
Finished	Sep 18 05:47:31 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473992284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1473992284
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.3655796243
Short name	T139
Test name
Test status
Simulation time	1348530752 ps
CPU time	53.75 seconds
Started	Sep 18 06:04:23 AM UTC 24
Finished	Sep 18 06:05:18 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655796243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3655796243
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2667125515
Short name	T305
Test name
Test status
Simulation time	8088802052 ps
CPU time	429.86 seconds
Started	Sep 18 05:52:35 AM UTC 24
Finished	Sep 18 05:59:50 AM UTC 24
Peak memory	232592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667125515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.2667125515
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.854511951
Short name	T223
Test name
Test status
Simulation time	24263321399 ps
CPU time	130.32 seconds
Started	Sep 18 05:47:01 AM UTC 24
Finished	Sep 18 05:49:13 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854511951 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.854511951
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.4252523124
Short name	T42
Test name
Test status
Simulation time	66627715 ps
CPU time	20.37 seconds
Started	Sep 18 05:54:35 AM UTC 24
Finished	Sep 18 05:54:57 AM UTC 24
Peak memory	217764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252523124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.4252523124
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3256388188
Short name	T40
Test name
Test status
Simulation time	1658786580 ps
CPU time	270.14 seconds
Started	Sep 18 06:05:00 AM UTC 24
Finished	Sep 18 06:09:34 AM UTC 24
Peak memory	222280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256388188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.3256388188
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.1318128629
Short name	T47
Test name
Test status
Simulation time	1923133212 ps
CPU time	30.86 seconds
Started	Sep 18 06:07:58 AM UTC 24
Finished	Sep 18 06:08:30 AM UTC 24
Peak memory	215728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318128629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1318128629
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3493022999
Short name	T320
Test name
Test status
Simulation time	3350323957 ps
CPU time	155.91 seconds
Started	Sep 18 05:47:36 AM UTC 24
Finished	Sep 18 05:50:14 AM UTC 24
Peak memory	221980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493022999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.3493022999
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1311601955
Short name	T213
Test name
Test status
Simulation time	136612311345 ps
CPU time	331.82 seconds
Started	Sep 18 05:52:45 AM UTC 24
Finished	Sep 18 05:58:21 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311601955 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1311601955
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.719291662
Short name	T69
Test name
Test status
Simulation time	336874675 ps
CPU time	16.15 seconds
Started	Sep 18 05:56:25 AM UTC 24
Finished	Sep 18 05:56:42 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719291662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.719291662
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.1866812252
Short name	T15
Test name
Test status
Simulation time	4136331705 ps
CPU time	33.18 seconds
Started	Sep 18 05:47:01 AM UTC 24
Finished	Sep 18 05:47:35 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866812252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1866812252
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1898894796
Short name	T13
Test name
Test status
Simulation time	177542464 ps
CPU time	16.91 seconds
Started	Sep 18 05:47:10 AM UTC 24
Finished	Sep 18 05:47:28 AM UTC 24
Peak memory	216036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898894796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1898894796
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.3495641848
Short name	T17
Test name
Test status
Simulation time	938321242 ps
CPU time	38.81 seconds
Started	Sep 18 05:46:58 AM UTC 24
Finished	Sep 18 05:47:38 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495641848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3495641848
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.2077513103
Short name	T35
Test name
Test status
Simulation time	34238152761 ps
CPU time	244.08 seconds
Started	Sep 18 05:47:01 AM UTC 24
Finished	Sep 18 05:51:08 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077513103 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2077513103
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.479609093
Short name	T36
Test name
Test status
Simulation time	13516516538 ps
CPU time	85.28 seconds
Started	Sep 18 05:47:01 AM UTC 24
Finished	Sep 18 05:48:28 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479609093 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.479609093
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.1649854243
Short name	T3
Test name
Test status
Simulation time	39088211 ps
CPU time	6.41 seconds
Started	Sep 18 05:46:58 AM UTC 24
Finished	Sep 18 05:47:06 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649854243 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1649854243
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.4145261640
Short name	T54
Test name
Test status
Simulation time	1915055570 ps
CPU time	35.62 seconds
Started	Sep 18 05:47:04 AM UTC 24
Finished	Sep 18 05:47:41 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145261640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.4145261640
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.2587409119
Short name	T2
Test name
Test status
Simulation time	430696787 ps
CPU time	5.03 seconds
Started	Sep 18 05:46:53 AM UTC 24
Finished	Sep 18 05:46:59 AM UTC 24
Peak memory	215884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587409119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2587409119
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1233550111
Short name	T12
Test name
Test status
Simulation time	8402422712 ps
CPU time	30.93 seconds
Started	Sep 18 05:46:55 AM UTC 24
Finished	Sep 18 05:47:27 AM UTC 24
Peak memory	216148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233550111 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1233550111
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2638537291
Short name	T7
Test name
Test status
Simulation time	2273077643 ps
CPU time	23.38 seconds
Started	Sep 18 05:46:57 AM UTC 24
Finished	Sep 18 05:47:21 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638537291 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2638537291
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3818298977
Short name	T1
Test name
Test status
Simulation time	69151445 ps
CPU time	3.01 seconds
Started	Sep 18 05:46:53 AM UTC 24
Finished	Sep 18 05:46:57 AM UTC 24
Peak memory	215816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818298977 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3818298977
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.341850511
Short name	T51
Test name
Test status
Simulation time	317671482 ps
CPU time	37.77 seconds
Started	Sep 18 05:47:15 AM UTC 24
Finished	Sep 18 05:47:54 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341850511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.341850511
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.721488062
Short name	T27
Test name
Test status
Simulation time	4914754702 ps
CPU time	417.85 seconds
Started	Sep 18 05:47:15 AM UTC 24
Finished	Sep 18 05:54:19 AM UTC 24
Peak memory	234188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721488062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.721488062
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1665069591
Short name	T86
Test name
Test status
Simulation time	4960198267 ps
CPU time	29.36 seconds
Started	Sep 18 05:47:25 AM UTC 24
Finished	Sep 18 05:47:56 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665069591 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.1665069591
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3416322415
Short name	T19
Test name
Test status
Simulation time	117162661 ps
CPU time	11.42 seconds
Started	Sep 18 05:47:29 AM UTC 24
Finished	Sep 18 05:47:42 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416322415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3416322415
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.3166955199
Short name	T20
Test name
Test status
Simulation time	206239720 ps
CPU time	14.86 seconds
Started	Sep 18 05:47:27 AM UTC 24
Finished	Sep 18 05:47:43 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166955199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3166955199
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.2323713325
Short name	T83
Test name
Test status
Simulation time	12777490549 ps
CPU time	57.93 seconds
Started	Sep 18 05:47:22 AM UTC 24
Finished	Sep 18 05:48:21 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323713325 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2323713325
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3150717975
Short name	T110
Test name
Test status
Simulation time	22856523879 ps
CPU time	223.06 seconds
Started	Sep 18 05:47:25 AM UTC 24
Finished	Sep 18 05:51:11 AM UTC 24
Peak memory	217612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150717975 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3150717975
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.896940266
Short name	T16
Test name
Test status
Simulation time	112189971 ps
CPU time	12.56 seconds
Started	Sep 18 05:47:22 AM UTC 24
Finished	Sep 18 05:47:36 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896940266 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.896940266
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.1614039486
Short name	T21
Test name
Test status
Simulation time	214436766 ps
CPU time	25.19 seconds
Started	Sep 18 05:47:27 AM UTC 24
Finished	Sep 18 05:47:54 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614039486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1614039486
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.4115341298
Short name	T9
Test name
Test status
Simulation time	42516976 ps
CPU time	3.16 seconds
Started	Sep 18 05:47:19 AM UTC 24
Finished	Sep 18 05:47:24 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115341298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.4115341298
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2029246264
Short name	T109
Test name
Test status
Simulation time	3986468102 ps
CPU time	43.7 seconds
Started	Sep 18 05:47:22 AM UTC 24
Finished	Sep 18 05:48:07 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029246264 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2029246264
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1608888025
Short name	T10
Test name
Test status
Simulation time	31503017 ps
CPU time	3.24 seconds
Started	Sep 18 05:47:19 AM UTC 24
Finished	Sep 18 05:47:24 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608888025 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1608888025
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3160510677
Short name	T52
Test name
Test status
Simulation time	150979257 ps
CPU time	60.15 seconds
Started	Sep 18 05:47:32 AM UTC 24
Finished	Sep 18 05:48:34 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160510677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.3160510677
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.2903785804
Short name	T56
Test name
Test status
Simulation time	713892536 ps
CPU time	19.85 seconds
Started	Sep 18 05:47:29 AM UTC 24
Finished	Sep 18 05:47:51 AM UTC 24
Peak memory	217824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903785804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2903785804
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.662584064
Short name	T158
Test name
Test status
Simulation time	865274337 ps
CPU time	32.6 seconds
Started	Sep 18 05:51:25 AM UTC 24
Finished	Sep 18 05:52:00 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662584064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.662584064
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.817184721
Short name	T426
Test name
Test status
Simulation time	33803988967 ps
CPU time	276.37 seconds
Started	Sep 18 05:51:28 AM UTC 24
Finished	Sep 18 05:56:08 AM UTC 24
Peak memory	218160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817184721 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.817184721
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3206330495
Short name	T241
Test name
Test status
Simulation time	769978837 ps
CPU time	15.39 seconds
Started	Sep 18 05:51:38 AM UTC 24
Finished	Sep 18 05:51:55 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206330495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3206330495
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.511140497
Short name	T194
Test name
Test status
Simulation time	75384441 ps
CPU time	3.5 seconds
Started	Sep 18 05:51:34 AM UTC 24
Finished	Sep 18 05:51:39 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511140497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.511140497
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.1705080483
Short name	T94
Test name
Test status
Simulation time	1725627451 ps
CPU time	47.92 seconds
Started	Sep 18 05:51:15 AM UTC 24
Finished	Sep 18 05:52:05 AM UTC 24
Peak memory	217820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705080483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1705080483
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.1638129035
Short name	T244
Test name
Test status
Simulation time	18988513688 ps
CPU time	47.92 seconds
Started	Sep 18 05:51:17 AM UTC 24
Finished	Sep 18 05:52:07 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638129035 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1638129035
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.4246715566
Short name	T112
Test name
Test status
Simulation time	80672225408 ps
CPU time	158.64 seconds
Started	Sep 18 05:51:19 AM UTC 24
Finished	Sep 18 05:54:02 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246715566 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.4246715566
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.2412716236
Short name	T191
Test name
Test status
Simulation time	210602639 ps
CPU time	10.74 seconds
Started	Sep 18 05:51:15 AM UTC 24
Finished	Sep 18 05:51:27 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412716236 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2412716236
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.32090523
Short name	T347
Test name
Test status
Simulation time	513939053 ps
CPU time	15.79 seconds
Started	Sep 18 05:51:33 AM UTC 24
Finished	Sep 18 05:51:50 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32090523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.32090523
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.1716832456
Short name	T157
Test name
Test status
Simulation time	203486739 ps
CPU time	5.49 seconds
Started	Sep 18 05:51:12 AM UTC 24
Finished	Sep 18 05:51:19 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716832456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1716832456
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3403382647
Short name	T242
Test name
Test status
Simulation time	7652203840 ps
CPU time	44.45 seconds
Started	Sep 18 05:51:12 AM UTC 24
Finished	Sep 18 05:51:58 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403382647 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3403382647
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.287655151
Short name	T64
Test name
Test status
Simulation time	5086570160 ps
CPU time	38.58 seconds
Started	Sep 18 05:51:13 AM UTC 24
Finished	Sep 18 05:51:53 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287655151 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.287655151
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1769891242
Short name	T346
Test name
Test status
Simulation time	29189035 ps
CPU time	2.82 seconds
Started	Sep 18 05:51:12 AM UTC 24
Finished	Sep 18 05:51:16 AM UTC 24
Peak memory	215752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769891242 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1769891242
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.3244548715
Short name	T366
Test name
Test status
Simulation time	427475844 ps
CPU time	65.13 seconds
Started	Sep 18 05:51:40 AM UTC 24
Finished	Sep 18 05:52:46 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244548715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3244548715
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2185898958
Short name	T368
Test name
Test status
Simulation time	10986071462 ps
CPU time	68.63 seconds
Started	Sep 18 05:51:42 AM UTC 24
Finished	Sep 18 05:52:52 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185898958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2185898958
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2413695183
Short name	T328
Test name
Test status
Simulation time	269199748 ps
CPU time	106.44 seconds
Started	Sep 18 05:51:42 AM UTC 24
Finished	Sep 18 05:53:30 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413695183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.2413695183
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1452754991
Short name	T422
Test name
Test status
Simulation time	19653417544 ps
CPU time	247.94 seconds
Started	Sep 18 05:51:47 AM UTC 24
Finished	Sep 18 05:55:58 AM UTC 24
Peak memory	232656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452754991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.1452754991
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.155315102
Short name	T349
Test name
Test status
Simulation time	353290864 ps
CPU time	14.5 seconds
Started	Sep 18 05:51:36 AM UTC 24
Finished	Sep 18 05:51:52 AM UTC 24
Peak memory	215720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155315102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.155315102
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.3222442564
Short name	T95
Test name
Test status
Simulation time	1121409896 ps
CPU time	24.77 seconds
Started	Sep 18 05:51:56 AM UTC 24
Finished	Sep 18 05:52:22 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222442564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3222442564
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1038256109
Short name	T319
Test name
Test status
Simulation time	38389839134 ps
CPU time	131.48 seconds
Started	Sep 18 05:51:59 AM UTC 24
Finished	Sep 18 05:54:12 AM UTC 24
Peak memory	218156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038256109 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1038256109
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.4048910041
Short name	T358
Test name
Test status
Simulation time	906396312 ps
CPU time	23.9 seconds
Started	Sep 18 05:52:06 AM UTC 24
Finished	Sep 18 05:52:31 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048910041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.4048910041
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.3032279465
Short name	T360
Test name
Test status
Simulation time	1496786942 ps
CPU time	27.17 seconds
Started	Sep 18 05:52:05 AM UTC 24
Finished	Sep 18 05:52:33 AM UTC 24
Peak memory	215720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032279465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3032279465
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.3656494350
Short name	T352
Test name
Test status
Simulation time	142441149 ps
CPU time	18.33 seconds
Started	Sep 18 05:51:53 AM UTC 24
Finished	Sep 18 05:52:13 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656494350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3656494350
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.1563955718
Short name	T453
Test name
Test status
Simulation time	86352655586 ps
CPU time	311.41 seconds
Started	Sep 18 05:51:55 AM UTC 24
Finished	Sep 18 05:57:10 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563955718 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1563955718
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.91909136
Short name	T127
Test name
Test status
Simulation time	25109096320 ps
CPU time	173.6 seconds
Started	Sep 18 05:51:55 AM UTC 24
Finished	Sep 18 05:54:51 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91909136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.91909136
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.1590527723
Short name	T205
Test name
Test status
Simulation time	167189871 ps
CPU time	10.53 seconds
Started	Sep 18 05:51:53 AM UTC 24
Finished	Sep 18 05:52:05 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590527723 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1590527723
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.1750093408
Short name	T172
Test name
Test status
Simulation time	4369383743 ps
CPU time	37.09 seconds
Started	Sep 18 05:52:01 AM UTC 24
Finished	Sep 18 05:52:39 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750093408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1750093408
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.4183996465
Short name	T240
Test name
Test status
Simulation time	110272372 ps
CPU time	5.03 seconds
Started	Sep 18 05:51:48 AM UTC 24
Finished	Sep 18 05:51:54 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183996465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.4183996465
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1491882586
Short name	T359
Test name
Test status
Simulation time	11029052052 ps
CPU time	40.84 seconds
Started	Sep 18 05:51:50 AM UTC 24
Finished	Sep 18 05:52:32 AM UTC 24
Peak memory	216088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491882586 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1491882586
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3793066324
Short name	T248
Test name
Test status
Simulation time	13392074007 ps
CPU time	35.73 seconds
Started	Sep 18 05:51:53 AM UTC 24
Finished	Sep 18 05:52:30 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793066324 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3793066324
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.106967242
Short name	T348
Test name
Test status
Simulation time	31012865 ps
CPU time	3 seconds
Started	Sep 18 05:51:48 AM UTC 24
Finished	Sep 18 05:51:52 AM UTC 24
Peak memory	215752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106967242 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.106967242
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.2187970595
Short name	T66
Test name
Test status
Simulation time	7078758845 ps
CPU time	197.84 seconds
Started	Sep 18 05:52:07 AM UTC 24
Finished	Sep 18 05:55:28 AM UTC 24
Peak memory	221988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187970595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2187970595
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3741918979
Short name	T46
Test name
Test status
Simulation time	8524312603 ps
CPU time	223.61 seconds
Started	Sep 18 05:52:08 AM UTC 24
Finished	Sep 18 05:55:56 AM UTC 24
Peak memory	222056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741918979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3741918979
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2744208365
Short name	T37
Test name
Test status
Simulation time	1324027338 ps
CPU time	99.53 seconds
Started	Sep 18 05:52:07 AM UTC 24
Finished	Sep 18 05:53:49 AM UTC 24
Peak memory	220076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744208365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.2744208365
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2783164032
Short name	T386
Test name
Test status
Simulation time	458468245 ps
CPU time	135.47 seconds
Started	Sep 18 05:52:10 AM UTC 24
Finished	Sep 18 05:54:27 AM UTC 24
Peak memory	221988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783164032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.2783164032
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.3140187701
Short name	T357
Test name
Test status
Simulation time	1747370379 ps
CPU time	17.1 seconds
Started	Sep 18 05:52:05 AM UTC 24
Finished	Sep 18 05:52:23 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140187701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3140187701
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.2459643661
Short name	T318
Test name
Test status
Simulation time	257049101 ps
CPU time	13.85 seconds
Started	Sep 18 05:52:24 AM UTC 24
Finished	Sep 18 05:52:39 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459643661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2459643661
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2777172089
Short name	T165
Test name
Test status
Simulation time	26838057939 ps
CPU time	124.75 seconds
Started	Sep 18 05:52:24 AM UTC 24
Finished	Sep 18 05:54:31 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777172089 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.2777172089
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2073066495
Short name	T361
Test name
Test status
Simulation time	45112874 ps
CPU time	3.02 seconds
Started	Sep 18 05:52:31 AM UTC 24
Finished	Sep 18 05:52:35 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073066495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2073066495
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.2682778902
Short name	T367
Test name
Test status
Simulation time	220227182 ps
CPU time	20.83 seconds
Started	Sep 18 05:52:28 AM UTC 24
Finished	Sep 18 05:52:50 AM UTC 24
Peak memory	215716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682778902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2682778902
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.1733360325
Short name	T216
Test name
Test status
Simulation time	493110396 ps
CPU time	24.12 seconds
Started	Sep 18 05:52:17 AM UTC 24
Finished	Sep 18 05:52:43 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733360325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1733360325
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.1841151085
Short name	T399
Test name
Test status
Simulation time	44102977548 ps
CPU time	168.69 seconds
Started	Sep 18 05:52:23 AM UTC 24
Finished	Sep 18 05:55:14 AM UTC 24
Peak memory	217692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841151085 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1841151085
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3792998670
Short name	T168
Test name
Test status
Simulation time	16242897771 ps
CPU time	134.48 seconds
Started	Sep 18 05:52:23 AM UTC 24
Finished	Sep 18 05:54:40 AM UTC 24
Peak memory	215732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792998670 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3792998670
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.2944530237
Short name	T212
Test name
Test status
Simulation time	710098258 ps
CPU time	29.26 seconds
Started	Sep 18 05:52:18 AM UTC 24
Finished	Sep 18 05:52:49 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944530237 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2944530237
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.894567501
Short name	T362
Test name
Test status
Simulation time	293599842 ps
CPU time	14.14 seconds
Started	Sep 18 05:52:27 AM UTC 24
Finished	Sep 18 05:52:42 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894567501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.894567501
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.2240836218
Short name	T353
Test name
Test status
Simulation time	31597666 ps
CPU time	3.4 seconds
Started	Sep 18 05:52:11 AM UTC 24
Finished	Sep 18 05:52:15 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240836218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2240836218
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1984780727
Short name	T176
Test name
Test status
Simulation time	4955936675 ps
CPU time	47.38 seconds
Started	Sep 18 05:52:14 AM UTC 24
Finished	Sep 18 05:53:03 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984780727 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1984780727
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1992421129
Short name	T177
Test name
Test status
Simulation time	4733855364 ps
CPU time	45.55 seconds
Started	Sep 18 05:52:16 AM UTC 24
Finished	Sep 18 05:53:03 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992421129 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1992421129
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.4073352078
Short name	T354
Test name
Test status
Simulation time	96831508 ps
CPU time	2.15 seconds
Started	Sep 18 05:52:13 AM UTC 24
Finished	Sep 18 05:52:16 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073352078 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.4073352078
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.2403171442
Short name	T98
Test name
Test status
Simulation time	2773043591 ps
CPU time	50.77 seconds
Started	Sep 18 05:52:32 AM UTC 24
Finished	Sep 18 05:53:24 AM UTC 24
Peak memory	220136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403171442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2403171442
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.552132291
Short name	T313
Test name
Test status
Simulation time	12664467278 ps
CPU time	184.82 seconds
Started	Sep 18 05:52:34 AM UTC 24
Finished	Sep 18 05:55:42 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552132291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.552132291
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1700195359
Short name	T268
Test name
Test status
Simulation time	4669258352 ps
CPU time	415.52 seconds
Started	Sep 18 05:52:33 AM UTC 24
Finished	Sep 18 05:59:34 AM UTC 24
Peak memory	220308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700195359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.1700195359
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.3648475979
Short name	T369
Test name
Test status
Simulation time	108273355 ps
CPU time	24.71 seconds
Started	Sep 18 05:52:28 AM UTC 24
Finished	Sep 18 05:52:54 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648475979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3648475979
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.4052226765
Short name	T295
Test name
Test status
Simulation time	921525270 ps
CPU time	41.41 seconds
Started	Sep 18 05:52:48 AM UTC 24
Finished	Sep 18 05:53:31 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052226765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.4052226765
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.107256248
Short name	T610
Test name
Test status
Simulation time	122706171536 ps
CPU time	563.89 seconds
Started	Sep 18 05:52:50 AM UTC 24
Finished	Sep 18 06:02:21 AM UTC 24
Peak memory	221540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107256248 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.107256248
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.804811704
Short name	T179
Test name
Test status
Simulation time	271183093 ps
CPU time	12.47 seconds
Started	Sep 18 05:52:55 AM UTC 24
Finished	Sep 18 05:53:09 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804811704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.804811704
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.1496618561
Short name	T184
Test name
Test status
Simulation time	154305236 ps
CPU time	24.38 seconds
Started	Sep 18 05:52:51 AM UTC 24
Finished	Sep 18 05:53:17 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496618561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1496618561
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.4229873506
Short name	T371
Test name
Test status
Simulation time	203116183 ps
CPU time	33.18 seconds
Started	Sep 18 05:52:44 AM UTC 24
Finished	Sep 18 05:53:18 AM UTC 24
Peak memory	215552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229873506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.4229873506
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.4294370603
Short name	T404
Test name
Test status
Simulation time	33251902026 ps
CPU time	158.6 seconds
Started	Sep 18 05:52:44 AM UTC 24
Finished	Sep 18 05:55:25 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294370603 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.4294370603
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.3051671252
Short name	T370
Test name
Test status
Simulation time	284154481 ps
CPU time	32.79 seconds
Started	Sep 18 05:52:44 AM UTC 24
Finished	Sep 18 05:53:18 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051671252 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3051671252
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1666178453
Short name	T111
Test name
Test status
Simulation time	1657280880 ps
CPU time	40.81 seconds
Started	Sep 18 05:52:50 AM UTC 24
Finished	Sep 18 05:53:33 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666178453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1666178453
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.2823543421
Short name	T363
Test name
Test status
Simulation time	36471324 ps
CPU time	3.37 seconds
Started	Sep 18 05:52:38 AM UTC 24
Finished	Sep 18 05:52:42 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823543421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2823543421
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3338760917
Short name	T374
Test name
Test status
Simulation time	6941954170 ps
CPU time	49.55 seconds
Started	Sep 18 05:52:40 AM UTC 24
Finished	Sep 18 05:53:31 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338760917 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3338760917
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2647789756
Short name	T207
Test name
Test status
Simulation time	10128138964 ps
CPU time	56.62 seconds
Started	Sep 18 05:52:43 AM UTC 24
Finished	Sep 18 05:53:42 AM UTC 24
Peak memory	215660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647789756 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2647789756
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.4226994947
Short name	T365
Test name
Test status
Simulation time	38553602 ps
CPU time	3.54 seconds
Started	Sep 18 05:52:39 AM UTC 24
Finished	Sep 18 05:52:44 AM UTC 24
Peak memory	215696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226994947 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.4226994947
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.671566941
Short name	T124
Test name
Test status
Simulation time	2286611612 ps
CPU time	107.91 seconds
Started	Sep 18 05:52:56 AM UTC 24
Finished	Sep 18 05:54:46 AM UTC 24
Peak memory	221988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671566941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.671566941
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2675701793
Short name	T178
Test name
Test status
Simulation time	6536988 ps
CPU time	1.13 seconds
Started	Sep 18 05:53:02 AM UTC 24
Finished	Sep 18 05:53:04 AM UTC 24
Peak memory	203296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675701793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2675701793
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.569059065
Short name	T182
Test name
Test status
Simulation time	77132720 ps
CPU time	11.95 seconds
Started	Sep 18 05:52:58 AM UTC 24
Finished	Sep 18 05:53:11 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569059065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.569059065
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.84322913
Short name	T324
Test name
Test status
Simulation time	5599704773 ps
CPU time	111.76 seconds
Started	Sep 18 05:53:04 AM UTC 24
Finished	Sep 18 05:54:58 AM UTC 24
Peak memory	222060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84322913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.84322913
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.3784754959
Short name	T183
Test name
Test status
Simulation time	109959934 ps
CPU time	18.64 seconds
Started	Sep 18 05:52:52 AM UTC 24
Finished	Sep 18 05:53:12 AM UTC 24
Peak memory	215792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784754959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3784754959
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.1381676510
Short name	T114
Test name
Test status
Simulation time	2444840896 ps
CPU time	68.61 seconds
Started	Sep 18 05:53:19 AM UTC 24
Finished	Sep 18 05:54:29 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381676510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1381676510
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.782555273
Short name	T637
Test name
Test status
Simulation time	172633687698 ps
CPU time	573.29 seconds
Started	Sep 18 05:53:19 AM UTC 24
Finished	Sep 18 06:02:59 AM UTC 24
Peak memory	219432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782555273 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.782555273
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2188601892
Short name	T375
Test name
Test status
Simulation time	164590046 ps
CPU time	7.72 seconds
Started	Sep 18 05:53:26 AM UTC 24
Finished	Sep 18 05:53:34 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188601892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2188601892
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.770339495
Short name	T373
Test name
Test status
Simulation time	59229756 ps
CPU time	5.88 seconds
Started	Sep 18 05:53:23 AM UTC 24
Finished	Sep 18 05:53:30 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770339495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.770339495
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.668510374
Short name	T97
Test name
Test status
Simulation time	150042578 ps
CPU time	9.44 seconds
Started	Sep 18 05:53:12 AM UTC 24
Finished	Sep 18 05:53:22 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668510374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.668510374
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.3535206498
Short name	T186
Test name
Test status
Simulation time	54160702304 ps
CPU time	234.95 seconds
Started	Sep 18 05:53:13 AM UTC 24
Finished	Sep 18 05:57:11 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535206498 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3535206498
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1573907815
Short name	T464
Test name
Test status
Simulation time	24920280335 ps
CPU time	244.58 seconds
Started	Sep 18 05:53:18 AM UTC 24
Finished	Sep 18 05:57:26 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573907815 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1573907815
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.3713718400
Short name	T372
Test name
Test status
Simulation time	76149651 ps
CPU time	9.97 seconds
Started	Sep 18 05:53:12 AM UTC 24
Finished	Sep 18 05:53:23 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713718400 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3713718400
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.2186381073
Short name	T44
Test name
Test status
Simulation time	1042164244 ps
CPU time	16.52 seconds
Started	Sep 18 05:53:23 AM UTC 24
Finished	Sep 18 05:53:41 AM UTC 24
Peak memory	215736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186381073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2186381073
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.1615017028
Short name	T181
Test name
Test status
Simulation time	287991836 ps
CPU time	4.85 seconds
Started	Sep 18 05:53:04 AM UTC 24
Finished	Sep 18 05:53:10 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615017028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1615017028
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1862125072
Short name	T32
Test name
Test status
Simulation time	6833777265 ps
CPU time	37.74 seconds
Started	Sep 18 05:53:10 AM UTC 24
Finished	Sep 18 05:53:49 AM UTC 24
Peak memory	215960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862125072 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1862125072
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.259675215
Short name	T378
Test name
Test status
Simulation time	4333371474 ps
CPU time	35.9 seconds
Started	Sep 18 05:53:10 AM UTC 24
Finished	Sep 18 05:53:48 AM UTC 24
Peak memory	215884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259675215 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.259675215
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3527005995
Short name	T180
Test name
Test status
Simulation time	35998462 ps
CPU time	2.77 seconds
Started	Sep 18 05:53:05 AM UTC 24
Finished	Sep 18 05:53:09 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527005995 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3527005995
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.3212904497
Short name	T317
Test name
Test status
Simulation time	12557954701 ps
CPU time	304.61 seconds
Started	Sep 18 05:53:27 AM UTC 24
Finished	Sep 18 05:58:36 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212904497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3212904497
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1150407049
Short name	T385
Test name
Test status
Simulation time	1903001435 ps
CPU time	48.54 seconds
Started	Sep 18 05:53:31 AM UTC 24
Finished	Sep 18 05:54:21 AM UTC 24
Peak memory	215716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150407049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1150407049
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.120242477
Short name	T45
Test name
Test status
Simulation time	446088584 ps
CPU time	106.76 seconds
Started	Sep 18 05:53:31 AM UTC 24
Finished	Sep 18 05:55:20 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120242477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.120242477
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1617772163
Short name	T428
Test name
Test status
Simulation time	2455585392 ps
CPU time	155.28 seconds
Started	Sep 18 05:53:34 AM UTC 24
Finished	Sep 18 05:56:12 AM UTC 24
Peak memory	222000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617772163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.1617772163
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.615371781
Short name	T245
Test name
Test status
Simulation time	2459146869 ps
CPU time	33.33 seconds
Started	Sep 18 05:53:24 AM UTC 24
Finished	Sep 18 05:53:59 AM UTC 24
Peak memory	217900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615371781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.615371781
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.713342441
Short name	T117
Test name
Test status
Simulation time	1257325468 ps
CPU time	57.5 seconds
Started	Sep 18 05:53:50 AM UTC 24
Finished	Sep 18 05:54:49 AM UTC 24
Peak memory	218088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713342441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.713342441
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3243314744
Short name	T816
Test name
Test status
Simulation time	78174689467 ps
CPU time	852.34 seconds
Started	Sep 18 05:53:50 AM UTC 24
Finished	Sep 18 06:08:13 AM UTC 24
Peak memory	221608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243314744 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.3243314744
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.846778639
Short name	T380
Test name
Test status
Simulation time	81895693 ps
CPU time	5.94 seconds
Started	Sep 18 05:54:03 AM UTC 24
Finished	Sep 18 05:54:10 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846778639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.846778639
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.2297454887
Short name	T167
Test name
Test status
Simulation time	1711544033 ps
CPU time	32.07 seconds
Started	Sep 18 05:54:01 AM UTC 24
Finished	Sep 18 05:54:34 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297454887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2297454887
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.2554121586
Short name	T297
Test name
Test status
Simulation time	665069155 ps
CPU time	22.83 seconds
Started	Sep 18 05:53:40 AM UTC 24
Finished	Sep 18 05:54:04 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554121586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2554121586
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.1947244627
Short name	T257
Test name
Test status
Simulation time	25856294226 ps
CPU time	172.14 seconds
Started	Sep 18 05:53:44 AM UTC 24
Finished	Sep 18 05:56:39 AM UTC 24
Peak memory	217888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947244627 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1947244627
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3220722574
Short name	T432
Test name
Test status
Simulation time	41928553606 ps
CPU time	147.66 seconds
Started	Sep 18 05:53:48 AM UTC 24
Finished	Sep 18 05:56:18 AM UTC 24
Peak memory	216104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220722574 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3220722574
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.3371719260
Short name	T381
Test name
Test status
Simulation time	189022090 ps
CPU time	29.25 seconds
Started	Sep 18 05:53:42 AM UTC 24
Finished	Sep 18 05:54:12 AM UTC 24
Peak memory	217824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371719260 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3371719260
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.4033041198
Short name	T298
Test name
Test status
Simulation time	168553898 ps
CPU time	5.34 seconds
Started	Sep 18 05:53:58 AM UTC 24
Finished	Sep 18 05:54:05 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033041198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.4033041198
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.1775635150
Short name	T376
Test name
Test status
Simulation time	144536904 ps
CPU time	3.26 seconds
Started	Sep 18 05:53:34 AM UTC 24
Finished	Sep 18 05:53:38 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775635150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1775635150
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1775958030
Short name	T379
Test name
Test status
Simulation time	11092164378 ps
CPU time	33.07 seconds
Started	Sep 18 05:53:35 AM UTC 24
Finished	Sep 18 05:54:10 AM UTC 24
Peak memory	216088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775958030 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1775958030
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3708988485
Short name	T387
Test name
Test status
Simulation time	19021277521 ps
CPU time	47.83 seconds
Started	Sep 18 05:53:40 AM UTC 24
Finished	Sep 18 05:54:29 AM UTC 24
Peak memory	216080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708988485 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3708988485
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2755403794
Short name	T377
Test name
Test status
Simulation time	104425155 ps
CPU time	3.55 seconds
Started	Sep 18 05:53:34 AM UTC 24
Finished	Sep 18 05:53:39 AM UTC 24
Peak memory	215692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755403794 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2755403794
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.3120240470
Short name	T217
Test name
Test status
Simulation time	10071173671 ps
CPU time	117.54 seconds
Started	Sep 18 05:54:05 AM UTC 24
Finished	Sep 18 05:56:05 AM UTC 24
Peak memory	220204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120240470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3120240470
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.844313066
Short name	T398
Test name
Test status
Simulation time	1049901042 ps
CPU time	66.96 seconds
Started	Sep 18 05:54:05 AM UTC 24
Finished	Sep 18 05:55:14 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844313066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.844313066
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3423706302
Short name	T299
Test name
Test status
Simulation time	6988358 ps
CPU time	1.26 seconds
Started	Sep 18 05:54:05 AM UTC 24
Finished	Sep 18 05:54:07 AM UTC 24
Peak memory	203304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423706302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.3423706302
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2640682128
Short name	T402
Test name
Test status
Simulation time	306492475 ps
CPU time	65.17 seconds
Started	Sep 18 05:54:09 AM UTC 24
Finished	Sep 18 05:55:16 AM UTC 24
Peak memory	220144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640682128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2640682128
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.754361165
Short name	T382
Test name
Test status
Simulation time	49345545 ps
CPU time	11.43 seconds
Started	Sep 18 05:54:01 AM UTC 24
Finished	Sep 18 05:54:13 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754361165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.754361165
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.2676996103
Short name	T116
Test name
Test status
Simulation time	593600401 ps
CPU time	25.73 seconds
Started	Sep 18 05:54:21 AM UTC 24
Finished	Sep 18 05:54:48 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676996103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2676996103
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.4253793756
Short name	T430
Test name
Test status
Simulation time	22513917181 ps
CPU time	108.17 seconds
Started	Sep 18 05:54:23 AM UTC 24
Finished	Sep 18 05:56:13 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253793756 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.4253793756
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1141273397
Short name	T130
Test name
Test status
Simulation time	185289327 ps
CPU time	19.36 seconds
Started	Sep 18 05:54:32 AM UTC 24
Finished	Sep 18 05:54:53 AM UTC 24
Peak memory	215720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141273397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1141273397
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.3981492585
Short name	T391
Test name
Test status
Simulation time	1841372225 ps
CPU time	31.4 seconds
Started	Sep 18 05:54:30 AM UTC 24
Finished	Sep 18 05:55:03 AM UTC 24
Peak memory	215608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981492585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3981492585
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.2307489315
Short name	T125
Test name
Test status
Simulation time	210365253 ps
CPU time	32.65 seconds
Started	Sep 18 05:54:16 AM UTC 24
Finished	Sep 18 05:54:50 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307489315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2307489315
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.3202549954
Short name	T444
Test name
Test status
Simulation time	23084281575 ps
CPU time	130.05 seconds
Started	Sep 18 05:54:18 AM UTC 24
Finished	Sep 18 05:56:30 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202549954 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3202549954
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.325626006
Short name	T258
Test name
Test status
Simulation time	12749366053 ps
CPU time	141.68 seconds
Started	Sep 18 05:54:21 AM UTC 24
Finished	Sep 18 05:56:45 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325626006 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.325626006
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.1438337764
Short name	T169
Test name
Test status
Simulation time	311892586 ps
CPU time	21.71 seconds
Started	Sep 18 05:54:18 AM UTC 24
Finished	Sep 18 05:54:41 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438337764 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1438337764
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.2121321222
Short name	T393
Test name
Test status
Simulation time	1795319361 ps
CPU time	36.76 seconds
Started	Sep 18 05:54:30 AM UTC 24
Finished	Sep 18 05:55:08 AM UTC 24
Peak memory	215712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121321222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2121321222
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.3291007998
Short name	T383
Test name
Test status
Simulation time	48170998 ps
CPU time	3.04 seconds
Started	Sep 18 05:54:11 AM UTC 24
Finished	Sep 18 05:54:16 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291007998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3291007998
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2229454860
Short name	T389
Test name
Test status
Simulation time	6807165781 ps
CPU time	43.74 seconds
Started	Sep 18 05:54:14 AM UTC 24
Finished	Sep 18 05:54:59 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229454860 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2229454860
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2517004086
Short name	T394
Test name
Test status
Simulation time	12091558642 ps
CPU time	55.11 seconds
Started	Sep 18 05:54:14 AM UTC 24
Finished	Sep 18 05:55:10 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517004086 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2517004086
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2343509370
Short name	T384
Test name
Test status
Simulation time	33291891 ps
CPU time	3.65 seconds
Started	Sep 18 05:54:11 AM UTC 24
Finished	Sep 18 05:54:16 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343509370 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2343509370
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.1185565020
Short name	T263
Test name
Test status
Simulation time	3410915938 ps
CPU time	131.32 seconds
Started	Sep 18 05:54:34 AM UTC 24
Finished	Sep 18 05:56:48 AM UTC 24
Peak memory	219940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185565020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1185565020
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2510081182
Short name	T437
Test name
Test status
Simulation time	3262416122 ps
CPU time	98.1 seconds
Started	Sep 18 05:54:41 AM UTC 24
Finished	Sep 18 05:56:22 AM UTC 24
Peak memory	216040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510081182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2510081182
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2287498303
Short name	T483
Test name
Test status
Simulation time	1041371396 ps
CPU time	216.23 seconds
Started	Sep 18 05:54:42 AM UTC 24
Finished	Sep 18 05:58:21 AM UTC 24
Peak memory	222476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287498303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.2287498303
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.2736666084
Short name	T129
Test name
Test status
Simulation time	227057979 ps
CPU time	18.78 seconds
Started	Sep 18 05:54:32 AM UTC 24
Finished	Sep 18 05:54:52 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736666084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2736666084
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.7939103
Short name	T118
Test name
Test status
Simulation time	4026662401 ps
CPU time	34.31 seconds
Started	Sep 18 05:54:52 AM UTC 24
Finished	Sep 18 05:55:28 AM UTC 24
Peak memory	218024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7939103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.7939103
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.112801514
Short name	T315
Test name
Test status
Simulation time	48465757663 ps
CPU time	346.79 seconds
Started	Sep 18 05:54:53 AM UTC 24
Finished	Sep 18 06:00:44 AM UTC 24
Peak memory	217900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112801514 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.112801514
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2308229702
Short name	T400
Test name
Test status
Simulation time	331134440 ps
CPU time	14.25 seconds
Started	Sep 18 05:55:00 AM UTC 24
Finished	Sep 18 05:55:15 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308229702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2308229702
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.3925787376
Short name	T392
Test name
Test status
Simulation time	71987697 ps
CPU time	6.38 seconds
Started	Sep 18 05:54:57 AM UTC 24
Finished	Sep 18 05:55:05 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925787376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3925787376
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.1913895656
Short name	T388
Test name
Test status
Simulation time	36965795 ps
CPU time	4.83 seconds
Started	Sep 18 05:54:51 AM UTC 24
Finished	Sep 18 05:54:57 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913895656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1913895656
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.750138173
Short name	T308
Test name
Test status
Simulation time	51517218806 ps
CPU time	315 seconds
Started	Sep 18 05:54:52 AM UTC 24
Finished	Sep 18 06:00:11 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750138173 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.750138173
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1557279863
Short name	T485
Test name
Test status
Simulation time	31219922948 ps
CPU time	207.8 seconds
Started	Sep 18 05:54:52 AM UTC 24
Finished	Sep 18 05:58:23 AM UTC 24
Peak memory	217904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557279863 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1557279863
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.3704897634
Short name	T390
Test name
Test status
Simulation time	47248664 ps
CPU time	7.7 seconds
Started	Sep 18 05:54:51 AM UTC 24
Finished	Sep 18 05:55:00 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704897634 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3704897634
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.3618426180
Short name	T403
Test name
Test status
Simulation time	221869295 ps
CPU time	22.52 seconds
Started	Sep 18 05:54:54 AM UTC 24
Finished	Sep 18 05:55:18 AM UTC 24
Peak memory	216040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618426180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3618426180
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.3851137791
Short name	T126
Test name
Test status
Simulation time	387721089 ps
CPU time	3.68 seconds
Started	Sep 18 05:54:46 AM UTC 24
Finished	Sep 18 05:54:50 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851137791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3851137791
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2308614502
Short name	T281
Test name
Test status
Simulation time	6496739201 ps
CPU time	52.53 seconds
Started	Sep 18 05:54:48 AM UTC 24
Finished	Sep 18 05:55:43 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308614502 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2308614502
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3334073993
Short name	T413
Test name
Test status
Simulation time	7365103369 ps
CPU time	55.46 seconds
Started	Sep 18 05:54:49 AM UTC 24
Finished	Sep 18 05:55:46 AM UTC 24
Peak memory	216080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334073993 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3334073993
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3888425302
Short name	T128
Test name
Test status
Simulation time	22153339 ps
CPU time	2.17 seconds
Started	Sep 18 05:54:48 AM UTC 24
Finished	Sep 18 05:54:51 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888425302 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3888425302
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.3520395504
Short name	T474
Test name
Test status
Simulation time	1523523786 ps
CPU time	172.54 seconds
Started	Sep 18 05:55:00 AM UTC 24
Finished	Sep 18 05:57:55 AM UTC 24
Peak memory	221860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520395504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3520395504
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.667229127
Short name	T414
Test name
Test status
Simulation time	370152921 ps
CPU time	44.45 seconds
Started	Sep 18 05:55:01 AM UTC 24
Finished	Sep 18 05:55:47 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667229127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.667229127
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3223429692
Short name	T433
Test name
Test status
Simulation time	125601064 ps
CPU time	76.69 seconds
Started	Sep 18 05:55:00 AM UTC 24
Finished	Sep 18 05:56:19 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223429692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.3223429692
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1208152519
Short name	T401
Test name
Test status
Simulation time	23983933 ps
CPU time	10.85 seconds
Started	Sep 18 05:55:03 AM UTC 24
Finished	Sep 18 05:55:15 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208152519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.1208152519
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.2134440989
Short name	T395
Test name
Test status
Simulation time	268235637 ps
CPU time	11.7 seconds
Started	Sep 18 05:54:59 AM UTC 24
Finished	Sep 18 05:55:11 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134440989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2134440989
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.3417364750
Short name	T416
Test name
Test status
Simulation time	289986516 ps
CPU time	31.99 seconds
Started	Sep 18 05:55:16 AM UTC 24
Finished	Sep 18 05:55:49 AM UTC 24
Peak memory	217764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417364750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3417364750
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2267412608
Short name	T861
Test name
Test status
Simulation time	204671563159 ps
CPU time	847.65 seconds
Started	Sep 18 05:55:16 AM UTC 24
Finished	Sep 18 06:09:33 AM UTC 24
Peak memory	221608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267412608 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.2267412608
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2197877923
Short name	T407
Test name
Test status
Simulation time	26928846 ps
CPU time	4.28 seconds
Started	Sep 18 05:55:25 AM UTC 24
Finished	Sep 18 05:55:31 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197877923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2197877923
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.1708057314
Short name	T410
Test name
Test status
Simulation time	155960574 ps
CPU time	19.7 seconds
Started	Sep 18 05:55:19 AM UTC 24
Finished	Sep 18 05:55:40 AM UTC 24
Peak memory	215712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708057314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1708057314
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.3548298778
Short name	T421
Test name
Test status
Simulation time	5925032714 ps
CPU time	43.18 seconds
Started	Sep 18 05:55:12 AM UTC 24
Finished	Sep 18 05:55:57 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548298778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3548298778
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.894578571
Short name	T274
Test name
Test status
Simulation time	39974230252 ps
CPU time	160.51 seconds
Started	Sep 18 05:55:15 AM UTC 24
Finished	Sep 18 05:57:58 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894578571 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.894578571
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1669815920
Short name	T187
Test name
Test status
Simulation time	18798698195 ps
CPU time	159.32 seconds
Started	Sep 18 05:55:15 AM UTC 24
Finished	Sep 18 05:57:57 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669815920 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1669815920
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.182350145
Short name	T412
Test name
Test status
Simulation time	474626326 ps
CPU time	28.6 seconds
Started	Sep 18 05:55:14 AM UTC 24
Finished	Sep 18 05:55:43 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182350145 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.182350145
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.3756452642
Short name	T409
Test name
Test status
Simulation time	226715230 ps
CPU time	20.03 seconds
Started	Sep 18 05:55:17 AM UTC 24
Finished	Sep 18 05:55:39 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756452642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3756452642
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.137715238
Short name	T396
Test name
Test status
Simulation time	128750216 ps
CPU time	4.96 seconds
Started	Sep 18 05:55:06 AM UTC 24
Finished	Sep 18 05:55:12 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137715238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.137715238
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2095303809
Short name	T415
Test name
Test status
Simulation time	16879546675 ps
CPU time	36.3 seconds
Started	Sep 18 05:55:11 AM UTC 24
Finished	Sep 18 05:55:49 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095303809 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2095303809
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3212978160
Short name	T67
Test name
Test status
Simulation time	4572395040 ps
CPU time	35.88 seconds
Started	Sep 18 05:55:12 AM UTC 24
Finished	Sep 18 05:55:49 AM UTC 24
Peak memory	216144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212978160 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3212978160
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3237213700
Short name	T397
Test name
Test status
Simulation time	44649404 ps
CPU time	2.9 seconds
Started	Sep 18 05:55:09 AM UTC 24
Finished	Sep 18 05:55:13 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237213700 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3237213700
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.1412649540
Short name	T406
Test name
Test status
Simulation time	6928112 ps
CPU time	1.32 seconds
Started	Sep 18 05:55:28 AM UTC 24
Finished	Sep 18 05:55:31 AM UTC 24
Peak memory	203292 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412649540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1412649540
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.757029339
Short name	T418
Test name
Test status
Simulation time	477297188 ps
CPU time	21.17 seconds
Started	Sep 18 05:55:30 AM UTC 24
Finished	Sep 18 05:55:52 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757029339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.757029339
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.139958889
Short name	T230
Test name
Test status
Simulation time	2755059785 ps
CPU time	84.36 seconds
Started	Sep 18 05:55:28 AM UTC 24
Finished	Sep 18 05:56:55 AM UTC 24
Peak memory	220204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139958889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.139958889
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1582075095
Short name	T604
Test name
Test status
Simulation time	5323610497 ps
CPU time	395.5 seconds
Started	Sep 18 05:55:32 AM UTC 24
Finished	Sep 18 06:02:13 AM UTC 24
Peak memory	232848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582075095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.1582075095
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.1851615319
Short name	T405
Test name
Test status
Simulation time	123110012 ps
CPU time	4.82 seconds
Started	Sep 18 05:55:21 AM UTC 24
Finished	Sep 18 05:55:27 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851615319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1851615319
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.1414798000
Short name	T419
Test name
Test status
Simulation time	205010139 ps
CPU time	7.94 seconds
Started	Sep 18 05:55:44 AM UTC 24
Finished	Sep 18 05:55:53 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414798000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1414798000
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2498200003
Short name	T148
Test name
Test status
Simulation time	174005814980 ps
CPU time	531.22 seconds
Started	Sep 18 05:55:44 AM UTC 24
Finished	Sep 18 06:04:42 AM UTC 24
Peak memory	219560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498200003 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2498200003
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2933009030
Short name	T436
Test name
Test status
Simulation time	1250283050 ps
CPU time	28.43 seconds
Started	Sep 18 05:55:50 AM UTC 24
Finished	Sep 18 05:56:20 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933009030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2933009030
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.3460762411
Short name	T420
Test name
Test status
Simulation time	37026849 ps
CPU time	5.21 seconds
Started	Sep 18 05:55:48 AM UTC 24
Finished	Sep 18 05:55:54 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460762411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3460762411
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.2291628810
Short name	T417
Test name
Test status
Simulation time	245437723 ps
CPU time	10.95 seconds
Started	Sep 18 05:55:40 AM UTC 24
Finished	Sep 18 05:55:52 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291628810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2291628810
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.2013456644
Short name	T523
Test name
Test status
Simulation time	45540330201 ps
CPU time	250.18 seconds
Started	Sep 18 05:55:43 AM UTC 24
Finished	Sep 18 05:59:57 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013456644 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2013456644
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2439048341
Short name	T131
Test name
Test status
Simulation time	46103594410 ps
CPU time	202.49 seconds
Started	Sep 18 05:55:43 AM UTC 24
Finished	Sep 18 05:59:09 AM UTC 24
Peak memory	216104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439048341 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2439048341
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.369354758
Short name	T425
Test name
Test status
Simulation time	216964025 ps
CPU time	25.83 seconds
Started	Sep 18 05:55:41 AM UTC 24
Finished	Sep 18 05:56:08 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369354758 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.369354758
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.569102477
Short name	T270
Test name
Test status
Simulation time	1545492213 ps
CPU time	29.61 seconds
Started	Sep 18 05:55:48 AM UTC 24
Finished	Sep 18 05:56:19 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569102477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.569102477
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.4080188462
Short name	T408
Test name
Test status
Simulation time	210647415 ps
CPU time	3.78 seconds
Started	Sep 18 05:55:32 AM UTC 24
Finished	Sep 18 05:55:37 AM UTC 24
Peak memory	215956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080188462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.4080188462
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1914527619
Short name	T443
Test name
Test status
Simulation time	16231060685 ps
CPU time	51.2 seconds
Started	Sep 18 05:55:37 AM UTC 24
Finished	Sep 18 05:56:30 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914527619 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1914527619
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3564939244
Short name	T68
Test name
Test status
Simulation time	3269620884 ps
CPU time	24.33 seconds
Started	Sep 18 05:55:38 AM UTC 24
Finished	Sep 18 05:56:04 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564939244 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3564939244
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.33915486
Short name	T411
Test name
Test status
Simulation time	34289576 ps
CPU time	3.45 seconds
Started	Sep 18 05:55:37 AM UTC 24
Finished	Sep 18 05:55:42 AM UTC 24
Peak memory	215948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33915486 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.33915486
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.3262637267
Short name	T48
Test name
Test status
Simulation time	4240411880 ps
CPU time	145.4 seconds
Started	Sep 18 05:55:51 AM UTC 24
Finished	Sep 18 05:58:19 AM UTC 24
Peak memory	218088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262637267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3262637267
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1191961921
Short name	T455
Test name
Test status
Simulation time	1910165590 ps
CPU time	79.15 seconds
Started	Sep 18 05:55:53 AM UTC 24
Finished	Sep 18 05:57:14 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191961921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1191961921
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2081109650
Short name	T465
Test name
Test status
Simulation time	278003021 ps
CPU time	93.85 seconds
Started	Sep 18 05:55:51 AM UTC 24
Finished	Sep 18 05:57:26 AM UTC 24
Peak memory	220076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081109650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.2081109650
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3956170651
Short name	T314
Test name
Test status
Simulation time	3589622318 ps
CPU time	178.12 seconds
Started	Sep 18 05:55:53 AM UTC 24
Finished	Sep 18 05:58:54 AM UTC 24
Peak memory	222192 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956170651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.3956170651
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.3281447981
Short name	T427
Test name
Test status
Simulation time	707172774 ps
CPU time	19.07 seconds
Started	Sep 18 05:55:50 AM UTC 24
Finished	Sep 18 05:56:11 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281447981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3281447981
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.170126743
Short name	T224
Test name
Test status
Simulation time	34223328261 ps
CPU time	198.24 seconds
Started	Sep 18 05:47:43 AM UTC 24
Finished	Sep 18 05:51:05 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170126743 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.170126743
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.4021161790
Short name	T80
Test name
Test status
Simulation time	582073120 ps
CPU time	22.68 seconds
Started	Sep 18 05:47:51 AM UTC 24
Finished	Sep 18 05:48:15 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021161790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.4021161790
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.3128390016
Short name	T84
Test name
Test status
Simulation time	3373228497 ps
CPU time	37.05 seconds
Started	Sep 18 05:47:47 AM UTC 24
Finished	Sep 18 05:48:26 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128390016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3128390016
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.28960782
Short name	T77
Test name
Test status
Simulation time	224667783 ps
CPU time	26.04 seconds
Started	Sep 18 05:47:39 AM UTC 24
Finished	Sep 18 05:48:06 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28960782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.28960782
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.2159872873
Short name	T312
Test name
Test status
Simulation time	99811874677 ps
CPU time	170.25 seconds
Started	Sep 18 05:47:40 AM UTC 24
Finished	Sep 18 05:50:33 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159872873 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2159872873
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.353391069
Short name	T41
Test name
Test status
Simulation time	16965563947 ps
CPU time	61.8 seconds
Started	Sep 18 05:47:41 AM UTC 24
Finished	Sep 18 05:48:45 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353391069 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.353391069
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.23675629
Short name	T22
Test name
Test status
Simulation time	132292463 ps
CPU time	13.14 seconds
Started	Sep 18 05:47:40 AM UTC 24
Finished	Sep 18 05:47:54 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23675629 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.23675629
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.3160295988
Short name	T57
Test name
Test status
Simulation time	1530043218 ps
CPU time	14.05 seconds
Started	Sep 18 05:47:45 AM UTC 24
Finished	Sep 18 05:48:00 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160295988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3160295988
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.3707552695
Short name	T43
Test name
Test status
Simulation time	26120865 ps
CPU time	2.13 seconds
Started	Sep 18 05:47:36 AM UTC 24
Finished	Sep 18 05:47:39 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707552695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3707552695
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3273522515
Short name	T81
Test name
Test status
Simulation time	7110332815 ps
CPU time	41.31 seconds
Started	Sep 18 05:47:36 AM UTC 24
Finished	Sep 18 05:48:18 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273522515 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3273522515
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2298763006
Short name	T59
Test name
Test status
Simulation time	5460235027 ps
CPU time	35.5 seconds
Started	Sep 18 05:47:37 AM UTC 24
Finished	Sep 18 05:48:14 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298763006 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2298763006
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3906021250
Short name	T78
Test name
Test status
Simulation time	61099357 ps
CPU time	3.33 seconds
Started	Sep 18 05:47:36 AM UTC 24
Finished	Sep 18 05:47:40 AM UTC 24
Peak memory	215948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906021250 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3906021250
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.590095104
Short name	T333
Test name
Test status
Simulation time	1714912478 ps
CPU time	105.59 seconds
Started	Sep 18 05:47:56 AM UTC 24
Finished	Sep 18 05:49:43 AM UTC 24
Peak memory	217764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590095104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.590095104
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.719476720
Short name	T26
Test name
Test status
Simulation time	4074534457 ps
CPU time	296.29 seconds
Started	Sep 18 05:47:56 AM UTC 24
Finished	Sep 18 05:52:56 AM UTC 24
Peak memory	219952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719476720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.719476720
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2767308948
Short name	T322
Test name
Test status
Simulation time	7508507948 ps
CPU time	266.5 seconds
Started	Sep 18 05:47:57 AM UTC 24
Finished	Sep 18 05:52:27 AM UTC 24
Peak memory	232620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767308948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.2767308948
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.3043830529
Short name	T24
Test name
Test status
Simulation time	593219045 ps
CPU time	17.45 seconds
Started	Sep 18 05:47:50 AM UTC 24
Finished	Sep 18 05:48:09 AM UTC 24
Peak memory	217760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043830529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3043830529
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.2993043007
Short name	T434
Test name
Test status
Simulation time	451756123 ps
CPU time	12.66 seconds
Started	Sep 18 05:56:06 AM UTC 24
Finished	Sep 18 05:56:20 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993043007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2993043007
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2275232753
Short name	T546
Test name
Test status
Simulation time	46813744097 ps
CPU time	269.08 seconds
Started	Sep 18 05:56:06 AM UTC 24
Finished	Sep 18 06:00:39 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275232753 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.2275232753
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2490171092
Short name	T441
Test name
Test status
Simulation time	629781062 ps
CPU time	13.46 seconds
Started	Sep 18 05:56:13 AM UTC 24
Finished	Sep 18 05:56:28 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490171092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2490171092
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.767655131
Short name	T429
Test name
Test status
Simulation time	16913219 ps
CPU time	2.85 seconds
Started	Sep 18 05:56:09 AM UTC 24
Finished	Sep 18 05:56:12 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767655131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.767655131
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.1342338878
Short name	T431
Test name
Test status
Simulation time	92188179 ps
CPU time	13.72 seconds
Started	Sep 18 05:55:59 AM UTC 24
Finished	Sep 18 05:56:14 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342338878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1342338878
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.2594825271
Short name	T563
Test name
Test status
Simulation time	217779530925 ps
CPU time	307.55 seconds
Started	Sep 18 05:56:01 AM UTC 24
Finished	Sep 18 06:01:12 AM UTC 24
Peak memory	216160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594825271 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2594825271
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3857133176
Short name	T447
Test name
Test status
Simulation time	4713660828 ps
CPU time	49.87 seconds
Started	Sep 18 05:56:05 AM UTC 24
Finished	Sep 18 05:56:56 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857133176 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3857133176
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.2460966694
Short name	T435
Test name
Test status
Simulation time	170852881 ps
CPU time	19.33 seconds
Started	Sep 18 05:55:59 AM UTC 24
Finished	Sep 18 05:56:20 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460966694 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2460966694
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.3988310015
Short name	T440
Test name
Test status
Simulation time	1916657403 ps
CPU time	14.84 seconds
Started	Sep 18 05:56:09 AM UTC 24
Finished	Sep 18 05:56:25 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988310015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3988310015
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.985130878
Short name	T423
Test name
Test status
Simulation time	52711658 ps
CPU time	3.18 seconds
Started	Sep 18 05:55:54 AM UTC 24
Finished	Sep 18 05:55:59 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985130878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.985130878
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3204033266
Short name	T185
Test name
Test status
Simulation time	5387561965 ps
CPU time	32.9 seconds
Started	Sep 18 05:55:57 AM UTC 24
Finished	Sep 18 05:56:31 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204033266 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3204033266
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.776025128
Short name	T445
Test name
Test status
Simulation time	2634621873 ps
CPU time	35.73 seconds
Started	Sep 18 05:55:58 AM UTC 24
Finished	Sep 18 05:56:35 AM UTC 24
Peak memory	216016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776025128 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.776025128
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2899839357
Short name	T424
Test name
Test status
Simulation time	30582281 ps
CPU time	3.57 seconds
Started	Sep 18 05:55:54 AM UTC 24
Finished	Sep 18 05:55:59 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899839357 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2899839357
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.2751102494
Short name	T454
Test name
Test status
Simulation time	484089413 ps
CPU time	56.88 seconds
Started	Sep 18 05:56:13 AM UTC 24
Finished	Sep 18 05:57:12 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751102494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2751102494
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1468171880
Short name	T316
Test name
Test status
Simulation time	4890538288 ps
CPU time	149.4 seconds
Started	Sep 18 05:56:15 AM UTC 24
Finished	Sep 18 05:58:48 AM UTC 24
Peak memory	222056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468171880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1468171880
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3331705831
Short name	T265
Test name
Test status
Simulation time	130964504 ps
CPU time	29.07 seconds
Started	Sep 18 05:56:19 AM UTC 24
Finished	Sep 18 05:56:49 AM UTC 24
Peak memory	217840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331705831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3331705831
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.3224711599
Short name	T310
Test name
Test status
Simulation time	1239601500 ps
CPU time	42.03 seconds
Started	Sep 18 05:56:12 AM UTC 24
Finished	Sep 18 05:56:55 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224711599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3224711599
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1487463604
Short name	T815
Test name
Test status
Simulation time	78757920232 ps
CPU time	694.74 seconds
Started	Sep 18 05:56:26 AM UTC 24
Finished	Sep 18 06:08:10 AM UTC 24
Peak memory	219816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487463604 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.1487463604
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2221590677
Short name	T448
Test name
Test status
Simulation time	1959168587 ps
CPU time	27.06 seconds
Started	Sep 18 05:56:31 AM UTC 24
Finished	Sep 18 05:56:59 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221590677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2221590677
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2389599585
Short name	T261
Test name
Test status
Simulation time	532521169 ps
CPU time	16.45 seconds
Started	Sep 18 05:56:30 AM UTC 24
Finished	Sep 18 05:56:47 AM UTC 24
Peak memory	215720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389599585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2389599585
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.1688250617
Short name	T442
Test name
Test status
Simulation time	257268731 ps
CPU time	6.39 seconds
Started	Sep 18 05:56:22 AM UTC 24
Finished	Sep 18 05:56:29 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688250617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1688250617
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.1240059437
Short name	T189
Test name
Test status
Simulation time	78466875496 ps
CPU time	192.66 seconds
Started	Sep 18 05:56:24 AM UTC 24
Finished	Sep 18 05:59:40 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240059437 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1240059437
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2953823750
Short name	T267
Test name
Test status
Simulation time	4904912659 ps
CPU time	45.84 seconds
Started	Sep 18 05:56:25 AM UTC 24
Finished	Sep 18 05:57:12 AM UTC 24
Peak memory	215468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953823750 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2953823750
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.2646770334
Short name	T260
Test name
Test status
Simulation time	293980253 ps
CPU time	21.33 seconds
Started	Sep 18 05:56:23 AM UTC 24
Finished	Sep 18 05:56:45 AM UTC 24
Peak memory	215712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646770334 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2646770334
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.3963552800
Short name	T262
Test name
Test status
Simulation time	291477136 ps
CPU time	16.88 seconds
Started	Sep 18 05:56:30 AM UTC 24
Finished	Sep 18 05:56:48 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963552800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3963552800
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.1622448240
Short name	T439
Test name
Test status
Simulation time	31147372 ps
CPU time	2.94 seconds
Started	Sep 18 05:56:20 AM UTC 24
Finished	Sep 18 05:56:24 AM UTC 24
Peak memory	215696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622448240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1622448240
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2227209053
Short name	T237
Test name
Test status
Simulation time	18076861541 ps
CPU time	62.49 seconds
Started	Sep 18 05:56:21 AM UTC 24
Finished	Sep 18 05:57:26 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227209053 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2227209053
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.768650902
Short name	T460
Test name
Test status
Simulation time	5416330579 ps
CPU time	54.47 seconds
Started	Sep 18 05:56:21 AM UTC 24
Finished	Sep 18 05:57:17 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768650902 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.768650902
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2740153281
Short name	T438
Test name
Test status
Simulation time	28993665 ps
CPU time	2.43 seconds
Started	Sep 18 05:56:20 AM UTC 24
Finished	Sep 18 05:56:23 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740153281 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2740153281
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.4020055131
Short name	T493
Test name
Test status
Simulation time	2884545383 ps
CPU time	125.2 seconds
Started	Sep 18 05:56:32 AM UTC 24
Finished	Sep 18 05:58:40 AM UTC 24
Peak memory	219944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020055131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.4020055131
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2398128545
Short name	T279
Test name
Test status
Simulation time	2678887682 ps
CPU time	82.25 seconds
Started	Sep 18 05:56:39 AM UTC 24
Finished	Sep 18 05:58:03 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398128545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2398128545
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3038886651
Short name	T550
Test name
Test status
Simulation time	6687923306 ps
CPU time	243.64 seconds
Started	Sep 18 05:56:36 AM UTC 24
Finished	Sep 18 06:00:43 AM UTC 24
Peak memory	222252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038886651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.3038886651
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3848379716
Short name	T675
Test name
Test status
Simulation time	16439149444 ps
CPU time	443.66 seconds
Started	Sep 18 05:56:40 AM UTC 24
Finished	Sep 18 06:04:10 AM UTC 24
Peak memory	232848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848379716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.3848379716
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.1132869385
Short name	T259
Test name
Test status
Simulation time	93717814 ps
CPU time	12.51 seconds
Started	Sep 18 05:56:31 AM UTC 24
Finished	Sep 18 05:56:45 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132869385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1132869385
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.2832171891
Short name	T450
Test name
Test status
Simulation time	360635260 ps
CPU time	14.01 seconds
Started	Sep 18 05:56:50 AM UTC 24
Finished	Sep 18 05:57:05 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832171891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2832171891
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.83597456
Short name	T136
Test name
Test status
Simulation time	53518407696 ps
CPU time	377.93 seconds
Started	Sep 18 05:56:51 AM UTC 24
Finished	Sep 18 06:03:14 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83597456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.83597456
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3315760664
Short name	T451
Test name
Test status
Simulation time	31622594 ps
CPU time	5.24 seconds
Started	Sep 18 05:57:01 AM UTC 24
Finished	Sep 18 05:57:07 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315760664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3315760664
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.3790825868
Short name	T449
Test name
Test status
Simulation time	367861017 ps
CPU time	6.92 seconds
Started	Sep 18 05:56:56 AM UTC 24
Finished	Sep 18 05:57:04 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790825868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3790825868
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.758658475
Short name	T457
Test name
Test status
Simulation time	1979365925 ps
CPU time	26.11 seconds
Started	Sep 18 05:56:49 AM UTC 24
Finished	Sep 18 05:57:16 AM UTC 24
Peak memory	217760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758658475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.758658475
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.2016164894
Short name	T564
Test name
Test status
Simulation time	54829584746 ps
CPU time	259.92 seconds
Started	Sep 18 05:56:49 AM UTC 24
Finished	Sep 18 06:01:12 AM UTC 24
Peak memory	218148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016164894 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2016164894
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.4204965203
Short name	T569
Test name
Test status
Simulation time	57164404474 ps
CPU time	264.11 seconds
Started	Sep 18 05:56:49 AM UTC 24
Finished	Sep 18 06:01:16 AM UTC 24
Peak memory	216104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204965203 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.4204965203
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.1068866608
Short name	T231
Test name
Test status
Simulation time	148933587 ps
CPU time	21 seconds
Started	Sep 18 05:56:49 AM UTC 24
Finished	Sep 18 05:57:11 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068866608 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1068866608
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.55102277
Short name	T452
Test name
Test status
Simulation time	1593230766 ps
CPU time	11.73 seconds
Started	Sep 18 05:56:55 AM UTC 24
Finished	Sep 18 05:57:08 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55102277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.55102277
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.4088052296
Short name	T264
Test name
Test status
Simulation time	84691422 ps
CPU time	3.41 seconds
Started	Sep 18 05:56:44 AM UTC 24
Finished	Sep 18 05:56:48 AM UTC 24
Peak memory	215956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088052296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.4088052296
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2565062959
Short name	T456
Test name
Test status
Simulation time	6535571678 ps
CPU time	27.92 seconds
Started	Sep 18 05:56:46 AM UTC 24
Finished	Sep 18 05:57:15 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565062959 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2565062959
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1554132117
Short name	T246
Test name
Test status
Simulation time	9508978609 ps
CPU time	65.87 seconds
Started	Sep 18 05:56:46 AM UTC 24
Finished	Sep 18 05:57:54 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554132117 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1554132117
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1018338092
Short name	T266
Test name
Test status
Simulation time	44055055 ps
CPU time	2.98 seconds
Started	Sep 18 05:56:46 AM UTC 24
Finished	Sep 18 05:56:50 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018338092 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1018338092
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.3820233459
Short name	T484
Test name
Test status
Simulation time	887889597 ps
CPU time	74.71 seconds
Started	Sep 18 05:57:05 AM UTC 24
Finished	Sep 18 05:58:21 AM UTC 24
Peak memory	219876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820233459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3820233459
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3092762274
Short name	T470
Test name
Test status
Simulation time	2030882718 ps
CPU time	39.84 seconds
Started	Sep 18 05:57:08 AM UTC 24
Finished	Sep 18 05:57:50 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092762274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3092762274
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3023315618
Short name	T326
Test name
Test status
Simulation time	240813719 ps
CPU time	60.62 seconds
Started	Sep 18 05:57:10 AM UTC 24
Finished	Sep 18 05:58:12 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023315618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.3023315618
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3700583690
Short name	T461
Test name
Test status
Simulation time	222376501 ps
CPU time	22.63 seconds
Started	Sep 18 05:56:58 AM UTC 24
Finished	Sep 18 05:57:21 AM UTC 24
Peak memory	217768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700583690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3700583690
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.465291771
Short name	T469
Test name
Test status
Simulation time	598303174 ps
CPU time	27.24 seconds
Started	Sep 18 05:57:18 AM UTC 24
Finished	Sep 18 05:57:46 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465291771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.465291771
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2306794963
Short name	T134
Test name
Test status
Simulation time	29718176394 ps
CPU time	281.35 seconds
Started	Sep 18 05:57:18 AM UTC 24
Finished	Sep 18 06:02:03 AM UTC 24
Peak memory	218220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306794963 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.2306794963
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.262003980
Short name	T272
Test name
Test status
Simulation time	1071805942 ps
CPU time	29.28 seconds
Started	Sep 18 05:57:26 AM UTC 24
Finished	Sep 18 05:57:57 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262003980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.262003980
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.3284586776
Short name	T467
Test name
Test status
Simulation time	1202974048 ps
CPU time	17.25 seconds
Started	Sep 18 05:57:22 AM UTC 24
Finished	Sep 18 05:57:40 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284586776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3284586776
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.3151669989
Short name	T462
Test name
Test status
Simulation time	321528777 ps
CPU time	8.86 seconds
Started	Sep 18 05:57:14 AM UTC 24
Finished	Sep 18 05:57:24 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151669989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3151669989
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.90402242
Short name	T531
Test name
Test status
Simulation time	30002714177 ps
CPU time	167.48 seconds
Started	Sep 18 05:57:16 AM UTC 24
Finished	Sep 18 06:00:06 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90402242 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.90402242
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3827129924
Short name	T511
Test name
Test status
Simulation time	22130016952 ps
CPU time	114.34 seconds
Started	Sep 18 05:57:16 AM UTC 24
Finished	Sep 18 05:59:13 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827129924 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3827129924
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.34693821
Short name	T466
Test name
Test status
Simulation time	70186874 ps
CPU time	10.53 seconds
Started	Sep 18 05:57:15 AM UTC 24
Finished	Sep 18 05:57:27 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34693821 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.34693821
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.918569216
Short name	T473
Test name
Test status
Simulation time	2143092117 ps
CPU time	32.23 seconds
Started	Sep 18 05:57:19 AM UTC 24
Finished	Sep 18 05:57:52 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918569216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.918569216
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.989652996
Short name	T459
Test name
Test status
Simulation time	299820580 ps
CPU time	4.99 seconds
Started	Sep 18 05:57:11 AM UTC 24
Finished	Sep 18 05:57:17 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989652996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.989652996
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.697034795
Short name	T475
Test name
Test status
Simulation time	14469849308 ps
CPU time	42.49 seconds
Started	Sep 18 05:57:13 AM UTC 24
Finished	Sep 18 05:57:56 AM UTC 24
Peak memory	216084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697034795 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.697034795
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2380481754
Short name	T277
Test name
Test status
Simulation time	4289269873 ps
CPU time	47.6 seconds
Started	Sep 18 05:57:14 AM UTC 24
Finished	Sep 18 05:58:03 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380481754 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2380481754
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.4195080630
Short name	T458
Test name
Test status
Simulation time	37244365 ps
CPU time	3.03 seconds
Started	Sep 18 05:57:13 AM UTC 24
Finished	Sep 18 05:57:17 AM UTC 24
Peak memory	215948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195080630 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.4195080630
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.1659164118
Short name	T509
Test name
Test status
Simulation time	2307788655 ps
CPU time	98.79 seconds
Started	Sep 18 05:57:26 AM UTC 24
Finished	Sep 18 05:59:07 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659164118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1659164118
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.137649702
Short name	T504
Test name
Test status
Simulation time	2990816334 ps
CPU time	93.56 seconds
Started	Sep 18 05:57:28 AM UTC 24
Finished	Sep 18 05:59:04 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137649702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.137649702
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3573001235
Short name	T480
Test name
Test status
Simulation time	118267180 ps
CPU time	46.81 seconds
Started	Sep 18 05:57:28 AM UTC 24
Finished	Sep 18 05:58:16 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573001235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.3573001235
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3876944816
Short name	T276
Test name
Test status
Simulation time	155274094 ps
CPU time	20.47 seconds
Started	Sep 18 05:57:41 AM UTC 24
Finished	Sep 18 05:58:03 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876944816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3876944816
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.2963243924
Short name	T468
Test name
Test status
Simulation time	912369230 ps
CPU time	19.11 seconds
Started	Sep 18 05:57:24 AM UTC 24
Finished	Sep 18 05:57:44 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963243924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2963243924
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.3075067250
Short name	T476
Test name
Test status
Simulation time	117270126 ps
CPU time	11.93 seconds
Started	Sep 18 05:57:57 AM UTC 24
Finished	Sep 18 05:58:10 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075067250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3075067250
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.4130661841
Short name	T549
Test name
Test status
Simulation time	17680765084 ps
CPU time	160.42 seconds
Started	Sep 18 05:57:58 AM UTC 24
Finished	Sep 18 06:00:42 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130661841 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.4130661841
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.4187015119
Short name	T481
Test name
Test status
Simulation time	1473299184 ps
CPU time	11.78 seconds
Started	Sep 18 05:58:04 AM UTC 24
Finished	Sep 18 05:58:17 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187015119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.4187015119
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.1900097035
Short name	T482
Test name
Test status
Simulation time	881317829 ps
CPU time	20.01 seconds
Started	Sep 18 05:57:59 AM UTC 24
Finished	Sep 18 05:58:20 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900097035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1900097035
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.654518831
Short name	T478
Test name
Test status
Simulation time	859142803 ps
CPU time	17.96 seconds
Started	Sep 18 05:57:53 AM UTC 24
Finished	Sep 18 05:58:12 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654518831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.654518831
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.1942609705
Short name	T292
Test name
Test status
Simulation time	19245393014 ps
CPU time	78.32 seconds
Started	Sep 18 05:57:55 AM UTC 24
Finished	Sep 18 05:59:15 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942609705 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1942609705
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1351276969
Short name	T495
Test name
Test status
Simulation time	9616027325 ps
CPU time	50.28 seconds
Started	Sep 18 05:57:56 AM UTC 24
Finished	Sep 18 05:58:48 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351276969 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1351276969
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.507366741
Short name	T275
Test name
Test status
Simulation time	102277989 ps
CPU time	8 seconds
Started	Sep 18 05:57:53 AM UTC 24
Finished	Sep 18 05:58:02 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507366741 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.507366741
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.3073165487
Short name	T278
Test name
Test status
Simulation time	75002603 ps
CPU time	3.09 seconds
Started	Sep 18 05:57:58 AM UTC 24
Finished	Sep 18 05:58:03 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073165487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3073165487
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.469858461
Short name	T471
Test name
Test status
Simulation time	105316015 ps
CPU time	4.29 seconds
Started	Sep 18 05:57:45 AM UTC 24
Finished	Sep 18 05:57:50 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469858461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.469858461
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1506134042
Short name	T489
Test name
Test status
Simulation time	5825767755 ps
CPU time	42.74 seconds
Started	Sep 18 05:57:51 AM UTC 24
Finished	Sep 18 05:58:35 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506134042 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1506134042
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3499883298
Short name	T271
Test name
Test status
Simulation time	5736553094 ps
CPU time	36.11 seconds
Started	Sep 18 05:57:52 AM UTC 24
Finished	Sep 18 05:58:29 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499883298 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3499883298
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.843981442
Short name	T472
Test name
Test status
Simulation time	34894492 ps
CPU time	3.71 seconds
Started	Sep 18 05:57:47 AM UTC 24
Finished	Sep 18 05:57:52 AM UTC 24
Peak memory	215684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843981442 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.843981442
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.1786607756
Short name	T498
Test name
Test status
Simulation time	463580284 ps
CPU time	46.76 seconds
Started	Sep 18 05:58:04 AM UTC 24
Finished	Sep 18 05:58:52 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786607756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1786607756
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3712349346
Short name	T477
Test name
Test status
Simulation time	181806641 ps
CPU time	4.36 seconds
Started	Sep 18 05:58:05 AM UTC 24
Finished	Sep 18 05:58:11 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712349346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3712349346
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1544083037
Short name	T208
Test name
Test status
Simulation time	1419177033 ps
CPU time	242.27 seconds
Started	Sep 18 05:58:04 AM UTC 24
Finished	Sep 18 06:02:10 AM UTC 24
Peak memory	222168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544083037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.1544083037
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2954084490
Short name	T518
Test name
Test status
Simulation time	343450293 ps
CPU time	85.34 seconds
Started	Sep 18 05:58:07 AM UTC 24
Finished	Sep 18 05:59:35 AM UTC 24
Peak memory	220080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954084490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.2954084490
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.2412872195
Short name	T188
Test name
Test status
Simulation time	479932494 ps
CPU time	16.01 seconds
Started	Sep 18 05:58:04 AM UTC 24
Finished	Sep 18 05:58:21 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412872195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2412872195
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.3622634331
Short name	T487
Test name
Test status
Simulation time	134474607 ps
CPU time	9.76 seconds
Started	Sep 18 05:58:18 AM UTC 24
Finished	Sep 18 05:58:29 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622634331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3622634331
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.286363088
Short name	T811
Test name
Test status
Simulation time	71357082099 ps
CPU time	573.12 seconds
Started	Sep 18 05:58:18 AM UTC 24
Finished	Sep 18 06:07:57 AM UTC 24
Peak memory	219496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286363088 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.286363088
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3737533408
Short name	T494
Test name
Test status
Simulation time	1303368254 ps
CPU time	20.95 seconds
Started	Sep 18 05:58:23 AM UTC 24
Finished	Sep 18 05:58:45 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737533408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3737533408
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.2755686988
Short name	T500
Test name
Test status
Simulation time	1527534800 ps
CPU time	36.69 seconds
Started	Sep 18 05:58:21 AM UTC 24
Finished	Sep 18 05:58:59 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755686988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2755686988
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.2980642188
Short name	T486
Test name
Test status
Simulation time	240699809 ps
CPU time	12.31 seconds
Started	Sep 18 05:58:15 AM UTC 24
Finished	Sep 18 05:58:28 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980642188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2980642188
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.2215501066
Short name	T613
Test name
Test status
Simulation time	49437411339 ps
CPU time	244.86 seconds
Started	Sep 18 05:58:16 AM UTC 24
Finished	Sep 18 06:02:24 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215501066 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2215501066
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.4175469338
Short name	T508
Test name
Test status
Simulation time	14241806006 ps
CPU time	47.77 seconds
Started	Sep 18 05:58:17 AM UTC 24
Finished	Sep 18 05:59:07 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175469338 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4175469338
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.2877328648
Short name	T492
Test name
Test status
Simulation time	368104792 ps
CPU time	22.16 seconds
Started	Sep 18 05:58:16 AM UTC 24
Finished	Sep 18 05:58:40 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877328648 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2877328648
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.2814865965
Short name	T232
Test name
Test status
Simulation time	213344146 ps
CPU time	14.43 seconds
Started	Sep 18 05:58:20 AM UTC 24
Finished	Sep 18 05:58:36 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814865965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2814865965
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.2644626476
Short name	T273
Test name
Test status
Simulation time	242493584 ps
CPU time	4.31 seconds
Started	Sep 18 05:58:11 AM UTC 24
Finished	Sep 18 05:58:16 AM UTC 24
Peak memory	215956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644626476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2644626476
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2228519058
Short name	T491
Test name
Test status
Simulation time	4603571004 ps
CPU time	24.5 seconds
Started	Sep 18 05:58:13 AM UTC 24
Finished	Sep 18 05:58:39 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228519058 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2228519058
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3550443862
Short name	T506
Test name
Test status
Simulation time	9358947518 ps
CPU time	49.52 seconds
Started	Sep 18 05:58:13 AM UTC 24
Finished	Sep 18 05:59:04 AM UTC 24
Peak memory	216016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550443862 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3550443862
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2024210093
Short name	T463
Test name
Test status
Simulation time	90084837 ps
CPU time	2.37 seconds
Started	Sep 18 05:58:12 AM UTC 24
Finished	Sep 18 05:58:15 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024210093 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2024210093
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.2133025533
Short name	T507
Test name
Test status
Simulation time	1586276868 ps
CPU time	42.8 seconds
Started	Sep 18 05:58:23 AM UTC 24
Finished	Sep 18 05:59:07 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133025533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2133025533
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.426776076
Short name	T543
Test name
Test status
Simulation time	12130422585 ps
CPU time	129.48 seconds
Started	Sep 18 05:58:24 AM UTC 24
Finished	Sep 18 06:00:36 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426776076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.426776076
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2767813964
Short name	T190
Test name
Test status
Simulation time	323520685 ps
CPU time	160.17 seconds
Started	Sep 18 05:58:23 AM UTC 24
Finished	Sep 18 06:01:06 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767813964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.2767813964
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.763614267
Short name	T592
Test name
Test status
Simulation time	1799819411 ps
CPU time	199.62 seconds
Started	Sep 18 05:58:29 AM UTC 24
Finished	Sep 18 06:01:52 AM UTC 24
Peak memory	232724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763614267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.763614267
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.2448555771
Short name	T291
Test name
Test status
Simulation time	526316042 ps
CPU time	9.08 seconds
Started	Sep 18 05:58:23 AM UTC 24
Finished	Sep 18 05:58:33 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448555771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2448555771
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.597102646
Short name	T516
Test name
Test status
Simulation time	1425660620 ps
CPU time	43.91 seconds
Started	Sep 18 05:58:40 AM UTC 24
Finished	Sep 18 05:59:25 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597102646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.597102646
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.643129461
Short name	T885
Test name
Test status
Simulation time	153825091875 ps
CPU time	771.23 seconds
Started	Sep 18 05:58:41 AM UTC 24
Finished	Sep 18 06:11:41 AM UTC 24
Peak memory	219564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643129461 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.643129461
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1006293488
Short name	T512
Test name
Test status
Simulation time	738914977 ps
CPU time	25.49 seconds
Started	Sep 18 05:58:49 AM UTC 24
Finished	Sep 18 05:59:16 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006293488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1006293488
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.491708099
Short name	T499
Test name
Test status
Simulation time	888202061 ps
CPU time	14.45 seconds
Started	Sep 18 05:58:42 AM UTC 24
Finished	Sep 18 05:58:58 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491708099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.491708099
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.1403792390
Short name	T497
Test name
Test status
Simulation time	395049956 ps
CPU time	13.94 seconds
Started	Sep 18 05:58:36 AM UTC 24
Finished	Sep 18 05:58:51 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403792390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1403792390
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.526087652
Short name	T596
Test name
Test status
Simulation time	71850271183 ps
CPU time	200.26 seconds
Started	Sep 18 05:58:38 AM UTC 24
Finished	Sep 18 06:02:01 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526087652 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.526087652
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3426917470
Short name	T529
Test name
Test status
Simulation time	18066288014 ps
CPU time	82.32 seconds
Started	Sep 18 05:58:38 AM UTC 24
Finished	Sep 18 06:00:02 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426917470 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3426917470
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.883224362
Short name	T496
Test name
Test status
Simulation time	64390805 ps
CPU time	10.96 seconds
Started	Sep 18 05:58:36 AM UTC 24
Finished	Sep 18 05:58:48 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883224362 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.883224362
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2796030909
Short name	T501
Test name
Test status
Simulation time	576107018 ps
CPU time	17.6 seconds
Started	Sep 18 05:58:41 AM UTC 24
Finished	Sep 18 05:59:00 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796030909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2796030909
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.970102735
Short name	T490
Test name
Test status
Simulation time	325671301 ps
CPU time	5.65 seconds
Started	Sep 18 05:58:29 AM UTC 24
Finished	Sep 18 05:58:36 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970102735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.970102735
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1951198163
Short name	T505
Test name
Test status
Simulation time	5317045305 ps
CPU time	28.85 seconds
Started	Sep 18 05:58:34 AM UTC 24
Finished	Sep 18 05:59:04 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951198163 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1951198163
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1046336911
Short name	T513
Test name
Test status
Simulation time	3526967528 ps
CPU time	39.72 seconds
Started	Sep 18 05:58:35 AM UTC 24
Finished	Sep 18 05:59:16 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046336911 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1046336911
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2379937659
Short name	T488
Test name
Test status
Simulation time	24243803 ps
CPU time	2.97 seconds
Started	Sep 18 05:58:30 AM UTC 24
Finished	Sep 18 05:58:34 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379937659 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2379937659
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.137066840
Short name	T584
Test name
Test status
Simulation time	2632998455 ps
CPU time	169.5 seconds
Started	Sep 18 05:58:49 AM UTC 24
Finished	Sep 18 06:01:41 AM UTC 24
Peak memory	219944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137066840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.137066840
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2001835422
Short name	T547
Test name
Test status
Simulation time	1347053478 ps
CPU time	105.55 seconds
Started	Sep 18 05:58:52 AM UTC 24
Finished	Sep 18 06:00:40 AM UTC 24
Peak memory	221928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001835422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2001835422
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.675109965
Short name	T304
Test name
Test status
Simulation time	125118396 ps
CPU time	56 seconds
Started	Sep 18 05:58:49 AM UTC 24
Finished	Sep 18 05:59:47 AM UTC 24
Peak memory	219876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675109965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.675109965
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3552439312
Short name	T557
Test name
Test status
Simulation time	1734398561 ps
CPU time	123.86 seconds
Started	Sep 18 05:58:53 AM UTC 24
Finished	Sep 18 06:01:00 AM UTC 24
Peak memory	221932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552439312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.3552439312
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.2362030179
Short name	T514
Test name
Test status
Simulation time	217095147 ps
CPU time	30.42 seconds
Started	Sep 18 05:58:45 AM UTC 24
Finished	Sep 18 05:59:17 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362030179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2362030179
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.1392335311
Short name	T307
Test name
Test status
Simulation time	1141605076 ps
CPU time	46.15 seconds
Started	Sep 18 05:59:06 AM UTC 24
Finished	Sep 18 05:59:54 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392335311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1392335311
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3969969037
Short name	T767
Test name
Test status
Simulation time	202522999720 ps
CPU time	443.82 seconds
Started	Sep 18 05:59:08 AM UTC 24
Finished	Sep 18 06:06:37 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969969037 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.3969969037
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.4128541861
Short name	T522
Test name
Test status
Simulation time	646490809 ps
CPU time	23.71 seconds
Started	Sep 18 05:59:14 AM UTC 24
Finished	Sep 18 05:59:39 AM UTC 24
Peak memory	215536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128541861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.4128541861
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.4220853432
Short name	T300
Test name
Test status
Simulation time	1552446953 ps
CPU time	29.79 seconds
Started	Sep 18 05:59:08 AM UTC 24
Finished	Sep 18 05:59:39 AM UTC 24
Peak memory	215716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220853432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.4220853432
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.2017905449
Short name	T510
Test name
Test status
Simulation time	538643548 ps
CPU time	10.47 seconds
Started	Sep 18 05:59:01 AM UTC 24
Finished	Sep 18 05:59:13 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017905449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2017905449
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.1175822248
Short name	T630
Test name
Test status
Simulation time	41605846343 ps
CPU time	220.88 seconds
Started	Sep 18 05:59:05 AM UTC 24
Finished	Sep 18 06:02:49 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175822248 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1175822248
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1862462859
Short name	T645
Test name
Test status
Simulation time	23972749729 ps
CPU time	239.2 seconds
Started	Sep 18 05:59:05 AM UTC 24
Finished	Sep 18 06:03:07 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862462859 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1862462859
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.3098228412
Short name	T521
Test name
Test status
Simulation time	217937184 ps
CPU time	31.04 seconds
Started	Sep 18 05:59:05 AM UTC 24
Finished	Sep 18 05:59:37 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098228412 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3098228412
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.488236229
Short name	T519
Test name
Test status
Simulation time	1379282709 ps
CPU time	25.6 seconds
Started	Sep 18 05:59:08 AM UTC 24
Finished	Sep 18 05:59:35 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488236229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.488236229
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.1178012850
Short name	T502
Test name
Test status
Simulation time	192639820 ps
CPU time	5.12 seconds
Started	Sep 18 05:58:55 AM UTC 24
Finished	Sep 18 05:59:01 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178012850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1178012850
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1329954
Short name	T302
Test name
Test status
Simulation time	6419808370 ps
CPU time	42.79 seconds
Started	Sep 18 05:59:00 AM UTC 24
Finished	Sep 18 05:59:44 AM UTC 24
Peak memory	215884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329954 -assert nopostproc +UVM_TESTNAME=xbar_base_t est +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1329954
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1776563009
Short name	T520
Test name
Test status
Simulation time	2550430348 ps
CPU time	34.36 seconds
Started	Sep 18 05:59:01 AM UTC 24
Finished	Sep 18 05:59:37 AM UTC 24
Peak memory	216016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776563009 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1776563009
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2219651843
Short name	T503
Test name
Test status
Simulation time	35992099 ps
CPU time	3.48 seconds
Started	Sep 18 05:58:59 AM UTC 24
Finished	Sep 18 05:59:03 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219651843 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2219651843
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.1647768707
Short name	T544
Test name
Test status
Simulation time	2551900094 ps
CPU time	81.82 seconds
Started	Sep 18 05:59:14 AM UTC 24
Finished	Sep 18 06:00:38 AM UTC 24
Peak memory	219788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647768707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1647768707
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.900475140
Short name	T50
Test name
Test status
Simulation time	7974549709 ps
CPU time	187.94 seconds
Started	Sep 18 05:59:16 AM UTC 24
Finished	Sep 18 06:02:27 AM UTC 24
Peak memory	219940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900475140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.900475140
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.716665470
Short name	T532
Test name
Test status
Simulation time	103658566 ps
CPU time	51.17 seconds
Started	Sep 18 05:59:16 AM UTC 24
Finished	Sep 18 06:00:09 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716665470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.716665470
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1888353368
Short name	T632
Test name
Test status
Simulation time	9787125744 ps
CPU time	211.49 seconds
Started	Sep 18 05:59:17 AM UTC 24
Finished	Sep 18 06:02:51 AM UTC 24
Peak memory	222256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888353368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.1888353368
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.1775636485
Short name	T301
Test name
Test status
Simulation time	800916796 ps
CPU time	28.84 seconds
Started	Sep 18 05:59:10 AM UTC 24
Finished	Sep 18 05:59:40 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775636485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1775636485
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.1784304860
Short name	T306
Test name
Test status
Simulation time	216775381 ps
CPU time	11.89 seconds
Started	Sep 18 05:59:38 AM UTC 24
Finished	Sep 18 05:59:51 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784304860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1784304860
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.877458808
Short name	T683
Test name
Test status
Simulation time	80685015835 ps
CPU time	278.39 seconds
Started	Sep 18 05:59:40 AM UTC 24
Finished	Sep 18 06:04:21 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877458808 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.877458808
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2097436505
Short name	T303
Test name
Test status
Simulation time	56517773 ps
CPU time	3.42 seconds
Started	Sep 18 05:59:41 AM UTC 24
Finished	Sep 18 05:59:45 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097436505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2097436505
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.3931368097
Short name	T528
Test name
Test status
Simulation time	582719430 ps
CPU time	19.11 seconds
Started	Sep 18 05:59:41 AM UTC 24
Finished	Sep 18 06:00:01 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931368097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3931368097
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.2623588044
Short name	T527
Test name
Test status
Simulation time	201119823 ps
CPU time	25.15 seconds
Started	Sep 18 05:59:35 AM UTC 24
Finished	Sep 18 06:00:01 AM UTC 24
Peak memory	218012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623588044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2623588044
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.3922251749
Short name	T565
Test name
Test status
Simulation time	18589605131 ps
CPU time	94.64 seconds
Started	Sep 18 05:59:36 AM UTC 24
Finished	Sep 18 06:01:13 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922251749 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3922251749
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3246452126
Short name	T539
Test name
Test status
Simulation time	8446638930 ps
CPU time	47.91 seconds
Started	Sep 18 05:59:38 AM UTC 24
Finished	Sep 18 06:00:28 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246452126 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3246452126
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.41933017
Short name	T70
Test name
Test status
Simulation time	315591058 ps
CPU time	22.71 seconds
Started	Sep 18 05:59:36 AM UTC 24
Finished	Sep 18 06:00:00 AM UTC 24
Peak memory	217820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41933017 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.41933017
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.2896774504
Short name	T526
Test name
Test status
Simulation time	1012918647 ps
CPU time	18.12 seconds
Started	Sep 18 05:59:41 AM UTC 24
Finished	Sep 18 06:00:00 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896774504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2896774504
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.3429722733
Short name	T515
Test name
Test status
Simulation time	27633833 ps
CPU time	3.52 seconds
Started	Sep 18 05:59:18 AM UTC 24
Finished	Sep 18 05:59:22 AM UTC 24
Peak memory	215956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429722733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3429722733
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3727379289
Short name	T533
Test name
Test status
Simulation time	21419930889 ps
CPU time	42.46 seconds
Started	Sep 18 05:59:26 AM UTC 24
Finished	Sep 18 06:00:10 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727379289 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3727379289
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1200747306
Short name	T534
Test name
Test status
Simulation time	16565121938 ps
CPU time	43.73 seconds
Started	Sep 18 05:59:27 AM UTC 24
Finished	Sep 18 06:00:12 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200747306 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1200747306
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1986159282
Short name	T517
Test name
Test status
Simulation time	109270868 ps
CPU time	2.94 seconds
Started	Sep 18 05:59:23 AM UTC 24
Finished	Sep 18 05:59:27 AM UTC 24
Peak memory	215948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986159282 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1986159282
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.2923486693
Short name	T579
Test name
Test status
Simulation time	6139402865 ps
CPU time	109.95 seconds
Started	Sep 18 05:59:45 AM UTC 24
Finished	Sep 18 06:01:38 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923486693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2923486693
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.613571654
Short name	T599
Test name
Test status
Simulation time	4462398026 ps
CPU time	137.09 seconds
Started	Sep 18 05:59:48 AM UTC 24
Finished	Sep 18 06:02:07 AM UTC 24
Peak memory	220200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613571654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.613571654
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1403039537
Short name	T235
Test name
Test status
Simulation time	293673575 ps
CPU time	241.66 seconds
Started	Sep 18 05:59:47 AM UTC 24
Finished	Sep 18 06:03:52 AM UTC 24
Peak memory	222124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403039537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.1403039537
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.173227875
Short name	T590
Test name
Test status
Simulation time	573842063 ps
CPU time	115.4 seconds
Started	Sep 18 05:59:51 AM UTC 24
Finished	Sep 18 06:01:49 AM UTC 24
Peak memory	222128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173227875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.173227875
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.2804790489
Short name	T530
Test name
Test status
Simulation time	139414010 ps
CPU time	23.96 seconds
Started	Sep 18 05:59:41 AM UTC 24
Finished	Sep 18 06:00:06 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804790489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2804790489
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.2534274300
Short name	T132
Test name
Test status
Simulation time	1811397763 ps
CPU time	22.04 seconds
Started	Sep 18 06:00:02 AM UTC 24
Finished	Sep 18 06:00:29 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534274300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2534274300
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.349395289
Short name	T137
Test name
Test status
Simulation time	23743965556 ps
CPU time	216.82 seconds
Started	Sep 18 06:00:02 AM UTC 24
Finished	Sep 18 06:03:46 AM UTC 24
Peak memory	217996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349395289 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.349395289
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.3259747740
Short name	T540
Test name
Test status
Simulation time	249818338 ps
CPU time	18.77 seconds
Started	Sep 18 06:00:11 AM UTC 24
Finished	Sep 18 06:00:31 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259747740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.3259747740
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.3225874745
Short name	T545
Test name
Test status
Simulation time	1661093095 ps
CPU time	29.12 seconds
Started	Sep 18 06:00:07 AM UTC 24
Finished	Sep 18 06:00:38 AM UTC 24
Peak memory	215712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225874745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3225874745
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.4265789562
Short name	T133
Test name
Test status
Simulation time	999612975 ps
CPU time	42.64 seconds
Started	Sep 18 06:00:00 AM UTC 24
Finished	Sep 18 06:00:49 AM UTC 24
Peak memory	215312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265789562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.4265789562
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.3004806299
Short name	T538
Test name
Test status
Simulation time	3626383242 ps
CPU time	21.72 seconds
Started	Sep 18 06:00:01 AM UTC 24
Finished	Sep 18 06:00:28 AM UTC 24
Peak memory	215836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004806299 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3004806299
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1420453307
Short name	T582
Test name
Test status
Simulation time	12987544296 ps
CPU time	91.61 seconds
Started	Sep 18 06:00:02 AM UTC 24
Finished	Sep 18 06:01:39 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420453307 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1420453307
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.2016245886
Short name	T537
Test name
Test status
Simulation time	144107756 ps
CPU time	21.31 seconds
Started	Sep 18 06:00:00 AM UTC 24
Finished	Sep 18 06:00:27 AM UTC 24
Peak memory	215412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016245886 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2016245886
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.1914413871
Short name	T536
Test name
Test status
Simulation time	1023839709 ps
CPU time	17.35 seconds
Started	Sep 18 06:00:03 AM UTC 24
Finished	Sep 18 06:00:25 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914413871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1914413871
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.2240893468
Short name	T524
Test name
Test status
Simulation time	145899430 ps
CPU time	5.56 seconds
Started	Sep 18 05:59:53 AM UTC 24
Finished	Sep 18 05:59:59 AM UTC 24
Peak memory	215696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240893468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2240893468
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2615110191
Short name	T548
Test name
Test status
Simulation time	17602037569 ps
CPU time	45.05 seconds
Started	Sep 18 05:59:55 AM UTC 24
Finished	Sep 18 06:00:42 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615110191 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2615110191
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1933127532
Short name	T558
Test name
Test status
Simulation time	13958218464 ps
CPU time	63.28 seconds
Started	Sep 18 05:59:58 AM UTC 24
Finished	Sep 18 06:01:03 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933127532 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1933127532
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3281974839
Short name	T525
Test name
Test status
Simulation time	49188490 ps
CPU time	3.02 seconds
Started	Sep 18 05:59:55 AM UTC 24
Finished	Sep 18 06:00:00 AM UTC 24
Peak memory	215948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281974839 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3281974839
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.3709929303
Short name	T717
Test name
Test status
Simulation time	7991091739 ps
CPU time	302.33 seconds
Started	Sep 18 06:00:11 AM UTC 24
Finished	Sep 18 06:05:18 AM UTC 24
Peak memory	222600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709929303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3709929303
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.4040360555
Short name	T662
Test name
Test status
Simulation time	7022997828 ps
CPU time	202.26 seconds
Started	Sep 18 06:00:13 AM UTC 24
Finished	Sep 18 06:03:38 AM UTC 24
Peak memory	219944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040360555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.4040360555
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2725033754
Short name	T309
Test name
Test status
Simulation time	3720615872 ps
CPU time	164.54 seconds
Started	Sep 18 06:00:12 AM UTC 24
Finished	Sep 18 06:02:59 AM UTC 24
Peak memory	219944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725033754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.2725033754
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3440278039
Short name	T672
Test name
Test status
Simulation time	15389391382 ps
CPU time	229.97 seconds
Started	Sep 18 06:00:15 AM UTC 24
Finished	Sep 18 06:04:09 AM UTC 24
Peak memory	222412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440278039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.3440278039
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.1651929800
Short name	T535
Test name
Test status
Simulation time	34562921 ps
CPU time	5.62 seconds
Started	Sep 18 06:00:07 AM UTC 24
Finished	Sep 18 06:00:14 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651929800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1651929800
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.4163911290
Short name	T154
Test name
Test status
Simulation time	1353765949 ps
CPU time	26.6 seconds
Started	Sep 18 05:48:08 AM UTC 24
Finished	Sep 18 05:48:36 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163911290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.4163911290
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.741129313
Short name	T200
Test name
Test status
Simulation time	3558192963 ps
CPU time	36.1 seconds
Started	Sep 18 05:48:13 AM UTC 24
Finished	Sep 18 05:48:51 AM UTC 24
Peak memory	215848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741129313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.741129313
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.4038483125
Short name	T85
Test name
Test status
Simulation time	293104559 ps
CPU time	14.07 seconds
Started	Sep 18 05:48:12 AM UTC 24
Finished	Sep 18 05:48:27 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038483125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.4038483125
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.912273376
Short name	T99
Test name
Test status
Simulation time	3331301201 ps
CPU time	30.47 seconds
Started	Sep 18 05:48:05 AM UTC 24
Finished	Sep 18 05:48:37 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912273376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.912273376
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.148407173
Short name	T174
Test name
Test status
Simulation time	68472832451 ps
CPU time	289.59 seconds
Started	Sep 18 05:48:08 AM UTC 24
Finished	Sep 18 05:53:01 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148407173 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.148407173
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1862572998
Short name	T351
Test name
Test status
Simulation time	33659713560 ps
CPU time	237.31 seconds
Started	Sep 18 05:48:08 AM UTC 24
Finished	Sep 18 05:52:08 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862572998 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1862572998
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.2678425932
Short name	T79
Test name
Test status
Simulation time	47884851 ps
CPU time	6.84 seconds
Started	Sep 18 05:48:05 AM UTC 24
Finished	Sep 18 05:48:13 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678425932 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2678425932
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.3049940427
Short name	T39
Test name
Test status
Simulation time	664584749 ps
CPU time	11.49 seconds
Started	Sep 18 05:48:12 AM UTC 24
Finished	Sep 18 05:48:24 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049940427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3049940427
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.181705636
Short name	T58
Test name
Test status
Simulation time	166990280 ps
CPU time	4.75 seconds
Started	Sep 18 05:47:58 AM UTC 24
Finished	Sep 18 05:48:04 AM UTC 24
Peak memory	215960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181705636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.181705636
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2840311826
Short name	T123
Test name
Test status
Simulation time	21422757304 ps
CPU time	29.1 seconds
Started	Sep 18 05:48:01 AM UTC 24
Finished	Sep 18 05:48:32 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840311826 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2840311826
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1567004415
Short name	T161
Test name
Test status
Simulation time	3791657340 ps
CPU time	36.75 seconds
Started	Sep 18 05:48:03 AM UTC 24
Finished	Sep 18 05:48:41 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567004415 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1567004415
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1089659894
Short name	T269
Test name
Test status
Simulation time	21440938 ps
CPU time	3.05 seconds
Started	Sep 18 05:48:00 AM UTC 24
Finished	Sep 18 05:48:04 AM UTC 24
Peak memory	215748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089659894 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1089659894
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1040511567
Short name	T229
Test name
Test status
Simulation time	1287361780 ps
CPU time	69.65 seconds
Started	Sep 18 05:48:20 AM UTC 24
Finished	Sep 18 05:49:31 AM UTC 24
Peak memory	219820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040511567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1040511567
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.325153466
Short name	T204
Test name
Test status
Simulation time	594617185 ps
CPU time	166.49 seconds
Started	Sep 18 05:48:17 AM UTC 24
Finished	Sep 18 05:51:06 AM UTC 24
Peak memory	222252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325153466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.325153466
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2341154917
Short name	T329
Test name
Test status
Simulation time	17119720184 ps
CPU time	442.22 seconds
Started	Sep 18 05:48:21 AM UTC 24
Finished	Sep 18 05:55:49 AM UTC 24
Peak memory	234252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341154917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.2341154917
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.3895987715
Short name	T159
Test name
Test status
Simulation time	2271843563 ps
CPU time	20.91 seconds
Started	Sep 18 05:48:13 AM UTC 24
Finished	Sep 18 05:48:35 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895987715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3895987715
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.2193315486
Short name	T570
Test name
Test status
Simulation time	686689402 ps
CPU time	38.75 seconds
Started	Sep 18 06:00:37 AM UTC 24
Finished	Sep 18 06:01:17 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193315486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2193315486
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.327960496
Short name	T702
Test name
Test status
Simulation time	54982028939 ps
CPU time	246.29 seconds
Started	Sep 18 06:00:39 AM UTC 24
Finished	Sep 18 06:04:49 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327960496 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.327960496
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.734667913
Short name	T555
Test name
Test status
Simulation time	515604891 ps
CPU time	10.99 seconds
Started	Sep 18 06:00:42 AM UTC 24
Finished	Sep 18 06:00:54 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734667913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.734667913
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.3935657244
Short name	T551
Test name
Test status
Simulation time	60640772 ps
CPU time	3.01 seconds
Started	Sep 18 06:00:40 AM UTC 24
Finished	Sep 18 06:00:44 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935657244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3935657244
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.2201248648
Short name	T71
Test name
Test status
Simulation time	255810236 ps
CPU time	8.76 seconds
Started	Sep 18 06:00:30 AM UTC 24
Finished	Sep 18 06:00:40 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201248648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2201248648
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.1113707606
Short name	T583
Test name
Test status
Simulation time	10625389036 ps
CPU time	66.66 seconds
Started	Sep 18 06:00:32 AM UTC 24
Finished	Sep 18 06:01:40 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113707606 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1113707606
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1188729891
Short name	T289
Test name
Test status
Simulation time	67340812915 ps
CPU time	248.18 seconds
Started	Sep 18 06:00:33 AM UTC 24
Finished	Sep 18 06:04:45 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188729891 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1188729891
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.3350953134
Short name	T554
Test name
Test status
Simulation time	181465618 ps
CPU time	18.49 seconds
Started	Sep 18 06:00:32 AM UTC 24
Finished	Sep 18 06:00:52 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350953134 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3350953134
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.798982928
Short name	T559
Test name
Test status
Simulation time	1715562744 ps
CPU time	24.96 seconds
Started	Sep 18 06:00:39 AM UTC 24
Finished	Sep 18 06:01:05 AM UTC 24
Peak memory	215680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798982928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.798982928
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.1916420785
Short name	T541
Test name
Test status
Simulation time	160104478 ps
CPU time	4.78 seconds
Started	Sep 18 06:00:25 AM UTC 24
Finished	Sep 18 06:00:31 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916420785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1916420785
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1722395417
Short name	T572
Test name
Test status
Simulation time	7821010820 ps
CPU time	50.89 seconds
Started	Sep 18 06:00:29 AM UTC 24
Finished	Sep 18 06:01:21 AM UTC 24
Peak memory	216088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722395417 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1722395417
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.715474263
Short name	T567
Test name
Test status
Simulation time	4465442897 ps
CPU time	44.06 seconds
Started	Sep 18 06:00:29 AM UTC 24
Finished	Sep 18 06:01:14 AM UTC 24
Peak memory	215884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715474263 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.715474263
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.671069592
Short name	T542
Test name
Test status
Simulation time	40323414 ps
CPU time	3.15 seconds
Started	Sep 18 06:00:29 AM UTC 24
Finished	Sep 18 06:00:33 AM UTC 24
Peak memory	215752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671069592 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.671069592
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.1159262181
Short name	T135
Test name
Test status
Simulation time	2257422595 ps
CPU time	83.39 seconds
Started	Sep 18 06:00:43 AM UTC 24
Finished	Sep 18 06:02:08 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159262181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1159262181
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1939545818
Short name	T624
Test name
Test status
Simulation time	1707283868 ps
CPU time	117.93 seconds
Started	Sep 18 06:00:44 AM UTC 24
Finished	Sep 18 06:02:45 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939545818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1939545818
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.152652103
Short name	T633
Test name
Test status
Simulation time	425537378 ps
CPU time	126.31 seconds
Started	Sep 18 06:00:43 AM UTC 24
Finished	Sep 18 06:02:52 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152652103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.152652103
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3021938776
Short name	T591
Test name
Test status
Simulation time	792268101 ps
CPU time	62.69 seconds
Started	Sep 18 06:00:46 AM UTC 24
Finished	Sep 18 06:01:50 AM UTC 24
Peak memory	219820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021938776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.3021938776
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.1242847268
Short name	T560
Test name
Test status
Simulation time	213799416 ps
CPU time	23.62 seconds
Started	Sep 18 06:00:41 AM UTC 24
Finished	Sep 18 06:01:05 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242847268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1242847268
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.2401518891
Short name	T562
Test name
Test status
Simulation time	126598347 ps
CPU time	9.67 seconds
Started	Sep 18 06:01:01 AM UTC 24
Finished	Sep 18 06:01:12 AM UTC 24
Peak memory	216044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401518891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2401518891
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3506972024
Short name	T890
Test name
Test status
Simulation time	82066487272 ps
CPU time	653.34 seconds
Started	Sep 18 06:01:04 AM UTC 24
Finished	Sep 18 06:12:04 AM UTC 24
Peak memory	221480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506972024 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.3506972024
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2340970423
Short name	T568
Test name
Test status
Simulation time	63592524 ps
CPU time	7.41 seconds
Started	Sep 18 06:01:07 AM UTC 24
Finished	Sep 18 06:01:15 AM UTC 24
Peak memory	215720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340970423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2340970423
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.244948822
Short name	T586
Test name
Test status
Simulation time	3493865894 ps
CPU time	35.26 seconds
Started	Sep 18 06:01:07 AM UTC 24
Finished	Sep 18 06:01:43 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244948822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.244948822
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.1597704833
Short name	T566
Test name
Test status
Simulation time	143312651 ps
CPU time	19.79 seconds
Started	Sep 18 06:00:53 AM UTC 24
Finished	Sep 18 06:01:14 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597704833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1597704833
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.2700477641
Short name	T607
Test name
Test status
Simulation time	8262175732 ps
CPU time	81.03 seconds
Started	Sep 18 06:00:55 AM UTC 24
Finished	Sep 18 06:02:18 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700477641 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2700477641
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1830987769
Short name	T725
Test name
Test status
Simulation time	160226764678 ps
CPU time	273.1 seconds
Started	Sep 18 06:00:57 AM UTC 24
Finished	Sep 18 06:05:33 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830987769 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1830987769
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.2367992757
Short name	T561
Test name
Test status
Simulation time	92352157 ps
CPU time	9.84 seconds
Started	Sep 18 06:00:55 AM UTC 24
Finished	Sep 18 06:01:06 AM UTC 24
Peak memory	215712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367992757 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2367992757
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.3510642580
Short name	T573
Test name
Test status
Simulation time	266154863 ps
CPU time	13.67 seconds
Started	Sep 18 06:01:07 AM UTC 24
Finished	Sep 18 06:01:21 AM UTC 24
Peak memory	215388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510642580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3510642580
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.67810849
Short name	T552
Test name
Test status
Simulation time	93730922 ps
CPU time	3.19 seconds
Started	Sep 18 06:00:46 AM UTC 24
Finished	Sep 18 06:00:50 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67810849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.67810849
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2831044999
Short name	T577
Test name
Test status
Simulation time	5381720782 ps
CPU time	34.54 seconds
Started	Sep 18 06:00:51 AM UTC 24
Finished	Sep 18 06:01:27 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831044999 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2831044999
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2683390545
Short name	T575
Test name
Test status
Simulation time	4903977207 ps
CPU time	31.1 seconds
Started	Sep 18 06:00:51 AM UTC 24
Finished	Sep 18 06:01:24 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683390545 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2683390545
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.4025339350
Short name	T556
Test name
Test status
Simulation time	72918107 ps
CPU time	3.44 seconds
Started	Sep 18 06:00:50 AM UTC 24
Finished	Sep 18 06:00:54 AM UTC 24
Peak memory	216012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025339350 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.4025339350
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.3490506953
Short name	T608
Test name
Test status
Simulation time	6044367650 ps
CPU time	63 seconds
Started	Sep 18 06:01:14 AM UTC 24
Finished	Sep 18 06:02:18 AM UTC 24
Peak memory	218024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490506953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3490506953
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3144956288
Short name	T578
Test name
Test status
Simulation time	172236708 ps
CPU time	17.99 seconds
Started	Sep 18 06:01:14 AM UTC 24
Finished	Sep 18 06:01:33 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144956288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3144956288
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2825858309
Short name	T593
Test name
Test status
Simulation time	269877775 ps
CPU time	38.26 seconds
Started	Sep 18 06:01:14 AM UTC 24
Finished	Sep 18 06:01:53 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825858309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.2825858309
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.757822067
Short name	T714
Test name
Test status
Simulation time	711185738 ps
CPU time	237.82 seconds
Started	Sep 18 06:01:14 AM UTC 24
Finished	Sep 18 06:05:15 AM UTC 24
Peak memory	232724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757822067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.757822067
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.4185232403
Short name	T581
Test name
Test status
Simulation time	2392835272 ps
CPU time	30.24 seconds
Started	Sep 18 06:01:07 AM UTC 24
Finished	Sep 18 06:01:38 AM UTC 24
Peak memory	215848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185232403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4185232403
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.3742609167
Short name	T238
Test name
Test status
Simulation time	73403286 ps
CPU time	4.24 seconds
Started	Sep 18 06:01:23 AM UTC 24
Finished	Sep 18 06:01:28 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742609167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3742609167
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.832183808
Short name	T701
Test name
Test status
Simulation time	29667031485 ps
CPU time	199.75 seconds
Started	Sep 18 06:01:25 AM UTC 24
Finished	Sep 18 06:04:48 AM UTC 24
Peak memory	217968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832183808 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.832183808
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3657759725
Short name	T594
Test name
Test status
Simulation time	628303626 ps
CPU time	19.92 seconds
Started	Sep 18 06:01:34 AM UTC 24
Finished	Sep 18 06:01:55 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657759725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3657759725
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.1770023399
Short name	T601
Test name
Test status
Simulation time	1708241220 ps
CPU time	38.38 seconds
Started	Sep 18 06:01:29 AM UTC 24
Finished	Sep 18 06:02:08 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770023399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1770023399
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.1389827351
Short name	T587
Test name
Test status
Simulation time	189039069 ps
CPU time	26.73 seconds
Started	Sep 18 06:01:18 AM UTC 24
Finished	Sep 18 06:01:46 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389827351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1389827351
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.2757505139
Short name	T690
Test name
Test status
Simulation time	67829387091 ps
CPU time	192.53 seconds
Started	Sep 18 06:01:23 AM UTC 24
Finished	Sep 18 06:04:38 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757505139 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2757505139
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3428741404
Short name	T778
Test name
Test status
Simulation time	62366709425 ps
CPU time	325.81 seconds
Started	Sep 18 06:01:23 AM UTC 24
Finished	Sep 18 06:06:53 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428741404 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3428741404
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.753160513
Short name	T576
Test name
Test status
Simulation time	43101396 ps
CPU time	4.95 seconds
Started	Sep 18 06:01:20 AM UTC 24
Finished	Sep 18 06:01:26 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753160513 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.753160513
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.2272527323
Short name	T585
Test name
Test status
Simulation time	313145905 ps
CPU time	13.98 seconds
Started	Sep 18 06:01:27 AM UTC 24
Finished	Sep 18 06:01:42 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272527323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2272527323
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.1596917367
Short name	T574
Test name
Test status
Simulation time	218160758 ps
CPU time	5.63 seconds
Started	Sep 18 06:01:15 AM UTC 24
Finished	Sep 18 06:01:22 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596917367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1596917367
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.845680978
Short name	T72
Test name
Test status
Simulation time	7183554882 ps
CPU time	42.67 seconds
Started	Sep 18 06:01:16 AM UTC 24
Finished	Sep 18 06:02:00 AM UTC 24
Peak memory	216084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845680978 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.845680978
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2133658439
Short name	T603
Test name
Test status
Simulation time	6792785270 ps
CPU time	51.05 seconds
Started	Sep 18 06:01:18 AM UTC 24
Finished	Sep 18 06:02:10 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133658439 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2133658439
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3205330469
Short name	T571
Test name
Test status
Simulation time	42187756 ps
CPU time	2.75 seconds
Started	Sep 18 06:01:15 AM UTC 24
Finished	Sep 18 06:01:19 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205330469 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3205330469
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.724868566
Short name	T218
Test name
Test status
Simulation time	6027339158 ps
CPU time	181.71 seconds
Started	Sep 18 06:01:38 AM UTC 24
Finished	Sep 18 06:04:43 AM UTC 24
Peak memory	220200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724868566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.724868566
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.539288805
Short name	T638
Test name
Test status
Simulation time	3136494646 ps
CPU time	77.29 seconds
Started	Sep 18 06:01:39 AM UTC 24
Finished	Sep 18 06:02:59 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539288805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.539288805
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2136428484
Short name	T642
Test name
Test status
Simulation time	383884706 ps
CPU time	84.78 seconds
Started	Sep 18 06:01:39 AM UTC 24
Finished	Sep 18 06:03:07 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136428484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.2136428484
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3674915483
Short name	T602
Test name
Test status
Simulation time	80333044 ps
CPU time	26.97 seconds
Started	Sep 18 06:01:41 AM UTC 24
Finished	Sep 18 06:02:09 AM UTC 24
Peak memory	217768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674915483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.3674915483
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.176090020
Short name	T580
Test name
Test status
Simulation time	60924697 ps
CPU time	8.62 seconds
Started	Sep 18 06:01:29 AM UTC 24
Finished	Sep 18 06:01:38 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176090020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.176090020
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.3782179133
Short name	T623
Test name
Test status
Simulation time	1768681766 ps
CPU time	51.25 seconds
Started	Sep 18 06:01:51 AM UTC 24
Finished	Sep 18 06:02:44 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782179133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3782179133
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2002748305
Short name	T142
Test name
Test status
Simulation time	51374723400 ps
CPU time	368.93 seconds
Started	Sep 18 06:01:54 AM UTC 24
Finished	Sep 18 06:08:07 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002748305 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.2002748305
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2917843504
Short name	T600
Test name
Test status
Simulation time	112408192 ps
CPU time	5.16 seconds
Started	Sep 18 06:02:02 AM UTC 24
Finished	Sep 18 06:02:08 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917843504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2917843504
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.1820547732
Short name	T609
Test name
Test status
Simulation time	1496801262 ps
CPU time	21.75 seconds
Started	Sep 18 06:01:56 AM UTC 24
Finished	Sep 18 06:02:19 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820547732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1820547732
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.479935439
Short name	T595
Test name
Test status
Simulation time	726567998 ps
CPU time	7.88 seconds
Started	Sep 18 06:01:47 AM UTC 24
Finished	Sep 18 06:01:56 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479935439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.479935439
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.2016340320
Short name	T657
Test name
Test status
Simulation time	13292244549 ps
CPU time	96.69 seconds
Started	Sep 18 06:01:48 AM UTC 24
Finished	Sep 18 06:03:27 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016340320 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2016340320
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2021325725
Short name	T621
Test name
Test status
Simulation time	10713877864 ps
CPU time	46.85 seconds
Started	Sep 18 06:01:50 AM UTC 24
Finished	Sep 18 06:02:38 AM UTC 24
Peak memory	216108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021325725 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2021325725
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.2060096081
Short name	T597
Test name
Test status
Simulation time	200865869 ps
CPU time	13.41 seconds
Started	Sep 18 06:01:47 AM UTC 24
Finished	Sep 18 06:02:02 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060096081 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2060096081
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.3591139210
Short name	T620
Test name
Test status
Simulation time	11545489294 ps
CPU time	41.26 seconds
Started	Sep 18 06:01:55 AM UTC 24
Finished	Sep 18 06:02:38 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591139210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3591139210
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.1072599237
Short name	T589
Test name
Test status
Simulation time	128800170 ps
CPU time	4.77 seconds
Started	Sep 18 06:01:42 AM UTC 24
Finished	Sep 18 06:01:48 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072599237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1072599237
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2276250423
Short name	T614
Test name
Test status
Simulation time	8360893107 ps
CPU time	40.74 seconds
Started	Sep 18 06:01:43 AM UTC 24
Finished	Sep 18 06:02:26 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276250423 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2276250423
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.629963623
Short name	T612
Test name
Test status
Simulation time	6816515306 ps
CPU time	36.68 seconds
Started	Sep 18 06:01:45 AM UTC 24
Finished	Sep 18 06:02:24 AM UTC 24
Peak memory	215884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629963623 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.629963623
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1362927774
Short name	T588
Test name
Test status
Simulation time	42177995 ps
CPU time	3.24 seconds
Started	Sep 18 06:01:42 AM UTC 24
Finished	Sep 18 06:01:46 AM UTC 24
Peak memory	215880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362927774 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1362927774
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.4275197427
Short name	T703
Test name
Test status
Simulation time	1484301126 ps
CPU time	167.17 seconds
Started	Sep 18 06:02:02 AM UTC 24
Finished	Sep 18 06:04:52 AM UTC 24
Peak memory	221924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275197427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.4275197427
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2933998760
Short name	T640
Test name
Test status
Simulation time	2528089147 ps
CPU time	58.45 seconds
Started	Sep 18 06:02:05 AM UTC 24
Finished	Sep 18 06:03:05 AM UTC 24
Peak memory	216040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933998760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2933998760
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.876436887
Short name	T219
Test name
Test status
Simulation time	1956705533 ps
CPU time	319.7 seconds
Started	Sep 18 06:02:03 AM UTC 24
Finished	Sep 18 06:07:27 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876436887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.876436887
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3672528757
Short name	T718
Test name
Test status
Simulation time	399792603 ps
CPU time	190.11 seconds
Started	Sep 18 06:02:05 AM UTC 24
Finished	Sep 18 06:05:18 AM UTC 24
Peak memory	222288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672528757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.3672528757
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.2618177457
Short name	T598
Test name
Test status
Simulation time	109986078 ps
CPU time	3.95 seconds
Started	Sep 18 06:01:58 AM UTC 24
Finished	Sep 18 06:02:03 AM UTC 24
Peak memory	215716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618177457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2618177457
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.729131067
Short name	T239
Test name
Test status
Simulation time	164891468 ps
CPU time	21.37 seconds
Started	Sep 18 06:02:14 AM UTC 24
Finished	Sep 18 06:02:36 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729131067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.729131067
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.192674309
Short name	T150
Test name
Test status
Simulation time	198349717339 ps
CPU time	645.18 seconds
Started	Sep 18 06:02:15 AM UTC 24
Finished	Sep 18 06:13:09 AM UTC 24
Peak memory	221544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192674309 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.192674309
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2615717074
Short name	T615
Test name
Test status
Simulation time	289124887 ps
CPU time	3.55 seconds
Started	Sep 18 06:02:22 AM UTC 24
Finished	Sep 18 06:02:26 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615717074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2615717074
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.3514470752
Short name	T616
Test name
Test status
Simulation time	321020650 ps
CPU time	8.52 seconds
Started	Sep 18 06:02:19 AM UTC 24
Finished	Sep 18 06:02:29 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514470752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3514470752
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.3163379195
Short name	T625
Test name
Test status
Simulation time	225888797 ps
CPU time	33.95 seconds
Started	Sep 18 06:02:11 AM UTC 24
Finished	Sep 18 06:02:46 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163379195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3163379195
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.3066584869
Short name	T661
Test name
Test status
Simulation time	17376334960 ps
CPU time	82.73 seconds
Started	Sep 18 06:02:12 AM UTC 24
Finished	Sep 18 06:03:36 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066584869 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3066584869
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2773293272
Short name	T734
Test name
Test status
Simulation time	39981334883 ps
CPU time	209.96 seconds
Started	Sep 18 06:02:14 AM UTC 24
Finished	Sep 18 06:05:47 AM UTC 24
Peak memory	216172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773293272 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2773293272
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.4219378373
Short name	T611
Test name
Test status
Simulation time	54065301 ps
CPU time	9.05 seconds
Started	Sep 18 06:02:12 AM UTC 24
Finished	Sep 18 06:02:22 AM UTC 24
Peak memory	215712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219378373 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.4219378373
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.3261824764
Short name	T627
Test name
Test status
Simulation time	1664934979 ps
CPU time	27.06 seconds
Started	Sep 18 06:02:19 AM UTC 24
Finished	Sep 18 06:02:48 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261824764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3261824764
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.3178365935
Short name	T606
Test name
Test status
Simulation time	142256646 ps
CPU time	5.8 seconds
Started	Sep 18 06:02:08 AM UTC 24
Finished	Sep 18 06:02:15 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178365935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3178365935
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.4278630877
Short name	T626
Test name
Test status
Simulation time	5080709693 ps
CPU time	35.83 seconds
Started	Sep 18 06:02:09 AM UTC 24
Finished	Sep 18 06:02:46 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278630877 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.4278630877
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3669795609
Short name	T631
Test name
Test status
Simulation time	7284961532 ps
CPU time	38.18 seconds
Started	Sep 18 06:02:09 AM UTC 24
Finished	Sep 18 06:02:49 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669795609 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3669795609
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.4139840322
Short name	T605
Test name
Test status
Simulation time	29048834 ps
CPU time	3.19 seconds
Started	Sep 18 06:02:09 AM UTC 24
Finished	Sep 18 06:02:13 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139840322 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.4139840322
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.2022178993
Short name	T704
Test name
Test status
Simulation time	26122337895 ps
CPU time	153.47 seconds
Started	Sep 18 06:02:23 AM UTC 24
Finished	Sep 18 06:04:59 AM UTC 24
Peak memory	222052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022178993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2022178993
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2459654538
Short name	T622
Test name
Test status
Simulation time	244843219 ps
CPU time	15.32 seconds
Started	Sep 18 06:02:25 AM UTC 24
Finished	Sep 18 06:02:42 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459654538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2459654538
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1449834922
Short name	T666
Test name
Test status
Simulation time	166160134 ps
CPU time	74.97 seconds
Started	Sep 18 06:02:24 AM UTC 24
Finished	Sep 18 06:03:41 AM UTC 24
Peak memory	220072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449834922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.1449834922
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3407506446
Short name	T867
Test name
Test status
Simulation time	3997754553 ps
CPU time	435.04 seconds
Started	Sep 18 06:02:26 AM UTC 24
Finished	Sep 18 06:09:47 AM UTC 24
Peak memory	232952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407506446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.3407506446
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.732884765
Short name	T619
Test name
Test status
Simulation time	330944116 ps
CPU time	14.34 seconds
Started	Sep 18 06:02:21 AM UTC 24
Finished	Sep 18 06:02:36 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732884765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.732884765
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.2198183511
Short name	T628
Test name
Test status
Simulation time	142313851 ps
CPU time	8.27 seconds
Started	Sep 18 06:02:39 AM UTC 24
Finished	Sep 18 06:02:48 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198183511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2198183511
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.396694430
Short name	T896
Test name
Test status
Simulation time	141234646039 ps
CPU time	606.52 seconds
Started	Sep 18 06:02:42 AM UTC 24
Finished	Sep 18 06:12:56 AM UTC 24
Peak memory	221604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396694430 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.396694430
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.155105411
Short name	T644
Test name
Test status
Simulation time	173076165 ps
CPU time	18.96 seconds
Started	Sep 18 06:02:47 AM UTC 24
Finished	Sep 18 06:03:07 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155105411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.155105411
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.882661269
Short name	T639
Test name
Test status
Simulation time	140329778 ps
CPU time	15.82 seconds
Started	Sep 18 06:02:46 AM UTC 24
Finished	Sep 18 06:03:03 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882661269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.882661269
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.3043737356
Short name	T635
Test name
Test status
Simulation time	287496889 ps
CPU time	18.29 seconds
Started	Sep 18 06:02:35 AM UTC 24
Finished	Sep 18 06:02:55 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043737356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3043737356
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.3418749231
Short name	T294
Test name
Test status
Simulation time	48521917048 ps
CPU time	210.64 seconds
Started	Sep 18 06:02:38 AM UTC 24
Finished	Sep 18 06:06:11 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418749231 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3418749231
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2882142967
Short name	T721
Test name
Test status
Simulation time	26994749389 ps
CPU time	162.12 seconds
Started	Sep 18 06:02:39 AM UTC 24
Finished	Sep 18 06:05:24 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882142967 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2882142967
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.2210273467
Short name	T629
Test name
Test status
Simulation time	134954267 ps
CPU time	10.93 seconds
Started	Sep 18 06:02:37 AM UTC 24
Finished	Sep 18 06:02:49 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210273467 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2210273467
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.1545245220
Short name	T643
Test name
Test status
Simulation time	911600967 ps
CPU time	21.11 seconds
Started	Sep 18 06:02:44 AM UTC 24
Finished	Sep 18 06:03:07 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545245220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1545245220
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.3839695488
Short name	T618
Test name
Test status
Simulation time	430114578 ps
CPU time	5.77 seconds
Started	Sep 18 06:02:28 AM UTC 24
Finished	Sep 18 06:02:34 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839695488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3839695488
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2088813353
Short name	T73
Test name
Test status
Simulation time	8856819160 ps
CPU time	40.77 seconds
Started	Sep 18 06:02:30 AM UTC 24
Finished	Sep 18 06:03:12 AM UTC 24
Peak memory	216088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088813353 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2088813353
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1555999366
Short name	T641
Test name
Test status
Simulation time	3370586808 ps
CPU time	31.67 seconds
Started	Sep 18 06:02:33 AM UTC 24
Finished	Sep 18 06:03:06 AM UTC 24
Peak memory	216016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555999366 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1555999366
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1130814057
Short name	T617
Test name
Test status
Simulation time	33212229 ps
CPU time	2.12 seconds
Started	Sep 18 06:02:29 AM UTC 24
Finished	Sep 18 06:02:32 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130814057 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1130814057
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.1082991485
Short name	T653
Test name
Test status
Simulation time	8619194796 ps
CPU time	56.45 seconds
Started	Sep 18 06:02:48 AM UTC 24
Finished	Sep 18 06:03:46 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082991485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1082991485
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3612639318
Short name	T694
Test name
Test status
Simulation time	5171326720 ps
CPU time	113.7 seconds
Started	Sep 18 06:02:50 AM UTC 24
Finished	Sep 18 06:04:46 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612639318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3612639318
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1143941315
Short name	T140
Test name
Test status
Simulation time	4267107448 ps
CPU time	163.2 seconds
Started	Sep 18 06:02:50 AM UTC 24
Finished	Sep 18 06:05:35 AM UTC 24
Peak memory	222124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143941315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.1143941315
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3590593617
Short name	T749
Test name
Test status
Simulation time	494740499 ps
CPU time	194.12 seconds
Started	Sep 18 06:02:50 AM UTC 24
Finished	Sep 18 06:06:07 AM UTC 24
Peak memory	222480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590593617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.3590593617
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.3396438809
Short name	T646
Test name
Test status
Simulation time	187129396 ps
CPU time	22.3 seconds
Started	Sep 18 06:02:47 AM UTC 24
Finished	Sep 18 06:03:10 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396438809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3396438809
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.3527971978
Short name	T648
Test name
Test status
Simulation time	100791488 ps
CPU time	13.92 seconds
Started	Sep 18 06:03:00 AM UTC 24
Finished	Sep 18 06:03:15 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527971978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3527971978
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.15773294
Short name	T151
Test name
Test status
Simulation time	79077713849 ps
CPU time	606.76 seconds
Started	Sep 18 06:03:04 AM UTC 24
Finished	Sep 18 06:13:17 AM UTC 24
Peak memory	221540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15773294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.15773294
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1331283718
Short name	T656
Test name
Test status
Simulation time	516298321 ps
CPU time	15.93 seconds
Started	Sep 18 06:03:09 AM UTC 24
Finished	Sep 18 06:03:26 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331283718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1331283718
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.1614027958
Short name	T647
Test name
Test status
Simulation time	239771150 ps
CPU time	3.47 seconds
Started	Sep 18 06:03:07 AM UTC 24
Finished	Sep 18 06:03:12 AM UTC 24
Peak memory	215672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614027958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1614027958
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.727961222
Short name	T153
Test name
Test status
Simulation time	290868792 ps
CPU time	25.52 seconds
Started	Sep 18 06:02:56 AM UTC 24
Finished	Sep 18 06:03:22 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727961222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.727961222
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2270317789
Short name	T728
Test name
Test status
Simulation time	44939903314 ps
CPU time	159.86 seconds
Started	Sep 18 06:03:00 AM UTC 24
Finished	Sep 18 06:05:43 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270317789 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2270317789
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.202392126
Short name	T654
Test name
Test status
Simulation time	2332802687 ps
CPU time	22.67 seconds
Started	Sep 18 06:03:00 AM UTC 24
Finished	Sep 18 06:03:24 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202392126 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.202392126
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.4182982221
Short name	T233
Test name
Test status
Simulation time	158327143 ps
CPU time	25.58 seconds
Started	Sep 18 06:02:57 AM UTC 24
Finished	Sep 18 06:03:24 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182982221 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.4182982221
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.3564011678
Short name	T665
Test name
Test status
Simulation time	1891540967 ps
CPU time	33.08 seconds
Started	Sep 18 06:03:06 AM UTC 24
Finished	Sep 18 06:03:40 AM UTC 24
Peak memory	216036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564011678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3564011678
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.1135804213
Short name	T634
Test name
Test status
Simulation time	126775432 ps
CPU time	2.51 seconds
Started	Sep 18 06:02:50 AM UTC 24
Finished	Sep 18 06:02:53 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135804213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1135804213
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.773890972
Short name	T652
Test name
Test status
Simulation time	7144303454 ps
CPU time	27.08 seconds
Started	Sep 18 06:02:53 AM UTC 24
Finished	Sep 18 06:03:22 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773890972 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.773890972
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2092683967
Short name	T663
Test name
Test status
Simulation time	6970485280 ps
CPU time	43.01 seconds
Started	Sep 18 06:02:54 AM UTC 24
Finished	Sep 18 06:03:39 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092683967 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2092683967
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.960663620
Short name	T636
Test name
Test status
Simulation time	24654232 ps
CPU time	2.43 seconds
Started	Sep 18 06:02:52 AM UTC 24
Finished	Sep 18 06:02:55 AM UTC 24
Peak memory	215748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960663620 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.960663620
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.3620794374
Short name	T660
Test name
Test status
Simulation time	296670340 ps
CPU time	25.51 seconds
Started	Sep 18 06:03:09 AM UTC 24
Finished	Sep 18 06:03:36 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620794374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3620794374
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.492759392
Short name	T684
Test name
Test status
Simulation time	863084659 ps
CPU time	68.77 seconds
Started	Sep 18 06:03:11 AM UTC 24
Finished	Sep 18 06:04:21 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492759392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.492759392
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.566096116
Short name	T143
Test name
Test status
Simulation time	5193659374 ps
CPU time	302.8 seconds
Started	Sep 18 06:03:09 AM UTC 24
Finished	Sep 18 06:08:16 AM UTC 24
Peak memory	222404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566096116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.566096116
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1626762547
Short name	T751
Test name
Test status
Simulation time	1976354058 ps
CPU time	173.22 seconds
Started	Sep 18 06:03:12 AM UTC 24
Finished	Sep 18 06:06:09 AM UTC 24
Peak memory	221936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626762547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.1626762547
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.3773272269
Short name	T649
Test name
Test status
Simulation time	95727179 ps
CPU time	9.39 seconds
Started	Sep 18 06:03:07 AM UTC 24
Finished	Sep 18 06:03:18 AM UTC 24
Peak memory	218092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773272269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3773272269
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.495252762
Short name	T671
Test name
Test status
Simulation time	6300980952 ps
CPU time	37.92 seconds
Started	Sep 18 06:03:25 AM UTC 24
Finished	Sep 18 06:04:04 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495252762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.495252762
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.124211633
Short name	T255
Test name
Test status
Simulation time	64618875517 ps
CPU time	225.29 seconds
Started	Sep 18 06:03:25 AM UTC 24
Finished	Sep 18 06:07:14 AM UTC 24
Peak memory	218220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124211633 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.124211633
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3189093916
Short name	T664
Test name
Test status
Simulation time	127867120 ps
CPU time	9.75 seconds
Started	Sep 18 06:03:29 AM UTC 24
Finished	Sep 18 06:03:40 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189093916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3189093916
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.2804308576
Short name	T669
Test name
Test status
Simulation time	3839402933 ps
CPU time	24.33 seconds
Started	Sep 18 06:03:26 AM UTC 24
Finished	Sep 18 06:03:52 AM UTC 24
Peak memory	216028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804308576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2804308576
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.3614172421
Short name	T658
Test name
Test status
Simulation time	410874096 ps
CPU time	6.84 seconds
Started	Sep 18 06:03:19 AM UTC 24
Finished	Sep 18 06:03:28 AM UTC 24
Peak memory	215732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614172421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3614172421
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2552453289
Short name	T144
Test name
Test status
Simulation time	43127035450 ps
CPU time	303.29 seconds
Started	Sep 18 06:03:23 AM UTC 24
Finished	Sep 18 06:08:30 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552453289 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2552453289
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3988335740
Short name	T831
Test name
Test status
Simulation time	28177765902 ps
CPU time	311.71 seconds
Started	Sep 18 06:03:24 AM UTC 24
Finished	Sep 18 06:08:40 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988335740 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3988335740
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.99114904
Short name	T655
Test name
Test status
Simulation time	21133718 ps
CPU time	2.8 seconds
Started	Sep 18 06:03:21 AM UTC 24
Finished	Sep 18 06:03:24 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99114904 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.99114904
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.2299414115
Short name	T670
Test name
Test status
Simulation time	2578893230 ps
CPU time	33.37 seconds
Started	Sep 18 06:03:25 AM UTC 24
Finished	Sep 18 06:04:00 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299414115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2299414115
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.1537171058
Short name	T651
Test name
Test status
Simulation time	147914877 ps
CPU time	4.68 seconds
Started	Sep 18 06:03:14 AM UTC 24
Finished	Sep 18 06:03:19 AM UTC 24
Peak memory	215956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537171058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1537171058
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3952548903
Short name	T686
Test name
Test status
Simulation time	7075037314 ps
CPU time	69.17 seconds
Started	Sep 18 06:03:16 AM UTC 24
Finished	Sep 18 06:04:27 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952548903 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3952548903
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2151834141
Short name	T676
Test name
Test status
Simulation time	6777281086 ps
CPU time	48.46 seconds
Started	Sep 18 06:03:19 AM UTC 24
Finished	Sep 18 06:04:10 AM UTC 24
Peak memory	215636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151834141 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2151834141
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.4006510055
Short name	T650
Test name
Test status
Simulation time	77613077 ps
CPU time	2.92 seconds
Started	Sep 18 06:03:15 AM UTC 24
Finished	Sep 18 06:03:19 AM UTC 24
Peak memory	215752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006510055 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.4006510055
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.2545061940
Short name	T234
Test name
Test status
Simulation time	415838784 ps
CPU time	10.9 seconds
Started	Sep 18 06:03:35 AM UTC 24
Finished	Sep 18 06:03:47 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545061940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2545061940
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1554909843
Short name	T732
Test name
Test status
Simulation time	1177305961 ps
CPU time	124.98 seconds
Started	Sep 18 06:03:38 AM UTC 24
Finished	Sep 18 06:05:45 AM UTC 24
Peak memory	221928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554909843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1554909843
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.396810743
Short name	T209
Test name
Test status
Simulation time	211773362 ps
CPU time	109.31 seconds
Started	Sep 18 06:03:36 AM UTC 24
Finished	Sep 18 06:05:28 AM UTC 24
Peak memory	219876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396810743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.396810743
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1087549958
Short name	T719
Test name
Test status
Simulation time	740004153 ps
CPU time	96.72 seconds
Started	Sep 18 06:03:39 AM UTC 24
Finished	Sep 18 06:05:18 AM UTC 24
Peak memory	219888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087549958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.1087549958
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.4196218856
Short name	T138
Test name
Test status
Simulation time	1902770258 ps
CPU time	34.86 seconds
Started	Sep 18 06:03:28 AM UTC 24
Finished	Sep 18 06:04:04 AM UTC 24
Peak memory	215720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196218856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.4196218856
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.1994768232
Short name	T682
Test name
Test status
Simulation time	323557529 ps
CPU time	30.65 seconds
Started	Sep 18 06:03:49 AM UTC 24
Finished	Sep 18 06:04:21 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994768232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1994768232
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3704592013
Short name	T145
Test name
Test status
Simulation time	71218491348 ps
CPU time	301.72 seconds
Started	Sep 18 06:03:52 AM UTC 24
Finished	Sep 18 06:08:58 AM UTC 24
Peak memory	218156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704592013 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.3704592013
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.4082551805
Short name	T673
Test name
Test status
Simulation time	29560098 ps
CPU time	2.66 seconds
Started	Sep 18 06:04:05 AM UTC 24
Finished	Sep 18 06:04:09 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082551805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.4082551805
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.3081914528
Short name	T677
Test name
Test status
Simulation time	502782658 ps
CPU time	15.02 seconds
Started	Sep 18 06:03:54 AM UTC 24
Finished	Sep 18 06:04:10 AM UTC 24
Peak memory	215716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081914528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3081914528
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.1209719976
Short name	T668
Test name
Test status
Simulation time	39128312 ps
CPU time	4.72 seconds
Started	Sep 18 06:03:46 AM UTC 24
Finished	Sep 18 06:03:51 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209719976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1209719976
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.2723528406
Short name	T873
Test name
Test status
Simulation time	198876020955 ps
CPU time	378.73 seconds
Started	Sep 18 06:03:47 AM UTC 24
Finished	Sep 18 06:10:11 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723528406 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2723528406
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2687056678
Short name	T700
Test name
Test status
Simulation time	27087081131 ps
CPU time	58.76 seconds
Started	Sep 18 06:03:47 AM UTC 24
Finished	Sep 18 06:04:48 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687056678 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2687056678
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.554902573
Short name	T674
Test name
Test status
Simulation time	162425273 ps
CPU time	20.65 seconds
Started	Sep 18 06:03:47 AM UTC 24
Finished	Sep 18 06:04:09 AM UTC 24
Peak memory	216036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554902573 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.554902573
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.1482427379
Short name	T678
Test name
Test status
Simulation time	674311512 ps
CPU time	17.07 seconds
Started	Sep 18 06:03:54 AM UTC 24
Finished	Sep 18 06:04:12 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482427379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1482427379
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.610586778
Short name	T74
Test name
Test status
Simulation time	98920426 ps
CPU time	4.46 seconds
Started	Sep 18 06:03:41 AM UTC 24
Finished	Sep 18 06:03:46 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610586778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.610586778
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.48236612
Short name	T689
Test name
Test status
Simulation time	5923798045 ps
CPU time	47.46 seconds
Started	Sep 18 06:03:42 AM UTC 24
Finished	Sep 18 06:04:31 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48236612 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.48236612
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.320097818
Short name	T679
Test name
Test status
Simulation time	7998850505 ps
CPU time	32.83 seconds
Started	Sep 18 06:03:42 AM UTC 24
Finished	Sep 18 06:04:17 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320097818 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.320097818
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1351239410
Short name	T667
Test name
Test status
Simulation time	49726720 ps
CPU time	2.86 seconds
Started	Sep 18 06:03:41 AM UTC 24
Finished	Sep 18 06:03:45 AM UTC 24
Peak memory	215692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351239410 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1351239410
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.1305953797
Short name	T731
Test name
Test status
Simulation time	14260219530 ps
CPU time	95.33 seconds
Started	Sep 18 06:04:07 AM UTC 24
Finished	Sep 18 06:05:44 AM UTC 24
Peak memory	220200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305953797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1305953797
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3447995154
Short name	T786
Test name
Test status
Simulation time	10189248133 ps
CPU time	181.29 seconds
Started	Sep 18 06:04:10 AM UTC 24
Finished	Sep 18 06:07:15 AM UTC 24
Peak memory	222056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447995154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3447995154
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3332723320
Short name	T705
Test name
Test status
Simulation time	96286501 ps
CPU time	47.22 seconds
Started	Sep 18 06:04:10 AM UTC 24
Finished	Sep 18 06:04:59 AM UTC 24
Peak memory	217840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332723320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.3332723320
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3491422773
Short name	T768
Test name
Test status
Simulation time	1064860722 ps
CPU time	144.51 seconds
Started	Sep 18 06:04:11 AM UTC 24
Finished	Sep 18 06:06:37 AM UTC 24
Peak memory	222284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491422773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.3491422773
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.1868298648
Short name	T687
Test name
Test status
Simulation time	513514480 ps
CPU time	25.41 seconds
Started	Sep 18 06:04:01 AM UTC 24
Finished	Sep 18 06:04:28 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868298648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1868298648
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1316746652
Short name	T803
Test name
Test status
Simulation time	28393531116 ps
CPU time	200.54 seconds
Started	Sep 18 06:04:23 AM UTC 24
Finished	Sep 18 06:07:46 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316746652 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.1316746652
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.754373519
Short name	T695
Test name
Test status
Simulation time	269428148 ps
CPU time	15.8 seconds
Started	Sep 18 06:04:29 AM UTC 24
Finished	Sep 18 06:04:46 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754373519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.754373519
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.2595534211
Short name	T691
Test name
Test status
Simulation time	80230521 ps
CPU time	9.74 seconds
Started	Sep 18 06:04:27 AM UTC 24
Finished	Sep 18 06:04:38 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595534211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2595534211
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.2815284521
Short name	T688
Test name
Test status
Simulation time	473120128 ps
CPU time	11.04 seconds
Started	Sep 18 06:04:18 AM UTC 24
Finished	Sep 18 06:04:31 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815284521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2815284521
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.133120881
Short name	T763
Test name
Test status
Simulation time	33667301599 ps
CPU time	130.78 seconds
Started	Sep 18 06:04:18 AM UTC 24
Finished	Sep 18 06:06:31 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133120881 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.133120881
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2840212158
Short name	T740
Test name
Test status
Simulation time	14053935012 ps
CPU time	92.51 seconds
Started	Sep 18 06:04:23 AM UTC 24
Finished	Sep 18 06:05:57 AM UTC 24
Peak memory	218220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840212158 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2840212158
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.1237416620
Short name	T685
Test name
Test status
Simulation time	26724367 ps
CPU time	4.39 seconds
Started	Sep 18 06:04:18 AM UTC 24
Finished	Sep 18 06:04:23 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237416620 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1237416620
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.2982267302
Short name	T697
Test name
Test status
Simulation time	1622934624 ps
CPU time	21.17 seconds
Started	Sep 18 06:04:24 AM UTC 24
Finished	Sep 18 06:04:47 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982267302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2982267302
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.2694670504
Short name	T681
Test name
Test status
Simulation time	133591988 ps
CPU time	5.56 seconds
Started	Sep 18 06:04:11 AM UTC 24
Finished	Sep 18 06:04:17 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694670504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2694670504
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3701703618
Short name	T698
Test name
Test status
Simulation time	15395902138 ps
CPU time	32.93 seconds
Started	Sep 18 06:04:12 AM UTC 24
Finished	Sep 18 06:04:47 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701703618 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3701703618
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.4079603691
Short name	T693
Test name
Test status
Simulation time	5772914020 ps
CPU time	29.9 seconds
Started	Sep 18 06:04:14 AM UTC 24
Finished	Sep 18 06:04:45 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079603691 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.4079603691
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1298621929
Short name	T680
Test name
Test status
Simulation time	34013330 ps
CPU time	3.33 seconds
Started	Sep 18 06:04:12 AM UTC 24
Finished	Sep 18 06:04:17 AM UTC 24
Peak memory	215884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298621929 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1298621929
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.2295661999
Short name	T744
Test name
Test status
Simulation time	634097622 ps
CPU time	85.94 seconds
Started	Sep 18 06:04:32 AM UTC 24
Finished	Sep 18 06:06:00 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295661999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2295661999
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.955503288
Short name	T752
Test name
Test status
Simulation time	819765623 ps
CPU time	89.68 seconds
Started	Sep 18 06:04:39 AM UTC 24
Finished	Sep 18 06:06:11 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955503288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.955503288
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3058444667
Short name	T780
Test name
Test status
Simulation time	161863770 ps
CPU time	140.45 seconds
Started	Sep 18 06:04:32 AM UTC 24
Finished	Sep 18 06:06:55 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058444667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.3058444667
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.536297940
Short name	T706
Test name
Test status
Simulation time	133160965 ps
CPU time	23.34 seconds
Started	Sep 18 06:04:39 AM UTC 24
Finished	Sep 18 06:05:03 AM UTC 24
Peak memory	218100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536297940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.536297940
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.3951371213
Short name	T692
Test name
Test status
Simulation time	67474455 ps
CPU time	11.14 seconds
Started	Sep 18 06:04:29 AM UTC 24
Finished	Sep 18 06:04:41 AM UTC 24
Peak memory	218096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951371213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3951371213
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.932607156
Short name	T34
Test name
Test status
Simulation time	424445908 ps
CPU time	53.27 seconds
Started	Sep 18 05:48:30 AM UTC 24
Finished	Sep 18 05:49:25 AM UTC 24
Peak memory	218024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932607156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.932607156
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.58877506
Short name	T215
Test name
Test status
Simulation time	22167561850 ps
CPU time	196.55 seconds
Started	Sep 18 05:48:33 AM UTC 24
Finished	Sep 18 05:51:52 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58877506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 7/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.58877506
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2207270499
Short name	T162
Test name
Test status
Simulation time	25349763 ps
CPU time	4.33 seconds
Started	Sep 18 05:48:36 AM UTC 24
Finished	Sep 18 05:48:41 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207270499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2207270499
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.1437011121
Short name	T160
Test name
Test status
Simulation time	57546804 ps
CPU time	2.67 seconds
Started	Sep 18 05:48:35 AM UTC 24
Finished	Sep 18 05:48:38 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437011121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1437011121
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.1549267576
Short name	T290
Test name
Test status
Simulation time	211261167 ps
CPU time	6.2 seconds
Started	Sep 18 05:48:27 AM UTC 24
Finished	Sep 18 05:48:35 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549267576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1549267576
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.243091900
Short name	T61
Test name
Test status
Simulation time	33807331280 ps
CPU time	122.53 seconds
Started	Sep 18 05:48:29 AM UTC 24
Finished	Sep 18 05:50:33 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243091900 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.243091900
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1529999217
Short name	T202
Test name
Test status
Simulation time	15680322695 ps
CPU time	122.43 seconds
Started	Sep 18 05:48:29 AM UTC 24
Finished	Sep 18 05:50:33 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529999217 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1529999217
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.3946483499
Short name	T100
Test name
Test status
Simulation time	327726926 ps
CPU time	23.21 seconds
Started	Sep 18 05:48:28 AM UTC 24
Finished	Sep 18 05:48:53 AM UTC 24
Peak memory	218076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946483499 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3946483499
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.2975152446
Short name	T103
Test name
Test status
Simulation time	290313774 ps
CPU time	24.73 seconds
Started	Sep 18 05:48:35 AM UTC 24
Finished	Sep 18 05:49:01 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975152446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2975152446
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.4225204682
Short name	T121
Test name
Test status
Simulation time	177065051 ps
CPU time	5.19 seconds
Started	Sep 18 05:48:22 AM UTC 24
Finished	Sep 18 05:48:28 AM UTC 24
Peak memory	215752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225204682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4225204682
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2516049595
Short name	T227
Test name
Test status
Simulation time	7506043807 ps
CPU time	54.6 seconds
Started	Sep 18 05:48:25 AM UTC 24
Finished	Sep 18 05:49:22 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516049595 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2516049595
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.949794705
Short name	T102
Test name
Test status
Simulation time	5831839477 ps
CPU time	31.45 seconds
Started	Sep 18 05:48:27 AM UTC 24
Finished	Sep 18 05:49:00 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949794705 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.949794705
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2771386
Short name	T122
Test name
Test status
Simulation time	33507634 ps
CPU time	3.25 seconds
Started	Sep 18 05:48:24 AM UTC 24
Finished	Sep 18 05:48:29 AM UTC 24
Peak memory	215752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771386 -assert nopostproc +UVM_TESTNAME=xbar_b ase_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2771386
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.3055029814
Short name	T88
Test name
Test status
Simulation time	1349496730 ps
CPU time	51.52 seconds
Started	Sep 18 05:48:38 AM UTC 24
Finished	Sep 18 05:49:30 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055029814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3055029814
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.642191541
Short name	T284
Test name
Test status
Simulation time	3313911557 ps
CPU time	116.58 seconds
Started	Sep 18 05:48:38 AM UTC 24
Finished	Sep 18 05:50:36 AM UTC 24
Peak memory	219940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642191541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.642191541
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2401285331
Short name	T211
Test name
Test status
Simulation time	1037048681 ps
CPU time	211.65 seconds
Started	Sep 18 05:48:38 AM UTC 24
Finished	Sep 18 05:52:13 AM UTC 24
Peak memory	221932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401285331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.2401285331
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.809645554
Short name	T325
Test name
Test status
Simulation time	3892308741 ps
CPU time	281.49 seconds
Started	Sep 18 05:48:40 AM UTC 24
Finished	Sep 18 05:53:25 AM UTC 24
Peak memory	232592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809645554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.809645554
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.2303280500
Short name	T199
Test name
Test status
Simulation time	157176575 ps
CPU time	9.51 seconds
Started	Sep 18 05:48:36 AM UTC 24
Finished	Sep 18 05:48:46 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303280500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2303280500
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.4131642916
Short name	T720
Test name
Test status
Simulation time	244391023 ps
CPU time	31.83 seconds
Started	Sep 18 06:04:48 AM UTC 24
Finished	Sep 18 06:05:21 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131642916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4131642916
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3151510565
Short name	T198
Test name
Test status
Simulation time	29977824899 ps
CPU time	257.61 seconds
Started	Sep 18 06:04:50 AM UTC 24
Finished	Sep 18 06:09:11 AM UTC 24
Peak memory	218156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151510565 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3151510565
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3447791577
Short name	T710
Test name
Test status
Simulation time	142447185 ps
CPU time	16.65 seconds
Started	Sep 18 06:04:51 AM UTC 24
Finished	Sep 18 06:05:09 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447791577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3447791577
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.3027042578
Short name	T707
Test name
Test status
Simulation time	368038060 ps
CPU time	13.73 seconds
Started	Sep 18 06:04:50 AM UTC 24
Finished	Sep 18 06:05:04 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027042578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3027042578
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.2516272493
Short name	T716
Test name
Test status
Simulation time	1737744105 ps
CPU time	27.89 seconds
Started	Sep 18 06:04:48 AM UTC 24
Finished	Sep 18 06:05:17 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516272493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2516272493
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.1668204801
Short name	T715
Test name
Test status
Simulation time	11471813200 ps
CPU time	27.59 seconds
Started	Sep 18 06:04:48 AM UTC 24
Finished	Sep 18 06:05:16 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668204801 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1668204801
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.316442001
Short name	T856
Test name
Test status
Simulation time	37030156314 ps
CPU time	262.04 seconds
Started	Sep 18 06:04:48 AM UTC 24
Finished	Sep 18 06:09:13 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316442001 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.316442001
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.1171837978
Short name	T708
Test name
Test status
Simulation time	105010927 ps
CPU time	18 seconds
Started	Sep 18 06:04:48 AM UTC 24
Finished	Sep 18 06:05:07 AM UTC 24
Peak memory	217824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171837978 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1171837978
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.1938635044
Short name	T722
Test name
Test status
Simulation time	1920971206 ps
CPU time	33.56 seconds
Started	Sep 18 06:04:50 AM UTC 24
Finished	Sep 18 06:05:24 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938635044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1938635044
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.3870614593
Short name	T696
Test name
Test status
Simulation time	33261374 ps
CPU time	2.6 seconds
Started	Sep 18 06:04:43 AM UTC 24
Finished	Sep 18 06:04:46 AM UTC 24
Peak memory	216020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870614593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3870614593
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2718911269
Short name	T724
Test name
Test status
Simulation time	32569373891 ps
CPU time	46.52 seconds
Started	Sep 18 06:04:44 AM UTC 24
Finished	Sep 18 06:05:32 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718911269 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2718911269
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1781996186
Short name	T713
Test name
Test status
Simulation time	5451854334 ps
CPU time	25.91 seconds
Started	Sep 18 06:04:47 AM UTC 24
Finished	Sep 18 06:05:15 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781996186 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1781996186
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1071234509
Short name	T699
Test name
Test status
Simulation time	27974046 ps
CPU time	3.1 seconds
Started	Sep 18 06:04:43 AM UTC 24
Finished	Sep 18 06:04:47 AM UTC 24
Peak memory	215948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071234509 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1071234509
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.2756643427
Short name	T758
Test name
Test status
Simulation time	532509981 ps
CPU time	85.55 seconds
Started	Sep 18 06:04:53 AM UTC 24
Finished	Sep 18 06:06:21 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756643427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2756643427
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2669167805
Short name	T730
Test name
Test status
Simulation time	512490942 ps
CPU time	42.18 seconds
Started	Sep 18 06:05:00 AM UTC 24
Finished	Sep 18 06:05:44 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669167805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2669167805
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.349429467
Short name	T832
Test name
Test status
Simulation time	10047173506 ps
CPU time	213.18 seconds
Started	Sep 18 06:05:04 AM UTC 24
Finished	Sep 18 06:08:41 AM UTC 24
Peak memory	222164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349429467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.349429467
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.2076384241
Short name	T709
Test name
Test status
Simulation time	295331958 ps
CPU time	16.03 seconds
Started	Sep 18 06:04:50 AM UTC 24
Finished	Sep 18 06:05:07 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076384241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2076384241
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.3586828546
Short name	T141
Test name
Test status
Simulation time	563806468 ps
CPU time	31.37 seconds
Started	Sep 18 06:05:18 AM UTC 24
Finished	Sep 18 06:05:51 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586828546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3586828546
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3503908366
Short name	T897
Test name
Test status
Simulation time	74227638846 ps
CPU time	501.14 seconds
Started	Sep 18 06:05:18 AM UTC 24
Finished	Sep 18 06:13:45 AM UTC 24
Peak memory	221608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503908366 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.3503908366
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.595185657
Short name	T743
Test name
Test status
Simulation time	2084975329 ps
CPU time	38.84 seconds
Started	Sep 18 06:05:20 AM UTC 24
Finished	Sep 18 06:06:00 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595185657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.595185657
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.62542690
Short name	T736
Test name
Test status
Simulation time	2397751205 ps
CPU time	29.36 seconds
Started	Sep 18 06:05:20 AM UTC 24
Finished	Sep 18 06:05:50 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62542690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.62542690
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.25084138
Short name	T735
Test name
Test status
Simulation time	633473357 ps
CPU time	33.91 seconds
Started	Sep 18 06:05:12 AM UTC 24
Finished	Sep 18 06:05:48 AM UTC 24
Peak memory	218024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25084138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.25084138
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.2622636281
Short name	T802
Test name
Test status
Simulation time	40964636049 ps
CPU time	147.41 seconds
Started	Sep 18 06:05:16 AM UTC 24
Finished	Sep 18 06:07:46 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622636281 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2622636281
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3493392918
Short name	T796
Test name
Test status
Simulation time	37425015287 ps
CPU time	129.49 seconds
Started	Sep 18 06:05:18 AM UTC 24
Finished	Sep 18 06:07:29 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493392918 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3493392918
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.2602088968
Short name	T723
Test name
Test status
Simulation time	161611373 ps
CPU time	15.55 seconds
Started	Sep 18 06:05:13 AM UTC 24
Finished	Sep 18 06:05:30 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602088968 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2602088968
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.1381839231
Short name	T311
Test name
Test status
Simulation time	7913255961 ps
CPU time	35.07 seconds
Started	Sep 18 06:05:20 AM UTC 24
Finished	Sep 18 06:05:56 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381839231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1381839231
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.3301261135
Short name	T712
Test name
Test status
Simulation time	150637986 ps
CPU time	5.47 seconds
Started	Sep 18 06:05:06 AM UTC 24
Finished	Sep 18 06:05:12 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301261135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3301261135
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1856401887
Short name	T729
Test name
Test status
Simulation time	8220795065 ps
CPU time	34.25 seconds
Started	Sep 18 06:05:07 AM UTC 24
Finished	Sep 18 06:05:43 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856401887 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1856401887
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3567002251
Short name	T733
Test name
Test status
Simulation time	4129692790 ps
CPU time	35.21 seconds
Started	Sep 18 06:05:10 AM UTC 24
Finished	Sep 18 06:05:46 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567002251 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3567002251
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1651369534
Short name	T711
Test name
Test status
Simulation time	29059495 ps
CPU time	3.07 seconds
Started	Sep 18 06:05:07 AM UTC 24
Finished	Sep 18 06:05:11 AM UTC 24
Peak memory	215592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651369534 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1651369534
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.686644987
Short name	T822
Test name
Test status
Simulation time	7287757525 ps
CPU time	175.99 seconds
Started	Sep 18 06:05:22 AM UTC 24
Finished	Sep 18 06:08:21 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686644987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.686644987
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2648176916
Short name	T801
Test name
Test status
Simulation time	5834928239 ps
CPU time	137.67 seconds
Started	Sep 18 06:05:25 AM UTC 24
Finished	Sep 18 06:07:45 AM UTC 24
Peak memory	222056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648176916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2648176916
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.2359775108
Short name	T860
Test name
Test status
Simulation time	5384986285 ps
CPU time	231.87 seconds
Started	Sep 18 06:05:25 AM UTC 24
Finished	Sep 18 06:09:21 AM UTC 24
Peak memory	222252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359775108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.2359775108
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2854369602
Short name	T766
Test name
Test status
Simulation time	765480823 ps
CPU time	64.89 seconds
Started	Sep 18 06:05:29 AM UTC 24
Finished	Sep 18 06:06:35 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854369602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.2854369602
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.2545614871
Short name	T737
Test name
Test status
Simulation time	1277885051 ps
CPU time	29.52 seconds
Started	Sep 18 06:05:20 AM UTC 24
Finished	Sep 18 06:05:51 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545614871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2545614871
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.4040062262
Short name	T738
Test name
Test status
Simulation time	722575108 ps
CPU time	5.2 seconds
Started	Sep 18 06:05:46 AM UTC 24
Finished	Sep 18 06:05:52 AM UTC 24
Peak memory	215716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040062262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.4040062262
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1724941873
Short name	T894
Test name
Test status
Simulation time	183391562751 ps
CPU time	413.25 seconds
Started	Sep 18 06:05:46 AM UTC 24
Finished	Sep 18 06:12:44 AM UTC 24
Peak memory	217904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724941873 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.1724941873
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3201402968
Short name	T753
Test name
Test status
Simulation time	503717683 ps
CPU time	21.22 seconds
Started	Sep 18 06:05:49 AM UTC 24
Finished	Sep 18 06:06:11 AM UTC 24
Peak memory	215468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201402968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3201402968
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.1455331088
Short name	T739
Test name
Test status
Simulation time	173085934 ps
CPU time	6.42 seconds
Started	Sep 18 06:05:47 AM UTC 24
Finished	Sep 18 06:05:55 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455331088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1455331088
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.4129961583
Short name	T747
Test name
Test status
Simulation time	538505101 ps
CPU time	23.23 seconds
Started	Sep 18 06:05:38 AM UTC 24
Finished	Sep 18 06:06:02 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129961583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.4129961583
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1472892960
Short name	T836
Test name
Test status
Simulation time	31197472805 ps
CPU time	181.09 seconds
Started	Sep 18 06:05:46 AM UTC 24
Finished	Sep 18 06:08:49 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472892960 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1472892960
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.219656007
Short name	T843
Test name
Test status
Simulation time	26536555916 ps
CPU time	190.36 seconds
Started	Sep 18 06:05:46 AM UTC 24
Finished	Sep 18 06:08:59 AM UTC 24
Peak memory	216104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219656007 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.219656007
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.4249107879
Short name	T741
Test name
Test status
Simulation time	255735558 ps
CPU time	19.32 seconds
Started	Sep 18 06:05:38 AM UTC 24
Finished	Sep 18 06:05:58 AM UTC 24
Peak memory	217824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249107879 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.4249107879
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.2649929423
Short name	T754
Test name
Test status
Simulation time	1227378293 ps
CPU time	25.74 seconds
Started	Sep 18 06:05:47 AM UTC 24
Finished	Sep 18 06:06:14 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649929423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2649929423
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.2322630045
Short name	T727
Test name
Test status
Simulation time	229569456 ps
CPU time	4.34 seconds
Started	Sep 18 06:05:31 AM UTC 24
Finished	Sep 18 06:05:36 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322630045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2322630045
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.4190248424
Short name	T750
Test name
Test status
Simulation time	4838341281 ps
CPU time	31.83 seconds
Started	Sep 18 06:05:35 AM UTC 24
Finished	Sep 18 06:06:08 AM UTC 24
Peak memory	216088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190248424 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.4190248424
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1240560330
Short name	T746
Test name
Test status
Simulation time	2915884571 ps
CPU time	23.62 seconds
Started	Sep 18 06:05:36 AM UTC 24
Finished	Sep 18 06:06:01 AM UTC 24
Peak memory	216016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240560330 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1240560330
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.559764707
Short name	T726
Test name
Test status
Simulation time	27720422 ps
CPU time	2.71 seconds
Started	Sep 18 06:05:32 AM UTC 24
Finished	Sep 18 06:05:36 AM UTC 24
Peak memory	215752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559764707 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.559764707
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.3716757800
Short name	T210
Test name
Test status
Simulation time	916474151 ps
CPU time	102.24 seconds
Started	Sep 18 06:05:52 AM UTC 24
Finished	Sep 18 06:07:36 AM UTC 24
Peak memory	220048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716757800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3716757800
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.315861352
Short name	T790
Test name
Test status
Simulation time	3274665843 ps
CPU time	85.21 seconds
Started	Sep 18 06:05:52 AM UTC 24
Finished	Sep 18 06:07:19 AM UTC 24
Peak memory	217900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315861352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.315861352
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1743246592
Short name	T887
Test name
Test status
Simulation time	1395396912 ps
CPU time	346.93 seconds
Started	Sep 18 06:05:52 AM UTC 24
Finished	Sep 18 06:11:43 AM UTC 24
Peak memory	222280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743246592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.1743246592
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1047398300
Short name	T757
Test name
Test status
Simulation time	50326783 ps
CPU time	25.56 seconds
Started	Sep 18 06:05:53 AM UTC 24
Finished	Sep 18 06:06:20 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047398300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.1047398300
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.496649427
Short name	T748
Test name
Test status
Simulation time	105462126 ps
CPU time	16.46 seconds
Started	Sep 18 06:05:49 AM UTC 24
Finished	Sep 18 06:06:06 AM UTC 24
Peak memory	215484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496649427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.496649427
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.2067463221
Short name	T777
Test name
Test status
Simulation time	5520247315 ps
CPU time	46.14 seconds
Started	Sep 18 06:06:03 AM UTC 24
Finished	Sep 18 06:06:51 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067463221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2067463221
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1907203270
Short name	T146
Test name
Test status
Simulation time	46851790845 ps
CPU time	303.82 seconds
Started	Sep 18 06:06:03 AM UTC 24
Finished	Sep 18 06:11:11 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907203270 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.1907203270
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3861176344
Short name	T772
Test name
Test status
Simulation time	1804550307 ps
CPU time	29.7 seconds
Started	Sep 18 06:06:10 AM UTC 24
Finished	Sep 18 06:06:41 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861176344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3861176344
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.3610918482
Short name	T764
Test name
Test status
Simulation time	543080814 ps
CPU time	20.09 seconds
Started	Sep 18 06:06:10 AM UTC 24
Finished	Sep 18 06:06:31 AM UTC 24
Peak memory	215712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610918482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3610918482
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.161739881
Short name	T256
Test name
Test status
Simulation time	113757919 ps
CPU time	17.68 seconds
Started	Sep 18 06:06:01 AM UTC 24
Finished	Sep 18 06:06:20 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161739881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.161739881
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.3178518567
Short name	T851
Test name
Test status
Simulation time	74296331919 ps
CPU time	182.53 seconds
Started	Sep 18 06:06:02 AM UTC 24
Finished	Sep 18 06:09:07 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178518567 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3178518567
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2711627768
Short name	T864
Test name
Test status
Simulation time	30174218041 ps
CPU time	214.96 seconds
Started	Sep 18 06:06:02 AM UTC 24
Finished	Sep 18 06:09:40 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711627768 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2711627768
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.3269423461
Short name	T756
Test name
Test status
Simulation time	123755214 ps
CPU time	14.93 seconds
Started	Sep 18 06:06:01 AM UTC 24
Finished	Sep 18 06:06:18 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269423461 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3269423461
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.261058879
Short name	T755
Test name
Test status
Simulation time	74951801 ps
CPU time	7.73 seconds
Started	Sep 18 06:06:08 AM UTC 24
Finished	Sep 18 06:06:16 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261058879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.261058879
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.1070703538
Short name	T742
Test name
Test status
Simulation time	42686363 ps
CPU time	3.09 seconds
Started	Sep 18 06:05:56 AM UTC 24
Finished	Sep 18 06:06:00 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070703538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1070703538
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3579760202
Short name	T769
Test name
Test status
Simulation time	8187489491 ps
CPU time	38.92 seconds
Started	Sep 18 06:05:58 AM UTC 24
Finished	Sep 18 06:06:38 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579760202 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3579760202
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1425257456
Short name	T762
Test name
Test status
Simulation time	10902545499 ps
CPU time	26.59 seconds
Started	Sep 18 06:06:00 AM UTC 24
Finished	Sep 18 06:06:27 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425257456 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1425257456
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1086348169
Short name	T745
Test name
Test status
Simulation time	75766615 ps
CPU time	2.39 seconds
Started	Sep 18 06:05:57 AM UTC 24
Finished	Sep 18 06:06:00 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086348169 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1086348169
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.4017542204
Short name	T799
Test name
Test status
Simulation time	5470637888 ps
CPU time	83.44 seconds
Started	Sep 18 06:06:12 AM UTC 24
Finished	Sep 18 06:07:37 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017542204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.4017542204
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.35470165
Short name	T849
Test name
Test status
Simulation time	27122100480 ps
CPU time	167.8 seconds
Started	Sep 18 06:06:13 AM UTC 24
Finished	Sep 18 06:09:04 AM UTC 24
Peak memory	218152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35470165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.35470165
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1920969903
Short name	T892
Test name
Test status
Simulation time	2650000113 ps
CPU time	376.04 seconds
Started	Sep 18 06:06:12 AM UTC 24
Finished	Sep 18 06:12:33 AM UTC 24
Peak memory	219948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920969903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.1920969903
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.628005699
Short name	T760
Test name
Test status
Simulation time	104198896 ps
CPU time	6.62 seconds
Started	Sep 18 06:06:15 AM UTC 24
Finished	Sep 18 06:06:23 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628005699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.628005699
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.2601439038
Short name	T247
Test name
Test status
Simulation time	945203542 ps
CPU time	30.42 seconds
Started	Sep 18 06:06:10 AM UTC 24
Finished	Sep 18 06:06:42 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601439038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2601439038
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.2832115644
Short name	T789
Test name
Test status
Simulation time	1794847446 ps
CPU time	47.77 seconds
Started	Sep 18 06:06:28 AM UTC 24
Finished	Sep 18 06:07:18 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832115644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2832115644
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.112962063
Short name	T900
Test name
Test status
Simulation time	57068716057 ps
CPU time	482.79 seconds
Started	Sep 18 06:06:33 AM UTC 24
Finished	Sep 18 06:14:42 AM UTC 24
Peak memory	219820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112962063 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.112962063
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2090316117
Short name	T782
Test name
Test status
Simulation time	252782656 ps
CPU time	23.11 seconds
Started	Sep 18 06:06:39 AM UTC 24
Finished	Sep 18 06:07:04 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090316117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2090316117
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1670156416
Short name	T793
Test name
Test status
Simulation time	1021918649 ps
CPU time	47.7 seconds
Started	Sep 18 06:06:35 AM UTC 24
Finished	Sep 18 06:07:25 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670156416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1670156416
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.10956526
Short name	T773
Test name
Test status
Simulation time	825980623 ps
CPU time	19.76 seconds
Started	Sep 18 06:06:22 AM UTC 24
Finished	Sep 18 06:06:43 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10956526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.10956526
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.5258842
Short name	T771
Test name
Test status
Simulation time	2557972876 ps
CPU time	14.86 seconds
Started	Sep 18 06:06:25 AM UTC 24
Finished	Sep 18 06:06:41 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5258842 -assert nopostproc +UVM_TESTNAME=xbar_base_t est +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.5258842
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2412327124
Short name	T880
Test name
Test status
Simulation time	56409607706 ps
CPU time	273.08 seconds
Started	Sep 18 06:06:25 AM UTC 24
Finished	Sep 18 06:11:02 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412327124 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2412327124
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.1676907865
Short name	T765
Test name
Test status
Simulation time	103092118 ps
CPU time	10.56 seconds
Started	Sep 18 06:06:22 AM UTC 24
Finished	Sep 18 06:06:34 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676907865 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1676907865
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3682491373
Short name	T770
Test name
Test status
Simulation time	183268072 ps
CPU time	6.21 seconds
Started	Sep 18 06:06:33 AM UTC 24
Finished	Sep 18 06:06:41 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682491373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3682491373
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.2836286548
Short name	T759
Test name
Test status
Simulation time	31011167 ps
CPU time	2.84 seconds
Started	Sep 18 06:06:18 AM UTC 24
Finished	Sep 18 06:06:22 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836286548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2836286548
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.933740774
Short name	T791
Test name
Test status
Simulation time	7508294346 ps
CPU time	58.57 seconds
Started	Sep 18 06:06:22 AM UTC 24
Finished	Sep 18 06:07:22 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933740774 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.933740774
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3549003461
Short name	T785
Test name
Test status
Simulation time	27721293856 ps
CPU time	46.79 seconds
Started	Sep 18 06:06:22 AM UTC 24
Finished	Sep 18 06:07:10 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549003461 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3549003461
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2391761750
Short name	T761
Test name
Test status
Simulation time	151188908 ps
CPU time	3.21 seconds
Started	Sep 18 06:06:19 AM UTC 24
Finished	Sep 18 06:06:23 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391761750 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2391761750
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1147549362
Short name	T776
Test name
Test status
Simulation time	154352369 ps
CPU time	10.15 seconds
Started	Sep 18 06:06:39 AM UTC 24
Finished	Sep 18 06:06:50 AM UTC 24
Peak memory	215712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147549362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1147549362
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2719653417
Short name	T871
Test name
Test status
Simulation time	11882336748 ps
CPU time	199.5 seconds
Started	Sep 18 06:06:42 AM UTC 24
Finished	Sep 18 06:10:05 AM UTC 24
Peak memory	222056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719653417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2719653417
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2382699814
Short name	T888
Test name
Test status
Simulation time	5396063957 ps
CPU time	307.64 seconds
Started	Sep 18 06:06:39 AM UTC 24
Finished	Sep 18 06:11:51 AM UTC 24
Peak memory	220012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382699814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.2382699814
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3536843186
Short name	T881
Test name
Test status
Simulation time	18230953567 ps
CPU time	265.94 seconds
Started	Sep 18 06:06:42 AM UTC 24
Finished	Sep 18 06:11:12 AM UTC 24
Peak memory	232656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536843186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.3536843186
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.177519220
Short name	T779
Test name
Test status
Simulation time	70390132 ps
CPU time	15.19 seconds
Started	Sep 18 06:06:36 AM UTC 24
Finished	Sep 18 06:06:53 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177519220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.177519220
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.3055217418
Short name	T784
Test name
Test status
Simulation time	390813799 ps
CPU time	13.97 seconds
Started	Sep 18 06:06:54 AM UTC 24
Finished	Sep 18 06:07:09 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055217418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3055217418
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.452120805
Short name	T812
Test name
Test status
Simulation time	9546993682 ps
CPU time	67.87 seconds
Started	Sep 18 06:06:56 AM UTC 24
Finished	Sep 18 06:08:06 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452120805 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.452120805
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1864990873
Short name	T787
Test name
Test status
Simulation time	174787895 ps
CPU time	4.47 seconds
Started	Sep 18 06:07:10 AM UTC 24
Finished	Sep 18 06:07:16 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864990873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1864990873
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.2852139674
Short name	T794
Test name
Test status
Simulation time	863751707 ps
CPU time	19.25 seconds
Started	Sep 18 06:07:05 AM UTC 24
Finished	Sep 18 06:07:25 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852139674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2852139674
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.3562770326
Short name	T781
Test name
Test status
Simulation time	214893787 ps
CPU time	5.89 seconds
Started	Sep 18 06:06:50 AM UTC 24
Finished	Sep 18 06:06:57 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562770326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3562770326
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.1442917291
Short name	T868
Test name
Test status
Simulation time	74943122072 ps
CPU time	184.49 seconds
Started	Sep 18 06:06:52 AM UTC 24
Finished	Sep 18 06:09:59 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442917291 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1442917291
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2316770891
Short name	T875
Test name
Test status
Simulation time	25641285086 ps
CPU time	202.29 seconds
Started	Sep 18 06:06:54 AM UTC 24
Finished	Sep 18 06:10:19 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316770891 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2316770891
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2584750498
Short name	T783
Test name
Test status
Simulation time	456533716 ps
CPU time	10.34 seconds
Started	Sep 18 06:06:52 AM UTC 24
Finished	Sep 18 06:07:04 AM UTC 24
Peak memory	215720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584750498 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2584750498
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.3538856490
Short name	T788
Test name
Test status
Simulation time	447513775 ps
CPU time	18.58 seconds
Started	Sep 18 06:06:58 AM UTC 24
Finished	Sep 18 06:07:17 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538856490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3538856490
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.430842078
Short name	T774
Test name
Test status
Simulation time	26346115 ps
CPU time	2.63 seconds
Started	Sep 18 06:06:44 AM UTC 24
Finished	Sep 18 06:06:47 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430842078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.430842078
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.60669993
Short name	T797
Test name
Test status
Simulation time	5196815537 ps
CPU time	44.33 seconds
Started	Sep 18 06:06:44 AM UTC 24
Finished	Sep 18 06:07:30 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60669993 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.60669993
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.683891394
Short name	T75
Test name
Test status
Simulation time	3077543845 ps
CPU time	40.83 seconds
Started	Sep 18 06:06:48 AM UTC 24
Finished	Sep 18 06:07:31 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683891394 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.683891394
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1196823796
Short name	T775
Test name
Test status
Simulation time	37027447 ps
CPU time	3.73 seconds
Started	Sep 18 06:06:44 AM UTC 24
Finished	Sep 18 06:06:49 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196823796 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1196823796
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1859713919
Short name	T800
Test name
Test status
Simulation time	143544731 ps
CPU time	24.39 seconds
Started	Sep 18 06:07:12 AM UTC 24
Finished	Sep 18 06:07:37 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859713919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1859713919
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1247967653
Short name	T829
Test name
Test status
Simulation time	530066322 ps
CPU time	80.75 seconds
Started	Sep 18 06:07:16 AM UTC 24
Finished	Sep 18 06:08:38 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247967653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1247967653
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.490593177
Short name	T858
Test name
Test status
Simulation time	4519874645 ps
CPU time	122.31 seconds
Started	Sep 18 06:07:14 AM UTC 24
Finished	Sep 18 06:09:19 AM UTC 24
Peak memory	220204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490593177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.490593177
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1273567685
Short name	T29
Test name
Test status
Simulation time	10767720330 ps
CPU time	258.45 seconds
Started	Sep 18 06:07:17 AM UTC 24
Finished	Sep 18 06:11:39 AM UTC 24
Peak memory	222416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273567685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.1273567685
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2561146871
Short name	T798
Test name
Test status
Simulation time	891736896 ps
CPU time	26.29 seconds
Started	Sep 18 06:07:05 AM UTC 24
Finished	Sep 18 06:07:33 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561146871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2561146871
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.871967085
Short name	T236
Test name
Test status
Simulation time	164948671 ps
CPU time	13.02 seconds
Started	Sep 18 06:07:28 AM UTC 24
Finished	Sep 18 06:07:42 AM UTC 24
Peak memory	215716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871967085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.871967085
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.745728597
Short name	T149
Test name
Test status
Simulation time	114459306311 ps
CPU time	273.44 seconds
Started	Sep 18 06:07:32 AM UTC 24
Finished	Sep 18 06:12:09 AM UTC 24
Peak memory	217900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745728597 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.745728597
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.984361861
Short name	T807
Test name
Test status
Simulation time	104275081 ps
CPU time	11.79 seconds
Started	Sep 18 06:07:39 AM UTC 24
Finished	Sep 18 06:07:52 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984361861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.984361861
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1970351431
Short name	T810
Test name
Test status
Simulation time	1074650474 ps
CPU time	23.95 seconds
Started	Sep 18 06:07:32 AM UTC 24
Finished	Sep 18 06:07:57 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970351431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1970351431
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.3270527953
Short name	T804
Test name
Test status
Simulation time	419591982 ps
CPU time	19.94 seconds
Started	Sep 18 06:07:25 AM UTC 24
Finished	Sep 18 06:07:46 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270527953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3270527953
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.487118516
Short name	T814
Test name
Test status
Simulation time	10890697563 ps
CPU time	40.5 seconds
Started	Sep 18 06:07:27 AM UTC 24
Finished	Sep 18 06:08:09 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487118516 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.487118516
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3823739757
Short name	T882
Test name
Test status
Simulation time	24682010715 ps
CPU time	222.91 seconds
Started	Sep 18 06:07:27 AM UTC 24
Finished	Sep 18 06:11:13 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823739757 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3823739757
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.503013356
Short name	T805
Test name
Test status
Simulation time	179379446 ps
CPU time	18.61 seconds
Started	Sep 18 06:07:27 AM UTC 24
Finished	Sep 18 06:07:47 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503013356 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.503013356
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.494221969
Short name	T806
Test name
Test status
Simulation time	212795825 ps
CPU time	16.68 seconds
Started	Sep 18 06:07:32 AM UTC 24
Finished	Sep 18 06:07:50 AM UTC 24
Peak memory	216032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494221969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.494221969
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.4181322785
Short name	T795
Test name
Test status
Simulation time	740875577 ps
CPU time	6.02 seconds
Started	Sep 18 06:07:18 AM UTC 24
Finished	Sep 18 06:07:26 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181322785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4181322785
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2607266364
Short name	T826
Test name
Test status
Simulation time	21379152686 ps
CPU time	67.75 seconds
Started	Sep 18 06:07:20 AM UTC 24
Finished	Sep 18 06:08:30 AM UTC 24
Peak memory	216088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607266364 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2607266364
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2973745134
Short name	T813
Test name
Test status
Simulation time	6704454607 ps
CPU time	41.89 seconds
Started	Sep 18 06:07:24 AM UTC 24
Finished	Sep 18 06:08:07 AM UTC 24
Peak memory	216020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973745134 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2973745134
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1824471505
Short name	T792
Test name
Test status
Simulation time	79350692 ps
CPU time	3.03 seconds
Started	Sep 18 06:07:20 AM UTC 24
Finished	Sep 18 06:07:24 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824471505 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1824471505
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.1285131602
Short name	T827
Test name
Test status
Simulation time	491901300 ps
CPU time	51.54 seconds
Started	Sep 18 06:07:39 AM UTC 24
Finished	Sep 18 06:08:32 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285131602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1285131602
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.723315208
Short name	T872
Test name
Test status
Simulation time	1931591849 ps
CPU time	139.51 seconds
Started	Sep 18 06:07:43 AM UTC 24
Finished	Sep 18 06:10:06 AM UTC 24
Peak memory	217764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723315208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.723315208
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1767914598
Short name	T879
Test name
Test status
Simulation time	408124310 ps
CPU time	184.59 seconds
Started	Sep 18 06:07:39 AM UTC 24
Finished	Sep 18 06:10:47 AM UTC 24
Peak memory	222120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767914598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.1767914598
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3200743658
Short name	T899
Test name
Test status
Simulation time	3771470992 ps
CPU time	357.34 seconds
Started	Sep 18 06:07:48 AM UTC 24
Finished	Sep 18 06:13:49 AM UTC 24
Peak memory	239096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200743658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.3200743658
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.2006159624
Short name	T809
Test name
Test status
Simulation time	179708395 ps
CPU time	18.94 seconds
Started	Sep 18 06:07:34 AM UTC 24
Finished	Sep 18 06:07:54 AM UTC 24
Peak memory	217824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006159624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2006159624
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.1481060861
Short name	T820
Test name
Test status
Simulation time	238754808 ps
CPU time	19.5 seconds
Started	Sep 18 06:07:56 AM UTC 24
Finished	Sep 18 06:08:16 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481060861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1481060861
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1547644876
Short name	T828
Test name
Test status
Simulation time	6465719408 ps
CPU time	37.27 seconds
Started	Sep 18 06:07:58 AM UTC 24
Finished	Sep 18 06:08:37 AM UTC 24
Peak memory	215876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547644876 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.1547644876
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3049151430
Short name	T817
Test name
Test status
Simulation time	19624450 ps
CPU time	3.59 seconds
Started	Sep 18 06:08:08 AM UTC 24
Finished	Sep 18 06:08:13 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049151430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3049151430
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.578048639
Short name	T819
Test name
Test status
Simulation time	64926872 ps
CPU time	8.22 seconds
Started	Sep 18 06:08:07 AM UTC 24
Finished	Sep 18 06:08:16 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578048639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.578048639
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.1410855508
Short name	T76
Test name
Test status
Simulation time	527528297 ps
CPU time	22.76 seconds
Started	Sep 18 06:07:51 AM UTC 24
Finished	Sep 18 06:08:15 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410855508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1410855508
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3810087142
Short name	T891
Test name
Test status
Simulation time	47276758898 ps
CPU time	250.69 seconds
Started	Sep 18 06:07:53 AM UTC 24
Finished	Sep 18 06:12:07 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810087142 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3810087142
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1252181998
Short name	T883
Test name
Test status
Simulation time	50152648724 ps
CPU time	205.25 seconds
Started	Sep 18 06:07:56 AM UTC 24
Finished	Sep 18 06:11:24 AM UTC 24
Peak memory	216108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252181998 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1252181998
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2321004233
Short name	T818
Test name
Test status
Simulation time	221376749 ps
CPU time	21.35 seconds
Started	Sep 18 06:07:53 AM UTC 24
Finished	Sep 18 06:08:16 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321004233 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2321004233
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.4247566425
Short name	T293
Test name
Test status
Simulation time	754105484 ps
CPU time	5.98 seconds
Started	Sep 18 06:07:48 AM UTC 24
Finished	Sep 18 06:07:54 AM UTC 24
Peak memory	215956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247566425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4247566425
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2336722220
Short name	T838
Test name
Test status
Simulation time	5504338652 ps
CPU time	61.86 seconds
Started	Sep 18 06:07:48 AM UTC 24
Finished	Sep 18 06:08:51 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336722220 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2336722220
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2815021195
Short name	T824
Test name
Test status
Simulation time	10561001892 ps
CPU time	33.42 seconds
Started	Sep 18 06:07:49 AM UTC 24
Finished	Sep 18 06:08:24 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815021195 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2815021195
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.4153051721
Short name	T808
Test name
Test status
Simulation time	31784095 ps
CPU time	3.31 seconds
Started	Sep 18 06:07:48 AM UTC 24
Finished	Sep 18 06:07:52 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153051721 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.4153051721
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2948768290
Short name	T870
Test name
Test status
Simulation time	4535081946 ps
CPU time	111.44 seconds
Started	Sep 18 06:08:10 AM UTC 24
Finished	Sep 18 06:10:03 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948768290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2948768290
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3929475127
Short name	T834
Test name
Test status
Simulation time	1243318928 ps
CPU time	32.81 seconds
Started	Sep 18 06:08:14 AM UTC 24
Finished	Sep 18 06:08:48 AM UTC 24
Peak memory	216036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929475127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3929475127
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3059700282
Short name	T850
Test name
Test status
Simulation time	214011371 ps
CPU time	52.09 seconds
Started	Sep 18 06:08:11 AM UTC 24
Finished	Sep 18 06:09:05 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059700282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.3059700282
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3375149601
Short name	T898
Test name
Test status
Simulation time	10158794610 ps
CPU time	328.51 seconds
Started	Sep 18 06:08:14 AM UTC 24
Finished	Sep 18 06:13:47 AM UTC 24
Peak memory	232652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375149601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.3375149601
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.8948010
Short name	T821
Test name
Test status
Simulation time	668522151 ps
CPU time	9.33 seconds
Started	Sep 18 06:08:08 AM UTC 24
Finished	Sep 18 06:08:19 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8948010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.8948010
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.2934620027
Short name	T844
Test name
Test status
Simulation time	537275944 ps
CPU time	31.56 seconds
Started	Sep 18 06:08:26 AM UTC 24
Finished	Sep 18 06:08:59 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934620027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2934620027
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3186816633
Short name	T889
Test name
Test status
Simulation time	112591544910 ps
CPU time	212.71 seconds
Started	Sep 18 06:08:26 AM UTC 24
Finished	Sep 18 06:12:02 AM UTC 24
Peak memory	218156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186816633 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.3186816633
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.113432913
Short name	T842
Test name
Test status
Simulation time	136035670 ps
CPU time	23.05 seconds
Started	Sep 18 06:08:33 AM UTC 24
Finished	Sep 18 06:08:58 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113432913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.113432913
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3444157412
Short name	T830
Test name
Test status
Simulation time	92935034 ps
CPU time	5.52 seconds
Started	Sep 18 06:08:32 AM UTC 24
Finished	Sep 18 06:08:39 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444157412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3444157412
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2650015685
Short name	T840
Test name
Test status
Simulation time	847572111 ps
CPU time	33.94 seconds
Started	Sep 18 06:08:20 AM UTC 24
Finished	Sep 18 06:08:56 AM UTC 24
Peak memory	215640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650015685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2650015685
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.3882449710
Short name	T884
Test name
Test status
Simulation time	46842140181 ps
CPU time	190.27 seconds
Started	Sep 18 06:08:23 AM UTC 24
Finished	Sep 18 06:11:36 AM UTC 24
Peak memory	218212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882449710 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3882449710
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3416675290
Short name	T877
Test name
Test status
Simulation time	15257296285 ps
CPU time	133.91 seconds
Started	Sep 18 06:08:24 AM UTC 24
Finished	Sep 18 06:10:41 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416675290 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3416675290
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.730737483
Short name	T833
Test name
Test status
Simulation time	283930129 ps
CPU time	25.18 seconds
Started	Sep 18 06:08:20 AM UTC 24
Finished	Sep 18 06:08:47 AM UTC 24
Peak memory	217820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730737483 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.730737483
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.2509766855
Short name	T845
Test name
Test status
Simulation time	5822961559 ps
CPU time	26.46 seconds
Started	Sep 18 06:08:32 AM UTC 24
Finished	Sep 18 06:09:00 AM UTC 24
Peak memory	215864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509766855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2509766855
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.3876567563
Short name	T825
Test name
Test status
Simulation time	137873133 ps
CPU time	5.13 seconds
Started	Sep 18 06:08:18 AM UTC 24
Finished	Sep 18 06:08:24 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876567563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3876567563
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2357450561
Short name	T837
Test name
Test status
Simulation time	7682847875 ps
CPU time	30.64 seconds
Started	Sep 18 06:08:18 AM UTC 24
Finished	Sep 18 06:08:50 AM UTC 24
Peak memory	215960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357450561 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2357450561
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3874067371
Short name	T846
Test name
Test status
Simulation time	3697924158 ps
CPU time	40.53 seconds
Started	Sep 18 06:08:18 AM UTC 24
Finished	Sep 18 06:09:00 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874067371 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3874067371
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3449728047
Short name	T823
Test name
Test status
Simulation time	52451504 ps
CPU time	3.14 seconds
Started	Sep 18 06:08:18 AM UTC 24
Finished	Sep 18 06:08:22 AM UTC 24
Peak memory	215948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449728047 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3449728047
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.4189668175
Short name	T152
Test name
Test status
Simulation time	7834759431 ps
CPU time	120.28 seconds
Started	Sep 18 06:08:38 AM UTC 24
Finished	Sep 18 06:10:41 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189668175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.4189668175
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.4257497281
Short name	T863
Test name
Test status
Simulation time	3735624734 ps
CPU time	55.68 seconds
Started	Sep 18 06:08:40 AM UTC 24
Finished	Sep 18 06:09:37 AM UTC 24
Peak memory	217500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257497281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.4257497281
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2273082799
Short name	T878
Test name
Test status
Simulation time	864100771 ps
CPU time	120.18 seconds
Started	Sep 18 06:08:40 AM UTC 24
Finished	Sep 18 06:10:43 AM UTC 24
Peak memory	219332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273082799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.2273082799
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3960519843
Short name	T841
Test name
Test status
Simulation time	44233092 ps
CPU time	12.83 seconds
Started	Sep 18 06:08:42 AM UTC 24
Finished	Sep 18 06:08:56 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960519843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.3960519843
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.2592750243
Short name	T854
Test name
Test status
Simulation time	887568052 ps
CPU time	36.77 seconds
Started	Sep 18 06:08:32 AM UTC 24
Finished	Sep 18 06:09:10 AM UTC 24
Peak memory	215672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592750243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2592750243
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.3890940944
Short name	T848
Test name
Test status
Simulation time	37382941 ps
CPU time	3.77 seconds
Started	Sep 18 06:08:58 AM UTC 24
Finished	Sep 18 06:09:03 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890940944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3890940944
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3565401062
Short name	T895
Test name
Test status
Simulation time	74582562037 ps
CPU time	232.52 seconds
Started	Sep 18 06:08:58 AM UTC 24
Finished	Sep 18 06:12:54 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565401062 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.3565401062
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.4251269562
Short name	T862
Test name
Test status
Simulation time	3409444966 ps
CPU time	34.36 seconds
Started	Sep 18 06:09:00 AM UTC 24
Finished	Sep 18 06:09:36 AM UTC 24
Peak memory	216040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251269562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.4251269562
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.3305858638
Short name	T852
Test name
Test status
Simulation time	71069009 ps
CPU time	7.64 seconds
Started	Sep 18 06:09:00 AM UTC 24
Finished	Sep 18 06:09:09 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305858638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3305858638
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2701876976
Short name	T859
Test name
Test status
Simulation time	3665516022 ps
CPU time	25 seconds
Started	Sep 18 06:08:53 AM UTC 24
Finished	Sep 18 06:09:19 AM UTC 24
Peak memory	215836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701876976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2701876976
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.828190072
Short name	T869
Test name
Test status
Simulation time	11551772978 ps
CPU time	68.64 seconds
Started	Sep 18 06:08:53 AM UTC 24
Finished	Sep 18 06:10:03 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828190072 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.828190072
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3696903916
Short name	T893
Test name
Test status
Simulation time	75778529625 ps
CPU time	225.33 seconds
Started	Sep 18 06:08:53 AM UTC 24
Finished	Sep 18 06:12:41 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696903916 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3696903916
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.4099732327
Short name	T847
Test name
Test status
Simulation time	34297299 ps
CPU time	7.65 seconds
Started	Sep 18 06:08:53 AM UTC 24
Finished	Sep 18 06:09:01 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099732327 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.4099732327
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.2386415197
Short name	T855
Test name
Test status
Simulation time	682088335 ps
CPU time	10.09 seconds
Started	Sep 18 06:09:00 AM UTC 24
Finished	Sep 18 06:09:11 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386415197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2386415197
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.907707027
Short name	T835
Test name
Test status
Simulation time	648169124 ps
CPU time	5.08 seconds
Started	Sep 18 06:08:42 AM UTC 24
Finished	Sep 18 06:08:48 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907707027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.907707027
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.4184145149
Short name	T865
Test name
Test status
Simulation time	8482209761 ps
CPU time	51.04 seconds
Started	Sep 18 06:08:50 AM UTC 24
Finished	Sep 18 06:09:43 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184145149 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.4184145149
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.404150292
Short name	T857
Test name
Test status
Simulation time	2968721337 ps
CPU time	26.03 seconds
Started	Sep 18 06:08:50 AM UTC 24
Finished	Sep 18 06:09:18 AM UTC 24
Peak memory	215820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404150292 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.404150292
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1248414306
Short name	T839
Test name
Test status
Simulation time	24655391 ps
CPU time	2.88 seconds
Started	Sep 18 06:08:48 AM UTC 24
Finished	Sep 18 06:08:52 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248414306 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1248414306
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3419925479
Short name	T886
Test name
Test status
Simulation time	19209549623 ps
CPU time	157.83 seconds
Started	Sep 18 06:09:02 AM UTC 24
Finished	Sep 18 06:11:43 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419925479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3419925479
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3888155705
Short name	T874
Test name
Test status
Simulation time	2659856841 ps
CPU time	70.88 seconds
Started	Sep 18 06:09:02 AM UTC 24
Finished	Sep 18 06:10:15 AM UTC 24
Peak memory	216104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888155705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3888155705
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2911949620
Short name	T876
Test name
Test status
Simulation time	375809010 ps
CPU time	79.24 seconds
Started	Sep 18 06:09:02 AM UTC 24
Finished	Sep 18 06:10:23 AM UTC 24
Peak memory	219888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911949620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.2911949620
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.4189217854
Short name	T866
Test name
Test status
Simulation time	172701779 ps
CPU time	38.88 seconds
Started	Sep 18 06:09:04 AM UTC 24
Finished	Sep 18 06:09:44 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189217854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.4189217854
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.197145242
Short name	T853
Test name
Test status
Simulation time	310804156 ps
CPU time	8.72 seconds
Started	Sep 18 06:09:00 AM UTC 24
Finished	Sep 18 06:09:10 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197145242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.197145242
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.531186495
Short name	T659
Test name
Test status
Simulation time	93495789169 ps
CPU time	876.2 seconds
Started	Sep 18 05:48:47 AM UTC 24
Finished	Sep 18 06:03:34 AM UTC 24
Peak memory	219492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531186495 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.531186495
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1535070296
Short name	T225
Test name
Test status
Simulation time	565380725 ps
CPU time	20.1 seconds
Started	Sep 18 05:48:54 AM UTC 24
Finished	Sep 18 05:49:16 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535070296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1535070296
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.1507320119
Short name	T105
Test name
Test status
Simulation time	956518717 ps
CPU time	11.01 seconds
Started	Sep 18 05:48:53 AM UTC 24
Finished	Sep 18 05:49:05 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507320119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1507320119
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.2784502818
Short name	T106
Test name
Test status
Simulation time	247925666 ps
CPU time	22.35 seconds
Started	Sep 18 05:48:45 AM UTC 24
Finished	Sep 18 05:49:09 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784502818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2784502818
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.1943751889
Short name	T173
Test name
Test status
Simulation time	67634112789 ps
CPU time	246.49 seconds
Started	Sep 18 05:48:46 AM UTC 24
Finished	Sep 18 05:52:56 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943751889 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1943751889
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.421207769
Short name	T364
Test name
Test status
Simulation time	61106417474 ps
CPU time	233.45 seconds
Started	Sep 18 05:48:46 AM UTC 24
Finished	Sep 18 05:52:43 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421207769 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.421207769
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.4122124083
Short name	T101
Test name
Test status
Simulation time	109365699 ps
CPU time	11.22 seconds
Started	Sep 18 05:48:46 AM UTC 24
Finished	Sep 18 05:48:58 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122124083 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.4122124083
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.2169112716
Short name	T104
Test name
Test status
Simulation time	504069799 ps
CPU time	11.13 seconds
Started	Sep 18 05:48:51 AM UTC 24
Finished	Sep 18 05:49:04 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169112716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2169112716
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.875044392
Short name	T163
Test name
Test status
Simulation time	30006753 ps
CPU time	3.22 seconds
Started	Sep 18 05:48:41 AM UTC 24
Finished	Sep 18 05:48:45 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875044392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.875044392
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.4230825104
Short name	T228
Test name
Test status
Simulation time	8426551857 ps
CPU time	42.21 seconds
Started	Sep 18 05:48:42 AM UTC 24
Finished	Sep 18 05:49:26 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230825104 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4230825104
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2088325079
Short name	T5
Test name
Test status
Simulation time	3172336944 ps
CPU time	39.6 seconds
Started	Sep 18 05:48:42 AM UTC 24
Finished	Sep 18 05:49:23 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088325079 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2088325079
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2306923888
Short name	T164
Test name
Test status
Simulation time	75015185 ps
CPU time	3.46 seconds
Started	Sep 18 05:48:41 AM UTC 24
Finished	Sep 18 05:48:45 AM UTC 24
Peak memory	215748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306923888 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2306923888
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.2459748191
Short name	T90
Test name
Test status
Simulation time	1186412345 ps
CPU time	39.51 seconds
Started	Sep 18 05:48:59 AM UTC 24
Finished	Sep 18 05:49:40 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459748191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2459748191
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3048342852
Short name	T4
Test name
Test status
Simulation time	85851516 ps
CPU time	14.39 seconds
Started	Sep 18 05:49:02 AM UTC 24
Finished	Sep 18 05:49:17 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048342852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3048342852
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.977406422
Short name	T446
Test name
Test status
Simulation time	1921454536 ps
CPU time	450.71 seconds
Started	Sep 18 05:49:01 AM UTC 24
Finished	Sep 18 05:56:37 AM UTC 24
Peak memory	222428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977406422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.977406422
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.4056385744
Short name	T31
Test name
Test status
Simulation time	4665701046 ps
CPU time	190.02 seconds
Started	Sep 18 05:49:05 AM UTC 24
Finished	Sep 18 05:52:18 AM UTC 24
Peak memory	222416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056385744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.4056385744
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.1821212191
Short name	T226
Test name
Test status
Simulation time	1051470382 ps
CPU time	21.43 seconds
Started	Sep 18 05:48:53 AM UTC 24
Finished	Sep 18 05:49:16 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821212191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1821212191
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.2904077994
Short name	T331
Test name
Test status
Simulation time	310904455 ps
CPU time	18.67 seconds
Started	Sep 18 05:49:22 AM UTC 24
Finished	Sep 18 05:49:42 AM UTC 24
Peak memory	216040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904077994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2904077994
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2476289722
Short name	T334
Test name
Test status
Simulation time	277300900 ps
CPU time	11.95 seconds
Started	Sep 18 05:49:31 AM UTC 24
Finished	Sep 18 05:49:44 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476289722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2476289722
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.1014926504
Short name	T332
Test name
Test status
Simulation time	613765512 ps
CPU time	15.01 seconds
Started	Sep 18 05:49:27 AM UTC 24
Finished	Sep 18 05:49:43 AM UTC 24
Peak memory	215620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014926504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1014926504
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.2668471772
Short name	T8
Test name
Test status
Simulation time	1571249575 ps
CPU time	26.35 seconds
Started	Sep 18 05:49:14 AM UTC 24
Finished	Sep 18 05:49:42 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668471772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2668471772
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.3680742004
Short name	T287
Test name
Test status
Simulation time	10614552066 ps
CPU time	84.26 seconds
Started	Sep 18 05:49:17 AM UTC 24
Finished	Sep 18 05:50:44 AM UTC 24
Peak memory	216100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680742004 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3680742004
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2218783336
Short name	T296
Test name
Test status
Simulation time	28644235319 ps
CPU time	280.66 seconds
Started	Sep 18 05:49:18 AM UTC 24
Finished	Sep 18 05:54:04 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218783336 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2218783336
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.2024920437
Short name	T337
Test name
Test status
Simulation time	909849606 ps
CPU time	32.63 seconds
Started	Sep 18 05:49:16 AM UTC 24
Finished	Sep 18 05:49:51 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024920437 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2024920437
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.3774854841
Short name	T170
Test name
Test status
Simulation time	4379703011 ps
CPU time	37.81 seconds
Started	Sep 18 05:49:27 AM UTC 24
Finished	Sep 18 05:50:06 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774854841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3774854841
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2741586720
Short name	T107
Test name
Test status
Simulation time	120088438 ps
CPU time	3.28 seconds
Started	Sep 18 05:49:06 AM UTC 24
Finished	Sep 18 05:49:10 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741586720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2741586720
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2025224236
Short name	T338
Test name
Test status
Simulation time	6437429835 ps
CPU time	41.47 seconds
Started	Sep 18 05:49:11 AM UTC 24
Finished	Sep 18 05:49:54 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025224236 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2025224236
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.4181975384
Short name	T60
Test name
Test status
Simulation time	4111380863 ps
CPU time	53.3 seconds
Started	Sep 18 05:49:14 AM UTC 24
Finished	Sep 18 05:50:09 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181975384 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.4181975384
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1723231367
Short name	T108
Test name
Test status
Simulation time	44858101 ps
CPU time	3.04 seconds
Started	Sep 18 05:49:09 AM UTC 24
Finished	Sep 18 05:49:13 AM UTC 24
Peak memory	215684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723231367 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1723231367
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.874440607
Short name	T93
Test name
Test status
Simulation time	4953305405 ps
CPU time	121.02 seconds
Started	Sep 18 05:49:32 AM UTC 24
Finished	Sep 18 05:51:35 AM UTC 24
Peak memory	219996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874440607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.874440607
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.975719665
Short name	T38
Test name
Test status
Simulation time	8476070350 ps
CPU time	251.79 seconds
Started	Sep 18 05:49:41 AM UTC 24
Finished	Sep 18 05:53:57 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975719665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.975719665
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3027781089
Short name	T175
Test name
Test status
Simulation time	610975584 ps
CPU time	256.05 seconds
Started	Sep 18 05:49:39 AM UTC 24
Finished	Sep 18 05:53:59 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027781089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.3027781089
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1270015713
Short name	T321
Test name
Test status
Simulation time	5946607339 ps
CPU time	217.66 seconds
Started	Sep 18 05:49:44 AM UTC 24
Finished	Sep 18 05:53:25 AM UTC 24
Peak memory	232652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270015713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.1270015713
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.3489138313
Short name	T214
Test name
Test status
Simulation time	440096223 ps
CPU time	19.51 seconds
Started	Sep 18 05:49:27 AM UTC 24
Finished	Sep 18 05:49:48 AM UTC 24
Peak memory	217764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489138313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3489138313
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.3754694916
Short name	T221
Test name
Test status
Simulation time	446515495 ps
CPU time	36.03 seconds
Started	Sep 18 05:49:50 AM UTC 24
Finished	Sep 18 05:50:27 AM UTC 24
Peak memory	217764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754694916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3754694916
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3069578702
Short name	T96
Test name
Test status
Simulation time	39599857282 ps
CPU time	176.1 seconds
Started	Sep 18 05:49:50 AM UTC 24
Finished	Sep 18 05:52:49 AM UTC 24
Peak memory	217968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069578702 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.3069578702
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1403865067
Short name	T342
Test name
Test status
Simulation time	526684409 ps
CPU time	22.76 seconds
Started	Sep 18 05:49:55 AM UTC 24
Finished	Sep 18 05:50:19 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403865067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1403865067
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.3829923993
Short name	T343
Test name
Test status
Simulation time	1382588486 ps
CPU time	30.15 seconds
Started	Sep 18 05:49:50 AM UTC 24
Finished	Sep 18 05:50:22 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829923993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3829923993
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.4246576677
Short name	T336
Test name
Test status
Simulation time	17107732 ps
CPU time	2.75 seconds
Started	Sep 18 05:49:45 AM UTC 24
Finished	Sep 18 05:49:49 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246576677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.4246576677
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.4173304148
Short name	T65
Test name
Test status
Simulation time	13957410749 ps
CPU time	155.43 seconds
Started	Sep 18 05:49:48 AM UTC 24
Finished	Sep 18 05:52:26 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173304148 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.4173304148
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4022179476
Short name	T355
Test name
Test status
Simulation time	25118359797 ps
CPU time	151.21 seconds
Started	Sep 18 05:49:48 AM UTC 24
Finished	Sep 18 05:52:22 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022179476 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4022179476
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.1789975797
Short name	T220
Test name
Test status
Simulation time	158021808 ps
CPU time	20.38 seconds
Started	Sep 18 05:49:48 AM UTC 24
Finished	Sep 18 05:50:09 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789975797 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1789975797
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.1876152370
Short name	T341
Test name
Test status
Simulation time	768874567 ps
CPU time	27.75 seconds
Started	Sep 18 05:49:50 AM UTC 24
Finished	Sep 18 05:50:19 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876152370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1876152370
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.3667172078
Short name	T330
Test name
Test status
Simulation time	32987765 ps
CPU time	3.29 seconds
Started	Sep 18 05:49:44 AM UTC 24
Finished	Sep 18 05:49:48 AM UTC 24
Peak memory	215692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667172078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3667172078
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3934464724
Short name	T344
Test name
Test status
Simulation time	4496443166 ps
CPU time	46.7 seconds
Started	Sep 18 05:49:44 AM UTC 24
Finished	Sep 18 05:50:32 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934464724 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3934464724
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.483643863
Short name	T171
Test name
Test status
Simulation time	4170750534 ps
CPU time	38.03 seconds
Started	Sep 18 05:49:45 AM UTC 24
Finished	Sep 18 05:50:24 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483643863 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.483643863
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3179557179
Short name	T335
Test name
Test status
Simulation time	31817091 ps
CPU time	3.05 seconds
Started	Sep 18 05:49:44 AM UTC 24
Finished	Sep 18 05:49:48 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179557179 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3179557179
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.4148653907
Short name	T206
Test name
Test status
Simulation time	3087756471 ps
CPU time	128.41 seconds
Started	Sep 18 05:49:59 AM UTC 24
Finished	Sep 18 05:52:10 AM UTC 24
Peak memory	220140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148653907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.4148653907
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.729544910
Short name	T192
Test name
Test status
Simulation time	3845393454 ps
CPU time	83.59 seconds
Started	Sep 18 05:50:07 AM UTC 24
Finished	Sep 18 05:51:32 AM UTC 24
Peak memory	218084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729544910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.729544910
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.172122217
Short name	T327
Test name
Test status
Simulation time	8316268 ps
CPU time	14.69 seconds
Started	Sep 18 05:50:02 AM UTC 24
Finished	Sep 18 05:50:18 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172122217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.172122217
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.116620763
Short name	T479
Test name
Test status
Simulation time	3939091021 ps
CPU time	476.97 seconds
Started	Sep 18 05:50:10 AM UTC 24
Finished	Sep 18 05:58:13 AM UTC 24
Peak memory	239100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116620763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.116620763
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.4123755756
Short name	T155
Test name
Test status
Simulation time	2273076369 ps
CPU time	30.7 seconds
Started	Sep 18 05:49:51 AM UTC 24
Finished	Sep 18 05:50:23 AM UTC 24
Peak memory	218152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123755756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.4123755756
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3483189539
Short name	T553
Test name
Test status
Simulation time	156042019359 ps
CPU time	619.63 seconds
Started	Sep 18 05:50:24 AM UTC 24
Finished	Sep 18 06:00:51 AM UTC 24
Peak memory	221540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483189539 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.3483189539
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.837660051
Short name	T345
Test name
Test status
Simulation time	841225809 ps
CPU time	29.67 seconds
Started	Sep 18 05:50:33 AM UTC 24
Finished	Sep 18 05:51:03 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837660051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.837660051
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.965485180
Short name	T283
Test name
Test status
Simulation time	111582503 ps
CPU time	6.22 seconds
Started	Sep 18 05:50:28 AM UTC 24
Finished	Sep 18 05:50:36 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965485180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.965485180
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.747847860
Short name	T63
Test name
Test status
Simulation time	1187162520 ps
CPU time	43.75 seconds
Started	Sep 18 05:50:19 AM UTC 24
Finished	Sep 18 05:51:04 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747847860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.747847860
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.1562600720
Short name	T113
Test name
Test status
Simulation time	64225664702 ps
CPU time	235.96 seconds
Started	Sep 18 05:50:20 AM UTC 24
Finished	Sep 18 05:54:19 AM UTC 24
Peak memory	218024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562600720 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1562600720
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.4232237875
Short name	T282
Test name
Test status
Simulation time	2510781355 ps
CPU time	12.22 seconds
Started	Sep 18 05:50:20 AM UTC 24
Finished	Sep 18 05:50:33 AM UTC 24
Peak memory	215836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232237875 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.4232237875
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.1653966536
Short name	T201
Test name
Test status
Simulation time	105365795 ps
CPU time	10.3 seconds
Started	Sep 18 05:50:20 AM UTC 24
Finished	Sep 18 05:50:31 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653966536 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1653966536
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.1482421012
Short name	T62
Test name
Test status
Simulation time	6456138051 ps
CPU time	24.88 seconds
Started	Sep 18 05:50:25 AM UTC 24
Finished	Sep 18 05:50:51 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482421012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1482421012
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.2959412843
Short name	T339
Test name
Test status
Simulation time	28833199 ps
CPU time	2.88 seconds
Started	Sep 18 05:50:11 AM UTC 24
Finished	Sep 18 05:50:15 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959412843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2959412843
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.541480472
Short name	T288
Test name
Test status
Simulation time	6900158022 ps
CPU time	43.07 seconds
Started	Sep 18 05:50:15 AM UTC 24
Finished	Sep 18 05:51:00 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541480472 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.541480472
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3992461615
Short name	T250
Test name
Test status
Simulation time	4724587211 ps
CPU time	48.59 seconds
Started	Sep 18 05:50:19 AM UTC 24
Finished	Sep 18 05:51:09 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992461615 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3992461615
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1524618479
Short name	T340
Test name
Test status
Simulation time	35442691 ps
CPU time	2.66 seconds
Started	Sep 18 05:50:15 AM UTC 24
Finished	Sep 18 05:50:19 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524618479 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1524618479
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.3440860356
Short name	T119
Test name
Test status
Simulation time	14075232425 ps
CPU time	299.37 seconds
Started	Sep 18 05:50:34 AM UTC 24
Finished	Sep 18 05:55:37 AM UTC 24
Peak memory	222404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440860356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3440860356
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.854077703
Short name	T25
Test name
Test status
Simulation time	3911828583 ps
CPU time	121 seconds
Started	Sep 18 05:50:34 AM UTC 24
Finished	Sep 18 05:52:37 AM UTC 24
Peak memory	220196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854077703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.854077703
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.4098984108
Short name	T350
Test name
Test status
Simulation time	551036696 ps
CPU time	91.54 seconds
Started	Sep 18 05:50:34 AM UTC 24
Finished	Sep 18 05:52:07 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098984108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.4098984108
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2023451077
Short name	T323
Test name
Test status
Simulation time	317507628 ps
CPU time	111.69 seconds
Started	Sep 18 05:50:34 AM UTC 24
Finished	Sep 18 05:52:28 AM UTC 24
Peak memory	221940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023451077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.2023451077
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.1681828492
Short name	T285
Test name
Test status
Simulation time	25334126 ps
CPU time	5.02 seconds
Started	Sep 18 05:50:32 AM UTC 24
Finished	Sep 18 05:50:38 AM UTC 24
Peak memory	216040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681828492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1681828492
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.2422187597
Short name	T254
Test name
Test status
Simulation time	321653100 ps
CPU time	13.35 seconds
Started	Sep 18 05:51:00 AM UTC 24
Finished	Sep 18 05:51:15 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422187597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2422187597
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3153554770
Short name	T280
Test name
Test status
Simulation time	47105515259 ps
CPU time	417.17 seconds
Started	Sep 18 05:51:04 AM UTC 24
Finished	Sep 18 05:58:07 AM UTC 24
Peak memory	217900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153554770 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.3153554770
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2996243089
Short name	T252
Test name
Test status
Simulation time	98488640 ps
CPU time	3.4 seconds
Started	Sep 18 05:51:07 AM UTC 24
Finished	Sep 18 05:51:12 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996243089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2996243089
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.2140302783
Short name	T253
Test name
Test status
Simulation time	170282589 ps
CPU time	6 seconds
Started	Sep 18 05:51:05 AM UTC 24
Finished	Sep 18 05:51:12 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140302783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2140302783
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.875302839
Short name	T156
Test name
Test status
Simulation time	480403141 ps
CPU time	25.68 seconds
Started	Sep 18 05:50:44 AM UTC 24
Finished	Sep 18 05:51:11 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875302839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.875302839
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.4134869788
Short name	T166
Test name
Test status
Simulation time	73103071156 ps
CPU time	216.75 seconds
Started	Sep 18 05:50:52 AM UTC 24
Finished	Sep 18 05:54:32 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134869788 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.4134869788
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2236495264
Short name	T356
Test name
Test status
Simulation time	8501177193 ps
CPU time	84.31 seconds
Started	Sep 18 05:50:57 AM UTC 24
Finished	Sep 18 05:52:23 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236495264 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2236495264
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.1733441092
Short name	T203
Test name
Test status
Simulation time	170454835 ps
CPU time	19.14 seconds
Started	Sep 18 05:50:44 AM UTC 24
Finished	Sep 18 05:51:05 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733441092 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1733441092
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.4294362000
Short name	T195
Test name
Test status
Simulation time	2324042481 ps
CPU time	38.9 seconds
Started	Sep 18 05:51:05 AM UTC 24
Finished	Sep 18 05:51:46 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294362000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.4294362000
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.2280620518
Short name	T222
Test name
Test status
Simulation time	168360677 ps
CPU time	5.59 seconds
Started	Sep 18 05:50:37 AM UTC 24
Finished	Sep 18 05:50:43 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280620518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2280620518
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.2467328494
Short name	T193
Test name
Test status
Simulation time	6054624392 ps
CPU time	56.8 seconds
Started	Sep 18 05:50:39 AM UTC 24
Finished	Sep 18 05:51:37 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467328494 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2467328494
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1150087429
Short name	T249
Test name
Test status
Simulation time	4075935288 ps
CPU time	24.37 seconds
Started	Sep 18 05:50:42 AM UTC 24
Finished	Sep 18 05:51:08 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150087429 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1150087429
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.87943949
Short name	T286
Test name
Test status
Simulation time	40668861 ps
CPU time	3.17 seconds
Started	Sep 18 05:50:37 AM UTC 24
Finished	Sep 18 05:50:41 AM UTC 24
Peak memory	215944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87943949 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.87943949
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.1040213984
Short name	T120
Test name
Test status
Simulation time	8077998876 ps
CPU time	291.86 seconds
Started	Sep 18 05:51:09 AM UTC 24
Finished	Sep 18 05:56:05 AM UTC 24
Peak memory	220008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040213984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1040213984
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3154471117
Short name	T243
Test name
Test status
Simulation time	637000844 ps
CPU time	54.73 seconds
Started	Sep 18 05:51:10 AM UTC 24
Finished	Sep 18 05:52:06 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154471117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3154471117
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1488201120
Short name	T196
Test name
Test status
Simulation time	104593549 ps
CPU time	35.61 seconds
Started	Sep 18 05:51:10 AM UTC 24
Finished	Sep 18 05:51:47 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488201120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.1488201120
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3409040977
Short name	T197
Test name
Test status
Simulation time	224965772 ps
CPU time	33.81 seconds
Started	Sep 18 05:51:12 AM UTC 24
Finished	Sep 18 05:51:47 AM UTC 24
Peak memory	220140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409040977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3409040977
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.2006437317
Short name	T251
Test name
Test status
Simulation time	63358633 ps
CPU time	4.04 seconds
Started	Sep 18 05:51:05 AM UTC 24
Finished	Sep 18 05:51:10 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006437317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2006437317
Directory	/workspaces/repo/scratch/os_regression_2024_09_17/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest