Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1795	1			T11	2		T14	1		T19	2
all_values[1]	1753	1			T11	3		T14	1		T19	1
all_values[2]	1865	1			T11	3		T19	2		T76	1
all_values[3]	1909	1			T11	3		T14	1		T19	1
all_values[4]	1844	1			T11	2		T14	1		T19	3
all_values[5]	1877	1			T11	2		T14	1		T19	2
all_values[6]	1806	1			T11	1		T14	2		T19	2
all_values[7]	1833	1			T11	4		T19	4		T48	3
all_values[8]	1853	1			T11	2		T48	3		T49	5
all_values[9]	1886	1			T11	2		T19	2		T48	4
all_values[10]	1797	1			T11	1		T19	2		T48	4
all_values[11]	1722	1			T11	2		T19	2		T48	5
all_values[12]	1772	1			T11	1		T19	4		T49	3
all_values[13]	1831	1			T11	2		T19	2		T49	2
all_values[14]	1852	1			T11	1		T14	1		T19	3
all_values[15]	1848	1			T11	3		T19	4		T48	1
all_values[16]	1844	1			T11	2		T19	4		T48	3
all_values[17]	1775	1			T11	3		T14	2		T19	4
all_values[18]	1783	1			T11	5		T14	1		T19	1
all_values[19]	1885	1			T11	4		T19	3		T48	4
all_values[20]	1829	1			T11	7		T19	3		T48	1
all_values[21]	1827	1			T11	2		T19	2		T76	1
all_values[22]	1813	1			T11	2		T19	2		T76	1
all_values[23]	1859	1			T11	2		T14	1		T19	1
all_values[24]	1764	1			T11	2		T19	6		T48	6
all_values[25]	1819	1			T11	5		T14	1		T19	4
all_values[26]	1836	1			T11	2		T19	1		T48	3
all_values[27]	1850	1			T11	1		T19	1		T76	1
all_values[28]	1778	1			T11	2		T14	1		T49	5
all_values[29]	1834	1			T11	4		T14	2		T19	1
all_values[30]	1839	1			T11	1		T19	4		T48	5
all_values[31]	1870	1			T11	5		T48	3		T49	2
all_values[32]	1883	1			T14	1		T48	1		T49	1
all_values[33]	1821	1			T11	1		T14	1		T19	3
all_values[34]	1819	1			T11	1		T14	1		T19	3
all_values[35]	1783	1			T11	4		T19	1		T48	2
all_values[36]	1805	1			T11	3		T19	2		T48	2
all_values[37]	1869	1			T11	5		T19	1		T48	4
all_values[38]	1903	1			T11	6		T19	1		T48	1
all_values[39]	1807	1			T11	3		T14	4		T76	1
all_values[40]	1749	1			T11	2		T19	3		T48	2
all_values[41]	1833	1			T11	1		T19	2		T48	2
all_values[42]	1813	1			T11	1		T14	1		T48	3
all_values[43]	1802	1			T11	2		T19	3		T76	1
all_values[44]	1873	1			T11	3		T19	1		T48	1
all_values[45]	1876	1			T14	1		T19	1		T76	1
all_values[46]	1870	1			T11	3		T14	1		T19	1
all_values[47]	1778	1			T11	2		T19	1		T48	5
all_values[48]	1801	1			T19	4		T76	1		T48	2
all_values[49]	1780	1			T11	2		T14	1		T76	1
all_values[50]	1863	1			T14	1		T48	2		T49	3
all_values[51]	1832	1			T11	1		T19	3		T48	2
all_values[52]	1851	1			T14	1		T19	5		T76	1
all_values[53]	1878	1			T11	2		T14	1		T49	7
all_values[54]	1826	1			T11	2		T19	2		T48	4
all_values[55]	1855	1			T19	4		T48	3		T49	4
all_values[56]	1870	1			T11	3		T19	4		T48	2
all_values[57]	1818	1			T11	2		T19	3		T48	2
all_values[58]	1874	1			T11	4		T14	1		T19	2
all_values[59]	1817	1			T11	3		T14	1		T19	1
all_values[60]	1794	1			T11	1		T19	2		T48	2
all_values[61]	1901	1			T11	3		T14	1		T19	3
all_values[62]	1811	1			T11	4		T14	2		T19	2
all_values[63]	1754	1			T11	2		T14	1		T49	7