Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.03	99.26	88.94	98.80		95.88	99.28	100.00

Total test records in report: 900

T767	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.2975303774	Sep 24 05:09:47 AM UTC 24	Sep 24 05:09:51 AM UTC 24	34918796 ps
T768	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.1875693647	Sep 24 05:09:25 AM UTC 24	Sep 24 05:09:52 AM UTC 24	266425350 ps
T769	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.991715114	Sep 24 05:09:48 AM UTC 24	Sep 24 05:09:52 AM UTC 24	64183062 ps
T770	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2818749036	Sep 24 05:08:39 AM UTC 24	Sep 24 05:09:53 AM UTC 24	6757521221 ps
T771	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1771853780	Sep 24 05:08:00 AM UTC 24	Sep 24 05:09:54 AM UTC 24	337286489 ps
T772	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.596447501	Sep 24 05:09:39 AM UTC 24	Sep 24 05:10:00 AM UTC 24	89554771 ps
T773	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.1758562101	Sep 24 05:09:53 AM UTC 24	Sep 24 05:10:08 AM UTC 24	178320823 ps
T141	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.4051674014	Sep 24 05:06:53 AM UTC 24	Sep 24 05:10:09 AM UTC 24	19632139447 ps
T774	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.868147088	Sep 24 05:09:28 AM UTC 24	Sep 24 05:10:11 AM UTC 24	2555410024 ps
T775	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2665493341	Sep 24 05:09:55 AM UTC 24	Sep 24 05:10:17 AM UTC 24	2195923786 ps
T776	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2133512574	Sep 24 05:07:01 AM UTC 24	Sep 24 05:10:20 AM UTC 24	8651689609 ps
T777	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.570280028	Sep 24 05:09:17 AM UTC 24	Sep 24 05:10:23 AM UTC 24	13194781321 ps
T778	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.4112479889	Sep 24 05:08:28 AM UTC 24	Sep 24 05:10:25 AM UTC 24	3979051881 ps
T779	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2040060008	Sep 24 05:05:56 AM UTC 24	Sep 24 05:10:26 AM UTC 24	3036439275 ps
T780	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.1825987651	Sep 24 05:05:43 AM UTC 24	Sep 24 05:10:26 AM UTC 24	44273411140 ps
T781	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1315107135	Sep 24 05:06:50 AM UTC 24	Sep 24 05:10:26 AM UTC 24	27096976062 ps
T782	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3004220362	Sep 24 05:09:53 AM UTC 24	Sep 24 05:10:27 AM UTC 24	6168800321 ps
T783	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.2100614441	Sep 24 05:09:24 AM UTC 24	Sep 24 05:10:27 AM UTC 24	2329843080 ps
T784	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.2872563189	Sep 24 05:10:11 AM UTC 24	Sep 24 05:10:28 AM UTC 24	669997663 ps
T785	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2642380385	Sep 24 05:10:18 AM UTC 24	Sep 24 05:10:29 AM UTC 24	387680682 ps
T786	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1507012832	Sep 24 05:09:36 AM UTC 24	Sep 24 05:10:33 AM UTC 24	12230195256 ps
T787	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.935893074	Sep 24 05:09:32 AM UTC 24	Sep 24 05:10:33 AM UTC 24	807849601 ps
T788	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1552215754	Sep 24 05:10:29 AM UTC 24	Sep 24 05:10:33 AM UTC 24	78963868 ps
T39	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3073083338	Sep 24 05:07:22 AM UTC 24	Sep 24 05:10:33 AM UTC 24	308271243 ps
T789	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3548201654	Sep 24 05:10:28 AM UTC 24	Sep 24 05:10:34 AM UTC 24	292814661 ps
T790	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2383471343	Sep 24 05:10:21 AM UTC 24	Sep 24 05:10:34 AM UTC 24	600146198 ps
T791	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3081821096	Sep 24 05:10:12 AM UTC 24	Sep 24 05:10:37 AM UTC 24	763665608 ps
T792	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2175239245	Sep 24 05:04:31 AM UTC 24	Sep 24 05:10:38 AM UTC 24	21836386101 ps
T793	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.2630501076	Sep 24 05:09:53 AM UTC 24	Sep 24 05:10:42 AM UTC 24	1324658304 ps
T794	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2972629492	Sep 24 05:09:53 AM UTC 24	Sep 24 05:10:43 AM UTC 24	11280475104 ps
T795	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.399306402	Sep 24 05:10:34 AM UTC 24	Sep 24 05:10:45 AM UTC 24	76484574 ps
T796	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1585415858	Sep 24 05:10:36 AM UTC 24	Sep 24 05:10:50 AM UTC 24	130358829 ps
T797	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3158966573	Sep 24 05:06:03 AM UTC 24	Sep 24 05:10:53 AM UTC 24	1613023991 ps
T798	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1937019355	Sep 24 05:07:11 AM UTC 24	Sep 24 05:10:53 AM UTC 24	86184514551 ps
T799	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1944224170	Sep 24 05:10:42 AM UTC 24	Sep 24 05:10:53 AM UTC 24	61221058 ps
T800	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2653617538	Sep 24 05:08:56 AM UTC 24	Sep 24 05:10:54 AM UTC 24	5600765089 ps
T801	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.4222269595	Sep 24 05:10:40 AM UTC 24	Sep 24 05:10:59 AM UTC 24	566018273 ps
T802	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.108783408	Sep 24 05:10:54 AM UTC 24	Sep 24 05:10:59 AM UTC 24	474000052 ps
T803	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.190675166	Sep 24 05:10:01 AM UTC 24	Sep 24 05:11:00 AM UTC 24	5343004035 ps
T804	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.1901477558	Sep 24 05:10:36 AM UTC 24	Sep 24 05:11:01 AM UTC 24	343813412 ps
T805	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1761007362	Sep 24 05:08:13 AM UTC 24	Sep 24 05:11:03 AM UTC 24	22680584106 ps
T806	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1119984832	Sep 24 05:10:38 AM UTC 24	Sep 24 05:11:04 AM UTC 24	296273908 ps
T807	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.1207050156	Sep 24 05:11:00 AM UTC 24	Sep 24 05:11:07 AM UTC 24	30321284 ps
T808	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2354188190	Sep 24 05:10:30 AM UTC 24	Sep 24 05:11:10 AM UTC 24	347194682 ps
T809	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1673802275	Sep 24 05:10:30 AM UTC 24	Sep 24 05:11:11 AM UTC 24	7291696948 ps
T810	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1273743954	Sep 24 05:06:40 AM UTC 24	Sep 24 05:11:13 AM UTC 24	6550940903 ps
T811	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.1581853458	Sep 24 05:07:21 AM UTC 24	Sep 24 05:11:15 AM UTC 24	20473474484 ps
T812	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3934710619	Sep 24 05:06:13 AM UTC 24	Sep 24 05:11:15 AM UTC 24	25858322967 ps
T247	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.780690221	Sep 24 05:11:00 AM UTC 24	Sep 24 05:11:17 AM UTC 24	522236136 ps
T813	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.693933964	Sep 24 05:08:43 AM UTC 24	Sep 24 05:11:19 AM UTC 24	21162569497 ps
T814	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1177957853	Sep 24 05:09:08 AM UTC 24	Sep 24 05:11:20 AM UTC 24	378982980 ps
T815	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.530794107	Sep 24 05:10:29 AM UTC 24	Sep 24 05:11:20 AM UTC 24	5514262766 ps
T816	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2736991358	Sep 24 05:11:22 AM UTC 24	Sep 24 05:11:25 AM UTC 24	35413750 ps
T817	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.380593533	Sep 24 05:07:11 AM UTC 24	Sep 24 05:11:26 AM UTC 24	64981315032 ps
T818	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.517959920	Sep 24 05:11:22 AM UTC 24	Sep 24 05:11:27 AM UTC 24	124945686 ps
T819	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2418509233	Sep 24 05:10:55 AM UTC 24	Sep 24 05:11:28 AM UTC 24	4121891391 ps
T820	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.701473887	Sep 24 05:08:48 AM UTC 24	Sep 24 05:11:28 AM UTC 24	36174056540 ps
T821	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.733232749	Sep 24 05:08:46 AM UTC 24	Sep 24 05:11:32 AM UTC 24	14288274863 ps
T822	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2759989712	Sep 24 05:11:00 AM UTC 24	Sep 24 05:11:32 AM UTC 24	3891448750 ps
T823	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.3128742518	Sep 24 05:11:11 AM UTC 24	Sep 24 05:11:32 AM UTC 24	416888060 ps
T824	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2527722595	Sep 24 05:11:14 AM UTC 24	Sep 24 05:11:34 AM UTC 24	1152211917 ps
T825	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2553201997	Sep 24 05:11:13 AM UTC 24	Sep 24 05:11:42 AM UTC 24	3126950533 ps
T826	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.1285777973	Sep 24 05:11:35 AM UTC 24	Sep 24 05:11:47 AM UTC 24	94019838 ps
T827	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1335909190	Sep 24 05:11:29 AM UTC 24	Sep 24 05:11:47 AM UTC 24	92068583 ps
T828	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3377639238	Sep 24 05:11:08 AM UTC 24	Sep 24 05:11:51 AM UTC 24	11396333282 ps
T204	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.876930076	Sep 24 05:08:27 AM UTC 24	Sep 24 05:11:51 AM UTC 24	1488716719 ps
T829	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.319569628	Sep 24 05:09:55 AM UTC 24	Sep 24 05:11:57 AM UTC 24	12983950923 ps
T830	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3274758031	Sep 24 05:11:43 AM UTC 24	Sep 24 05:11:59 AM UTC 24	121659139 ps
T831	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2355216093	Sep 24 05:02:25 AM UTC 24	Sep 24 05:12:02 AM UTC 24	105320817838 ps
T832	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4032973717	Sep 24 05:11:28 AM UTC 24	Sep 24 05:12:02 AM UTC 24	4889167064 ps
T833	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.1997021138	Sep 24 05:04:39 AM UTC 24	Sep 24 05:12:03 AM UTC 24	10752949381 ps
T834	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3001775264	Sep 24 05:11:02 AM UTC 24	Sep 24 05:12:03 AM UTC 24	21470732492 ps
T835	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.583454419	Sep 24 05:11:49 AM UTC 24	Sep 24 05:12:06 AM UTC 24	276056497 ps
T836	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1063234936	Sep 24 05:11:29 AM UTC 24	Sep 24 05:12:07 AM UTC 24	6605123271 ps
T837	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.4248437073	Sep 24 05:12:04 AM UTC 24	Sep 24 05:12:08 AM UTC 24	26766988 ps
T838	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3469831991	Sep 24 05:11:49 AM UTC 24	Sep 24 05:12:08 AM UTC 24	520912138 ps
T839	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3461131732	Sep 24 05:11:03 AM UTC 24	Sep 24 05:12:09 AM UTC 24	1231131978 ps
T840	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.2166876432	Sep 24 05:12:04 AM UTC 24	Sep 24 05:12:11 AM UTC 24	329690466 ps
T841	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.320718904	Sep 24 05:11:28 AM UTC 24	Sep 24 05:12:12 AM UTC 24	1106410893 ps
T842	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.452106035	Sep 24 05:11:26 AM UTC 24	Sep 24 05:12:13 AM UTC 24	7841109913 ps
T843	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3190516666	Sep 24 05:12:09 AM UTC 24	Sep 24 05:12:19 AM UTC 24	64813554 ps
T844	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3642541246	Sep 24 05:11:33 AM UTC 24	Sep 24 05:12:19 AM UTC 24	440231914 ps
T845	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3181121024	Sep 24 05:05:00 AM UTC 24	Sep 24 05:12:19 AM UTC 24	2094404042 ps
T846	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.517147152	Sep 24 05:05:31 AM UTC 24	Sep 24 05:12:23 AM UTC 24	9497770370 ps
T847	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.122085911	Sep 24 05:11:18 AM UTC 24	Sep 24 05:12:26 AM UTC 24	2672049424 ps
T848	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1710783260	Sep 24 05:12:13 AM UTC 24	Sep 24 05:12:31 AM UTC 24	1495884153 ps
T849	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3292085545	Sep 24 05:07:24 AM UTC 24	Sep 24 05:12:37 AM UTC 24	34541987119 ps
T850	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2261048686	Sep 24 05:12:09 AM UTC 24	Sep 24 05:12:37 AM UTC 24	601671534 ps
T851	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.1106459518	Sep 24 05:12:21 AM UTC 24	Sep 24 05:12:39 AM UTC 24	451476315 ps
T852	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.377327763	Sep 24 05:06:17 AM UTC 24	Sep 24 05:12:40 AM UTC 24	47791031997 ps
T853	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3453010104	Sep 24 05:09:02 AM UTC 24	Sep 24 05:12:42 AM UTC 24	5143229235 ps
T854	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.996666482	Sep 24 05:12:15 AM UTC 24	Sep 24 05:12:44 AM UTC 24	265893145 ps
T855	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.5603684	Sep 24 05:11:21 AM UTC 24	Sep 24 05:12:47 AM UTC 24	147122107 ps
T856	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2875473803	Sep 24 05:10:46 AM UTC 24	Sep 24 05:12:47 AM UTC 24	355385223 ps
T857	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.4014195841	Sep 24 05:12:21 AM UTC 24	Sep 24 05:12:52 AM UTC 24	1275220783 ps
T242	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3643316818	Sep 24 05:10:26 AM UTC 24	Sep 24 05:12:54 AM UTC 24	1344887042 ps
T858	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3585722964	Sep 24 05:06:19 AM UTC 24	Sep 24 05:12:56 AM UTC 24	9020193501 ps
T859	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.273177114	Sep 24 05:12:05 AM UTC 24	Sep 24 05:12:57 AM UTC 24	3094735476 ps
T860	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.4065193389	Sep 24 05:12:05 AM UTC 24	Sep 24 05:13:05 AM UTC 24	7009865585 ps
T151	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2662186335	Sep 24 05:10:10 AM UTC 24	Sep 24 05:13:06 AM UTC 24	64780602351 ps
T861	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3894181162	Sep 24 05:12:21 AM UTC 24	Sep 24 05:13:06 AM UTC 24	1654956171 ps
T862	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1972888956	Sep 24 05:08:13 AM UTC 24	Sep 24 05:13:06 AM UTC 24	33210917754 ps
T863	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2336486110	Sep 24 04:59:08 AM UTC 24	Sep 24 05:13:08 AM UTC 24	90182172850 ps
T864	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.831433824	Sep 24 05:09:22 AM UTC 24	Sep 24 05:13:19 AM UTC 24	33672460706 ps
T865	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.610636564	Sep 24 05:07:01 AM UTC 24	Sep 24 05:13:21 AM UTC 24	7974536097 ps
T866	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1821226062	Sep 24 05:12:33 AM UTC 24	Sep 24 05:13:26 AM UTC 24	267324550 ps
T867	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.4086128581	Sep 24 05:10:24 AM UTC 24	Sep 24 05:13:35 AM UTC 24	3556756164 ps
T154	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2875483590	Sep 24 05:12:12 AM UTC 24	Sep 24 05:13:43 AM UTC 24	3830190396 ps
T44	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1563876884	Sep 24 05:12:24 AM UTC 24	Sep 24 05:13:45 AM UTC 24	109703729 ps
T868	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2228552435	Sep 24 05:00:40 AM UTC 24	Sep 24 05:13:46 AM UTC 24	166132186534 ps
T869	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2399053878	Sep 24 05:10:28 AM UTC 24	Sep 24 05:13:53 AM UTC 24	11689694954 ps
T870	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1335460669	Sep 24 05:07:14 AM UTC 24	Sep 24 05:13:54 AM UTC 24	121393845825 ps
T139	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.145675243	Sep 24 05:10:44 AM UTC 24	Sep 24 05:14:07 AM UTC 24	9160301234 ps
T871	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2050784914	Sep 24 05:12:28 AM UTC 24	Sep 24 05:14:09 AM UTC 24	3246436531 ps
T872	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3447324644	Sep 24 05:03:39 AM UTC 24	Sep 24 05:14:12 AM UTC 24	116698331704 ps
T873	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.869524319	Sep 24 05:12:00 AM UTC 24	Sep 24 05:14:13 AM UTC 24	447780490 ps
T874	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2585618399	Sep 24 05:11:59 AM UTC 24	Sep 24 05:14:15 AM UTC 24	6906813887 ps
T875	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2023139013	Sep 24 05:11:33 AM UTC 24	Sep 24 05:14:20 AM UTC 24	16609970167 ps
T876	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.2727296478	Sep 24 05:12:09 AM UTC 24	Sep 24 05:14:21 AM UTC 24	38305363791 ps
T877	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1148640061	Sep 24 05:10:34 AM UTC 24	Sep 24 05:14:21 AM UTC 24	162586995947 ps
T232	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1570920311	Sep 24 05:01:58 AM UTC 24	Sep 24 05:14:27 AM UTC 24	75496467561 ps
T878	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.280460041	Sep 24 05:09:32 AM UTC 24	Sep 24 05:14:30 AM UTC 24	740188987 ps
T248	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1789339236	Sep 24 05:09:00 AM UTC 24	Sep 24 05:14:33 AM UTC 24	2439544407 ps
T879	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.72717602	Sep 24 05:10:54 AM UTC 24	Sep 24 05:14:36 AM UTC 24	559319104 ps
T880	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.744906368	Sep 24 05:08:03 AM UTC 24	Sep 24 05:14:37 AM UTC 24	10368919779 ps
T881	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2939790272	Sep 24 05:10:52 AM UTC 24	Sep 24 05:14:43 AM UTC 24	16961440492 ps
T882	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.136445343	Sep 24 05:11:16 AM UTC 24	Sep 24 05:14:47 AM UTC 24	4572778681 ps
T883	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2769034794	Sep 24 05:02:51 AM UTC 24	Sep 24 05:14:57 AM UTC 24	102906340679 ps
T884	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3251657727	Sep 24 05:11:05 AM UTC 24	Sep 24 05:15:09 AM UTC 24	32522497560 ps
T885	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1676331762	Sep 24 05:11:02 AM UTC 24	Sep 24 05:15:15 AM UTC 24	74036560697 ps
T69	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3180042186	Sep 24 05:10:34 AM UTC 24	Sep 24 05:15:20 AM UTC 24	21619969722 ps
T886	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.3872101252	Sep 24 05:11:52 AM UTC 24	Sep 24 05:15:27 AM UTC 24	6840503739 ps
T887	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3311741234	Sep 24 05:10:28 AM UTC 24	Sep 24 05:15:30 AM UTC 24	1941074427 ps
T888	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.950206574	Sep 24 05:11:52 AM UTC 24	Sep 24 05:15:36 AM UTC 24	1292785965 ps
T889	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2214917730	Sep 24 05:04:55 AM UTC 24	Sep 24 05:15:39 AM UTC 24	127655980585 ps
T890	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1937431101	Sep 24 05:09:24 AM UTC 24	Sep 24 05:15:52 AM UTC 24	162190756484 ps
T205	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2307038237	Sep 24 05:12:10 AM UTC 24	Sep 24 05:16:25 AM UTC 24	54538541681 ps
T891	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.45254552	Sep 24 05:08:15 AM UTC 24	Sep 24 05:16:40 AM UTC 24	64615974357 ps
T892	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3239118857	Sep 24 05:10:36 AM UTC 24	Sep 24 05:16:48 AM UTC 24	49790680893 ps
T893	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2236591386	Sep 24 05:05:46 AM UTC 24	Sep 24 05:16:53 AM UTC 24	91567148590 ps
T894	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.813212619	Sep 24 05:04:25 AM UTC 24	Sep 24 05:16:53 AM UTC 24	216924042232 ps
T895	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3968272208	Sep 24 05:11:16 AM UTC 24	Sep 24 05:16:54 AM UTC 24	1858435012 ps
T896	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2378518405	Sep 24 04:57:41 AM UTC 24	Sep 24 05:16:56 AM UTC 24	364784525111 ps
T897	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2633332922	Sep 24 05:06:34 AM UTC 24	Sep 24 05:17:21 AM UTC 24	115428876142 ps
T898	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2541282782	Sep 24 05:03:22 AM UTC 24	Sep 24 05:17:27 AM UTC 24	340447258116 ps
T180	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2731767404	Sep 24 05:05:23 AM UTC 24	Sep 24 05:18:07 AM UTC 24	105217973363 ps
T140	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2156322257	Sep 24 05:09:24 AM UTC 24	Sep 24 05:22:09 AM UTC 24	64816464265 ps
T899	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3307271559	Sep 24 05:05:33 AM UTC 24	Sep 24 05:22:23 AM UTC 24	24555900185 ps
T152	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.944337654	Sep 24 05:11:34 AM UTC 24	Sep 24 05:24:00 AM UTC 24	125310608502 ps
T900	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3836962970	Sep 24 05:12:12 AM UTC 24	Sep 24 05:28:47 AM UTC 24	132253798545 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.973235512
Short name	T3
Test name
Test status
Simulation time	503229050 ps
CPU time	19.56 seconds
Started	Sep 24 04:40:59 AM UTC 24
Finished	Sep 24 04:41:20 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973235512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.973235512
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.4128754038
Short name	T115
Test name
Test status
Simulation time	100888554171 ps
CPU time	877.3 seconds
Started	Sep 24 04:47:12 AM UTC 24
Finished	Sep 24 05:02:02 AM UTC 24
Peak memory	220204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128754038 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.4128754038
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.2253760974
Short name	T21
Test name
Test status
Simulation time	6056826237 ps
CPU time	69.5 seconds
Started	Sep 24 04:41:35 AM UTC 24
Finished	Sep 24 04:42:46 AM UTC 24
Peak memory	217280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253760974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2253760974
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2683427883
Short name	T136
Test name
Test status
Simulation time	433719725734 ps
CPU time	934.97 seconds
Started	Sep 24 04:48:04 AM UTC 24
Finished	Sep 24 05:03:52 AM UTC 24
Peak memory	220008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683427883 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.2683427883
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2978293537
Short name	T47
Test name
Test status
Simulation time	10362603461 ps
CPU time	71.84 seconds
Started	Sep 24 04:41:42 AM UTC 24
Finished	Sep 24 04:42:55 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978293537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2978293537
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.467271670
Short name	T80
Test name
Test status
Simulation time	2498597614 ps
CPU time	77.86 seconds
Started	Sep 24 04:42:02 AM UTC 24
Finished	Sep 24 04:43:22 AM UTC 24
Peak memory	218148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467271670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.467271670
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.3333114528
Short name	T427
Test name
Test status
Simulation time	469267031 ps
CPU time	55.17 seconds
Started	Sep 24 04:58:50 AM UTC 24
Finished	Sep 24 04:59:47 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333114528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3333114528
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.2242914877
Short name	T11
Test name
Test status
Simulation time	402146346 ps
CPU time	19.86 seconds
Started	Sep 24 04:41:12 AM UTC 24
Finished	Sep 24 04:41:33 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242914877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2242914877
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.4085178530
Short name	T263
Test name
Test status
Simulation time	48815684882 ps
CPU time	471.83 seconds
Started	Sep 24 04:46:20 AM UTC 24
Finished	Sep 24 04:54:19 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085178530 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.4085178530
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.3365994059
Short name	T84
Test name
Test status
Simulation time	6335594248 ps
CPU time	219.95 seconds
Started	Sep 24 04:42:17 AM UTC 24
Finished	Sep 24 04:46:01 AM UTC 24
Peak memory	222052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365994059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3365994059
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1341608028
Short name	T22
Test name
Test status
Simulation time	10992864121 ps
CPU time	40.49 seconds
Started	Sep 24 04:40:56 AM UTC 24
Finished	Sep 24 04:41:38 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341608028 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1341608028
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.658729670
Short name	T254
Test name
Test status
Simulation time	11271776201 ps
CPU time	207.66 seconds
Started	Sep 24 04:44:16 AM UTC 24
Finished	Sep 24 04:47:48 AM UTC 24
Peak memory	222056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658729670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.658729670
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2176805870
Short name	T32
Test name
Test status
Simulation time	504357029 ps
CPU time	140.02 seconds
Started	Sep 24 04:41:44 AM UTC 24
Finished	Sep 24 04:44:07 AM UTC 24
Peak memory	222064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176805870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.2176805870
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.3906144752
Short name	T193
Test name
Test status
Simulation time	1643945963 ps
CPU time	72.93 seconds
Started	Sep 24 04:50:48 AM UTC 24
Finished	Sep 24 04:52:03 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906144752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3906144752
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3150912073
Short name	T240
Test name
Test status
Simulation time	456533879 ps
CPU time	140.4 seconds
Started	Sep 24 04:44:17 AM UTC 24
Finished	Sep 24 04:46:41 AM UTC 24
Peak memory	221928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150912073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.3150912073
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.753304266
Short name	T81
Test name
Test status
Simulation time	13925119265 ps
CPU time	181.72 seconds
Started	Sep 24 04:41:41 AM UTC 24
Finished	Sep 24 04:44:47 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753304266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.753304266
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2258509818
Short name	T210
Test name
Test status
Simulation time	1810941775 ps
CPU time	155.52 seconds
Started	Sep 24 04:59:37 AM UTC 24
Finished	Sep 24 05:02:16 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258509818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.2258509818
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2972260147
Short name	T636
Test name
Test status
Simulation time	6757387020 ps
CPU time	273.52 seconds
Started	Sep 24 05:01:34 AM UTC 24
Finished	Sep 24 05:06:12 AM UTC 24
Peak memory	232720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972260147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2972260147
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.2915609603
Short name	T9
Test name
Test status
Simulation time	259772959 ps
CPU time	19.33 seconds
Started	Sep 24 04:41:02 AM UTC 24
Finished	Sep 24 04:41:23 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915609603 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2915609603
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1604007435
Short name	T42
Test name
Test status
Simulation time	734953191 ps
CPU time	307.52 seconds
Started	Sep 24 05:01:03 AM UTC 24
Finished	Sep 24 05:06:15 AM UTC 24
Peak memory	232528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604007435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.1604007435
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.993217206
Short name	T36
Test name
Test status
Simulation time	5284934826 ps
CPU time	238.01 seconds
Started	Sep 24 04:53:38 AM UTC 24
Finished	Sep 24 04:57:40 AM UTC 24
Peak memory	220008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993217206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.993217206
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3641715746
Short name	T43
Test name
Test status
Simulation time	8638188318 ps
CPU time	574.71 seconds
Started	Sep 24 04:58:59 AM UTC 24
Finished	Sep 24 05:08:41 AM UTC 24
Peak memory	222352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641715746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.3641715746
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2943510377
Short name	T38
Test name
Test status
Simulation time	7598199953 ps
CPU time	337.5 seconds
Started	Sep 24 05:03:07 AM UTC 24
Finished	Sep 24 05:08:50 AM UTC 24
Peak memory	234704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943510377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.2943510377
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1937268895
Short name	T30
Test name
Test status
Simulation time	1359008985 ps
CPU time	211.22 seconds
Started	Sep 24 05:03:28 AM UTC 24
Finished	Sep 24 05:07:03 AM UTC 24
Peak memory	222280 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937268895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.1937268895
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3073083338
Short name	T39
Test name
Test status
Simulation time	308271243 ps
CPU time	187.49 seconds
Started	Sep 24 05:07:22 AM UTC 24
Finished	Sep 24 05:10:33 AM UTC 24
Peak memory	219892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073083338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.3073083338
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3235068433
Short name	T35
Test name
Test status
Simulation time	4537688419 ps
CPU time	262.13 seconds
Started	Sep 24 04:41:41 AM UTC 24
Finished	Sep 24 04:46:08 AM UTC 24
Peak memory	222128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235068433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.3235068433
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.1510838
Short name	T26
Test name
Test status
Simulation time	1474714341 ps
CPU time	41.64 seconds
Started	Sep 24 04:41:07 AM UTC 24
Finished	Sep 24 04:41:51 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1510838
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.730022407
Short name	T163
Test name
Test status
Simulation time	8406486349 ps
CPU time	87.28 seconds
Started	Sep 24 04:41:11 AM UTC 24
Finished	Sep 24 04:42:40 AM UTC 24
Peak memory	216160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730022407 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.730022407
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1887022900
Short name	T12
Test name
Test status
Simulation time	133961723 ps
CPU time	16.26 seconds
Started	Sep 24 04:41:16 AM UTC 24
Finished	Sep 24 04:41:33 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887022900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1887022900
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.1909397093
Short name	T16
Test name
Test status
Simulation time	288265930 ps
CPU time	27.02 seconds
Started	Sep 24 04:41:14 AM UTC 24
Finished	Sep 24 04:41:43 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909397093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1909397093
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.3561094050
Short name	T34
Test name
Test status
Simulation time	50361910419 ps
CPU time	175.53 seconds
Started	Sep 24 04:41:02 AM UTC 24
Finished	Sep 24 04:44:01 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561094050 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3561094050
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2014689623
Short name	T182
Test name
Test status
Simulation time	28384102759 ps
CPU time	223.74 seconds
Started	Sep 24 04:41:07 AM UTC 24
Finished	Sep 24 04:44:55 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014689623 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2014689623
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.1699549578
Short name	T1
Test name
Test status
Simulation time	27964004 ps
CPU time	2.73 seconds
Started	Sep 24 04:40:53 AM UTC 24
Finished	Sep 24 04:40:57 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699549578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1699549578
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.175696801
Short name	T13
Test name
Test status
Simulation time	3149076340 ps
CPU time	38.21 seconds
Started	Sep 24 04:40:58 AM UTC 24
Finished	Sep 24 04:41:37 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175696801 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.175696801
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3832129976
Short name	T2
Test name
Test status
Simulation time	53169545 ps
CPU time	2.54 seconds
Started	Sep 24 04:40:54 AM UTC 24
Finished	Sep 24 04:40:58 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832129976 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3832129976
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.509774054
Short name	T49
Test name
Test status
Simulation time	7090319626 ps
CPU time	138.98 seconds
Started	Sep 24 04:41:16 AM UTC 24
Finished	Sep 24 04:43:38 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509774054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.509774054
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3335293828
Short name	T252
Test name
Test status
Simulation time	15824315737 ps
CPU time	177.14 seconds
Started	Sep 24 04:41:20 AM UTC 24
Finished	Sep 24 04:44:21 AM UTC 24
Peak memory	220204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335293828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3335293828
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3826884870
Short name	T269
Test name
Test status
Simulation time	6235712296 ps
CPU time	290.49 seconds
Started	Sep 24 04:41:19 AM UTC 24
Finished	Sep 24 04:46:15 AM UTC 24
Peak memory	220208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826884870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.3826884870
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3286629365
Short name	T227
Test name
Test status
Simulation time	685036419 ps
CPU time	212.03 seconds
Started	Sep 24 04:41:20 AM UTC 24
Finished	Sep 24 04:44:56 AM UTC 24
Peak memory	232524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286629365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.3286629365
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.3939931503
Short name	T8
Test name
Test status
Simulation time	841236399 ps
CPU time	16.49 seconds
Started	Sep 24 04:41:16 AM UTC 24
Finished	Sep 24 04:41:33 AM UTC 24
Peak memory	215848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939931503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3939931503
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2284452514
Short name	T83
Test name
Test status
Simulation time	48169497171 ps
CPU time	212.17 seconds
Started	Sep 24 04:41:35 AM UTC 24
Finished	Sep 24 04:45:11 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284452514 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2284452514
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1023125143
Short name	T25
Test name
Test status
Simulation time	858926123 ps
CPU time	19 seconds
Started	Sep 24 04:41:40 AM UTC 24
Finished	Sep 24 04:42:00 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023125143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1023125143
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.1403506126
Short name	T72
Test name
Test status
Simulation time	894640002 ps
CPU time	23.75 seconds
Started	Sep 24 04:41:38 AM UTC 24
Finished	Sep 24 04:42:03 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403506126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1403506126
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.4160420390
Short name	T23
Test name
Test status
Simulation time	495627722 ps
CPU time	15.04 seconds
Started	Sep 24 04:41:29 AM UTC 24
Finished	Sep 24 04:41:45 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160420390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.4160420390
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.583460032
Short name	T24
Test name
Test status
Simulation time	4900543101 ps
CPU time	17.8 seconds
Started	Sep 24 04:41:30 AM UTC 24
Finished	Sep 24 04:41:49 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583460032 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.583460032
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3839106633
Short name	T303
Test name
Test status
Simulation time	107985671164 ps
CPU time	395.32 seconds
Started	Sep 24 04:41:35 AM UTC 24
Finished	Sep 24 04:48:17 AM UTC 24
Peak memory	218048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839106633 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3839106633
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.3638191584
Short name	T15
Test name
Test status
Simulation time	146368294 ps
CPU time	9.61 seconds
Started	Sep 24 04:41:30 AM UTC 24
Finished	Sep 24 04:41:41 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638191584 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3638191584
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.2378165108
Short name	T14
Test name
Test status
Simulation time	101151506 ps
CPU time	5 seconds
Started	Sep 24 04:41:35 AM UTC 24
Finished	Sep 24 04:41:41 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378165108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2378165108
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.2379958434
Short name	T7
Test name
Test status
Simulation time	142335559 ps
CPU time	4.39 seconds
Started	Sep 24 04:41:23 AM UTC 24
Finished	Sep 24 04:41:29 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379958434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2379958434
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.850029702
Short name	T51
Test name
Test status
Simulation time	14299592538 ps
CPU time	51.82 seconds
Started	Sep 24 04:41:28 AM UTC 24
Finished	Sep 24 04:42:21 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850029702 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.850029702
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.158902097
Short name	T73
Test name
Test status
Simulation time	4205873147 ps
CPU time	44.73 seconds
Started	Sep 24 04:41:29 AM UTC 24
Finished	Sep 24 04:42:15 AM UTC 24
Peak memory	216020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158902097 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.158902097
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.4048003559
Short name	T10
Test name
Test status
Simulation time	31294049 ps
CPU time	2.75 seconds
Started	Sep 24 04:41:25 AM UTC 24
Finished	Sep 24 04:41:28 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048003559 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.4048003559
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.107409037
Short name	T50
Test name
Test status
Simulation time	3508281778 ps
CPU time	23.23 seconds
Started	Sep 24 04:41:38 AM UTC 24
Finished	Sep 24 04:42:02 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107409037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.107409037
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.583066623
Short name	T172
Test name
Test status
Simulation time	323440149 ps
CPU time	8.48 seconds
Started	Sep 24 04:49:09 AM UTC 24
Finished	Sep 24 04:49:18 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583066623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.583066623
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.4252700991
Short name	T257
Test name
Test status
Simulation time	236737382222 ps
CPU time	765.64 seconds
Started	Sep 24 04:49:11 AM UTC 24
Finished	Sep 24 05:02:07 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252700991 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.4252700991
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.4072537528
Short name	T95
Test name
Test status
Simulation time	1950629332 ps
CPU time	24.98 seconds
Started	Sep 24 04:49:27 AM UTC 24
Finished	Sep 24 04:49:54 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072537528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.4072537528
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.423591720
Short name	T176
Test name
Test status
Simulation time	152580796 ps
CPU time	13.31 seconds
Started	Sep 24 04:49:19 AM UTC 24
Finished	Sep 24 04:49:33 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423591720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.423591720
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.2926281336
Short name	T55
Test name
Test status
Simulation time	1221273778 ps
CPU time	19.99 seconds
Started	Sep 24 04:48:46 AM UTC 24
Finished	Sep 24 04:49:07 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926281336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2926281336
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.2923295714
Short name	T177
Test name
Test status
Simulation time	11554719439 ps
CPU time	26.33 seconds
Started	Sep 24 04:49:07 AM UTC 24
Finished	Sep 24 04:49:35 AM UTC 24
Peak memory	216100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923295714 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2923295714
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2379685336
Short name	T108
Test name
Test status
Simulation time	173559497865 ps
CPU time	394 seconds
Started	Sep 24 04:49:09 AM UTC 24
Finished	Sep 24 04:55:49 AM UTC 24
Peak memory	216104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379685336 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2379685336
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.224382711
Short name	T310
Test name
Test status
Simulation time	113801777 ps
CPU time	17.27 seconds
Started	Sep 24 04:48:49 AM UTC 24
Finished	Sep 24 04:49:08 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224382711 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.224382711
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.798146597
Short name	T92
Test name
Test status
Simulation time	1569788236 ps
CPU time	45 seconds
Started	Sep 24 04:49:13 AM UTC 24
Finished	Sep 24 04:49:59 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798146597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.798146597
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.885149535
Short name	T308
Test name
Test status
Simulation time	30524125 ps
CPU time	2.99 seconds
Started	Sep 24 04:48:37 AM UTC 24
Finished	Sep 24 04:48:41 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885149535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.885149535
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3318327249
Short name	T173
Test name
Test status
Simulation time	4295897699 ps
CPU time	34.86 seconds
Started	Sep 24 04:48:43 AM UTC 24
Finished	Sep 24 04:49:19 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318327249 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3318327249
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3333263038
Short name	T174
Test name
Test status
Simulation time	6096475049 ps
CPU time	41.85 seconds
Started	Sep 24 04:48:43 AM UTC 24
Finished	Sep 24 04:49:26 AM UTC 24
Peak memory	216080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333263038 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3333263038
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2979521172
Short name	T5
Test name
Test status
Simulation time	29402346 ps
CPU time	2.83 seconds
Started	Sep 24 04:48:42 AM UTC 24
Finished	Sep 24 04:48:45 AM UTC 24
Peak memory	216016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979521172 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2979521172
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.1637488537
Short name	T192
Test name
Test status
Simulation time	647573872 ps
CPU time	87.96 seconds
Started	Sep 24 04:49:27 AM UTC 24
Finished	Sep 24 04:50:58 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637488537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1637488537
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.743793917
Short name	T318
Test name
Test status
Simulation time	2163454020 ps
CPU time	125.28 seconds
Started	Sep 24 04:49:36 AM UTC 24
Finished	Sep 24 04:51:44 AM UTC 24
Peak memory	219944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743793917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.743793917
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2654126301
Short name	T124
Test name
Test status
Simulation time	2264417055 ps
CPU time	473.43 seconds
Started	Sep 24 04:49:35 AM UTC 24
Finished	Sep 24 04:57:36 AM UTC 24
Peak memory	232524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654126301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.2654126301
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3422508345
Short name	T272
Test name
Test status
Simulation time	2684366849 ps
CPU time	165.47 seconds
Started	Sep 24 04:49:37 AM UTC 24
Finished	Sep 24 04:52:26 AM UTC 24
Peak memory	222088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422508345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.3422508345
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.3122362290
Short name	T178
Test name
Test status
Simulation time	68548178 ps
CPU time	14.39 seconds
Started	Sep 24 04:49:20 AM UTC 24
Finished	Sep 24 04:49:36 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122362290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3122362290
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.2258747080
Short name	T226
Test name
Test status
Simulation time	803061677 ps
CPU time	36.73 seconds
Started	Sep 24 04:50:15 AM UTC 24
Finished	Sep 24 04:50:53 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258747080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2258747080
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1788973708
Short name	T268
Test name
Test status
Simulation time	13686937408 ps
CPU time	147.56 seconds
Started	Sep 24 04:50:17 AM UTC 24
Finished	Sep 24 04:52:47 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788973708 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1788973708
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.74046522
Short name	T315
Test name
Test status
Simulation time	5276871599 ps
CPU time	28.36 seconds
Started	Sep 24 04:50:42 AM UTC 24
Finished	Sep 24 04:51:12 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74046522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.74046522
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.1630659579
Short name	T314
Test name
Test status
Simulation time	241184594 ps
CPU time	17.9 seconds
Started	Sep 24 04:50:38 AM UTC 24
Finished	Sep 24 04:50:57 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630659579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1630659579
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.49564203
Short name	T98
Test name
Test status
Simulation time	274387099 ps
CPU time	12.49 seconds
Started	Sep 24 04:49:56 AM UTC 24
Finished	Sep 24 04:50:09 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49564203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.49564203
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.1395089815
Short name	T222
Test name
Test status
Simulation time	87176598501 ps
CPU time	391.95 seconds
Started	Sep 24 04:50:01 AM UTC 24
Finished	Sep 24 04:56:39 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395089815 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1395089815
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1987339531
Short name	T335
Test name
Test status
Simulation time	25511657828 ps
CPU time	211.54 seconds
Started	Sep 24 04:50:10 AM UTC 24
Finished	Sep 24 04:53:46 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987339531 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1987339531
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.2403418350
Short name	T100
Test name
Test status
Simulation time	127866376 ps
CPU time	14.44 seconds
Started	Sep 24 04:50:00 AM UTC 24
Finished	Sep 24 04:50:16 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403418350 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2403418350
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.3520260851
Short name	T312
Test name
Test status
Simulation time	72840128 ps
CPU time	4.87 seconds
Started	Sep 24 04:50:36 AM UTC 24
Finished	Sep 24 04:50:42 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520260851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3520260851
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.252171080
Short name	T56
Test name
Test status
Simulation time	246452010 ps
CPU time	4.36 seconds
Started	Sep 24 04:49:49 AM UTC 24
Finished	Sep 24 04:49:55 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252171080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.252171080
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.4085487921
Short name	T311
Test name
Test status
Simulation time	9474949224 ps
CPU time	38.53 seconds
Started	Sep 24 04:49:55 AM UTC 24
Finished	Sep 24 04:50:35 AM UTC 24
Peak memory	216080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085487921 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.4085487921
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.252182099
Short name	T57
Test name
Test status
Simulation time	5537887780 ps
CPU time	40.6 seconds
Started	Sep 24 04:49:56 AM UTC 24
Finished	Sep 24 04:50:38 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252182099 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.252182099
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2584838984
Short name	T96
Test name
Test status
Simulation time	32530574 ps
CPU time	2.6 seconds
Started	Sep 24 04:49:51 AM UTC 24
Finished	Sep 24 04:49:55 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584838984 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2584838984
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1661159196
Short name	T328
Test name
Test status
Simulation time	1104640375 ps
CPU time	106.15 seconds
Started	Sep 24 04:50:58 AM UTC 24
Finished	Sep 24 04:52:47 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661159196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1661159196
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.528788281
Short name	T165
Test name
Test status
Simulation time	1045710501 ps
CPU time	204.94 seconds
Started	Sep 24 04:50:54 AM UTC 24
Finished	Sep 24 04:54:22 AM UTC 24
Peak memory	220068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528788281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.528788281
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3998469516
Short name	T319
Test name
Test status
Simulation time	193683309 ps
CPU time	57.49 seconds
Started	Sep 24 04:50:59 AM UTC 24
Finished	Sep 24 04:51:58 AM UTC 24
Peak memory	219888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998469516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.3998469516
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.1921626304
Short name	T313
Test name
Test status
Simulation time	132931055 ps
CPU time	6.15 seconds
Started	Sep 24 04:50:39 AM UTC 24
Finished	Sep 24 04:50:46 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921626304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1921626304
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.2915437679
Short name	T194
Test name
Test status
Simulation time	735347970 ps
CPU time	22.92 seconds
Started	Sep 24 04:52:03 AM UTC 24
Finished	Sep 24 04:52:29 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915437679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2915437679
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3314406312
Short name	T264
Test name
Test status
Simulation time	52586497606 ps
CPU time	607.72 seconds
Started	Sep 24 04:52:05 AM UTC 24
Finished	Sep 24 05:02:23 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314406312 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.3314406312
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3083282643
Short name	T323
Test name
Test status
Simulation time	18339584 ps
CPU time	3.82 seconds
Started	Sep 24 04:52:27 AM UTC 24
Finished	Sep 24 04:52:32 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083282643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3083282643
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.2505471102
Short name	T329
Test name
Test status
Simulation time	346635048 ps
CPU time	26.37 seconds
Started	Sep 24 04:52:16 AM UTC 24
Finished	Sep 24 04:52:47 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505471102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2505471102
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.1159576829
Short name	T243
Test name
Test status
Simulation time	4743189356 ps
CPU time	40.24 seconds
Started	Sep 24 04:51:22 AM UTC 24
Finished	Sep 24 04:52:04 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159576829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1159576829
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.3790948881
Short name	T220
Test name
Test status
Simulation time	8205006021 ps
CPU time	52.14 seconds
Started	Sep 24 04:52:00 AM UTC 24
Finished	Sep 24 04:52:54 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790948881 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3790948881
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.1928503965
Short name	T126
Test name
Test status
Simulation time	28162108208 ps
CPU time	336.6 seconds
Started	Sep 24 04:52:00 AM UTC 24
Finished	Sep 24 04:57:42 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928503965 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1928503965
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.2525267715
Short name	T322
Test name
Test status
Simulation time	169116029 ps
CPU time	27.94 seconds
Started	Sep 24 04:51:45 AM UTC 24
Finished	Sep 24 04:52:15 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525267715 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2525267715
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.3344212152
Short name	T324
Test name
Test status
Simulation time	1019689606 ps
CPU time	24.18 seconds
Started	Sep 24 04:52:07 AM UTC 24
Finished	Sep 24 04:52:33 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344212152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3344212152
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.3654489926
Short name	T249
Test name
Test status
Simulation time	129166187 ps
CPU time	4.72 seconds
Started	Sep 24 04:51:06 AM UTC 24
Finished	Sep 24 04:51:12 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654489926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3654489926
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1179112857
Short name	T321
Test name
Test status
Simulation time	6195632270 ps
CPU time	49.42 seconds
Started	Sep 24 04:51:14 AM UTC 24
Finished	Sep 24 04:52:05 AM UTC 24
Peak memory	215808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179112857 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1179112857
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.811667970
Short name	T320
Test name
Test status
Simulation time	4541863842 ps
CPU time	39.42 seconds
Started	Sep 24 04:51:18 AM UTC 24
Finished	Sep 24 04:51:59 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811667970 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.811667970
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3535595352
Short name	T316
Test name
Test status
Simulation time	43469807 ps
CPU time	2.51 seconds
Started	Sep 24 04:51:13 AM UTC 24
Finished	Sep 24 04:51:17 AM UTC 24
Peak memory	215804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535595352 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3535595352
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.3726776440
Short name	T107
Test name
Test status
Simulation time	5554896026 ps
CPU time	83.62 seconds
Started	Sep 24 04:52:30 AM UTC 24
Finished	Sep 24 04:53:56 AM UTC 24
Peak memory	219976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726776440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3726776440
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3464211098
Short name	T354
Test name
Test status
Simulation time	1893183476 ps
CPU time	189.11 seconds
Started	Sep 24 04:52:32 AM UTC 24
Finished	Sep 24 04:55:45 AM UTC 24
Peak memory	221928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464211098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3464211098
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2548139870
Short name	T111
Test name
Test status
Simulation time	6376024677 ps
CPU time	273.48 seconds
Started	Sep 24 04:52:30 AM UTC 24
Finished	Sep 24 04:57:09 AM UTC 24
Peak memory	222460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548139870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2548139870
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2199205454
Short name	T332
Test name
Test status
Simulation time	178438586 ps
CPU time	57.84 seconds
Started	Sep 24 04:52:33 AM UTC 24
Finished	Sep 24 04:53:33 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199205454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.2199205454
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.3782678203
Short name	T93
Test name
Test status
Simulation time	298525530 ps
CPU time	9.05 seconds
Started	Sep 24 04:52:24 AM UTC 24
Finished	Sep 24 04:52:34 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782678203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3782678203
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.3041534802
Short name	T189
Test name
Test status
Simulation time	2607563563 ps
CPU time	47.39 seconds
Started	Sep 24 04:52:55 AM UTC 24
Finished	Sep 24 04:53:44 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041534802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3041534802
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.614377968
Short name	T261
Test name
Test status
Simulation time	12638035541 ps
CPU time	53.17 seconds
Started	Sep 24 04:52:58 AM UTC 24
Finished	Sep 24 04:53:53 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614377968 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.614377968
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.3167609504
Short name	T333
Test name
Test status
Simulation time	42968304 ps
CPU time	3.02 seconds
Started	Sep 24 04:53:32 AM UTC 24
Finished	Sep 24 04:53:37 AM UTC 24
Peak memory	215712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167609504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3167609504
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.775148324
Short name	T336
Test name
Test status
Simulation time	2650604353 ps
CPU time	32.34 seconds
Started	Sep 24 04:53:15 AM UTC 24
Finished	Sep 24 04:53:49 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775148324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.775148324
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.2015951838
Short name	T221
Test name
Test status
Simulation time	4022164474 ps
CPU time	42.24 seconds
Started	Sep 24 04:52:47 AM UTC 24
Finished	Sep 24 04:53:31 AM UTC 24
Peak memory	218096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015951838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2015951838
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.998172609
Short name	T224
Test name
Test status
Simulation time	12523534159 ps
CPU time	107.53 seconds
Started	Sep 24 04:52:48 AM UTC 24
Finished	Sep 24 04:54:38 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998172609 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.998172609
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2601150148
Short name	T61
Test name
Test status
Simulation time	86492916653 ps
CPU time	228.38 seconds
Started	Sep 24 04:52:50 AM UTC 24
Finished	Sep 24 04:56:42 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601150148 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2601150148
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.3542224587
Short name	T331
Test name
Test status
Simulation time	649560269 ps
CPU time	24.28 seconds
Started	Sep 24 04:52:48 AM UTC 24
Finished	Sep 24 04:53:14 AM UTC 24
Peak memory	217820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542224587 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3542224587
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.3360628171
Short name	T334
Test name
Test status
Simulation time	221005222 ps
CPU time	20.84 seconds
Started	Sep 24 04:53:15 AM UTC 24
Finished	Sep 24 04:53:37 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360628171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3360628171
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.3412808401
Short name	T326
Test name
Test status
Simulation time	141731548 ps
CPU time	3.83 seconds
Started	Sep 24 04:52:35 AM UTC 24
Finished	Sep 24 04:52:40 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412808401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3412808401
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2459905812
Short name	T59
Test name
Test status
Simulation time	5844305327 ps
CPU time	49.28 seconds
Started	Sep 24 04:52:41 AM UTC 24
Finished	Sep 24 04:53:32 AM UTC 24
Peak memory	216076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459905812 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2459905812
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.359998733
Short name	T330
Test name
Test status
Simulation time	3846589092 ps
CPU time	31.32 seconds
Started	Sep 24 04:52:41 AM UTC 24
Finished	Sep 24 04:53:14 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359998733 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.359998733
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3525183512
Short name	T327
Test name
Test status
Simulation time	34653113 ps
CPU time	2.95 seconds
Started	Sep 24 04:52:36 AM UTC 24
Finished	Sep 24 04:52:40 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525183512 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3525183512
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.3750020121
Short name	T109
Test name
Test status
Simulation time	6216382229 ps
CPU time	132.82 seconds
Started	Sep 24 04:53:35 AM UTC 24
Finished	Sep 24 04:55:50 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750020121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3750020121
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3316001403
Short name	T359
Test name
Test status
Simulation time	7164039873 ps
CPU time	143.21 seconds
Started	Sep 24 04:53:38 AM UTC 24
Finished	Sep 24 04:56:04 AM UTC 24
Peak memory	220204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316001403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3316001403
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2079064016
Short name	T345
Test name
Test status
Simulation time	195253556 ps
CPU time	46.6 seconds
Started	Sep 24 04:53:44 AM UTC 24
Finished	Sep 24 04:54:32 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079064016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.2079064016
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.738236459
Short name	T338
Test name
Test status
Simulation time	145424513 ps
CPU time	17.67 seconds
Started	Sep 24 04:53:32 AM UTC 24
Finished	Sep 24 04:53:51 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738236459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.738236459
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.1805194191
Short name	T347
Test name
Test status
Simulation time	660096231 ps
CPU time	21.03 seconds
Started	Sep 24 04:54:16 AM UTC 24
Finished	Sep 24 04:54:38 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805194191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1805194191
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3915137164
Short name	T642
Test name
Test status
Simulation time	64960439317 ps
CPU time	708.89 seconds
Started	Sep 24 04:54:18 AM UTC 24
Finished	Sep 24 05:06:16 AM UTC 24
Peak memory	219948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915137164 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.3915137164
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1979081093
Short name	T346
Test name
Test status
Simulation time	57574025 ps
CPU time	9.48 seconds
Started	Sep 24 04:54:25 AM UTC 24
Finished	Sep 24 04:54:36 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979081093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1979081093
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.4133454670
Short name	T343
Test name
Test status
Simulation time	173009119 ps
CPU time	6.85 seconds
Started	Sep 24 04:54:20 AM UTC 24
Finished	Sep 24 04:54:29 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133454670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.4133454670
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.2600155032
Short name	T341
Test name
Test status
Simulation time	227054400 ps
CPU time	23.06 seconds
Started	Sep 24 04:53:52 AM UTC 24
Finished	Sep 24 04:54:17 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600155032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2600155032
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.858225971
Short name	T369
Test name
Test status
Simulation time	21991065145 ps
CPU time	182.03 seconds
Started	Sep 24 04:53:53 AM UTC 24
Finished	Sep 24 04:56:59 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858225971 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.858225971
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2825729756
Short name	T386
Test name
Test status
Simulation time	89588243640 ps
CPU time	269.29 seconds
Started	Sep 24 04:53:57 AM UTC 24
Finished	Sep 24 04:58:32 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825729756 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2825729756
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.2579366526
Short name	T340
Test name
Test status
Simulation time	251694021 ps
CPU time	19.69 seconds
Started	Sep 24 04:53:53 AM UTC 24
Finished	Sep 24 04:54:15 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579366526 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2579366526
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.1912494328
Short name	T342
Test name
Test status
Simulation time	95482032 ps
CPU time	3.38 seconds
Started	Sep 24 04:54:19 AM UTC 24
Finished	Sep 24 04:54:24 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912494328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1912494328
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.639976091
Short name	T337
Test name
Test status
Simulation time	289698849 ps
CPU time	3.89 seconds
Started	Sep 24 04:53:46 AM UTC 24
Finished	Sep 24 04:53:51 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639976091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.639976091
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2495282707
Short name	T155
Test name
Test status
Simulation time	3546702336 ps
CPU time	32.97 seconds
Started	Sep 24 04:53:50 AM UTC 24
Finished	Sep 24 04:54:24 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495282707 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2495282707
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.224033313
Short name	T60
Test name
Test status
Simulation time	5418044500 ps
CPU time	35.27 seconds
Started	Sep 24 04:53:52 AM UTC 24
Finished	Sep 24 04:54:29 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224033313 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.224033313
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2561203477
Short name	T339
Test name
Test status
Simulation time	103558957 ps
CPU time	2.7 seconds
Started	Sep 24 04:53:49 AM UTC 24
Finished	Sep 24 04:53:52 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561203477 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2561203477
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.1094468983
Short name	T259
Test name
Test status
Simulation time	3501140308 ps
CPU time	82.84 seconds
Started	Sep 24 04:54:25 AM UTC 24
Finished	Sep 24 04:55:50 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094468983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1094468983
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1803452280
Short name	T363
Test name
Test status
Simulation time	6199647761 ps
CPU time	119.22 seconds
Started	Sep 24 04:54:30 AM UTC 24
Finished	Sep 24 04:56:32 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803452280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1803452280
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1703920965
Short name	T271
Test name
Test status
Simulation time	112485027 ps
CPU time	61.12 seconds
Started	Sep 24 04:54:29 AM UTC 24
Finished	Sep 24 04:55:32 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703920965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.1703920965
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2825764685
Short name	T468
Test name
Test status
Simulation time	4639642587 ps
CPU time	399.78 seconds
Started	Sep 24 04:54:31 AM UTC 24
Finished	Sep 24 05:01:18 AM UTC 24
Peak memory	222416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825764685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.2825764685
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.4024552178
Short name	T184
Test name
Test status
Simulation time	986758097 ps
CPU time	33.38 seconds
Started	Sep 24 04:54:24 AM UTC 24
Finished	Sep 24 04:54:59 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024552178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.4024552178
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.222082791
Short name	T353
Test name
Test status
Simulation time	572116884 ps
CPU time	38.02 seconds
Started	Sep 24 04:55:05 AM UTC 24
Finished	Sep 24 04:55:45 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222082791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.222082791
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.622826003
Short name	T179
Test name
Test status
Simulation time	285583591297 ps
CPU time	769.17 seconds
Started	Sep 24 04:55:06 AM UTC 24
Finished	Sep 24 05:08:06 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622826003 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.622826003
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3360916983
Short name	T357
Test name
Test status
Simulation time	95710814 ps
CPU time	14.61 seconds
Started	Sep 24 04:55:45 AM UTC 24
Finished	Sep 24 04:56:01 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360916983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3360916983
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.1889982813
Short name	T360
Test name
Test status
Simulation time	1743776246 ps
CPU time	30.83 seconds
Started	Sep 24 04:55:33 AM UTC 24
Finished	Sep 24 04:56:05 AM UTC 24
Peak memory	216028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889982813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1889982813
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.4201601339
Short name	T185
Test name
Test status
Simulation time	625786097 ps
CPU time	22.7 seconds
Started	Sep 24 04:54:41 AM UTC 24
Finished	Sep 24 04:55:05 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201601339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.4201601339
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.900080298
Short name	T441
Test name
Test status
Simulation time	93558390348 ps
CPU time	337.71 seconds
Started	Sep 24 04:54:45 AM UTC 24
Finished	Sep 24 05:00:28 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900080298 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.900080298
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.2826538970
Short name	T209
Test name
Test status
Simulation time	48449036441 ps
CPU time	190.45 seconds
Started	Sep 24 04:55:00 AM UTC 24
Finished	Sep 24 04:58:14 AM UTC 24
Peak memory	218152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826538970 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2826538970
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.4003672780
Short name	T213
Test name
Test status
Simulation time	154142947 ps
CPU time	22.11 seconds
Started	Sep 24 04:54:42 AM UTC 24
Finished	Sep 24 04:55:05 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003672780 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.4003672780
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.2072770042
Short name	T352
Test name
Test status
Simulation time	925693417 ps
CPU time	15.59 seconds
Started	Sep 24 04:55:28 AM UTC 24
Finished	Sep 24 04:55:45 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072770042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2072770042
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.2831378598
Short name	T348
Test name
Test status
Simulation time	522690737 ps
CPU time	4.9 seconds
Started	Sep 24 04:54:34 AM UTC 24
Finished	Sep 24 04:54:40 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831378598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2831378598
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3430155731
Short name	T350
Test name
Test status
Simulation time	11962792064 ps
CPU time	46.15 seconds
Started	Sep 24 04:54:39 AM UTC 24
Finished	Sep 24 04:55:27 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430155731 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3430155731
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3297862476
Short name	T351
Test name
Test status
Simulation time	17932799409 ps
CPU time	52.18 seconds
Started	Sep 24 04:54:39 AM UTC 24
Finished	Sep 24 04:55:33 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297862476 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3297862476
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1321127547
Short name	T349
Test name
Test status
Simulation time	22372540 ps
CPU time	2.8 seconds
Started	Sep 24 04:54:37 AM UTC 24
Finished	Sep 24 04:54:41 AM UTC 24
Peak memory	215752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321127547 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1321127547
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.1233406045
Short name	T231
Test name
Test status
Simulation time	3487021738 ps
CPU time	76.85 seconds
Started	Sep 24 04:55:46 AM UTC 24
Finished	Sep 24 04:57:05 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233406045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1233406045
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1924633709
Short name	T361
Test name
Test status
Simulation time	276038343 ps
CPU time	20.08 seconds
Started	Sep 24 04:55:49 AM UTC 24
Finished	Sep 24 04:56:11 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924633709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1924633709
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.881942350
Short name	T127
Test name
Test status
Simulation time	362872357 ps
CPU time	114 seconds
Started	Sep 24 04:55:46 AM UTC 24
Finished	Sep 24 04:57:43 AM UTC 24
Peak memory	219676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881942350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.881942350
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2498487329
Short name	T451
Test name
Test status
Simulation time	1537778502 ps
CPU time	281.31 seconds
Started	Sep 24 04:55:52 AM UTC 24
Finished	Sep 24 05:00:38 AM UTC 24
Peak memory	222476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498487329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2498487329
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.2352456404
Short name	T356
Test name
Test status
Simulation time	2232313395 ps
CPU time	24.88 seconds
Started	Sep 24 04:55:34 AM UTC 24
Finished	Sep 24 04:56:00 AM UTC 24
Peak memory	218084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352456404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2352456404
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.1964372963
Short name	T112
Test name
Test status
Simulation time	6352797177 ps
CPU time	79.67 seconds
Started	Sep 24 04:56:27 AM UTC 24
Finished	Sep 24 04:57:49 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964372963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1964372963
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1462011632
Short name	T262
Test name
Test status
Simulation time	33351817054 ps
CPU time	299.09 seconds
Started	Sep 24 04:56:28 AM UTC 24
Finished	Sep 24 05:01:32 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462011632 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.1462011632
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.4230675141
Short name	T366
Test name
Test status
Simulation time	66348555 ps
CPU time	8.61 seconds
Started	Sep 24 04:56:40 AM UTC 24
Finished	Sep 24 04:56:50 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230675141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.4230675141
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.211005793
Short name	T367
Test name
Test status
Simulation time	456746329 ps
CPU time	15.88 seconds
Started	Sep 24 04:56:35 AM UTC 24
Finished	Sep 24 04:56:52 AM UTC 24
Peak memory	215680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211005793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.211005793
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.480014206
Short name	T166
Test name
Test status
Simulation time	468809577 ps
CPU time	22.27 seconds
Started	Sep 24 04:56:02 AM UTC 24
Finished	Sep 24 04:56:26 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480014206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.480014206
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.1100275069
Short name	T409
Test name
Test status
Simulation time	20500263854 ps
CPU time	184.61 seconds
Started	Sep 24 04:56:06 AM UTC 24
Finished	Sep 24 04:59:14 AM UTC 24
Peak memory	216168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100275069 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1100275069
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1290659867
Short name	T147
Test name
Test status
Simulation time	14631073560 ps
CPU time	102.88 seconds
Started	Sep 24 04:56:12 AM UTC 24
Finished	Sep 24 04:57:57 AM UTC 24
Peak memory	216172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290659867 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1290659867
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.2399306629
Short name	T362
Test name
Test status
Simulation time	186148889 ps
CPU time	20.81 seconds
Started	Sep 24 04:56:06 AM UTC 24
Finished	Sep 24 04:56:28 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399306629 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2399306629
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.3070787742
Short name	T123
Test name
Test status
Simulation time	2260234333 ps
CPU time	42.49 seconds
Started	Sep 24 04:56:33 AM UTC 24
Finished	Sep 24 04:57:17 AM UTC 24
Peak memory	215836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070787742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3070787742
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.1127652736
Short name	T355
Test name
Test status
Simulation time	137236877 ps
CPU time	3.84 seconds
Started	Sep 24 04:55:52 AM UTC 24
Finished	Sep 24 04:55:57 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127652736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1127652736
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1839950480
Short name	T368
Test name
Test status
Simulation time	20544171220 ps
CPU time	55.61 seconds
Started	Sep 24 04:56:01 AM UTC 24
Finished	Sep 24 04:56:58 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839950480 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1839950480
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.4051520693
Short name	T364
Test name
Test status
Simulation time	5321770064 ps
CPU time	30.09 seconds
Started	Sep 24 04:56:02 AM UTC 24
Finished	Sep 24 04:56:34 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051520693 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.4051520693
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.992862023
Short name	T358
Test name
Test status
Simulation time	31659934 ps
CPU time	2.33 seconds
Started	Sep 24 04:55:58 AM UTC 24
Finished	Sep 24 04:56:01 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992862023 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.992862023
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.292428276
Short name	T255
Test name
Test status
Simulation time	5984188727 ps
CPU time	149.8 seconds
Started	Sep 24 04:56:42 AM UTC 24
Finished	Sep 24 04:59:15 AM UTC 24
Peak memory	220012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292428276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.292428276
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3321413282
Short name	T391
Test name
Test status
Simulation time	7377889656 ps
CPU time	110.15 seconds
Started	Sep 24 04:56:51 AM UTC 24
Finished	Sep 24 04:58:44 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321413282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3321413282
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.246976470
Short name	T461
Test name
Test status
Simulation time	342712745 ps
CPU time	248.93 seconds
Started	Sep 24 04:56:50 AM UTC 24
Finished	Sep 24 05:01:03 AM UTC 24
Peak memory	219876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246976470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.246976470
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.981390090
Short name	T266
Test name
Test status
Simulation time	9464839536 ps
CPU time	187.04 seconds
Started	Sep 24 04:56:53 AM UTC 24
Finished	Sep 24 05:00:04 AM UTC 24
Peak memory	222292 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981390090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.981390090
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.3473772222
Short name	T365
Test name
Test status
Simulation time	168347498 ps
CPU time	12.78 seconds
Started	Sep 24 04:56:35 AM UTC 24
Finished	Sep 24 04:56:49 AM UTC 24
Peak memory	217680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473772222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3473772222
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.288400473
Short name	T131
Test name
Test status
Simulation time	1493403160 ps
CPU time	50.44 seconds
Started	Sep 24 04:57:39 AM UTC 24
Finished	Sep 24 04:58:31 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288400473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.288400473
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2378518405
Short name	T896
Test name
Test status
Simulation time	364784525111 ps
CPU time	1140.78 seconds
Started	Sep 24 04:57:41 AM UTC 24
Finished	Sep 24 05:16:56 AM UTC 24
Peak memory	219952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378518405 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.2378518405
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.406571464
Short name	T130
Test name
Test status
Simulation time	102056811 ps
CPU time	4.27 seconds
Started	Sep 24 04:57:43 AM UTC 24
Finished	Sep 24 04:57:48 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406571464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.406571464
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.170450414
Short name	T148
Test name
Test status
Simulation time	504869569 ps
CPU time	15.47 seconds
Started	Sep 24 04:57:43 AM UTC 24
Finished	Sep 24 04:58:00 AM UTC 24
Peak memory	216024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170450414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.170450414
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.1595309312
Short name	T128
Test name
Test status
Simulation time	731361203 ps
CPU time	36.86 seconds
Started	Sep 24 04:57:06 AM UTC 24
Finished	Sep 24 04:57:45 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595309312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1595309312
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.4090358090
Short name	T495
Test name
Test status
Simulation time	134971379020 ps
CPU time	300.08 seconds
Started	Sep 24 04:57:19 AM UTC 24
Finished	Sep 24 05:02:23 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090358090 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4090358090
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1381225842
Short name	T113
Test name
Test status
Simulation time	14224435537 ps
CPU time	78.67 seconds
Started	Sep 24 04:57:37 AM UTC 24
Finished	Sep 24 04:58:58 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381225842 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1381225842
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.1316671516
Short name	T129
Test name
Test status
Simulation time	718170816 ps
CPU time	34.04 seconds
Started	Sep 24 04:57:10 AM UTC 24
Finished	Sep 24 04:57:46 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316671516 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1316671516
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.2622576689
Short name	T146
Test name
Test status
Simulation time	187604123 ps
CPU time	12.79 seconds
Started	Sep 24 04:57:42 AM UTC 24
Finished	Sep 24 04:57:55 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622576689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2622576689
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.961728978
Short name	T371
Test name
Test status
Simulation time	145050235 ps
CPU time	3.85 seconds
Started	Sep 24 04:56:59 AM UTC 24
Finished	Sep 24 04:57:04 AM UTC 24
Peak memory	215696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961728978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.961728978
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2208533250
Short name	T145
Test name
Test status
Simulation time	17418994377 ps
CPU time	48.56 seconds
Started	Sep 24 04:57:05 AM UTC 24
Finished	Sep 24 04:57:55 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208533250 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2208533250
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1010417655
Short name	T125
Test name
Test status
Simulation time	3824371165 ps
CPU time	33.88 seconds
Started	Sep 24 04:57:06 AM UTC 24
Finished	Sep 24 04:57:42 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010417655 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1010417655
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1248694937
Short name	T370
Test name
Test status
Simulation time	26934560 ps
CPU time	2.59 seconds
Started	Sep 24 04:57:01 AM UTC 24
Finished	Sep 24 04:57:04 AM UTC 24
Peak memory	215692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248694937 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1248694937
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.2215845999
Short name	T219
Test name
Test status
Simulation time	1266664959 ps
CPU time	54.86 seconds
Started	Sep 24 04:57:44 AM UTC 24
Finished	Sep 24 04:58:41 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215845999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2215845999
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2243181179
Short name	T442
Test name
Test status
Simulation time	1395891205 ps
CPU time	157.25 seconds
Started	Sep 24 04:57:48 AM UTC 24
Finished	Sep 24 05:00:28 AM UTC 24
Peak memory	221864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243181179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2243181179
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.4256176311
Short name	T523
Test name
Test status
Simulation time	512526128 ps
CPU time	327.85 seconds
Started	Sep 24 04:57:46 AM UTC 24
Finished	Sep 24 05:03:19 AM UTC 24
Peak memory	221928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256176311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.4256176311
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.4013451348
Short name	T265
Test name
Test status
Simulation time	6384390949 ps
CPU time	209.76 seconds
Started	Sep 24 04:57:48 AM UTC 24
Finished	Sep 24 05:01:21 AM UTC 24
Peak memory	222064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013451348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.4013451348
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.2512228722
Short name	T142
Test name
Test status
Simulation time	237738401 ps
CPU time	7.08 seconds
Started	Sep 24 04:57:43 AM UTC 24
Finished	Sep 24 04:57:51 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512228722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2512228722
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.2084864138
Short name	T214
Test name
Test status
Simulation time	210093802 ps
CPU time	25.91 seconds
Started	Sep 24 04:57:56 AM UTC 24
Finished	Sep 24 04:58:23 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084864138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2084864138
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.284097130
Short name	T135
Test name
Test status
Simulation time	34927971937 ps
CPU time	330.27 seconds
Started	Sep 24 04:57:56 AM UTC 24
Finished	Sep 24 05:03:31 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284097130 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.284097130
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.731897533
Short name	T149
Test name
Test status
Simulation time	56235514 ps
CPU time	2.65 seconds
Started	Sep 24 04:57:59 AM UTC 24
Finished	Sep 24 04:58:02 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731897533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.731897533
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.1442448309
Short name	T384
Test name
Test status
Simulation time	1345483350 ps
CPU time	28.18 seconds
Started	Sep 24 04:57:58 AM UTC 24
Finished	Sep 24 04:58:27 AM UTC 24
Peak memory	215700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442448309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1442448309
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.3906141284
Short name	T374
Test name
Test status
Simulation time	101712029 ps
CPU time	16.98 seconds
Started	Sep 24 04:57:52 AM UTC 24
Finished	Sep 24 04:58:11 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906141284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3906141284
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.299496465
Short name	T379
Test name
Test status
Simulation time	7171992983 ps
CPU time	26.53 seconds
Started	Sep 24 04:57:54 AM UTC 24
Finished	Sep 24 04:58:22 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299496465 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.299496465
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1134563101
Short name	T377
Test name
Test status
Simulation time	2070293131 ps
CPU time	20.6 seconds
Started	Sep 24 04:57:54 AM UTC 24
Finished	Sep 24 04:58:16 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134563101 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1134563101
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.4195761163
Short name	T372
Test name
Test status
Simulation time	99221543 ps
CPU time	14.46 seconds
Started	Sep 24 04:57:54 AM UTC 24
Finished	Sep 24 04:58:09 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195761163 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.4195761163
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.1029226984
Short name	T150
Test name
Test status
Simulation time	114182363 ps
CPU time	8.41 seconds
Started	Sep 24 04:57:58 AM UTC 24
Finished	Sep 24 04:58:07 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029226984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1029226984
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.3723306453
Short name	T144
Test name
Test status
Simulation time	164689683 ps
CPU time	4.38 seconds
Started	Sep 24 04:57:48 AM UTC 24
Finished	Sep 24 04:57:53 AM UTC 24
Peak memory	215956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723306453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3723306453
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.593891152
Short name	T380
Test name
Test status
Simulation time	4374140730 ps
CPU time	32.77 seconds
Started	Sep 24 04:57:50 AM UTC 24
Finished	Sep 24 04:58:24 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593891152 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.593891152
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.273322725
Short name	T62
Test name
Test status
Simulation time	5210849510 ps
CPU time	33.94 seconds
Started	Sep 24 04:57:51 AM UTC 24
Finished	Sep 24 04:58:27 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273322725 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.273322725
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3022537946
Short name	T143
Test name
Test status
Simulation time	41860407 ps
CPU time	2.69 seconds
Started	Sep 24 04:57:49 AM UTC 24
Finished	Sep 24 04:57:53 AM UTC 24
Peak memory	215752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022537946 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3022537946
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.3007748176
Short name	T373
Test name
Test status
Simulation time	298465578 ps
CPU time	7.61 seconds
Started	Sep 24 04:58:01 AM UTC 24
Finished	Sep 24 04:58:10 AM UTC 24
Peak memory	216032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007748176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3007748176
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3362784607
Short name	T381
Test name
Test status
Simulation time	440845237 ps
CPU time	20.44 seconds
Started	Sep 24 04:58:04 AM UTC 24
Finished	Sep 24 04:58:26 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362784607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3362784607
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2233984051
Short name	T531
Test name
Test status
Simulation time	6569926040 ps
CPU time	318.28 seconds
Started	Sep 24 04:58:03 AM UTC 24
Finished	Sep 24 05:03:26 AM UTC 24
Peak memory	232848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233984051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.2233984051
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.695826083
Short name	T490
Test name
Test status
Simulation time	487396099 ps
CPU time	246.61 seconds
Started	Sep 24 04:58:08 AM UTC 24
Finished	Sep 24 05:02:19 AM UTC 24
Peak memory	232720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695826083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.695826083
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.1657764476
Short name	T223
Test name
Test status
Simulation time	349935838 ps
CPU time	9.15 seconds
Started	Sep 24 04:57:58 AM UTC 24
Finished	Sep 24 04:58:08 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657764476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1657764476
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.2656230719
Short name	T132
Test name
Test status
Simulation time	1585247669 ps
CPU time	64.88 seconds
Started	Sep 24 04:58:14 AM UTC 24
Finished	Sep 24 04:59:20 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656230719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2656230719
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.579147124
Short name	T134
Test name
Test status
Simulation time	27120513613 ps
CPU time	275.37 seconds
Started	Sep 24 04:58:15 AM UTC 24
Finished	Sep 24 05:02:54 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579147124 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.579147124
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2841024062
Short name	T392
Test name
Test status
Simulation time	691109984 ps
CPU time	23.78 seconds
Started	Sep 24 04:58:20 AM UTC 24
Finished	Sep 24 04:58:46 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841024062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2841024062
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1330937270
Short name	T390
Test name
Test status
Simulation time	579283860 ps
CPU time	21.77 seconds
Started	Sep 24 04:58:17 AM UTC 24
Finished	Sep 24 04:58:40 AM UTC 24
Peak memory	215960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330937270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1330937270
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.1701271249
Short name	T389
Test name
Test status
Simulation time	726507689 ps
CPU time	26.91 seconds
Started	Sep 24 04:58:11 AM UTC 24
Finished	Sep 24 04:58:39 AM UTC 24
Peak memory	215720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701271249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1701271249
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.3932268920
Short name	T513
Test name
Test status
Simulation time	42144362940 ps
CPU time	284.28 seconds
Started	Sep 24 04:58:12 AM UTC 24
Finished	Sep 24 05:03:01 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932268920 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3932268920
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.62382851
Short name	T456
Test name
Test status
Simulation time	20821052279 ps
CPU time	163.13 seconds
Started	Sep 24 04:58:12 AM UTC 24
Finished	Sep 24 05:00:59 AM UTC 24
Peak memory	216096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62382851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.62382851
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.4001424890
Short name	T382
Test name
Test status
Simulation time	155449409 ps
CPU time	13.8 seconds
Started	Sep 24 04:58:11 AM UTC 24
Finished	Sep 24 04:58:26 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001424890 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.4001424890
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.3775602130
Short name	T378
Test name
Test status
Simulation time	138800532 ps
CPU time	4.48 seconds
Started	Sep 24 04:58:15 AM UTC 24
Finished	Sep 24 04:58:20 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775602130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3775602130
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.2217529159
Short name	T376
Test name
Test status
Simulation time	196143307 ps
CPU time	4.83 seconds
Started	Sep 24 04:58:09 AM UTC 24
Finished	Sep 24 04:58:14 AM UTC 24
Peak memory	215752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217529159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2217529159
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3935687986
Short name	T63
Test name
Test status
Simulation time	31124004445 ps
CPU time	56.72 seconds
Started	Sep 24 04:58:11 AM UTC 24
Finished	Sep 24 04:59:10 AM UTC 24
Peak memory	216080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935687986 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3935687986
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.288415554
Short name	T399
Test name
Test status
Simulation time	6731733470 ps
CPU time	46.9 seconds
Started	Sep 24 04:58:11 AM UTC 24
Finished	Sep 24 04:59:00 AM UTC 24
Peak memory	216148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288415554 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.288415554
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1969676907
Short name	T375
Test name
Test status
Simulation time	26834657 ps
CPU time	3.32 seconds
Started	Sep 24 04:58:09 AM UTC 24
Finished	Sep 24 04:58:13 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969676907 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1969676907
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.2079575879
Short name	T542
Test name
Test status
Simulation time	9897729578 ps
CPU time	318.14 seconds
Started	Sep 24 04:58:20 AM UTC 24
Finished	Sep 24 05:03:44 AM UTC 24
Peak memory	221988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079575879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2079575879
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1765369990
Short name	T464
Test name
Test status
Simulation time	1532217816 ps
CPU time	163.1 seconds
Started	Sep 24 04:58:22 AM UTC 24
Finished	Sep 24 05:01:08 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765369990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1765369990
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2202061687
Short name	T478
Test name
Test status
Simulation time	2891904214 ps
CPU time	201.18 seconds
Started	Sep 24 04:58:22 AM UTC 24
Finished	Sep 24 05:01:46 AM UTC 24
Peak memory	221996 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202061687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.2202061687
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3064636107
Short name	T514
Test name
Test status
Simulation time	3466797851 ps
CPU time	275.93 seconds
Started	Sep 24 04:58:23 AM UTC 24
Finished	Sep 24 05:03:04 AM UTC 24
Peak memory	232592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064636107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.3064636107
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.3316399059
Short name	T398
Test name
Test status
Simulation time	1184621218 ps
CPU time	32.98 seconds
Started	Sep 24 04:58:20 AM UTC 24
Finished	Sep 24 04:58:55 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316399059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3316399059
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3864578751
Short name	T212
Test name
Test status
Simulation time	24734355392 ps
CPU time	252.55 seconds
Started	Sep 24 04:42:02 AM UTC 24
Finished	Sep 24 04:46:19 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864578751 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.3864578751
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1227290991
Short name	T31
Test name
Test status
Simulation time	4160717162 ps
CPU time	36.52 seconds
Started	Sep 24 04:42:13 AM UTC 24
Finished	Sep 24 04:42:52 AM UTC 24
Peak memory	215852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227290991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1227290991
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.3589735828
Short name	T17
Test name
Test status
Simulation time	166235902 ps
CPU time	4.88 seconds
Started	Sep 24 04:42:04 AM UTC 24
Finished	Sep 24 04:42:10 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589735828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3589735828
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.87001321
Short name	T18
Test name
Test status
Simulation time	1303628061 ps
CPU time	20.32 seconds
Started	Sep 24 04:41:51 AM UTC 24
Finished	Sep 24 04:42:13 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87001321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.87001321
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.4250308261
Short name	T225
Test name
Test status
Simulation time	74422252877 ps
CPU time	230.19 seconds
Started	Sep 24 04:42:00 AM UTC 24
Finished	Sep 24 04:45:54 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250308261 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.4250308261
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2782403864
Short name	T120
Test name
Test status
Simulation time	23003208235 ps
CPU time	107.13 seconds
Started	Sep 24 04:42:00 AM UTC 24
Finished	Sep 24 04:43:50 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782403864 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2782403864
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.3984098831
Short name	T20
Test name
Test status
Simulation time	269102854 ps
CPU time	28.65 seconds
Started	Sep 24 04:41:51 AM UTC 24
Finished	Sep 24 04:42:21 AM UTC 24
Peak memory	217816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984098831 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3984098831
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.3038855463
Short name	T19
Test name
Test status
Simulation time	405071911 ps
CPU time	16.09 seconds
Started	Sep 24 04:42:03 AM UTC 24
Finished	Sep 24 04:42:20 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038855463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3038855463
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.1944997154
Short name	T70
Test name
Test status
Simulation time	30031056 ps
CPU time	2.45 seconds
Started	Sep 24 04:41:45 AM UTC 24
Finished	Sep 24 04:41:48 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944997154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1944997154
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2152037379
Short name	T162
Test name
Test status
Simulation time	5682833595 ps
CPU time	46.35 seconds
Started	Sep 24 04:41:49 AM UTC 24
Finished	Sep 24 04:42:37 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152037379 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2152037379
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2286992492
Short name	T207
Test name
Test status
Simulation time	7448008175 ps
CPU time	48.85 seconds
Started	Sep 24 04:41:50 AM UTC 24
Finished	Sep 24 04:42:41 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286992492 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2286992492
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.264226036
Short name	T71
Test name
Test status
Simulation time	76777456 ps
CPU time	3.28 seconds
Started	Sep 24 04:41:46 AM UTC 24
Finished	Sep 24 04:41:50 AM UTC 24
Peak memory	215692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264226036 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.264226036
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.217943577
Short name	T48
Test name
Test status
Simulation time	873626389 ps
CPU time	41.51 seconds
Started	Sep 24 04:42:22 AM UTC 24
Finished	Sep 24 04:43:05 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217943577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.217943577
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1835738527
Short name	T88
Test name
Test status
Simulation time	4618356951 ps
CPU time	280.12 seconds
Started	Sep 24 04:42:18 AM UTC 24
Finished	Sep 24 04:47:03 AM UTC 24
Peak memory	220012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835738527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.1835738527
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1599403580
Short name	T270
Test name
Test status
Simulation time	391144802 ps
CPU time	130.77 seconds
Started	Sep 24 04:42:23 AM UTC 24
Finished	Sep 24 04:44:37 AM UTC 24
Peak memory	221936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599403580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.1599403580
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.1325112132
Short name	T52
Test name
Test status
Simulation time	322662169 ps
CPU time	13.47 seconds
Started	Sep 24 04:42:11 AM UTC 24
Finished	Sep 24 04:42:26 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325112132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1325112132
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.3820094437
Short name	T396
Test name
Test status
Simulation time	467304831 ps
CPU time	21.04 seconds
Started	Sep 24 04:58:28 AM UTC 24
Finished	Sep 24 04:58:51 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820094437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3820094437
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1943979012
Short name	T445
Test name
Test status
Simulation time	14045569499 ps
CPU time	121.75 seconds
Started	Sep 24 04:58:28 AM UTC 24
Finished	Sep 24 05:00:33 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943979012 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.1943979012
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1394322962
Short name	T401
Test name
Test status
Simulation time	1146661912 ps
CPU time	27.51 seconds
Started	Sep 24 04:58:33 AM UTC 24
Finished	Sep 24 04:59:02 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394322962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1394322962
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.3638238561
Short name	T387
Test name
Test status
Simulation time	22033553 ps
CPU time	3.8 seconds
Started	Sep 24 04:58:30 AM UTC 24
Finished	Sep 24 04:58:35 AM UTC 24
Peak memory	215704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638238561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3638238561
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.627843637
Short name	T395
Test name
Test status
Simulation time	253992367 ps
CPU time	20.08 seconds
Started	Sep 24 04:58:27 AM UTC 24
Finished	Sep 24 04:58:48 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627843637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.627843637
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.2896550186
Short name	T412
Test name
Test status
Simulation time	14783395992 ps
CPU time	46.91 seconds
Started	Sep 24 04:58:27 AM UTC 24
Finished	Sep 24 04:59:16 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896550186 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2896550186
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1889802149
Short name	T541
Test name
Test status
Simulation time	115221764625 ps
CPU time	309.26 seconds
Started	Sep 24 04:58:28 AM UTC 24
Finished	Sep 24 05:03:42 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889802149 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1889802149
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.1819504528
Short name	T388
Test name
Test status
Simulation time	62316304 ps
CPU time	6.8 seconds
Started	Sep 24 04:58:27 AM UTC 24
Finished	Sep 24 04:58:35 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819504528 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1819504528
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.3005974972
Short name	T403
Test name
Test status
Simulation time	1419007828 ps
CPU time	32.42 seconds
Started	Sep 24 04:58:30 AM UTC 24
Finished	Sep 24 04:59:03 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005974972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3005974972
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.2934988078
Short name	T383
Test name
Test status
Simulation time	63712899 ps
CPU time	2.93 seconds
Started	Sep 24 04:58:23 AM UTC 24
Finished	Sep 24 04:58:27 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934988078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2934988078
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1738241531
Short name	T418
Test name
Test status
Simulation time	16516200237 ps
CPU time	59.12 seconds
Started	Sep 24 04:58:25 AM UTC 24
Finished	Sep 24 04:59:27 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738241531 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1738241531
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.477189495
Short name	T411
Test name
Test status
Simulation time	6741552526 ps
CPU time	46.74 seconds
Started	Sep 24 04:58:27 AM UTC 24
Finished	Sep 24 04:59:15 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477189495 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.477189495
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1588092591
Short name	T385
Test name
Test status
Simulation time	85635300 ps
CPU time	2.79 seconds
Started	Sep 24 04:58:24 AM UTC 24
Finished	Sep 24 04:58:28 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588092591 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1588092591
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.3576028144
Short name	T540
Test name
Test status
Simulation time	13164269173 ps
CPU time	301.55 seconds
Started	Sep 24 04:58:33 AM UTC 24
Finished	Sep 24 05:03:40 AM UTC 24
Peak memory	222056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576028144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3576028144
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1743466483
Short name	T489
Test name
Test status
Simulation time	1760390997 ps
CPU time	215.73 seconds
Started	Sep 24 04:58:37 AM UTC 24
Finished	Sep 24 05:02:16 AM UTC 24
Peak memory	222124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743466483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1743466483
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2774985703
Short name	T612
Test name
Test status
Simulation time	1879144938 ps
CPU time	410.45 seconds
Started	Sep 24 04:58:35 AM UTC 24
Finished	Sep 24 05:05:32 AM UTC 24
Peak memory	222228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774985703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.2774985703
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3846137314
Short name	T539
Test name
Test status
Simulation time	2116794584 ps
CPU time	291.68 seconds
Started	Sep 24 04:58:41 AM UTC 24
Finished	Sep 24 05:03:37 AM UTC 24
Peak memory	232524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846137314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3846137314
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.1711825671
Short name	T397
Test name
Test status
Simulation time	394185376 ps
CPU time	20.52 seconds
Started	Sep 24 04:58:32 AM UTC 24
Finished	Sep 24 04:58:54 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711825671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1711825671
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3090193309
Short name	T169
Test name
Test status
Simulation time	14953047906 ps
CPU time	130.27 seconds
Started	Sep 24 04:58:52 AM UTC 24
Finished	Sep 24 05:01:05 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090193309 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3090193309
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.768017584
Short name	T402
Test name
Test status
Simulation time	154402940 ps
CPU time	6.1 seconds
Started	Sep 24 04:58:56 AM UTC 24
Finished	Sep 24 04:59:03 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768017584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.768017584
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.1089792819
Short name	T6
Test name
Test status
Simulation time	555991567 ps
CPU time	16.48 seconds
Started	Sep 24 04:58:54 AM UTC 24
Finished	Sep 24 04:59:12 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089792819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1089792819
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.1330853553
Short name	T410
Test name
Test status
Simulation time	249983887 ps
CPU time	25.3 seconds
Started	Sep 24 04:58:48 AM UTC 24
Finished	Sep 24 04:59:15 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330853553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1330853553
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.1676349099
Short name	T533
Test name
Test status
Simulation time	114313081803 ps
CPU time	276.92 seconds
Started	Sep 24 04:58:49 AM UTC 24
Finished	Sep 24 05:03:31 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676349099 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1676349099
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1890299562
Short name	T439
Test name
Test status
Simulation time	5844995354 ps
CPU time	77.54 seconds
Started	Sep 24 04:58:49 AM UTC 24
Finished	Sep 24 05:00:09 AM UTC 24
Peak memory	215848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890299562 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1890299562
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.1590511384
Short name	T408
Test name
Test status
Simulation time	203463094 ps
CPU time	22.1 seconds
Started	Sep 24 04:58:48 AM UTC 24
Finished	Sep 24 04:59:12 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590511384 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1590511384
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.1526815814
Short name	T406
Test name
Test status
Simulation time	154677978 ps
CPU time	13.55 seconds
Started	Sep 24 04:58:53 AM UTC 24
Finished	Sep 24 04:59:07 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526815814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1526815814
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.2090136733
Short name	T393
Test name
Test status
Simulation time	153230870 ps
CPU time	3.97 seconds
Started	Sep 24 04:58:41 AM UTC 24
Finished	Sep 24 04:58:46 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090136733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2090136733
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3348702721
Short name	T423
Test name
Test status
Simulation time	11915857149 ps
CPU time	48.35 seconds
Started	Sep 24 04:58:45 AM UTC 24
Finished	Sep 24 04:59:35 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348702721 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3348702721
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1795657723
Short name	T417
Test name
Test status
Simulation time	3175460864 ps
CPU time	35.88 seconds
Started	Sep 24 04:58:46 AM UTC 24
Finished	Sep 24 04:59:24 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795657723 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1795657723
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1916451735
Short name	T394
Test name
Test status
Simulation time	25828582 ps
CPU time	2.81 seconds
Started	Sep 24 04:58:43 AM UTC 24
Finished	Sep 24 04:58:47 AM UTC 24
Peak memory	216016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916451735 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1916451735
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.3494877840
Short name	T195
Test name
Test status
Simulation time	1146626795 ps
CPU time	190.79 seconds
Started	Sep 24 04:58:57 AM UTC 24
Finished	Sep 24 05:02:11 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494877840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3494877840
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1732363065
Short name	T449
Test name
Test status
Simulation time	21663167483 ps
CPU time	96.51 seconds
Started	Sep 24 04:58:59 AM UTC 24
Finished	Sep 24 05:00:38 AM UTC 24
Peak memory	218152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732363065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1732363065
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.171760229
Short name	T565
Test name
Test status
Simulation time	2551928498 ps
CPU time	312.02 seconds
Started	Sep 24 04:59:00 AM UTC 24
Finished	Sep 24 05:04:17 AM UTC 24
Peak memory	232576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171760229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.171760229
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.3999443790
Short name	T420
Test name
Test status
Simulation time	128673450 ps
CPU time	30.93 seconds
Started	Sep 24 04:58:55 AM UTC 24
Finished	Sep 24 04:59:28 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999443790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3999443790
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.2907750453
Short name	T114
Test name
Test status
Simulation time	1499622306 ps
CPU time	72.69 seconds
Started	Sep 24 04:59:08 AM UTC 24
Finished	Sep 24 05:00:23 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907750453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2907750453
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2336486110
Short name	T863
Test name
Test status
Simulation time	90182172850 ps
CPU time	829.14 seconds
Started	Sep 24 04:59:08 AM UTC 24
Finished	Sep 24 05:13:08 AM UTC 24
Peak memory	220016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336486110 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2336486110
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3307857490
Short name	T419
Test name
Test status
Simulation time	591646162 ps
CPU time	12.45 seconds
Started	Sep 24 04:59:13 AM UTC 24
Finished	Sep 24 04:59:27 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307857490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3307857490
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.30967382
Short name	T433
Test name
Test status
Simulation time	1050125369 ps
CPU time	43.46 seconds
Started	Sep 24 04:59:13 AM UTC 24
Finished	Sep 24 04:59:58 AM UTC 24
Peak memory	215716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30967382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.30967382
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.732044503
Short name	T422
Test name
Test status
Simulation time	410257165 ps
CPU time	27.96 seconds
Started	Sep 24 04:59:04 AM UTC 24
Finished	Sep 24 04:59:34 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732044503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.732044503
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.573979225
Short name	T552
Test name
Test status
Simulation time	68324883782 ps
CPU time	290.25 seconds
Started	Sep 24 04:59:07 AM UTC 24
Finished	Sep 24 05:04:02 AM UTC 24
Peak memory	218152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573979225 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.573979225
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2834739311
Short name	T250
Test name
Test status
Simulation time	31071491624 ps
CPU time	333.75 seconds
Started	Sep 24 04:59:08 AM UTC 24
Finished	Sep 24 05:04:47 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834739311 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2834739311
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.2293539881
Short name	T407
Test name
Test status
Simulation time	21225377 ps
CPU time	3.84 seconds
Started	Sep 24 04:59:05 AM UTC 24
Finished	Sep 24 04:59:11 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293539881 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2293539881
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.3865362940
Short name	T415
Test name
Test status
Simulation time	166707937 ps
CPU time	11.4 seconds
Started	Sep 24 04:59:11 AM UTC 24
Finished	Sep 24 04:59:23 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865362940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3865362940
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.4093078686
Short name	T404
Test name
Test status
Simulation time	401958310 ps
CPU time	3.96 seconds
Started	Sep 24 04:59:01 AM UTC 24
Finished	Sep 24 04:59:06 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093078686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.4093078686
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3150610623
Short name	T428
Test name
Test status
Simulation time	9897569177 ps
CPU time	42.52 seconds
Started	Sep 24 04:59:04 AM UTC 24
Finished	Sep 24 04:59:49 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150610623 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3150610623
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3308831863
Short name	T64
Test name
Test status
Simulation time	3498168285 ps
CPU time	46.46 seconds
Started	Sep 24 04:59:04 AM UTC 24
Finished	Sep 24 04:59:53 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308831863 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3308831863
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3554609313
Short name	T405
Test name
Test status
Simulation time	29737314 ps
CPU time	3.33 seconds
Started	Sep 24 04:59:03 AM UTC 24
Finished	Sep 24 04:59:07 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554609313 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3554609313
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.274383055
Short name	T546
Test name
Test status
Simulation time	5870017221 ps
CPU time	271.95 seconds
Started	Sep 24 04:59:14 AM UTC 24
Finished	Sep 24 05:03:50 AM UTC 24
Peak memory	222060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274383055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.274383055
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2600182403
Short name	T504
Test name
Test status
Simulation time	38560831100 ps
CPU time	199.11 seconds
Started	Sep 24 04:59:17 AM UTC 24
Finished	Sep 24 05:02:40 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600182403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2600182403
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3649371083
Short name	T414
Test name
Test status
Simulation time	8805051 ps
CPU time	6.14 seconds
Started	Sep 24 04:59:15 AM UTC 24
Finished	Sep 24 04:59:22 AM UTC 24
Peak memory	215700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649371083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.3649371083
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2041618634
Short name	T669
Test name
Test status
Simulation time	10789783413 ps
CPU time	445.9 seconds
Started	Sep 24 04:59:17 AM UTC 24
Finished	Sep 24 05:06:49 AM UTC 24
Peak memory	232652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041618634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2041618634
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3676175313
Short name	T421
Test name
Test status
Simulation time	158529070 ps
CPU time	18.46 seconds
Started	Sep 24 04:59:13 AM UTC 24
Finished	Sep 24 04:59:33 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676175313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3676175313
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.1691141335
Short name	T438
Test name
Test status
Simulation time	807396481 ps
CPU time	42.82 seconds
Started	Sep 24 04:59:25 AM UTC 24
Finished	Sep 24 05:00:09 AM UTC 24
Peak memory	216040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691141335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1691141335
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1808237653
Short name	T171
Test name
Test status
Simulation time	21966727039 ps
CPU time	206.45 seconds
Started	Sep 24 04:59:28 AM UTC 24
Finished	Sep 24 05:02:58 AM UTC 24
Peak memory	216112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808237653 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.1808237653
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3805652334
Short name	T430
Test name
Test status
Simulation time	1815316729 ps
CPU time	17.5 seconds
Started	Sep 24 04:59:35 AM UTC 24
Finished	Sep 24 04:59:54 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805652334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3805652334
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.3014700358
Short name	T426
Test name
Test status
Simulation time	158731752 ps
CPU time	10.19 seconds
Started	Sep 24 04:59:29 AM UTC 24
Finished	Sep 24 04:59:41 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014700358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3014700358
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.3284970742
Short name	T425
Test name
Test status
Simulation time	1330759694 ps
CPU time	16.27 seconds
Started	Sep 24 04:59:23 AM UTC 24
Finished	Sep 24 04:59:41 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284970742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3284970742
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.2245037477
Short name	T574
Test name
Test status
Simulation time	70249922656 ps
CPU time	296.05 seconds
Started	Sep 24 04:59:25 AM UTC 24
Finished	Sep 24 05:04:25 AM UTC 24
Peak memory	218152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245037477 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2245037477
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2637131318
Short name	T600
Test name
Test status
Simulation time	37478526571 ps
CPU time	346.23 seconds
Started	Sep 24 04:59:25 AM UTC 24
Finished	Sep 24 05:05:16 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637131318 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2637131318
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.367516076
Short name	T429
Test name
Test status
Simulation time	244672380 ps
CPU time	25.75 seconds
Started	Sep 24 04:59:23 AM UTC 24
Finished	Sep 24 04:59:50 AM UTC 24
Peak memory	217756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367516076 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.367516076
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.43910318
Short name	T424
Test name
Test status
Simulation time	71577098 ps
CPU time	7.72 seconds
Started	Sep 24 04:59:28 AM UTC 24
Finished	Sep 24 04:59:37 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43910318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.43910318
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.4158949987
Short name	T416
Test name
Test status
Simulation time	266279326 ps
CPU time	4.79 seconds
Started	Sep 24 04:59:17 AM UTC 24
Finished	Sep 24 04:59:23 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158949987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.4158949987
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1360881283
Short name	T440
Test name
Test status
Simulation time	20458175169 ps
CPU time	55.68 seconds
Started	Sep 24 04:59:20 AM UTC 24
Finished	Sep 24 05:00:17 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360881283 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1360881283
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.108014527
Short name	T436
Test name
Test status
Simulation time	6024897623 ps
CPU time	42.61 seconds
Started	Sep 24 04:59:21 AM UTC 24
Finished	Sep 24 05:00:05 AM UTC 24
Peak memory	216084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108014527 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.108014527
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1880773672
Short name	T413
Test name
Test status
Simulation time	47144334 ps
CPU time	3.14 seconds
Started	Sep 24 04:59:18 AM UTC 24
Finished	Sep 24 04:59:22 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880773672 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1880773672
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.1868236023
Short name	T475
Test name
Test status
Simulation time	913833220 ps
CPU time	121.96 seconds
Started	Sep 24 04:59:36 AM UTC 24
Finished	Sep 24 05:01:41 AM UTC 24
Peak memory	219812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868236023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1868236023
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.991054875
Short name	T470
Test name
Test status
Simulation time	925362796 ps
CPU time	100.06 seconds
Started	Sep 24 04:59:42 AM UTC 24
Finished	Sep 24 05:01:24 AM UTC 24
Peak memory	217652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991054875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.991054875
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1239529365
Short name	T549
Test name
Test status
Simulation time	7454494124 ps
CPU time	250.97 seconds
Started	Sep 24 04:59:42 AM UTC 24
Finished	Sep 24 05:03:57 AM UTC 24
Peak memory	220272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239529365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.1239529365
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.14401182
Short name	T435
Test name
Test status
Simulation time	489408966 ps
CPU time	28.11 seconds
Started	Sep 24 04:59:34 AM UTC 24
Finished	Sep 24 05:00:03 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14401182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.14401182
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.1098383260
Short name	T458
Test name
Test status
Simulation time	628222830 ps
CPU time	51.36 seconds
Started	Sep 24 05:00:09 AM UTC 24
Finished	Sep 24 05:01:02 AM UTC 24
Peak memory	215848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098383260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1098383260
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.847630166
Short name	T579
Test name
Test status
Simulation time	28981186065 ps
CPU time	264.99 seconds
Started	Sep 24 05:00:09 AM UTC 24
Finished	Sep 24 05:04:37 AM UTC 24
Peak memory	218216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847630166 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.847630166
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2682245922
Short name	T452
Test name
Test status
Simulation time	1000298486 ps
CPU time	30.64 seconds
Started	Sep 24 05:00:10 AM UTC 24
Finished	Sep 24 05:00:42 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682245922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2682245922
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.2656052669
Short name	T460
Test name
Test status
Simulation time	1333961534 ps
CPU time	51.68 seconds
Started	Sep 24 05:00:09 AM UTC 24
Finished	Sep 24 05:01:02 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656052669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2656052669
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.1597632572
Short name	T434
Test name
Test status
Simulation time	65193166 ps
CPU time	7.1 seconds
Started	Sep 24 04:59:55 AM UTC 24
Finished	Sep 24 05:00:03 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597632572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1597632572
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.1054560857
Short name	T502
Test name
Test status
Simulation time	40561930208 ps
CPU time	156.42 seconds
Started	Sep 24 04:59:56 AM UTC 24
Finished	Sep 24 05:02:36 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054560857 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1054560857
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3212579542
Short name	T153
Test name
Test status
Simulation time	90578927284 ps
CPU time	358.77 seconds
Started	Sep 24 04:59:59 AM UTC 24
Finished	Sep 24 05:06:03 AM UTC 24
Peak memory	218152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212579542 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3212579542
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.2261510458
Short name	T437
Test name
Test status
Simulation time	99845012 ps
CPU time	11.65 seconds
Started	Sep 24 04:59:55 AM UTC 24
Finished	Sep 24 05:00:08 AM UTC 24
Peak memory	215960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261510458 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2261510458
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.591759677
Short name	T448
Test name
Test status
Simulation time	236366400 ps
CPU time	27.4 seconds
Started	Sep 24 05:00:09 AM UTC 24
Finished	Sep 24 05:00:38 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591759677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.591759677
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.3829955839
Short name	T432
Test name
Test status
Simulation time	138077259 ps
CPU time	5.53 seconds
Started	Sep 24 04:59:48 AM UTC 24
Finished	Sep 24 04:59:55 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829955839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3829955839
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2163044253
Short name	T450
Test name
Test status
Simulation time	12853298184 ps
CPU time	44.81 seconds
Started	Sep 24 04:59:51 AM UTC 24
Finished	Sep 24 05:00:38 AM UTC 24
Peak memory	215884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163044253 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2163044253
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.4146092362
Short name	T443
Test name
Test status
Simulation time	2899615998 ps
CPU time	34.56 seconds
Started	Sep 24 04:59:54 AM UTC 24
Finished	Sep 24 05:00:30 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146092362 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.4146092362
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2122524142
Short name	T431
Test name
Test status
Simulation time	117029125 ps
CPU time	3.69 seconds
Started	Sep 24 04:59:49 AM UTC 24
Finished	Sep 24 04:59:54 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122524142 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2122524142
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.3755018206
Short name	T522
Test name
Test status
Simulation time	4839073219 ps
CPU time	184.59 seconds
Started	Sep 24 05:00:10 AM UTC 24
Finished	Sep 24 05:03:18 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755018206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3755018206
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3499889772
Short name	T496
Test name
Test status
Simulation time	782295567 ps
CPU time	116.45 seconds
Started	Sep 24 05:00:25 AM UTC 24
Finished	Sep 24 05:02:24 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499889772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3499889772
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2191177183
Short name	T630
Test name
Test status
Simulation time	773059717 ps
CPU time	339.67 seconds
Started	Sep 24 05:00:18 AM UTC 24
Finished	Sep 24 05:06:04 AM UTC 24
Peak memory	222128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191177183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.2191177183
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3434560679
Short name	T692
Test name
Test status
Simulation time	6952396870 ps
CPU time	405.5 seconds
Started	Sep 24 05:00:29 AM UTC 24
Finished	Sep 24 05:07:20 AM UTC 24
Peak memory	232652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434560679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.3434560679
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.2557663311
Short name	T444
Test name
Test status
Simulation time	138526284 ps
CPU time	19.39 seconds
Started	Sep 24 05:00:09 AM UTC 24
Finished	Sep 24 05:00:30 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557663311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2557663311
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.2326719319
Short name	T453
Test name
Test status
Simulation time	83161969 ps
CPU time	8.17 seconds
Started	Sep 24 05:00:40 AM UTC 24
Finished	Sep 24 05:00:50 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326719319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2326719319
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2228552435
Short name	T868
Test name
Test status
Simulation time	166132186534 ps
CPU time	776.32 seconds
Started	Sep 24 05:00:40 AM UTC 24
Finished	Sep 24 05:13:46 AM UTC 24
Peak memory	220016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228552435 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.2228552435
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2283928531
Short name	T457
Test name
Test status
Simulation time	28003052 ps
CPU time	6.21 seconds
Started	Sep 24 05:00:52 AM UTC 24
Finished	Sep 24 05:00:59 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283928531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2283928531
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.2717301271
Short name	T466
Test name
Test status
Simulation time	188580686 ps
CPU time	19.01 seconds
Started	Sep 24 05:00:51 AM UTC 24
Finished	Sep 24 05:01:11 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717301271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2717301271
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.610991398
Short name	T400
Test name
Test status
Simulation time	450332416 ps
CPU time	13.79 seconds
Started	Sep 24 05:00:35 AM UTC 24
Finished	Sep 24 05:00:50 AM UTC 24
Peak memory	216036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610991398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.610991398
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.3026740652
Short name	T454
Test name
Test status
Simulation time	1674161012 ps
CPU time	11.27 seconds
Started	Sep 24 05:00:38 AM UTC 24
Finished	Sep 24 05:00:51 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026740652 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3026740652
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.294995529
Short name	T497
Test name
Test status
Simulation time	52425267381 ps
CPU time	104.12 seconds
Started	Sep 24 05:00:40 AM UTC 24
Finished	Sep 24 05:02:27 AM UTC 24
Peak memory	216096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294995529 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.294995529
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.1770386381
Short name	T455
Test name
Test status
Simulation time	111010742 ps
CPU time	16.41 seconds
Started	Sep 24 05:00:36 AM UTC 24
Finished	Sep 24 05:00:54 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770386381 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1770386381
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.2659547530
Short name	T459
Test name
Test status
Simulation time	1102502948 ps
CPU time	17.13 seconds
Started	Sep 24 05:00:43 AM UTC 24
Finished	Sep 24 05:01:02 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659547530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2659547530
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.4177432201
Short name	T447
Test name
Test status
Simulation time	825750532 ps
CPU time	5.19 seconds
Started	Sep 24 05:00:29 AM UTC 24
Finished	Sep 24 05:00:35 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177432201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4177432201
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3386002172
Short name	T471
Test name
Test status
Simulation time	22960196033 ps
CPU time	55.09 seconds
Started	Sep 24 05:00:30 AM UTC 24
Finished	Sep 24 05:01:27 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386002172 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3386002172
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2023984284
Short name	T462
Test name
Test status
Simulation time	3379778909 ps
CPU time	31.43 seconds
Started	Sep 24 05:00:34 AM UTC 24
Finished	Sep 24 05:01:07 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023984284 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2023984284
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3995917504
Short name	T446
Test name
Test status
Simulation time	62759731 ps
CPU time	2.64 seconds
Started	Sep 24 05:00:30 AM UTC 24
Finished	Sep 24 05:00:34 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995917504 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3995917504
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.3913277912
Short name	T467
Test name
Test status
Simulation time	600959175 ps
CPU time	15.76 seconds
Started	Sep 24 05:00:55 AM UTC 24
Finished	Sep 24 05:01:12 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913277912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3913277912
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.735369317
Short name	T487
Test name
Test status
Simulation time	2340388214 ps
CPU time	72.03 seconds
Started	Sep 24 05:01:00 AM UTC 24
Finished	Sep 24 05:02:14 AM UTC 24
Peak memory	218088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735369317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.735369317
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.451159002
Short name	T706
Test name
Test status
Simulation time	2881237241 ps
CPU time	409.94 seconds
Started	Sep 24 05:00:59 AM UTC 24
Finished	Sep 24 05:07:55 AM UTC 24
Peak memory	221992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451159002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.451159002
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.2399593249
Short name	T463
Test name
Test status
Simulation time	352989278 ps
CPU time	15.94 seconds
Started	Sep 24 05:00:51 AM UTC 24
Finished	Sep 24 05:01:08 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399593249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2399593249
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.605755982
Short name	T479
Test name
Test status
Simulation time	239374207 ps
CPU time	41.14 seconds
Started	Sep 24 05:01:09 AM UTC 24
Finished	Sep 24 05:01:52 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605755982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.605755982
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.616845846
Short name	T498
Test name
Test status
Simulation time	6350763169 ps
CPU time	75.62 seconds
Started	Sep 24 05:01:12 AM UTC 24
Finished	Sep 24 05:02:29 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616845846 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.616845846
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1841228057
Short name	T480
Test name
Test status
Simulation time	1185692742 ps
CPU time	27.17 seconds
Started	Sep 24 05:01:24 AM UTC 24
Finished	Sep 24 05:01:52 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841228057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1841228057
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.3938411190
Short name	T481
Test name
Test status
Simulation time	2001555037 ps
CPU time	35.75 seconds
Started	Sep 24 05:01:19 AM UTC 24
Finished	Sep 24 05:01:56 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938411190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3938411190
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.3429402416
Short name	T170
Test name
Test status
Simulation time	1525787001 ps
CPU time	53.5 seconds
Started	Sep 24 05:01:09 AM UTC 24
Finished	Sep 24 05:02:04 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429402416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3429402416
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.91671931
Short name	T570
Test name
Test status
Simulation time	50512161069 ps
CPU time	188.18 seconds
Started	Sep 24 05:01:09 AM UTC 24
Finished	Sep 24 05:04:21 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91671931 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.91671931
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2439699700
Short name	T474
Test name
Test status
Simulation time	2683306614 ps
CPU time	28.59 seconds
Started	Sep 24 05:01:09 AM UTC 24
Finished	Sep 24 05:01:39 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439699700 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2439699700
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.3757408900
Short name	T472
Test name
Test status
Simulation time	311717032 ps
CPU time	21.92 seconds
Started	Sep 24 05:01:09 AM UTC 24
Finished	Sep 24 05:01:32 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757408900 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3757408900
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.617967945
Short name	T469
Test name
Test status
Simulation time	80654621 ps
CPU time	9.43 seconds
Started	Sep 24 05:01:13 AM UTC 24
Finished	Sep 24 05:01:23 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617967945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.617967945
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.3313758181
Short name	T65
Test name
Test status
Simulation time	33353664 ps
CPU time	3.99 seconds
Started	Sep 24 05:01:03 AM UTC 24
Finished	Sep 24 05:01:08 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313758181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3313758181
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1538459696
Short name	T483
Test name
Test status
Simulation time	12388262086 ps
CPU time	56.23 seconds
Started	Sep 24 05:01:05 AM UTC 24
Finished	Sep 24 05:02:02 AM UTC 24
Peak memory	216080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538459696 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1538459696
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.296938477
Short name	T484
Test name
Test status
Simulation time	7805866649 ps
CPU time	57.79 seconds
Started	Sep 24 05:01:06 AM UTC 24
Finished	Sep 24 05:02:06 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296938477 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.296938477
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.4041063375
Short name	T465
Test name
Test status
Simulation time	80188061 ps
CPU time	4.17 seconds
Started	Sep 24 05:01:03 AM UTC 24
Finished	Sep 24 05:01:08 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041063375 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.4041063375
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.1069046897
Short name	T500
Test name
Test status
Simulation time	1886354588 ps
CPU time	63.49 seconds
Started	Sep 24 05:01:25 AM UTC 24
Finished	Sep 24 05:02:30 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069046897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1069046897
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1709195380
Short name	T510
Test name
Test status
Simulation time	3543915118 ps
CPU time	75.3 seconds
Started	Sep 24 05:01:33 AM UTC 24
Finished	Sep 24 05:02:50 AM UTC 24
Peak memory	217900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709195380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1709195380
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3686802570
Short name	T41
Test name
Test status
Simulation time	209798226 ps
CPU time	102.31 seconds
Started	Sep 24 05:01:28 AM UTC 24
Finished	Sep 24 05:03:13 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686802570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3686802570
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.3760786975
Short name	T473
Test name
Test status
Simulation time	297551311 ps
CPU time	12.84 seconds
Started	Sep 24 05:01:23 AM UTC 24
Finished	Sep 24 05:01:37 AM UTC 24
Peak memory	218016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760786975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3760786975
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.4064137882
Short name	T133
Test name
Test status
Simulation time	633383641 ps
CPU time	26.63 seconds
Started	Sep 24 05:01:57 AM UTC 24
Finished	Sep 24 05:02:25 AM UTC 24
Peak memory	217824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064137882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.4064137882
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1570920311
Short name	T232
Test name
Test status
Simulation time	75496467561 ps
CPU time	740.27 seconds
Started	Sep 24 05:01:58 AM UTC 24
Finished	Sep 24 05:14:27 AM UTC 24
Peak memory	217968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570920311 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.1570920311
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2600225516
Short name	T506
Test name
Test status
Simulation time	2125172690 ps
CPU time	40.23 seconds
Started	Sep 24 05:02:06 AM UTC 24
Finished	Sep 24 05:02:48 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600225516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2600225516
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.2939173120
Short name	T492
Test name
Test status
Simulation time	512393331 ps
CPU time	14.88 seconds
Started	Sep 24 05:02:04 AM UTC 24
Finished	Sep 24 05:02:20 AM UTC 24
Peak memory	215960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939173120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2939173120
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.214498220
Short name	T482
Test name
Test status
Simulation time	220761905 ps
CPU time	9.69 seconds
Started	Sep 24 05:01:46 AM UTC 24
Finished	Sep 24 05:01:57 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214498220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.214498220
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.1226127100
Short name	T562
Test name
Test status
Simulation time	32642587601 ps
CPU time	137.78 seconds
Started	Sep 24 05:01:53 AM UTC 24
Finished	Sep 24 05:04:13 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226127100 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1226127100
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3146325897
Short name	T702
Test name
Test status
Simulation time	33112101749 ps
CPU time	349.48 seconds
Started	Sep 24 05:01:54 AM UTC 24
Finished	Sep 24 05:07:48 AM UTC 24
Peak memory	215848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146325897 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3146325897
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.2895466250
Short name	T486
Test name
Test status
Simulation time	317574683 ps
CPU time	23.94 seconds
Started	Sep 24 05:01:47 AM UTC 24
Finished	Sep 24 05:02:13 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895466250 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2895466250
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.3622304920
Short name	T494
Test name
Test status
Simulation time	1223261493 ps
CPU time	17.46 seconds
Started	Sep 24 05:02:04 AM UTC 24
Finished	Sep 24 05:02:22 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622304920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3622304920
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.2122048820
Short name	T476
Test name
Test status
Simulation time	597417915 ps
CPU time	4.44 seconds
Started	Sep 24 05:01:38 AM UTC 24
Finished	Sep 24 05:01:44 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122048820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2122048820
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1496378983
Short name	T488
Test name
Test status
Simulation time	8870207627 ps
CPU time	31.51 seconds
Started	Sep 24 05:01:42 AM UTC 24
Finished	Sep 24 05:02:15 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496378983 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1496378983
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3004669145
Short name	T507
Test name
Test status
Simulation time	9905778514 ps
CPU time	61.79 seconds
Started	Sep 24 05:01:45 AM UTC 24
Finished	Sep 24 05:02:48 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004669145 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3004669145
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1554984317
Short name	T477
Test name
Test status
Simulation time	32225875 ps
CPU time	3.36 seconds
Started	Sep 24 05:01:40 AM UTC 24
Finished	Sep 24 05:01:45 AM UTC 24
Peak memory	216016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554984317 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1554984317
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.1571277633
Short name	T244
Test name
Test status
Simulation time	3885917519 ps
CPU time	68.24 seconds
Started	Sep 24 05:02:08 AM UTC 24
Finished	Sep 24 05:03:18 AM UTC 24
Peak memory	218152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571277633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1571277633
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.853523418
Short name	T537
Test name
Test status
Simulation time	2320815738 ps
CPU time	80.21 seconds
Started	Sep 24 05:02:12 AM UTC 24
Finished	Sep 24 05:03:34 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853523418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.853523418
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.359690126
Short name	T722
Test name
Test status
Simulation time	1953642412 ps
CPU time	358.57 seconds
Started	Sep 24 05:02:12 AM UTC 24
Finished	Sep 24 05:08:15 AM UTC 24
Peak memory	232520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359690126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.359690126
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.629610025
Short name	T46
Test name
Test status
Simulation time	233351733 ps
CPU time	104.72 seconds
Started	Sep 24 05:02:14 AM UTC 24
Finished	Sep 24 05:04:01 AM UTC 24
Peak memory	219820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629610025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.629610025
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.2049008290
Short name	T485
Test name
Test status
Simulation time	24526743 ps
CPU time	4.33 seconds
Started	Sep 24 05:02:05 AM UTC 24
Finished	Sep 24 05:02:10 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049008290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2049008290
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.1735150003
Short name	T499
Test name
Test status
Simulation time	64617643 ps
CPU time	5.33 seconds
Started	Sep 24 05:02:23 AM UTC 24
Finished	Sep 24 05:02:29 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735150003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1735150003
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2355216093
Short name	T831
Test name
Test status
Simulation time	105320817838 ps
CPU time	570.08 seconds
Started	Sep 24 05:02:25 AM UTC 24
Finished	Sep 24 05:12:02 AM UTC 24
Peak memory	220012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355216093 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2355216093
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3382161250
Short name	T511
Test name
Test status
Simulation time	1735662226 ps
CPU time	22.84 seconds
Started	Sep 24 05:02:27 AM UTC 24
Finished	Sep 24 05:02:52 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382161250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3382161250
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.2816034080
Short name	T516
Test name
Test status
Simulation time	2973837516 ps
CPU time	38.71 seconds
Started	Sep 24 05:02:25 AM UTC 24
Finished	Sep 24 05:03:05 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816034080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2816034080
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.1959463701
Short name	T520
Test name
Test status
Simulation time	1474182547 ps
CPU time	53.66 seconds
Started	Sep 24 05:02:20 AM UTC 24
Finished	Sep 24 05:03:16 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959463701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1959463701
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.507960350
Short name	T556
Test name
Test status
Simulation time	11477069481 ps
CPU time	101.21 seconds
Started	Sep 24 05:02:22 AM UTC 24
Finished	Sep 24 05:04:05 AM UTC 24
Peak memory	215736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507960350 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.507960350
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2560549127
Short name	T548
Test name
Test status
Simulation time	8708393002 ps
CPU time	90.3 seconds
Started	Sep 24 05:02:23 AM UTC 24
Finished	Sep 24 05:03:55 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560549127 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2560549127
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.3914747537
Short name	T508
Test name
Test status
Simulation time	304219589 ps
CPU time	25.91 seconds
Started	Sep 24 05:02:22 AM UTC 24
Finished	Sep 24 05:02:49 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914747537 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3914747537
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.236021336
Short name	T503
Test name
Test status
Simulation time	395494053 ps
CPU time	10.31 seconds
Started	Sep 24 05:02:25 AM UTC 24
Finished	Sep 24 05:02:36 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236021336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.236021336
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.3940429870
Short name	T493
Test name
Test status
Simulation time	254418314 ps
CPU time	5.86 seconds
Started	Sep 24 05:02:15 AM UTC 24
Finished	Sep 24 05:02:22 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940429870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3940429870
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1391457854
Short name	T515
Test name
Test status
Simulation time	12067183682 ps
CPU time	45.94 seconds
Started	Sep 24 05:02:17 AM UTC 24
Finished	Sep 24 05:03:04 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391457854 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1391457854
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2380549227
Short name	T509
Test name
Test status
Simulation time	7911402952 ps
CPU time	31.48 seconds
Started	Sep 24 05:02:17 AM UTC 24
Finished	Sep 24 05:02:50 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380549227 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2380549227
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.99539993
Short name	T491
Test name
Test status
Simulation time	23220136 ps
CPU time	3.26 seconds
Started	Sep 24 05:02:15 AM UTC 24
Finished	Sep 24 05:02:20 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99539993 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.99539993
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.1208007971
Short name	T610
Test name
Test status
Simulation time	16882655255 ps
CPU time	176.48 seconds
Started	Sep 24 05:02:30 AM UTC 24
Finished	Sep 24 05:05:29 AM UTC 24
Peak memory	220264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208007971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1208007971
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.762363752
Short name	T512
Test name
Test status
Simulation time	966967369 ps
CPU time	26.37 seconds
Started	Sep 24 05:02:31 AM UTC 24
Finished	Sep 24 05:02:59 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762363752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.762363752
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2672869287
Short name	T745
Test name
Test status
Simulation time	1114527551 ps
CPU time	384.4 seconds
Started	Sep 24 05:02:30 AM UTC 24
Finished	Sep 24 05:09:00 AM UTC 24
Peak memory	222064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672869287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.2672869287
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.4113362015
Short name	T563
Test name
Test status
Simulation time	398977101 ps
CPU time	97.23 seconds
Started	Sep 24 05:02:34 AM UTC 24
Finished	Sep 24 05:04:14 AM UTC 24
Peak memory	219816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113362015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.4113362015
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.663279638
Short name	T501
Test name
Test status
Simulation time	27115286 ps
CPU time	6.11 seconds
Started	Sep 24 05:02:26 AM UTC 24
Finished	Sep 24 05:02:33 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663279638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.663279638
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.2924953949
Short name	T245
Test name
Test status
Simulation time	803217522 ps
CPU time	33.59 seconds
Started	Sep 24 05:02:51 AM UTC 24
Finished	Sep 24 05:03:26 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924953949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2924953949
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2769034794
Short name	T883
Test name
Test status
Simulation time	102906340679 ps
CPU time	717.4 seconds
Started	Sep 24 05:02:51 AM UTC 24
Finished	Sep 24 05:14:57 AM UTC 24
Peak memory	220016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769034794 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.2769034794
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2138187217
Short name	T517
Test name
Test status
Simulation time	108726267 ps
CPU time	11.09 seconds
Started	Sep 24 05:03:00 AM UTC 24
Finished	Sep 24 05:03:12 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138187217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2138187217
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.2883498541
Short name	T521
Test name
Test status
Simulation time	209547740 ps
CPU time	19.28 seconds
Started	Sep 24 05:02:56 AM UTC 24
Finished	Sep 24 05:03:16 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883498541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2883498541
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.4236286634
Short name	T518
Test name
Test status
Simulation time	962847879 ps
CPU time	29.23 seconds
Started	Sep 24 05:02:43 AM UTC 24
Finished	Sep 24 05:03:13 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236286634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.4236286634
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.4116981467
Short name	T619
Test name
Test status
Simulation time	39461679696 ps
CPU time	171.27 seconds
Started	Sep 24 05:02:49 AM UTC 24
Finished	Sep 24 05:05:44 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116981467 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.4116981467
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3738259543
Short name	T585
Test name
Test status
Simulation time	13262462062 ps
CPU time	118.25 seconds
Started	Sep 24 05:02:49 AM UTC 24
Finished	Sep 24 05:04:50 AM UTC 24
Peak memory	216108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738259543 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3738259543
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.1068001872
Short name	T527
Test name
Test status
Simulation time	873740113 ps
CPU time	29.55 seconds
Started	Sep 24 05:02:49 AM UTC 24
Finished	Sep 24 05:03:20 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068001872 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1068001872
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.2990457264
Short name	T529
Test name
Test status
Simulation time	878270928 ps
CPU time	31.63 seconds
Started	Sep 24 05:02:52 AM UTC 24
Finished	Sep 24 05:03:25 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990457264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2990457264
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.4276506397
Short name	T505
Test name
Test status
Simulation time	90752790 ps
CPU time	3.52 seconds
Started	Sep 24 05:02:37 AM UTC 24
Finished	Sep 24 05:02:41 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276506397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4276506397
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.885360469
Short name	T519
Test name
Test status
Simulation time	4752136382 ps
CPU time	32.38 seconds
Started	Sep 24 05:02:41 AM UTC 24
Finished	Sep 24 05:03:15 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885360469 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.885360469
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1861515774
Short name	T528
Test name
Test status
Simulation time	9201106579 ps
CPU time	38.14 seconds
Started	Sep 24 05:02:41 AM UTC 24
Finished	Sep 24 05:03:21 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861515774 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1861515774
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1839628198
Short name	T66
Test name
Test status
Simulation time	29199465 ps
CPU time	2.74 seconds
Started	Sep 24 05:02:37 AM UTC 24
Finished	Sep 24 05:02:41 AM UTC 24
Peak memory	215692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839628198 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1839628198
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.1315206598
Short name	T526
Test name
Test status
Simulation time	224501362 ps
CPU time	16.49 seconds
Started	Sep 24 05:03:02 AM UTC 24
Finished	Sep 24 05:03:20 AM UTC 24
Peak memory	218088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315206598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1315206598
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1545840041
Short name	T627
Test name
Test status
Simulation time	12368184595 ps
CPU time	164.47 seconds
Started	Sep 24 05:03:07 AM UTC 24
Finished	Sep 24 05:05:54 AM UTC 24
Peak memory	220008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545840041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1545840041
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.264549131
Short name	T590
Test name
Test status
Simulation time	370347486 ps
CPU time	106.54 seconds
Started	Sep 24 05:03:05 AM UTC 24
Finished	Sep 24 05:04:54 AM UTC 24
Peak memory	220068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264549131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.264549131
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.2910285004
Short name	T156
Test name
Test status
Simulation time	1535767749 ps
CPU time	20.08 seconds
Started	Sep 24 05:02:59 AM UTC 24
Finished	Sep 24 05:03:20 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910285004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2910285004
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.3939311201
Short name	T77
Test name
Test status
Simulation time	118647869 ps
CPU time	10.14 seconds
Started	Sep 24 04:42:47 AM UTC 24
Finished	Sep 24 04:42:58 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939311201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3939311201
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2958386435
Short name	T256
Test name
Test status
Simulation time	9525193564 ps
CPU time	109.47 seconds
Started	Sep 24 04:42:53 AM UTC 24
Finished	Sep 24 04:44:45 AM UTC 24
Peak memory	215736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958386435 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.2958386435
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2073645422
Short name	T78
Test name
Test status
Simulation time	71228725 ps
CPU time	4.44 seconds
Started	Sep 24 04:42:58 AM UTC 24
Finished	Sep 24 04:43:04 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073645422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2073645422
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.275468884
Short name	T79
Test name
Test status
Simulation time	143997497 ps
CPU time	8.28 seconds
Started	Sep 24 04:42:55 AM UTC 24
Finished	Sep 24 04:43:04 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275468884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.275468884
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.3704942529
Short name	T75
Test name
Test status
Simulation time	252292874 ps
CPU time	23.25 seconds
Started	Sep 24 04:42:29 AM UTC 24
Finished	Sep 24 04:42:54 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704942529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3704942529
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.3073103382
Short name	T190
Test name
Test status
Simulation time	64869943572 ps
CPU time	216.33 seconds
Started	Sep 24 04:42:42 AM UTC 24
Finished	Sep 24 04:46:22 AM UTC 24
Peak memory	217944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073103382 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3073103382
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2350674930
Short name	T208
Test name
Test status
Simulation time	109760961066 ps
CPU time	296.64 seconds
Started	Sep 24 04:42:42 AM UTC 24
Finished	Sep 24 04:47:43 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350674930 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2350674930
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.1357852866
Short name	T74
Test name
Test status
Simulation time	115546671 ps
CPU time	12.94 seconds
Started	Sep 24 04:42:37 AM UTC 24
Finished	Sep 24 04:42:52 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357852866 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1357852866
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.942206209
Short name	T76
Test name
Test status
Simulation time	28303183 ps
CPU time	3.26 seconds
Started	Sep 24 04:42:53 AM UTC 24
Finished	Sep 24 04:42:57 AM UTC 24
Peak memory	215660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942206209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.942206209
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.193285408
Short name	T160
Test name
Test status
Simulation time	142636634 ps
CPU time	3.61 seconds
Started	Sep 24 04:42:23 AM UTC 24
Finished	Sep 24 04:42:28 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193285408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.193285408
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1450976348
Short name	T117
Test name
Test status
Simulation time	21564761716 ps
CPU time	62.67 seconds
Started	Sep 24 04:42:27 AM UTC 24
Finished	Sep 24 04:43:32 AM UTC 24
Peak memory	216148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450976348 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1450976348
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2060165162
Short name	T217
Test name
Test status
Simulation time	7003873742 ps
CPU time	38.33 seconds
Started	Sep 24 04:42:28 AM UTC 24
Finished	Sep 24 04:43:08 AM UTC 24
Peak memory	215896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060165162 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2060165162
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1291436151
Short name	T161
Test name
Test status
Simulation time	28279759 ps
CPU time	2.99 seconds
Started	Sep 24 04:42:24 AM UTC 24
Finished	Sep 24 04:42:28 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291436151 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1291436151
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.3996602324
Short name	T200
Test name
Test status
Simulation time	2529703952 ps
CPU time	140.71 seconds
Started	Sep 24 04:42:59 AM UTC 24
Finished	Sep 24 04:45:23 AM UTC 24
Peak memory	219940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996602324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3996602324
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.544547710
Short name	T228
Test name
Test status
Simulation time	18552812037 ps
CPU time	119.07 seconds
Started	Sep 24 04:43:05 AM UTC 24
Finished	Sep 24 04:45:07 AM UTC 24
Peak memory	220008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544547710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.544547710
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.4158126361
Short name	T188
Test name
Test status
Simulation time	1354434637 ps
CPU time	183.43 seconds
Started	Sep 24 04:43:04 AM UTC 24
Finished	Sep 24 04:46:11 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158126361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.4158126361
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1671351273
Short name	T122
Test name
Test status
Simulation time	121163667 ps
CPU time	56.72 seconds
Started	Sep 24 04:43:05 AM UTC 24
Finished	Sep 24 04:44:04 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671351273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.1671351273
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.1197686317
Short name	T116
Test name
Test status
Simulation time	283109988 ps
CPU time	25.87 seconds
Started	Sep 24 04:42:56 AM UTC 24
Finished	Sep 24 04:43:23 AM UTC 24
Peak memory	217760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197686317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1197686317
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.4293692273
Short name	T555
Test name
Test status
Simulation time	919167938 ps
CPU time	42.87 seconds
Started	Sep 24 05:03:20 AM UTC 24
Finished	Sep 24 05:04:05 AM UTC 24
Peak memory	217772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293692273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.4293692273
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2541282782
Short name	T898
Test name
Test status
Simulation time	340447258116 ps
CPU time	835.11 seconds
Started	Sep 24 05:03:22 AM UTC 24
Finished	Sep 24 05:17:27 AM UTC 24
Peak memory	218160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541282782 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.2541282782
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1161377520
Short name	T536
Test name
Test status
Simulation time	451173829 ps
CPU time	9.61 seconds
Started	Sep 24 05:03:22 AM UTC 24
Finished	Sep 24 05:03:33 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161377520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.1161377520
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.1661264532
Short name	T550
Test name
Test status
Simulation time	1622149857 ps
CPU time	35.92 seconds
Started	Sep 24 05:03:22 AM UTC 24
Finished	Sep 24 05:04:00 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661264532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1661264532
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.3987554773
Short name	T532
Test name
Test status
Simulation time	156171402 ps
CPU time	8.59 seconds
Started	Sep 24 05:03:17 AM UTC 24
Finished	Sep 24 05:03:27 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987554773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3987554773
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.2659119043
Short name	T67
Test name
Test status
Simulation time	13135895509 ps
CPU time	86.74 seconds
Started	Sep 24 05:03:20 AM UTC 24
Finished	Sep 24 05:04:49 AM UTC 24
Peak memory	215812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659119043 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2659119043
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1317530954
Short name	T705
Test name
Test status
Simulation time	27634684618 ps
CPU time	265.16 seconds
Started	Sep 24 05:03:20 AM UTC 24
Finished	Sep 24 05:07:49 AM UTC 24
Peak memory	215852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317530954 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1317530954
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.3693615855
Short name	T530
Test name
Test status
Simulation time	98991824 ps
CPU time	7.5 seconds
Started	Sep 24 05:03:17 AM UTC 24
Finished	Sep 24 05:03:26 AM UTC 24
Peak memory	215900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693615855 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3693615855
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.1097809060
Short name	T535
Test name
Test status
Simulation time	436324229 ps
CPU time	8.86 seconds
Started	Sep 24 05:03:22 AM UTC 24
Finished	Sep 24 05:03:32 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097809060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1097809060
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.2041243237
Short name	T524
Test name
Test status
Simulation time	132499301 ps
CPU time	4.95 seconds
Started	Sep 24 05:03:13 AM UTC 24
Finished	Sep 24 05:03:19 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041243237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2041243237
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2361973978
Short name	T561
Test name
Test status
Simulation time	30856792198 ps
CPU time	55.69 seconds
Started	Sep 24 05:03:15 AM UTC 24
Finished	Sep 24 05:04:12 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361973978 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2361973978
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1330787323
Short name	T558
Test name
Test status
Simulation time	7177179763 ps
CPU time	50.2 seconds
Started	Sep 24 05:03:17 AM UTC 24
Finished	Sep 24 05:04:09 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330787323 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1330787323
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1851943808
Short name	T525
Test name
Test status
Simulation time	26578147 ps
CPU time	3.31 seconds
Started	Sep 24 05:03:15 AM UTC 24
Finished	Sep 24 05:03:19 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851943808 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1851943808
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.2303371771
Short name	T564
Test name
Test status
Simulation time	393846642 ps
CPU time	51.58 seconds
Started	Sep 24 05:03:24 AM UTC 24
Finished	Sep 24 05:04:17 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303371771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2303371771
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2524333590
Short name	T571
Test name
Test status
Simulation time	10571991202 ps
CPU time	54.07 seconds
Started	Sep 24 05:03:26 AM UTC 24
Finished	Sep 24 05:04:23 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524333590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2524333590
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1284690303
Short name	T137
Test name
Test status
Simulation time	321022743 ps
CPU time	116.46 seconds
Started	Sep 24 05:03:26 AM UTC 24
Finished	Sep 24 05:05:25 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284690303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.1284690303
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.1131693886
Short name	T545
Test name
Test status
Simulation time	227904553 ps
CPU time	22.93 seconds
Started	Sep 24 05:03:22 AM UTC 24
Finished	Sep 24 05:03:47 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131693886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1131693886
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.3953571998
Short name	T557
Test name
Test status
Simulation time	432729612 ps
CPU time	27.91 seconds
Started	Sep 24 05:03:36 AM UTC 24
Finished	Sep 24 05:04:05 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953571998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3953571998
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3447324644
Short name	T872
Test name
Test status
Simulation time	116698331704 ps
CPU time	625.76 seconds
Started	Sep 24 05:03:39 AM UTC 24
Finished	Sep 24 05:14:12 AM UTC 24
Peak memory	217968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447324644 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.3447324644
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3963620845
Short name	T559
Test name
Test status
Simulation time	1313714091 ps
CPU time	19.97 seconds
Started	Sep 24 05:03:47 AM UTC 24
Finished	Sep 24 05:04:09 AM UTC 24
Peak memory	216008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963620845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3963620845
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.1359634410
Short name	T567
Test name
Test status
Simulation time	1641434044 ps
CPU time	32.81 seconds
Started	Sep 24 05:03:43 AM UTC 24
Finished	Sep 24 05:04:18 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359634410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1359634410
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.1828897770
Short name	T544
Test name
Test status
Simulation time	315018200 ps
CPU time	11.24 seconds
Started	Sep 24 05:03:33 AM UTC 24
Finished	Sep 24 05:03:46 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828897770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1828897770
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.398753363
Short name	T665
Test name
Test status
Simulation time	25878473193 ps
CPU time	189.82 seconds
Started	Sep 24 05:03:35 AM UTC 24
Finished	Sep 24 05:06:47 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398753363 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.398753363
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1445578264
Short name	T675
Test name
Test status
Simulation time	33221813666 ps
CPU time	199.61 seconds
Started	Sep 24 05:03:36 AM UTC 24
Finished	Sep 24 05:06:59 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445578264 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1445578264
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.691230592
Short name	T543
Test name
Test status
Simulation time	58501001 ps
CPU time	9.61 seconds
Started	Sep 24 05:03:35 AM UTC 24
Finished	Sep 24 05:03:45 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691230592 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.691230592
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.2534562543
Short name	T566
Test name
Test status
Simulation time	7443550021 ps
CPU time	34.98 seconds
Started	Sep 24 05:03:41 AM UTC 24
Finished	Sep 24 05:04:18 AM UTC 24
Peak memory	215840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534562543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2534562543
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.1784603253
Short name	T538
Test name
Test status
Simulation time	217704696 ps
CPU time	5.06 seconds
Started	Sep 24 05:03:28 AM UTC 24
Finished	Sep 24 05:03:34 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784603253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1784603253
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2821615558
Short name	T573
Test name
Test status
Simulation time	15133375058 ps
CPU time	51.43 seconds
Started	Sep 24 05:03:31 AM UTC 24
Finished	Sep 24 05:04:25 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821615558 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2821615558
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2061582341
Short name	T553
Test name
Test status
Simulation time	2806745585 ps
CPU time	27.31 seconds
Started	Sep 24 05:03:33 AM UTC 24
Finished	Sep 24 05:04:02 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061582341 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2061582341
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.523296280
Short name	T534
Test name
Test status
Simulation time	38058964 ps
CPU time	2.77 seconds
Started	Sep 24 05:03:28 AM UTC 24
Finished	Sep 24 05:03:32 AM UTC 24
Peak memory	215948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523296280 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.523296280
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.3507519933
Short name	T547
Test name
Test status
Simulation time	118865791 ps
CPU time	5.75 seconds
Started	Sep 24 05:03:47 AM UTC 24
Finished	Sep 24 05:03:54 AM UTC 24
Peak memory	217792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507519933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3507519933
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3000442948
Short name	T643
Test name
Test status
Simulation time	3359363475 ps
CPU time	143.35 seconds
Started	Sep 24 05:03:51 AM UTC 24
Finished	Sep 24 05:06:17 AM UTC 24
Peak memory	217900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000442948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3000442948
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.750972175
Short name	T651
Test name
Test status
Simulation time	320841558 ps
CPU time	157.68 seconds
Started	Sep 24 05:03:49 AM UTC 24
Finished	Sep 24 05:06:29 AM UTC 24
Peak memory	220072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750972175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.750972175
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3797336566
Short name	T601
Test name
Test status
Simulation time	632834651 ps
CPU time	80.77 seconds
Started	Sep 24 05:03:53 AM UTC 24
Finished	Sep 24 05:05:16 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797336566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.3797336566
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.48945378
Short name	T196
Test name
Test status
Simulation time	3723203104 ps
CPU time	27.31 seconds
Started	Sep 24 05:03:45 AM UTC 24
Finished	Sep 24 05:04:14 AM UTC 24
Peak memory	218080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48945378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.48945378
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.1824244859
Short name	T157
Test name
Test status
Simulation time	162405377 ps
CPU time	14.59 seconds
Started	Sep 24 05:04:03 AM UTC 24
Finished	Sep 24 05:04:19 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824244859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1824244859
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2052498238
Short name	T762
Test name
Test status
Simulation time	42514350732 ps
CPU time	324.67 seconds
Started	Sep 24 05:04:06 AM UTC 24
Finished	Sep 24 05:09:35 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052498238 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.2052498238
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2889332821
Short name	T568
Test name
Test status
Simulation time	68247324 ps
CPU time	8.75 seconds
Started	Sep 24 05:04:10 AM UTC 24
Finished	Sep 24 05:04:20 AM UTC 24
Peak memory	216044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889332821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2889332821
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.3482141473
Short name	T577
Test name
Test status
Simulation time	504194224 ps
CPU time	21.33 seconds
Started	Sep 24 05:04:06 AM UTC 24
Finished	Sep 24 05:04:29 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482141473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3482141473
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.531038753
Short name	T575
Test name
Test status
Simulation time	1031889985 ps
CPU time	21.26 seconds
Started	Sep 24 05:04:03 AM UTC 24
Finished	Sep 24 05:04:25 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531038753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.531038753
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.2216747973
Short name	T667
Test name
Test status
Simulation time	27973922705 ps
CPU time	163.55 seconds
Started	Sep 24 05:04:03 AM UTC 24
Finished	Sep 24 05:06:49 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216747973 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2216747973
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3924908868
Short name	T631
Test name
Test status
Simulation time	15236249916 ps
CPU time	118.38 seconds
Started	Sep 24 05:04:03 AM UTC 24
Finished	Sep 24 05:06:04 AM UTC 24
Peak memory	216040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924908868 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3924908868
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.1981027017
Short name	T560
Test name
Test status
Simulation time	33234909 ps
CPU time	6.63 seconds
Started	Sep 24 05:04:03 AM UTC 24
Finished	Sep 24 05:04:11 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981027017 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1981027017
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.1036118066
Short name	T576
Test name
Test status
Simulation time	187256364 ps
CPU time	19.11 seconds
Started	Sep 24 05:04:06 AM UTC 24
Finished	Sep 24 05:04:26 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036118066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1036118066
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.3121513816
Short name	T554
Test name
Test status
Simulation time	344310118 ps
CPU time	5.15 seconds
Started	Sep 24 05:03:56 AM UTC 24
Finished	Sep 24 05:04:02 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121513816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3121513816
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1818742496
Short name	T586
Test name
Test status
Simulation time	20817344013 ps
CPU time	51.89 seconds
Started	Sep 24 05:03:59 AM UTC 24
Finished	Sep 24 05:04:52 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818742496 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1818742496
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2027388115
Short name	T578
Test name
Test status
Simulation time	5452965980 ps
CPU time	27.72 seconds
Started	Sep 24 05:04:01 AM UTC 24
Finished	Sep 24 05:04:30 AM UTC 24
Peak memory	216144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027388115 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2027388115
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3791101555
Short name	T551
Test name
Test status
Simulation time	65923222 ps
CPU time	3.36 seconds
Started	Sep 24 05:03:57 AM UTC 24
Finished	Sep 24 05:04:02 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791101555 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3791101555
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.3860940135
Short name	T138
Test name
Test status
Simulation time	10073560304 ps
CPU time	125.29 seconds
Started	Sep 24 05:04:13 AM UTC 24
Finished	Sep 24 05:06:21 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860940135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3860940135
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.591386281
Short name	T652
Test name
Test status
Simulation time	5241588005 ps
CPU time	133.25 seconds
Started	Sep 24 05:04:15 AM UTC 24
Finished	Sep 24 05:06:31 AM UTC 24
Peak memory	220204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591386281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.591386281
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1043608135
Short name	T662
Test name
Test status
Simulation time	1318795976 ps
CPU time	147.44 seconds
Started	Sep 24 05:04:15 AM UTC 24
Finished	Sep 24 05:06:45 AM UTC 24
Peak memory	219816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043608135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.1043608135
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3543216098
Short name	T661
Test name
Test status
Simulation time	3923892830 ps
CPU time	146.03 seconds
Started	Sep 24 05:04:15 AM UTC 24
Finished	Sep 24 05:06:44 AM UTC 24
Peak memory	221932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543216098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.3543216098
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.4125430714
Short name	T580
Test name
Test status
Simulation time	776308696 ps
CPU time	28.7 seconds
Started	Sep 24 05:04:10 AM UTC 24
Finished	Sep 24 05:04:40 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125430714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.4125430714
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.3414380737
Short name	T603
Test name
Test status
Simulation time	539350425 ps
CPU time	52.63 seconds
Started	Sep 24 05:04:25 AM UTC 24
Finished	Sep 24 05:05:20 AM UTC 24
Peak memory	218024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414380737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3414380737
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.813212619
Short name	T894
Test name
Test status
Simulation time	216924042232 ps
CPU time	739.05 seconds
Started	Sep 24 05:04:25 AM UTC 24
Finished	Sep 24 05:16:53 AM UTC 24
Peak memory	220008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813212619 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.813212619
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1096997030
Short name	T589
Test name
Test status
Simulation time	720322121 ps
CPU time	24.87 seconds
Started	Sep 24 05:04:27 AM UTC 24
Finished	Sep 24 05:04:53 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096997030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1096997030
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.436898614
Short name	T582
Test name
Test status
Simulation time	340585491 ps
CPU time	16.17 seconds
Started	Sep 24 05:04:27 AM UTC 24
Finished	Sep 24 05:04:44 AM UTC 24
Peak memory	215704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436898614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.436898614
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.1707907593
Short name	T587
Test name
Test status
Simulation time	1415195439 ps
CPU time	31.98 seconds
Started	Sep 24 05:04:19 AM UTC 24
Finished	Sep 24 05:04:53 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707907593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1707907593
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.973110356
Short name	T645
Test name
Test status
Simulation time	27762013664 ps
CPU time	113.02 seconds
Started	Sep 24 05:04:22 AM UTC 24
Finished	Sep 24 05:06:17 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973110356 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.973110356
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.938573210
Short name	T592
Test name
Test status
Simulation time	4640576200 ps
CPU time	34.72 seconds
Started	Sep 24 05:04:22 AM UTC 24
Finished	Sep 24 05:04:58 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938573210 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.938573210
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.2450853624
Short name	T591
Test name
Test status
Simulation time	776059064 ps
CPU time	33.3 seconds
Started	Sep 24 05:04:22 AM UTC 24
Finished	Sep 24 05:04:57 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450853624 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2450853624
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.2943401103
Short name	T595
Test name
Test status
Simulation time	1929935306 ps
CPU time	38.95 seconds
Started	Sep 24 05:04:25 AM UTC 24
Finished	Sep 24 05:05:06 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943401103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2943401103
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.2088175237
Short name	T569
Test name
Test status
Simulation time	147125920 ps
CPU time	4.44 seconds
Started	Sep 24 05:04:15 AM UTC 24
Finished	Sep 24 05:04:20 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088175237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2088175237
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.182884204
Short name	T605
Test name
Test status
Simulation time	5428704288 ps
CPU time	62.79 seconds
Started	Sep 24 05:04:19 AM UTC 24
Finished	Sep 24 05:05:24 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182884204 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.182884204
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.836167809
Short name	T246
Test name
Test status
Simulation time	8111739054 ps
CPU time	37.79 seconds
Started	Sep 24 05:04:19 AM UTC 24
Finished	Sep 24 05:04:59 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836167809 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.836167809
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3610928781
Short name	T572
Test name
Test status
Simulation time	41938963 ps
CPU time	3.4 seconds
Started	Sep 24 05:04:19 AM UTC 24
Finished	Sep 24 05:04:24 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610928781 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3610928781
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.3282437775
Short name	T685
Test name
Test status
Simulation time	9328307499 ps
CPU time	160.12 seconds
Started	Sep 24 05:04:27 AM UTC 24
Finished	Sep 24 05:07:10 AM UTC 24
Peak memory	220204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282437775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3282437775
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2175239245
Short name	T792
Test name
Test status
Simulation time	21836386101 ps
CPU time	361.89 seconds
Started	Sep 24 05:04:31 AM UTC 24
Finished	Sep 24 05:10:38 AM UTC 24
Peak memory	232648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175239245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2175239245
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1505142024
Short name	T593
Test name
Test status
Simulation time	77210837 ps
CPU time	27.76 seconds
Started	Sep 24 05:04:29 AM UTC 24
Finished	Sep 24 05:04:59 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505142024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.1505142024
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.1997021138
Short name	T833
Test name
Test status
Simulation time	10752949381 ps
CPU time	438.21 seconds
Started	Sep 24 05:04:39 AM UTC 24
Finished	Sep 24 05:12:03 AM UTC 24
Peak memory	236748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997021138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.1997021138
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.3547263921
Short name	T581
Test name
Test status
Simulation time	179333631 ps
CPU time	11.85 seconds
Started	Sep 24 05:04:27 AM UTC 24
Finished	Sep 24 05:04:40 AM UTC 24
Peak memory	215680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547263921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3547263921
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.2197779103
Short name	T607
Test name
Test status
Simulation time	3033764199 ps
CPU time	32 seconds
Started	Sep 24 05:04:53 AM UTC 24
Finished	Sep 24 05:05:26 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197779103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2197779103
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2214917730
Short name	T889
Test name
Test status
Simulation time	127655980585 ps
CPU time	636.85 seconds
Started	Sep 24 05:04:55 AM UTC 24
Finished	Sep 24 05:15:39 AM UTC 24
Peak memory	220016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214917730 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.2214917730
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.438490841
Short name	T596
Test name
Test status
Simulation time	194156054 ps
CPU time	10.3 seconds
Started	Sep 24 05:04:58 AM UTC 24
Finished	Sep 24 05:05:09 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438490841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.438490841
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.647226594
Short name	T594
Test name
Test status
Simulation time	1078006784 ps
CPU time	9.74 seconds
Started	Sep 24 05:04:55 AM UTC 24
Finished	Sep 24 05:05:06 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647226594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.647226594
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.3362010737
Short name	T609
Test name
Test status
Simulation time	623842922 ps
CPU time	38.27 seconds
Started	Sep 24 05:04:49 AM UTC 24
Finished	Sep 24 05:05:29 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362010737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3362010737
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.1691973770
Short name	T623
Test name
Test status
Simulation time	31367564964 ps
CPU time	53.77 seconds
Started	Sep 24 05:04:52 AM UTC 24
Finished	Sep 24 05:05:47 AM UTC 24
Peak memory	215836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691973770 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1691973770
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.4134884817
Short name	T650
Test name
Test status
Simulation time	20279942804 ps
CPU time	94.15 seconds
Started	Sep 24 05:04:52 AM UTC 24
Finished	Sep 24 05:06:28 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134884817 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.4134884817
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.633582521
Short name	T588
Test name
Test status
Simulation time	21250112 ps
CPU time	2.59 seconds
Started	Sep 24 05:04:49 AM UTC 24
Finished	Sep 24 05:04:53 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633582521 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.633582521
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.714765807
Short name	T597
Test name
Test status
Simulation time	266647556 ps
CPU time	17.41 seconds
Started	Sep 24 05:04:55 AM UTC 24
Finished	Sep 24 05:05:14 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714765807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.714765807
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.2209938840
Short name	T584
Test name
Test status
Simulation time	231086897 ps
CPU time	5.12 seconds
Started	Sep 24 05:04:42 AM UTC 24
Finished	Sep 24 05:04:48 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209938840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2209938840
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.999273346
Short name	T606
Test name
Test status
Simulation time	6889839834 ps
CPU time	38.44 seconds
Started	Sep 24 05:04:45 AM UTC 24
Finished	Sep 24 05:05:25 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999273346 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.999273346
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2840408976
Short name	T613
Test name
Test status
Simulation time	3493405306 ps
CPU time	42.91 seconds
Started	Sep 24 05:04:48 AM UTC 24
Finished	Sep 24 05:05:32 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840408976 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2840408976
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1573221613
Short name	T583
Test name
Test status
Simulation time	29765569 ps
CPU time	3.91 seconds
Started	Sep 24 05:04:42 AM UTC 24
Finished	Sep 24 05:04:47 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573221613 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1573221613
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.1575955434
Short name	T604
Test name
Test status
Simulation time	623871826 ps
CPU time	21.03 seconds
Started	Sep 24 05:05:00 AM UTC 24
Finished	Sep 24 05:05:22 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575955434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1575955434
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.4276392328
Short name	T629
Test name
Test status
Simulation time	2669563668 ps
CPU time	60.28 seconds
Started	Sep 24 05:05:00 AM UTC 24
Finished	Sep 24 05:06:02 AM UTC 24
Peak memory	215848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276392328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.4276392328
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3181121024
Short name	T845
Test name
Test status
Simulation time	2094404042 ps
CPU time	433.5 seconds
Started	Sep 24 05:05:00 AM UTC 24
Finished	Sep 24 05:12:19 AM UTC 24
Peak memory	222128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181121024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.3181121024
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1685928676
Short name	T625
Test name
Test status
Simulation time	266956874 ps
CPU time	39.59 seconds
Started	Sep 24 05:05:08 AM UTC 24
Finished	Sep 24 05:05:49 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685928676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.1685928676
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.4084699464
Short name	T602
Test name
Test status
Simulation time	220602484 ps
CPU time	20.74 seconds
Started	Sep 24 05:04:57 AM UTC 24
Finished	Sep 24 05:05:19 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084699464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.4084699464
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.675349620
Short name	T614
Test name
Test status
Simulation time	159400032 ps
CPU time	9.03 seconds
Started	Sep 24 05:05:22 AM UTC 24
Finished	Sep 24 05:05:32 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675349620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.675349620
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2731767404
Short name	T180
Test name
Test status
Simulation time	105217973363 ps
CPU time	754.61 seconds
Started	Sep 24 05:05:23 AM UTC 24
Finished	Sep 24 05:18:07 AM UTC 24
Peak memory	220012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731767404 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.2731767404
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1308208302
Short name	T615
Test name
Test status
Simulation time	131392481 ps
CPU time	3.46 seconds
Started	Sep 24 05:05:29 AM UTC 24
Finished	Sep 24 05:05:34 AM UTC 24
Peak memory	216032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308208302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1308208302
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.1216654280
Short name	T620
Test name
Test status
Simulation time	364849394 ps
CPU time	14.95 seconds
Started	Sep 24 05:05:27 AM UTC 24
Finished	Sep 24 05:05:44 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216654280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1216654280
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.1509487848
Short name	T628
Test name
Test status
Simulation time	1470345500 ps
CPU time	36.86 seconds
Started	Sep 24 05:05:18 AM UTC 24
Finished	Sep 24 05:05:57 AM UTC 24
Peak memory	217764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509487848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1509487848
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.2997098974
Short name	T688
Test name
Test status
Simulation time	15004272635 ps
CPU time	116.78 seconds
Started	Sep 24 05:05:18 AM UTC 24
Finished	Sep 24 05:07:17 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997098974 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2997098974
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3223790135
Short name	T158
Test name
Test status
Simulation time	6890331123 ps
CPU time	54.51 seconds
Started	Sep 24 05:05:20 AM UTC 24
Finished	Sep 24 05:06:16 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223790135 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3223790135
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.4104781437
Short name	T608
Test name
Test status
Simulation time	111917569 ps
CPU time	8.24 seconds
Started	Sep 24 05:05:18 AM UTC 24
Finished	Sep 24 05:05:28 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104781437 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.4104781437
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.1577715632
Short name	T618
Test name
Test status
Simulation time	306876888 ps
CPU time	14.01 seconds
Started	Sep 24 05:05:27 AM UTC 24
Finished	Sep 24 05:05:43 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577715632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1577715632
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.3374841166
Short name	T599
Test name
Test status
Simulation time	175682599 ps
CPU time	5.7 seconds
Started	Sep 24 05:05:08 AM UTC 24
Finished	Sep 24 05:05:15 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374841166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3374841166
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3474105264
Short name	T632
Test name
Test status
Simulation time	34036399906 ps
CPU time	48.37 seconds
Started	Sep 24 05:05:15 AM UTC 24
Finished	Sep 24 05:06:05 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474105264 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3474105264
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.822575179
Short name	T626
Test name
Test status
Simulation time	2431701446 ps
CPU time	33.41 seconds
Started	Sep 24 05:05:18 AM UTC 24
Finished	Sep 24 05:05:53 AM UTC 24
Peak memory	216020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822575179 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.822575179
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1788930122
Short name	T598
Test name
Test status
Simulation time	130569848 ps
CPU time	3.33 seconds
Started	Sep 24 05:05:11 AM UTC 24
Finished	Sep 24 05:05:15 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788930122 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1788930122
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.4190337439
Short name	T611
Test name
Test status
Simulation time	6441567 ps
CPU time	1.41 seconds
Started	Sep 24 05:05:29 AM UTC 24
Finished	Sep 24 05:05:32 AM UTC 24
Peak memory	203296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190337439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.4190337439
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3181832611
Short name	T732
Test name
Test status
Simulation time	8461504780 ps
CPU time	181.32 seconds
Started	Sep 24 05:05:31 AM UTC 24
Finished	Sep 24 05:08:35 AM UTC 24
Peak memory	220012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181832611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3181832611
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.517147152
Short name	T846
Test name
Test status
Simulation time	9497770370 ps
CPU time	405.35 seconds
Started	Sep 24 05:05:31 AM UTC 24
Finished	Sep 24 05:12:23 AM UTC 24
Peak memory	220008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517147152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.517147152
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3307271559
Short name	T899
Test name
Test status
Simulation time	24555900185 ps
CPU time	997.07 seconds
Started	Sep 24 05:05:33 AM UTC 24
Finished	Sep 24 05:22:23 AM UTC 24
Peak memory	234704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307271559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.3307271559
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.216615479
Short name	T624
Test name
Test status
Simulation time	632399994 ps
CPU time	20.23 seconds
Started	Sep 24 05:05:27 AM UTC 24
Finished	Sep 24 05:05:49 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216615479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.216615479
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.2657050479
Short name	T647
Test name
Test status
Simulation time	3296210527 ps
CPU time	35.74 seconds
Started	Sep 24 05:05:46 AM UTC 24
Finished	Sep 24 05:06:23 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657050479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2657050479
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2236591386
Short name	T893
Test name
Test status
Simulation time	91567148590 ps
CPU time	659.92 seconds
Started	Sep 24 05:05:46 AM UTC 24
Finished	Sep 24 05:16:53 AM UTC 24
Peak memory	217900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236591386 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.2236591386
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.4138579079
Short name	T637
Test name
Test status
Simulation time	642711725 ps
CPU time	20.6 seconds
Started	Sep 24 05:05:51 AM UTC 24
Finished	Sep 24 05:06:13 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138579079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.4138579079
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.1819293365
Short name	T640
Test name
Test status
Simulation time	206556350 ps
CPU time	24.83 seconds
Started	Sep 24 05:05:49 AM UTC 24
Finished	Sep 24 05:06:15 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819293365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1819293365
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.621462504
Short name	T621
Test name
Test status
Simulation time	57645674 ps
CPU time	3.44 seconds
Started	Sep 24 05:05:40 AM UTC 24
Finished	Sep 24 05:05:44 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621462504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.621462504
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.1825987651
Short name	T780
Test name
Test status
Simulation time	44273411140 ps
CPU time	278.36 seconds
Started	Sep 24 05:05:43 AM UTC 24
Finished	Sep 24 05:10:26 AM UTC 24
Peak memory	215848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825987651 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1825987651
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3234573177
Short name	T663
Test name
Test status
Simulation time	5854968307 ps
CPU time	57.88 seconds
Started	Sep 24 05:05:46 AM UTC 24
Finished	Sep 24 05:06:45 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234573177 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3234573177
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.3385509075
Short name	T622
Test name
Test status
Simulation time	18234986 ps
CPU time	3.37 seconds
Started	Sep 24 05:05:41 AM UTC 24
Finished	Sep 24 05:05:46 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385509075 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3385509075
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.1808566313
Short name	T641
Test name
Test status
Simulation time	1434064704 ps
CPU time	26.42 seconds
Started	Sep 24 05:05:47 AM UTC 24
Finished	Sep 24 05:06:15 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808566313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.1808566313
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.1131633128
Short name	T616
Test name
Test status
Simulation time	294362379 ps
CPU time	4.28 seconds
Started	Sep 24 05:05:33 AM UTC 24
Finished	Sep 24 05:05:39 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131633128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1131633128
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1379418668
Short name	T644
Test name
Test status
Simulation time	7451912341 ps
CPU time	40.48 seconds
Started	Sep 24 05:05:35 AM UTC 24
Finished	Sep 24 05:06:17 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379418668 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1379418668
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3803184661
Short name	T638
Test name
Test status
Simulation time	4124181738 ps
CPU time	37.36 seconds
Started	Sep 24 05:05:35 AM UTC 24
Finished	Sep 24 05:06:14 AM UTC 24
Peak memory	216080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803184661 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3803184661
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1698986005
Short name	T617
Test name
Test status
Simulation time	33058105 ps
CPU time	3.26 seconds
Started	Sep 24 05:05:35 AM UTC 24
Finished	Sep 24 05:05:40 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698986005 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1698986005
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.2724356338
Short name	T655
Test name
Test status
Simulation time	919700318 ps
CPU time	38.81 seconds
Started	Sep 24 05:05:54 AM UTC 24
Finished	Sep 24 05:06:35 AM UTC 24
Peak memory	217824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724356338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2724356338
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.816882590
Short name	T657
Test name
Test status
Simulation time	2787690595 ps
CPU time	35.71 seconds
Started	Sep 24 05:05:58 AM UTC 24
Finished	Sep 24 05:06:35 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816882590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.816882590
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2040060008
Short name	T779
Test name
Test status
Simulation time	3036439275 ps
CPU time	265.88 seconds
Started	Sep 24 05:05:56 AM UTC 24
Finished	Sep 24 05:10:26 AM UTC 24
Peak memory	222000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040060008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.2040060008
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3158966573
Short name	T797
Test name
Test status
Simulation time	1613023991 ps
CPU time	285.35 seconds
Started	Sep 24 05:06:03 AM UTC 24
Finished	Sep 24 05:10:53 AM UTC 24
Peak memory	232528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158966573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3158966573
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.2141010090
Short name	T633
Test name
Test status
Simulation time	388371947 ps
CPU time	15.84 seconds
Started	Sep 24 05:05:50 AM UTC 24
Finished	Sep 24 05:06:07 AM UTC 24
Peak memory	218024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141010090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2141010090
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.797409490
Short name	T646
Test name
Test status
Simulation time	71272795 ps
CPU time	5 seconds
Started	Sep 24 05:06:14 AM UTC 24
Finished	Sep 24 05:06:21 AM UTC 24
Peak memory	215852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797409490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.797409490
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.377327763
Short name	T852
Test name
Test status
Simulation time	47791031997 ps
CPU time	377.99 seconds
Started	Sep 24 05:06:17 AM UTC 24
Finished	Sep 24 05:12:40 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377327763 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.377327763
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1722409080
Short name	T653
Test name
Test status
Simulation time	88261282 ps
CPU time	14.03 seconds
Started	Sep 24 05:06:17 AM UTC 24
Finished	Sep 24 05:06:33 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722409080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1722409080
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.74762400
Short name	T672
Test name
Test status
Simulation time	3125131651 ps
CPU time	36.19 seconds
Started	Sep 24 05:06:17 AM UTC 24
Finished	Sep 24 05:06:55 AM UTC 24
Peak memory	215848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74762400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.74762400
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1728247383
Short name	T639
Test name
Test status
Simulation time	40597862 ps
CPU time	5.49 seconds
Started	Sep 24 05:06:08 AM UTC 24
Finished	Sep 24 05:06:15 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728247383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1728247383
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.59622436
Short name	T695
Test name
Test status
Simulation time	8225399885 ps
CPU time	72.68 seconds
Started	Sep 24 05:06:11 AM UTC 24
Finished	Sep 24 05:07:25 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59622436 -assert nopostproc +UVM_TESTNAME=xbar_base_ test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.59622436
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3934710619
Short name	T812
Test name
Test status
Simulation time	25858322967 ps
CPU time	297.34 seconds
Started	Sep 24 05:06:13 AM UTC 24
Finished	Sep 24 05:11:15 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934710619 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3934710619
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.2686430621
Short name	T656
Test name
Test status
Simulation time	399516764 ps
CPU time	24.27 seconds
Started	Sep 24 05:06:09 AM UTC 24
Finished	Sep 24 05:06:35 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686430621 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2686430621
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.1178714463
Short name	T654
Test name
Test status
Simulation time	312209099 ps
CPU time	14.6 seconds
Started	Sep 24 05:06:17 AM UTC 24
Finished	Sep 24 05:06:33 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178714463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1178714463
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.3559589915
Short name	T634
Test name
Test status
Simulation time	31904172 ps
CPU time	2.5 seconds
Started	Sep 24 05:06:05 AM UTC 24
Finished	Sep 24 05:06:09 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559589915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3559589915
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.4164605741
Short name	T664
Test name
Test status
Simulation time	14170204254 ps
CPU time	38.79 seconds
Started	Sep 24 05:06:05 AM UTC 24
Finished	Sep 24 05:06:46 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164605741 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.4164605741
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2019031831
Short name	T658
Test name
Test status
Simulation time	6997699538 ps
CPU time	30.53 seconds
Started	Sep 24 05:06:07 AM UTC 24
Finished	Sep 24 05:06:38 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019031831 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2019031831
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.4272820655
Short name	T635
Test name
Test status
Simulation time	28384389 ps
CPU time	3.15 seconds
Started	Sep 24 05:06:05 AM UTC 24
Finished	Sep 24 05:06:09 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272820655 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.4272820655
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.1344300092
Short name	T759
Test name
Test status
Simulation time	20037295974 ps
CPU time	187.64 seconds
Started	Sep 24 05:06:17 AM UTC 24
Finished	Sep 24 05:09:28 AM UTC 24
Peak memory	217952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344300092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1344300092
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2100313361
Short name	T754
Test name
Test status
Simulation time	1311159846 ps
CPU time	179.57 seconds
Started	Sep 24 05:06:20 AM UTC 24
Finished	Sep 24 05:09:22 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100313361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2100313361
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3585722964
Short name	T858
Test name
Test status
Simulation time	9020193501 ps
CPU time	390.29 seconds
Started	Sep 24 05:06:19 AM UTC 24
Finished	Sep 24 05:12:56 AM UTC 24
Peak memory	222256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585722964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.3585722964
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3566522180
Short name	T659
Test name
Test status
Simulation time	46131926 ps
CPU time	21.53 seconds
Started	Sep 24 05:06:20 AM UTC 24
Finished	Sep 24 05:06:42 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566522180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3566522180
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.3112851625
Short name	T159
Test name
Test status
Simulation time	113810915 ps
CPU time	17.66 seconds
Started	Sep 24 05:06:17 AM UTC 24
Finished	Sep 24 05:06:36 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112851625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3112851625
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.3806534023
Short name	T683
Test name
Test status
Simulation time	484314643 ps
CPU time	35.55 seconds
Started	Sep 24 05:06:32 AM UTC 24
Finished	Sep 24 05:07:09 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806534023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3806534023
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2633332922
Short name	T897
Test name
Test status
Simulation time	115428876142 ps
CPU time	638.64 seconds
Started	Sep 24 05:06:34 AM UTC 24
Finished	Sep 24 05:17:21 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633332922 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.2633332922
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2713607760
Short name	T666
Test name
Test status
Simulation time	195701422 ps
CPU time	10.18 seconds
Started	Sep 24 05:06:36 AM UTC 24
Finished	Sep 24 05:06:48 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713607760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2713607760
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.492221996
Short name	T660
Test name
Test status
Simulation time	81583870 ps
CPU time	6.55 seconds
Started	Sep 24 05:06:36 AM UTC 24
Finished	Sep 24 05:06:44 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492221996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.492221996
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.1989998901
Short name	T679
Test name
Test status
Simulation time	1151977733 ps
CPU time	33.79 seconds
Started	Sep 24 05:06:28 AM UTC 24
Finished	Sep 24 05:07:03 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989998901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1989998901
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.3118643848
Short name	T744
Test name
Test status
Simulation time	38527956816 ps
CPU time	147.04 seconds
Started	Sep 24 05:06:29 AM UTC 24
Finished	Sep 24 05:08:59 AM UTC 24
Peak memory	216104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118643848 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3118643848
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2852646912
Short name	T68
Test name
Test status
Simulation time	3244417049 ps
CPU time	30.02 seconds
Started	Sep 24 05:06:30 AM UTC 24
Finished	Sep 24 05:07:02 AM UTC 24
Peak memory	215848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852646912 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2852646912
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.205993834
Short name	T674
Test name
Test status
Simulation time	388991590 ps
CPU time	27.53 seconds
Started	Sep 24 05:06:28 AM UTC 24
Finished	Sep 24 05:06:57 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205993834 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.205993834
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.3932433020
Short name	T673
Test name
Test status
Simulation time	1173947327 ps
CPU time	20.74 seconds
Started	Sep 24 05:06:34 AM UTC 24
Finished	Sep 24 05:06:57 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932433020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3932433020
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.782010349
Short name	T648
Test name
Test status
Simulation time	223123984 ps
CPU time	4.98 seconds
Started	Sep 24 05:06:20 AM UTC 24
Finished	Sep 24 05:06:26 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782010349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.782010349
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.698769775
Short name	T678
Test name
Test status
Simulation time	4869242335 ps
CPU time	36.29 seconds
Started	Sep 24 05:06:22 AM UTC 24
Finished	Sep 24 05:07:00 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698769775 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.698769775
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3033810639
Short name	T671
Test name
Test status
Simulation time	3373384650 ps
CPU time	27.54 seconds
Started	Sep 24 05:06:24 AM UTC 24
Finished	Sep 24 05:06:52 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033810639 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3033810639
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3130317270
Short name	T649
Test name
Test status
Simulation time	104626269 ps
CPU time	2.65 seconds
Started	Sep 24 05:06:22 AM UTC 24
Finished	Sep 24 05:06:26 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130317270 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3130317270
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.694066394
Short name	T710
Test name
Test status
Simulation time	785463383 ps
CPU time	79.08 seconds
Started	Sep 24 05:06:38 AM UTC 24
Finished	Sep 24 05:07:58 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694066394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.694066394
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.71965806
Short name	T712
Test name
Test status
Simulation time	2640228910 ps
CPU time	75.64 seconds
Started	Sep 24 05:06:44 AM UTC 24
Finished	Sep 24 05:08:01 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71965806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.71965806
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1273743954
Short name	T810
Test name
Test status
Simulation time	6550940903 ps
CPU time	268.44 seconds
Started	Sep 24 05:06:40 AM UTC 24
Finished	Sep 24 05:11:13 AM UTC 24
Peak memory	232652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273743954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.1273743954
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3501699708
Short name	T686
Test name
Test status
Simulation time	68655433 ps
CPU time	26.32 seconds
Started	Sep 24 05:06:45 AM UTC 24
Finished	Sep 24 05:07:13 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501699708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.3501699708
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.1897588132
Short name	T677
Test name
Test status
Simulation time	707539143 ps
CPU time	22.01 seconds
Started	Sep 24 05:06:36 AM UTC 24
Finished	Sep 24 05:06:59 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897588132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1897588132
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.815891347
Short name	T691
Test name
Test status
Simulation time	721611674 ps
CPU time	27.88 seconds
Started	Sep 24 05:06:51 AM UTC 24
Finished	Sep 24 05:07:20 AM UTC 24
Peak memory	217768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815891347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.815891347
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.4051674014
Short name	T141
Test name
Test status
Simulation time	19632139447 ps
CPU time	193.32 seconds
Started	Sep 24 05:06:53 AM UTC 24
Finished	Sep 24 05:10:09 AM UTC 24
Peak memory	218160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051674014 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.4051674014
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.790641343
Short name	T690
Test name
Test status
Simulation time	1253637314 ps
CPU time	20.05 seconds
Started	Sep 24 05:06:58 AM UTC 24
Finished	Sep 24 05:07:19 AM UTC 24
Peak memory	215692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790641343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.790641343
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.3505403932
Short name	T680
Test name
Test status
Simulation time	48225738 ps
CPU time	6.01 seconds
Started	Sep 24 05:06:56 AM UTC 24
Finished	Sep 24 05:07:04 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505403932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3505403932
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.63112089
Short name	T676
Test name
Test status
Simulation time	450512183 ps
CPU time	9.32 seconds
Started	Sep 24 05:06:49 AM UTC 24
Finished	Sep 24 05:06:59 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63112089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.63112089
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.1630943047
Short name	T747
Test name
Test status
Simulation time	25950825407 ps
CPU time	135.47 seconds
Started	Sep 24 05:06:50 AM UTC 24
Finished	Sep 24 05:09:08 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630943047 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1630943047
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1315107135
Short name	T781
Test name
Test status
Simulation time	27096976062 ps
CPU time	212.42 seconds
Started	Sep 24 05:06:50 AM UTC 24
Finished	Sep 24 05:10:26 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315107135 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1315107135
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.2914149760
Short name	T684
Test name
Test status
Simulation time	279640701 ps
CPU time	19.78 seconds
Started	Sep 24 05:06:49 AM UTC 24
Finished	Sep 24 05:07:10 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914149760 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2914149760
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.346740249
Short name	T698
Test name
Test status
Simulation time	1338310111 ps
CPU time	41.06 seconds
Started	Sep 24 05:06:54 AM UTC 24
Finished	Sep 24 05:07:37 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346740249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.346740249
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.137877196
Short name	T668
Test name
Test status
Simulation time	37897956 ps
CPU time	3.1 seconds
Started	Sep 24 05:06:45 AM UTC 24
Finished	Sep 24 05:06:49 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137877196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.137877196
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3163438082
Short name	T700
Test name
Test status
Simulation time	9477384992 ps
CPU time	51.84 seconds
Started	Sep 24 05:06:47 AM UTC 24
Finished	Sep 24 05:07:41 AM UTC 24
Peak memory	216080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163438082 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3163438082
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1639871707
Short name	T694
Test name
Test status
Simulation time	4638028760 ps
CPU time	35.13 seconds
Started	Sep 24 05:06:47 AM UTC 24
Finished	Sep 24 05:07:24 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639871707 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1639871707
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.3042195899
Short name	T670
Test name
Test status
Simulation time	41201124 ps
CPU time	3.83 seconds
Started	Sep 24 05:06:47 AM UTC 24
Finished	Sep 24 05:06:52 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042195899 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.3042195899
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.1909613421
Short name	T753
Test name
Test status
Simulation time	9139853670 ps
CPU time	138.11 seconds
Started	Sep 24 05:07:01 AM UTC 24
Finished	Sep 24 05:09:22 AM UTC 24
Peak memory	220004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909613421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1909613421
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2133512574
Short name	T776
Test name
Test status
Simulation time	8651689609 ps
CPU time	195.51 seconds
Started	Sep 24 05:07:01 AM UTC 24
Finished	Sep 24 05:10:20 AM UTC 24
Peak memory	222604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133512574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2133512574
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2006734178
Short name	T725
Test name
Test status
Simulation time	142934233 ps
CPU time	78.28 seconds
Started	Sep 24 05:07:01 AM UTC 24
Finished	Sep 24 05:08:22 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006734178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.2006734178
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.610636564
Short name	T865
Test name
Test status
Simulation time	7974536097 ps
CPU time	374.49 seconds
Started	Sep 24 05:07:01 AM UTC 24
Finished	Sep 24 05:13:21 AM UTC 24
Peak memory	232656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610636564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.610636564
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.2997172679
Short name	T687
Test name
Test status
Simulation time	122611107 ps
CPU time	16.83 seconds
Started	Sep 24 05:06:58 AM UTC 24
Finished	Sep 24 05:07:16 AM UTC 24
Peak memory	217948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997172679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2997172679
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.3116215012
Short name	T186
Test name
Test status
Simulation time	712169662 ps
CPU time	47.33 seconds
Started	Sep 24 04:43:47 AM UTC 24
Finished	Sep 24 04:44:36 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116215012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3116215012
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.4266532635
Short name	T164
Test name
Test status
Simulation time	71457547249 ps
CPU time	313.62 seconds
Started	Sep 24 04:43:50 AM UTC 24
Finished	Sep 24 04:49:09 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266532635 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.4266532635
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2878347006
Short name	T280
Test name
Test status
Simulation time	5544469881 ps
CPU time	37.1 seconds
Started	Sep 24 04:44:08 AM UTC 24
Finished	Sep 24 04:44:47 AM UTC 24
Peak memory	216108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878347006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2878347006
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.1407489886
Short name	T276
Test name
Test status
Simulation time	149168945 ps
CPU time	13.44 seconds
Started	Sep 24 04:44:02 AM UTC 24
Finished	Sep 24 04:44:16 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407489886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1407489886
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.3106092478
Short name	T118
Test name
Test status
Simulation time	193326115 ps
CPU time	13.91 seconds
Started	Sep 24 04:43:24 AM UTC 24
Finished	Sep 24 04:43:39 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106092478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3106092478
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.663019942
Short name	T105
Test name
Test status
Simulation time	69668930422 ps
CPU time	328.39 seconds
Started	Sep 24 04:43:38 AM UTC 24
Finished	Sep 24 04:49:12 AM UTC 24
Peak memory	217892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663019942 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.663019942
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3179541942
Short name	T121
Test name
Test status
Simulation time	2436277377 ps
CPU time	14.52 seconds
Started	Sep 24 04:43:40 AM UTC 24
Finished	Sep 24 04:43:56 AM UTC 24
Peak memory	216036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179541942 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3179541942
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.2989467887
Short name	T119
Test name
Test status
Simulation time	188891320 ps
CPU time	11.94 seconds
Started	Sep 24 04:43:33 AM UTC 24
Finished	Sep 24 04:43:46 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989467887 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2989467887
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.3467236076
Short name	T168
Test name
Test status
Simulation time	484223356 ps
CPU time	14.95 seconds
Started	Sep 24 04:43:57 AM UTC 24
Finished	Sep 24 04:44:14 AM UTC 24
Peak memory	216036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467236076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3467236076
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.771403412
Short name	T211
Test name
Test status
Simulation time	403952575 ps
CPU time	5.05 seconds
Started	Sep 24 04:43:09 AM UTC 24
Finished	Sep 24 04:43:15 AM UTC 24
Peak memory	215960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771403412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.771403412
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3096669455
Short name	T277
Test name
Test status
Simulation time	11111057658 ps
CPU time	57.55 seconds
Started	Sep 24 04:43:21 AM UTC 24
Finished	Sep 24 04:44:20 AM UTC 24
Peak memory	216084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096669455 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3096669455
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.199300194
Short name	T167
Test name
Test status
Simulation time	4478834423 ps
CPU time	48.33 seconds
Started	Sep 24 04:43:23 AM UTC 24
Finished	Sep 24 04:44:13 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199300194 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.199300194
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2601746168
Short name	T218
Test name
Test status
Simulation time	67956235 ps
CPU time	3.04 seconds
Started	Sep 24 04:43:16 AM UTC 24
Finished	Sep 24 04:43:20 AM UTC 24
Peak memory	215948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601746168 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2601746168
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.3105341794
Short name	T103
Test name
Test status
Simulation time	3847184613 ps
CPU time	107.14 seconds
Started	Sep 24 04:44:14 AM UTC 24
Finished	Sep 24 04:46:03 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105341794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3105341794
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2301243183
Short name	T206
Test name
Test status
Simulation time	434519344 ps
CPU time	141.67 seconds
Started	Sep 24 04:44:14 AM UTC 24
Finished	Sep 24 04:46:39 AM UTC 24
Peak memory	219820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301243183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.2301243183
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.1500713347
Short name	T53
Test name
Test status
Simulation time	232824586 ps
CPU time	8.98 seconds
Started	Sep 24 04:44:05 AM UTC 24
Finished	Sep 24 04:44:15 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500713347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1500713347
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.424957473
Short name	T704
Test name
Test status
Simulation time	1489425853 ps
CPU time	35.8 seconds
Started	Sep 24 05:07:12 AM UTC 24
Finished	Sep 24 05:07:49 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424957473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.424957473
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1335460669
Short name	T870
Test name
Test status
Simulation time	121393845825 ps
CPU time	394.36 seconds
Started	Sep 24 05:07:14 AM UTC 24
Finished	Sep 24 05:13:54 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335460669 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.1335460669
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3260959745
Short name	T707
Test name
Test status
Simulation time	2466432692 ps
CPU time	34.16 seconds
Started	Sep 24 05:07:21 AM UTC 24
Finished	Sep 24 05:07:56 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260959745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3260959745
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.3101074897
Short name	T703
Test name
Test status
Simulation time	2703681467 ps
CPU time	28.93 seconds
Started	Sep 24 05:07:18 AM UTC 24
Finished	Sep 24 05:07:48 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101074897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3101074897
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.27515412
Short name	T693
Test name
Test status
Simulation time	345150425 ps
CPU time	12.26 seconds
Started	Sep 24 05:07:09 AM UTC 24
Finished	Sep 24 05:07:22 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27515412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.27515412
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.380593533
Short name	T817
Test name
Test status
Simulation time	64981315032 ps
CPU time	251.37 seconds
Started	Sep 24 05:07:11 AM UTC 24
Finished	Sep 24 05:11:26 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380593533 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.380593533
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1937019355
Short name	T798
Test name
Test status
Simulation time	86184514551 ps
CPU time	219.08 seconds
Started	Sep 24 05:07:11 AM UTC 24
Finished	Sep 24 05:10:53 AM UTC 24
Peak memory	218092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937019355 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1937019355
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.2436256873
Short name	T689
Test name
Test status
Simulation time	49357003 ps
CPU time	5.74 seconds
Started	Sep 24 05:07:11 AM UTC 24
Finished	Sep 24 05:07:18 AM UTC 24
Peak memory	215960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436256873 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2436256873
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.2250811709
Short name	T697
Test name
Test status
Simulation time	902533100 ps
CPU time	16.63 seconds
Started	Sep 24 05:07:17 AM UTC 24
Finished	Sep 24 05:07:35 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250811709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2250811709
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.298157516
Short name	T681
Test name
Test status
Simulation time	147097586 ps
CPU time	4.58 seconds
Started	Sep 24 05:07:03 AM UTC 24
Finished	Sep 24 05:07:08 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298157516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.298157516
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.4201591179
Short name	T711
Test name
Test status
Simulation time	35032658482 ps
CPU time	54.3 seconds
Started	Sep 24 05:07:05 AM UTC 24
Finished	Sep 24 05:08:00 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201591179 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.4201591179
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.4076606126
Short name	T713
Test name
Test status
Simulation time	27185006576 ps
CPU time	56.27 seconds
Started	Sep 24 05:07:05 AM UTC 24
Finished	Sep 24 05:08:02 AM UTC 24
Peak memory	216020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076606126 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.4076606126
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1922672674
Short name	T682
Test name
Test status
Simulation time	42727962 ps
CPU time	3.1 seconds
Started	Sep 24 05:07:05 AM UTC 24
Finished	Sep 24 05:07:09 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922672674 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1922672674
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.1581853458
Short name	T811
Test name
Test status
Simulation time	20473474484 ps
CPU time	230.46 seconds
Started	Sep 24 05:07:21 AM UTC 24
Finished	Sep 24 05:11:15 AM UTC 24
Peak memory	220200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581853458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1581853458
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3292085545
Short name	T849
Test name
Test status
Simulation time	34541987119 ps
CPU time	308.5 seconds
Started	Sep 24 05:07:24 AM UTC 24
Finished	Sep 24 05:12:37 AM UTC 24
Peak memory	222056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292085545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3292085545
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.883241431
Short name	T757
Test name
Test status
Simulation time	621469970 ps
CPU time	117.62 seconds
Started	Sep 24 05:07:25 AM UTC 24
Finished	Sep 24 05:09:25 AM UTC 24
Peak memory	222064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883241431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.883241431
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.3156837968
Short name	T701
Test name
Test status
Simulation time	413323708 ps
CPU time	26.24 seconds
Started	Sep 24 05:07:18 AM UTC 24
Finished	Sep 24 05:07:46 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156837968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3156837968
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.4078270766
Short name	T721
Test name
Test status
Simulation time	570588890 ps
CPU time	21.7 seconds
Started	Sep 24 05:07:51 AM UTC 24
Finished	Sep 24 05:08:14 AM UTC 24
Peak memory	215848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078270766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.4078270766
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.578246951
Short name	T733
Test name
Test status
Simulation time	14271724426 ps
CPU time	44.22 seconds
Started	Sep 24 05:07:51 AM UTC 24
Finished	Sep 24 05:08:37 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578246951 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.578246951
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.247822588
Short name	T726
Test name
Test status
Simulation time	1029983669 ps
CPU time	25.96 seconds
Started	Sep 24 05:07:58 AM UTC 24
Finished	Sep 24 05:08:26 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247822588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.247822588
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.4224117490
Short name	T723
Test name
Test status
Simulation time	3777325101 ps
CPU time	19.09 seconds
Started	Sep 24 05:07:57 AM UTC 24
Finished	Sep 24 05:08:17 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224117490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.4224117490
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.1924681884
Short name	T708
Test name
Test status
Simulation time	506687628 ps
CPU time	16.67 seconds
Started	Sep 24 05:07:39 AM UTC 24
Finished	Sep 24 05:07:57 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924681884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1924681884
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.3263736651
Short name	T735
Test name
Test status
Simulation time	17617212512 ps
CPU time	50.12 seconds
Started	Sep 24 05:07:47 AM UTC 24
Finished	Sep 24 05:08:39 AM UTC 24
Peak memory	216104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263736651 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3263736651
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1802140556
Short name	T743
Test name
Test status
Simulation time	4072904404 ps
CPU time	61.86 seconds
Started	Sep 24 05:07:51 AM UTC 24
Finished	Sep 24 05:08:55 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802140556 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1802140556
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.94276555
Short name	T709
Test name
Test status
Simulation time	167856761 ps
CPU time	14.94 seconds
Started	Sep 24 05:07:41 AM UTC 24
Finished	Sep 24 05:07:58 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94276555 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.94276555
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.2883035150
Short name	T716
Test name
Test status
Simulation time	541943758 ps
CPU time	16.55 seconds
Started	Sep 24 05:07:51 AM UTC 24
Finished	Sep 24 05:08:09 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883035150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2883035150
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.3174949449
Short name	T696
Test name
Test status
Simulation time	195507855 ps
CPU time	5.32 seconds
Started	Sep 24 05:07:26 AM UTC 24
Finished	Sep 24 05:07:33 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174949449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3174949449
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3113005711
Short name	T718
Test name
Test status
Simulation time	9736716663 ps
CPU time	33.93 seconds
Started	Sep 24 05:07:35 AM UTC 24
Finished	Sep 24 05:08:11 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113005711 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3113005711
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.4077403525
Short name	T714
Test name
Test status
Simulation time	4374321881 ps
CPU time	28.65 seconds
Started	Sep 24 05:07:38 AM UTC 24
Finished	Sep 24 05:08:08 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077403525 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4077403525
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3545467985
Short name	T699
Test name
Test status
Simulation time	33461728 ps
CPU time	3.18 seconds
Started	Sep 24 05:07:34 AM UTC 24
Finished	Sep 24 05:07:38 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545467985 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3545467985
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.3161486054
Short name	T758
Test name
Test status
Simulation time	608882066 ps
CPU time	85.16 seconds
Started	Sep 24 05:08:00 AM UTC 24
Finished	Sep 24 05:09:27 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161486054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3161486054
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3396021883
Short name	T720
Test name
Test status
Simulation time	430538777 ps
CPU time	8.71 seconds
Started	Sep 24 05:08:01 AM UTC 24
Finished	Sep 24 05:08:11 AM UTC 24
Peak memory	215716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396021883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3396021883
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1771853780
Short name	T771
Test name
Test status
Simulation time	337286489 ps
CPU time	111.04 seconds
Started	Sep 24 05:08:00 AM UTC 24
Finished	Sep 24 05:09:54 AM UTC 24
Peak memory	220076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771853780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.1771853780
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.744906368
Short name	T880
Test name
Test status
Simulation time	10368919779 ps
CPU time	387.92 seconds
Started	Sep 24 05:08:03 AM UTC 24
Finished	Sep 24 05:14:37 AM UTC 24
Peak memory	232656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744906368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.744906368
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.3287750105
Short name	T717
Test name
Test status
Simulation time	52006148 ps
CPU time	9.71 seconds
Started	Sep 24 05:07:58 AM UTC 24
Finished	Sep 24 05:08:09 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287750105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3287750105
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.3861794195
Short name	T741
Test name
Test status
Simulation time	856789247 ps
CPU time	37.51 seconds
Started	Sep 24 05:08:13 AM UTC 24
Finished	Sep 24 05:08:52 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861794195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3861794195
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.45254552
Short name	T891
Test name
Test status
Simulation time	64615974357 ps
CPU time	498.67 seconds
Started	Sep 24 05:08:15 AM UTC 24
Finished	Sep 24 05:16:40 AM UTC 24
Peak memory	218088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45254552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.45254552
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3489778491
Short name	T738
Test name
Test status
Simulation time	376786126 ps
CPU time	20.99 seconds
Started	Sep 24 05:08:23 AM UTC 24
Finished	Sep 24 05:08:45 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489778491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3489778491
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.1726950155
Short name	T734
Test name
Test status
Simulation time	395347149 ps
CPU time	18.38 seconds
Started	Sep 24 05:08:19 AM UTC 24
Finished	Sep 24 05:08:38 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726950155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1726950155
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.1816735528
Short name	T731
Test name
Test status
Simulation time	149912452 ps
CPU time	21.52 seconds
Started	Sep 24 05:08:11 AM UTC 24
Finished	Sep 24 05:08:34 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816735528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1816735528
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1972888956
Short name	T862
Test name
Test status
Simulation time	33210917754 ps
CPU time	289.07 seconds
Started	Sep 24 05:08:13 AM UTC 24
Finished	Sep 24 05:13:06 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972888956 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1972888956
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1761007362
Short name	T805
Test name
Test status
Simulation time	22680584106 ps
CPU time	166.61 seconds
Started	Sep 24 05:08:13 AM UTC 24
Finished	Sep 24 05:11:03 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761007362 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1761007362
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.484644568
Short name	T724
Test name
Test status
Simulation time	90315667 ps
CPU time	8.3 seconds
Started	Sep 24 05:08:11 AM UTC 24
Finished	Sep 24 05:08:21 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484644568 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.484644568
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.1320668546
Short name	T728
Test name
Test status
Simulation time	77128205 ps
CPU time	8.78 seconds
Started	Sep 24 05:08:17 AM UTC 24
Finished	Sep 24 05:08:27 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320668546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1320668546
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.1505482686
Short name	T715
Test name
Test status
Simulation time	29450257 ps
CPU time	3.3 seconds
Started	Sep 24 05:08:04 AM UTC 24
Finished	Sep 24 05:08:09 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505482686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1505482686
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1033160935
Short name	T742
Test name
Test status
Simulation time	7861798189 ps
CPU time	39.98 seconds
Started	Sep 24 05:08:11 AM UTC 24
Finished	Sep 24 05:08:53 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033160935 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1033160935
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2832696208
Short name	T739
Test name
Test status
Simulation time	2245921420 ps
CPU time	32.79 seconds
Started	Sep 24 05:08:11 AM UTC 24
Finished	Sep 24 05:08:45 AM UTC 24
Peak memory	215820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832696208 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2832696208
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2662766700
Short name	T719
Test name
Test status
Simulation time	131493667 ps
CPU time	3.54 seconds
Started	Sep 24 05:08:06 AM UTC 24
Finished	Sep 24 05:08:11 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662766700 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2662766700
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.876930076
Short name	T204
Test name
Test status
Simulation time	1488716719 ps
CPU time	200.6 seconds
Started	Sep 24 05:08:27 AM UTC 24
Finished	Sep 24 05:11:51 AM UTC 24
Peak memory	222288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876930076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.876930076
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.4112479889
Short name	T778
Test name
Test status
Simulation time	3979051881 ps
CPU time	114.05 seconds
Started	Sep 24 05:08:28 AM UTC 24
Finished	Sep 24 05:10:25 AM UTC 24
Peak memory	218156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112479889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.4112479889
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3605428626
Short name	T730
Test name
Test status
Simulation time	7391576 ps
CPU time	3.58 seconds
Started	Sep 24 05:08:28 AM UTC 24
Finished	Sep 24 05:08:33 AM UTC 24
Peak memory	215704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605428626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.3605428626
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2562529487
Short name	T752
Test name
Test status
Simulation time	202745856 ps
CPU time	44.12 seconds
Started	Sep 24 05:08:35 AM UTC 24
Finished	Sep 24 05:09:20 AM UTC 24
Peak memory	217840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562529487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.2562529487
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.2169657137
Short name	T727
Test name
Test status
Simulation time	51456775 ps
CPU time	3.05 seconds
Started	Sep 24 05:08:22 AM UTC 24
Finished	Sep 24 05:08:26 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169657137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2169657137
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.436973987
Short name	T765
Test name
Test status
Simulation time	1922171285 ps
CPU time	58.83 seconds
Started	Sep 24 05:08:46 AM UTC 24
Finished	Sep 24 05:09:47 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436973987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.436973987
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.701473887
Short name	T820
Test name
Test status
Simulation time	36174056540 ps
CPU time	157.27 seconds
Started	Sep 24 05:08:48 AM UTC 24
Finished	Sep 24 05:11:28 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701473887 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.701473887
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.322368099
Short name	T755
Test name
Test status
Simulation time	180071722 ps
CPU time	27.02 seconds
Started	Sep 24 05:08:54 AM UTC 24
Finished	Sep 24 05:09:22 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322368099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.322368099
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.551536854
Short name	T750
Test name
Test status
Simulation time	630841953 ps
CPU time	23.85 seconds
Started	Sep 24 05:08:51 AM UTC 24
Finished	Sep 24 05:09:16 AM UTC 24
Peak memory	216032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551536854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.551536854
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.375072302
Short name	T229
Test name
Test status
Simulation time	905365968 ps
CPU time	39.26 seconds
Started	Sep 24 05:08:40 AM UTC 24
Finished	Sep 24 05:09:21 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375072302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.375072302
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.693933964
Short name	T813
Test name
Test status
Simulation time	21162569497 ps
CPU time	153.11 seconds
Started	Sep 24 05:08:43 AM UTC 24
Finished	Sep 24 05:11:19 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693933964 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.693933964
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.733232749
Short name	T821
Test name
Test status
Simulation time	14288274863 ps
CPU time	162.52 seconds
Started	Sep 24 05:08:46 AM UTC 24
Finished	Sep 24 05:11:32 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733232749 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.733232749
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.2017641776
Short name	T740
Test name
Test status
Simulation time	35687258 ps
CPU time	4.32 seconds
Started	Sep 24 05:08:43 AM UTC 24
Finished	Sep 24 05:08:49 AM UTC 24
Peak memory	215960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017641776 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2017641776
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.111086702
Short name	T746
Test name
Test status
Simulation time	1066683633 ps
CPU time	16.93 seconds
Started	Sep 24 05:08:49 AM UTC 24
Finished	Sep 24 05:09:07 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111086702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.111086702
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.2614791935
Short name	T737
Test name
Test status
Simulation time	195577639 ps
CPU time	6.42 seconds
Started	Sep 24 05:08:37 AM UTC 24
Finished	Sep 24 05:08:45 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614791935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2614791935
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2818749036
Short name	T770
Test name
Test status
Simulation time	6757521221 ps
CPU time	72.25 seconds
Started	Sep 24 05:08:39 AM UTC 24
Finished	Sep 24 05:09:53 AM UTC 24
Peak memory	216080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818749036 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2818749036
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2013285028
Short name	T756
Test name
Test status
Simulation time	5759416061 ps
CPU time	43.05 seconds
Started	Sep 24 05:08:40 AM UTC 24
Finished	Sep 24 05:09:25 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013285028 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2013285028
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2042213825
Short name	T736
Test name
Test status
Simulation time	157855169 ps
CPU time	3.62 seconds
Started	Sep 24 05:08:37 AM UTC 24
Finished	Sep 24 05:08:42 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042213825 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2042213825
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2653617538
Short name	T800
Test name
Test status
Simulation time	5600765089 ps
CPU time	115.74 seconds
Started	Sep 24 05:08:56 AM UTC 24
Finished	Sep 24 05:10:54 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653617538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2653617538
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3453010104
Short name	T853
Test name
Test status
Simulation time	5143229235 ps
CPU time	216.97 seconds
Started	Sep 24 05:09:02 AM UTC 24
Finished	Sep 24 05:12:42 AM UTC 24
Peak memory	222056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453010104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3453010104
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1789339236
Short name	T248
Test name
Test status
Simulation time	2439544407 ps
CPU time	328.23 seconds
Started	Sep 24 05:09:00 AM UTC 24
Finished	Sep 24 05:14:33 AM UTC 24
Peak memory	219948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789339236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.1789339236
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1177957853
Short name	T814
Test name
Test status
Simulation time	378982980 ps
CPU time	128.59 seconds
Started	Sep 24 05:09:08 AM UTC 24
Finished	Sep 24 05:11:20 AM UTC 24
Peak memory	221928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177957853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.1177957853
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.3883219188
Short name	T748
Test name
Test status
Simulation time	110302473 ps
CPU time	16.03 seconds
Started	Sep 24 05:08:54 AM UTC 24
Finished	Sep 24 05:09:11 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883219188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3883219188
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.2100614441
Short name	T783
Test name
Test status
Simulation time	2329843080 ps
CPU time	61.38 seconds
Started	Sep 24 05:09:24 AM UTC 24
Finished	Sep 24 05:10:27 AM UTC 24
Peak memory	218088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100614441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2100614441
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2156322257
Short name	T140
Test name
Test status
Simulation time	64816464265 ps
CPU time	755.7 seconds
Started	Sep 24 05:09:24 AM UTC 24
Finished	Sep 24 05:22:09 AM UTC 24
Peak memory	220016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156322257 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.2156322257
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1868490566
Short name	T763
Test name
Test status
Simulation time	159474313 ps
CPU time	6.83 seconds
Started	Sep 24 05:09:30 AM UTC 24
Finished	Sep 24 05:09:38 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868490566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1868490566
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.2540181708
Short name	T761
Test name
Test status
Simulation time	18781678 ps
CPU time	2.67 seconds
Started	Sep 24 05:09:27 AM UTC 24
Finished	Sep 24 05:09:31 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540181708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2540181708
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.3167565632
Short name	T764
Test name
Test status
Simulation time	601830864 ps
CPU time	26.27 seconds
Started	Sep 24 05:09:18 AM UTC 24
Finished	Sep 24 05:09:46 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167565632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.3167565632
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.831433824
Short name	T864
Test name
Test status
Simulation time	33672460706 ps
CPU time	233.7 seconds
Started	Sep 24 05:09:22 AM UTC 24
Finished	Sep 24 05:13:19 AM UTC 24
Peak memory	218212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831433824 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.831433824
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1937431101
Short name	T890
Test name
Test status
Simulation time	162190756484 ps
CPU time	382.77 seconds
Started	Sep 24 05:09:24 AM UTC 24
Finished	Sep 24 05:15:52 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937431101 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1937431101
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.4008365542
Short name	T760
Test name
Test status
Simulation time	45305651 ps
CPU time	6.54 seconds
Started	Sep 24 05:09:22 AM UTC 24
Finished	Sep 24 05:09:30 AM UTC 24
Peak memory	215960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008365542 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.4008365542
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.1875693647
Short name	T768
Test name
Test status
Simulation time	266425350 ps
CPU time	24.88 seconds
Started	Sep 24 05:09:25 AM UTC 24
Finished	Sep 24 05:09:52 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875693647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1875693647
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.966646889
Short name	T749
Test name
Test status
Simulation time	28065629 ps
CPU time	3.23 seconds
Started	Sep 24 05:09:10 AM UTC 24
Finished	Sep 24 05:09:14 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966646889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.966646889
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.328623182
Short name	T766
Test name
Test status
Simulation time	8883207327 ps
CPU time	34.01 seconds
Started	Sep 24 05:09:16 AM UTC 24
Finished	Sep 24 05:09:51 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328623182 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.328623182
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.570280028
Short name	T777
Test name
Test status
Simulation time	13194781321 ps
CPU time	64.19 seconds
Started	Sep 24 05:09:17 AM UTC 24
Finished	Sep 24 05:10:23 AM UTC 24
Peak memory	216084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570280028 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.570280028
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3393772000
Short name	T751
Test name
Test status
Simulation time	52280921 ps
CPU time	3.27 seconds
Started	Sep 24 05:09:13 AM UTC 24
Finished	Sep 24 05:09:17 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393772000 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3393772000
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.935893074
Short name	T787
Test name
Test status
Simulation time	807849601 ps
CPU time	59.46 seconds
Started	Sep 24 05:09:32 AM UTC 24
Finished	Sep 24 05:10:33 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935893074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.935893074
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1507012832
Short name	T786
Test name
Test status
Simulation time	12230195256 ps
CPU time	55.05 seconds
Started	Sep 24 05:09:36 AM UTC 24
Finished	Sep 24 05:10:33 AM UTC 24
Peak memory	216172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507012832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1507012832
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.280460041
Short name	T878
Test name
Test status
Simulation time	740188987 ps
CPU time	294.01 seconds
Started	Sep 24 05:09:32 AM UTC 24
Finished	Sep 24 05:14:30 AM UTC 24
Peak memory	219876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280460041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.280460041
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.596447501
Short name	T772
Test name
Test status
Simulation time	89554771 ps
CPU time	19.21 seconds
Started	Sep 24 05:09:39 AM UTC 24
Finished	Sep 24 05:10:00 AM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596447501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.596447501
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.868147088
Short name	T774
Test name
Test status
Simulation time	2555410024 ps
CPU time	41.31 seconds
Started	Sep 24 05:09:28 AM UTC 24
Finished	Sep 24 05:10:11 AM UTC 24
Peak memory	218084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868147088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.868147088
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.190675166
Short name	T803
Test name
Test status
Simulation time	5343004035 ps
CPU time	56.78 seconds
Started	Sep 24 05:10:01 AM UTC 24
Finished	Sep 24 05:11:00 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190675166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.190675166
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2662186335
Short name	T151
Test name
Test status
Simulation time	64780602351 ps
CPU time	173.44 seconds
Started	Sep 24 05:10:10 AM UTC 24
Finished	Sep 24 05:13:06 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662186335 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.2662186335
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2383471343
Short name	T790
Test name
Test status
Simulation time	600146198 ps
CPU time	11.75 seconds
Started	Sep 24 05:10:21 AM UTC 24
Finished	Sep 24 05:10:34 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383471343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2383471343
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3081821096
Short name	T791
Test name
Test status
Simulation time	763665608 ps
CPU time	23.37 seconds
Started	Sep 24 05:10:12 AM UTC 24
Finished	Sep 24 05:10:37 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081821096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3081821096
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.2630501076
Short name	T793
Test name
Test status
Simulation time	1324658304 ps
CPU time	46.84 seconds
Started	Sep 24 05:09:53 AM UTC 24
Finished	Sep 24 05:10:42 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630501076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2630501076
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2665493341
Short name	T775
Test name
Test status
Simulation time	2195923786 ps
CPU time	20.54 seconds
Started	Sep 24 05:09:55 AM UTC 24
Finished	Sep 24 05:10:17 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665493341 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2665493341
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.319569628
Short name	T829
Test name
Test status
Simulation time	12983950923 ps
CPU time	119.6 seconds
Started	Sep 24 05:09:55 AM UTC 24
Finished	Sep 24 05:11:57 AM UTC 24
Peak memory	215904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319569628 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.319569628
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.1758562101
Short name	T773
Test name
Test status
Simulation time	178320823 ps
CPU time	14.06 seconds
Started	Sep 24 05:09:53 AM UTC 24
Finished	Sep 24 05:10:08 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758562101 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1758562101
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.2872563189
Short name	T784
Test name
Test status
Simulation time	669997663 ps
CPU time	15.88 seconds
Started	Sep 24 05:10:11 AM UTC 24
Finished	Sep 24 05:10:28 AM UTC 24
Peak memory	216032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872563189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2872563189
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.2975303774
Short name	T767
Test name
Test status
Simulation time	34918796 ps
CPU time	3.58 seconds
Started	Sep 24 05:09:47 AM UTC 24
Finished	Sep 24 05:09:51 AM UTC 24
Peak memory	215956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975303774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2975303774
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2972629492
Short name	T794
Test name
Test status
Simulation time	11280475104 ps
CPU time	48.2 seconds
Started	Sep 24 05:09:53 AM UTC 24
Finished	Sep 24 05:10:43 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972629492 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2972629492
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3004220362
Short name	T782
Test name
Test status
Simulation time	6168800321 ps
CPU time	32.28 seconds
Started	Sep 24 05:09:53 AM UTC 24
Finished	Sep 24 05:10:27 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004220362 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3004220362
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.991715114
Short name	T769
Test name
Test status
Simulation time	64183062 ps
CPU time	3.14 seconds
Started	Sep 24 05:09:48 AM UTC 24
Finished	Sep 24 05:09:52 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991715114 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.991715114
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.4086128581
Short name	T867
Test name
Test status
Simulation time	3556756164 ps
CPU time	187.24 seconds
Started	Sep 24 05:10:24 AM UTC 24
Finished	Sep 24 05:13:35 AM UTC 24
Peak memory	222248 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086128581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.4086128581
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2399053878
Short name	T869
Test name
Test status
Simulation time	11689694954 ps
CPU time	201.48 seconds
Started	Sep 24 05:10:28 AM UTC 24
Finished	Sep 24 05:13:53 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399053878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2399053878
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3643316818
Short name	T242
Test name
Test status
Simulation time	1344887042 ps
CPU time	145.28 seconds
Started	Sep 24 05:10:26 AM UTC 24
Finished	Sep 24 05:12:54 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643316818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.3643316818
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3311741234
Short name	T887
Test name
Test status
Simulation time	1941074427 ps
CPU time	297.2 seconds
Started	Sep 24 05:10:28 AM UTC 24
Finished	Sep 24 05:15:30 AM UTC 24
Peak memory	232592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311741234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.3311741234
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2642380385
Short name	T785
Test name
Test status
Simulation time	387680682 ps
CPU time	9.7 seconds
Started	Sep 24 05:10:18 AM UTC 24
Finished	Sep 24 05:10:29 AM UTC 24
Peak memory	216040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642380385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2642380385
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.1901477558
Short name	T804
Test name
Test status
Simulation time	343813412 ps
CPU time	23.65 seconds
Started	Sep 24 05:10:36 AM UTC 24
Finished	Sep 24 05:11:01 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901477558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1901477558
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3239118857
Short name	T892
Test name
Test status
Simulation time	49790680893 ps
CPU time	367.34 seconds
Started	Sep 24 05:10:36 AM UTC 24
Finished	Sep 24 05:16:48 AM UTC 24
Peak memory	217964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239118857 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.3239118857
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1944224170
Short name	T799
Test name
Test status
Simulation time	61221058 ps
CPU time	9.92 seconds
Started	Sep 24 05:10:42 AM UTC 24
Finished	Sep 24 05:10:53 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944224170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1944224170
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1119984832
Short name	T806
Test name
Test status
Simulation time	296273908 ps
CPU time	23.88 seconds
Started	Sep 24 05:10:38 AM UTC 24
Finished	Sep 24 05:11:04 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119984832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1119984832
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2354188190
Short name	T808
Test name
Test status
Simulation time	347194682 ps
CPU time	38.28 seconds
Started	Sep 24 05:10:30 AM UTC 24
Finished	Sep 24 05:11:10 AM UTC 24
Peak memory	215976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354188190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2354188190
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1148640061
Short name	T877
Test name
Test status
Simulation time	162586995947 ps
CPU time	223.86 seconds
Started	Sep 24 05:10:34 AM UTC 24
Finished	Sep 24 05:14:21 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148640061 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1148640061
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3180042186
Short name	T69
Test name
Test status
Simulation time	21619969722 ps
CPU time	281.28 seconds
Started	Sep 24 05:10:34 AM UTC 24
Finished	Sep 24 05:15:20 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180042186 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3180042186
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.399306402
Short name	T795
Test name
Test status
Simulation time	76484574 ps
CPU time	10.3 seconds
Started	Sep 24 05:10:34 AM UTC 24
Finished	Sep 24 05:10:45 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399306402 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.399306402
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1585415858
Short name	T796
Test name
Test status
Simulation time	130358829 ps
CPU time	13.05 seconds
Started	Sep 24 05:10:36 AM UTC 24
Finished	Sep 24 05:10:50 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585415858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1585415858
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3548201654
Short name	T789
Test name
Test status
Simulation time	292814661 ps
CPU time	3.9 seconds
Started	Sep 24 05:10:28 AM UTC 24
Finished	Sep 24 05:10:34 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548201654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3548201654
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.530794107
Short name	T815
Test name
Test status
Simulation time	5514262766 ps
CPU time	49.81 seconds
Started	Sep 24 05:10:29 AM UTC 24
Finished	Sep 24 05:11:20 AM UTC 24
Peak memory	216084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530794107 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.530794107
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1673802275
Short name	T809
Test name
Test status
Simulation time	7291696948 ps
CPU time	39.44 seconds
Started	Sep 24 05:10:30 AM UTC 24
Finished	Sep 24 05:11:11 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673802275 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1673802275
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1552215754
Short name	T788
Test name
Test status
Simulation time	78963868 ps
CPU time	3.17 seconds
Started	Sep 24 05:10:29 AM UTC 24
Finished	Sep 24 05:10:33 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552215754 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1552215754
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.145675243
Short name	T139
Test name
Test status
Simulation time	9160301234 ps
CPU time	200.49 seconds
Started	Sep 24 05:10:44 AM UTC 24
Finished	Sep 24 05:14:07 AM UTC 24
Peak memory	222188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145675243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.145675243
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2939790272
Short name	T881
Test name
Test status
Simulation time	16961440492 ps
CPU time	227.72 seconds
Started	Sep 24 05:10:52 AM UTC 24
Finished	Sep 24 05:14:43 AM UTC 24
Peak memory	222056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939790272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2939790272
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2875473803
Short name	T856
Test name
Test status
Simulation time	355385223 ps
CPU time	118.74 seconds
Started	Sep 24 05:10:46 AM UTC 24
Finished	Sep 24 05:12:47 AM UTC 24
Peak memory	219820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875473803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.2875473803
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.72717602
Short name	T879
Test name
Test status
Simulation time	559319104 ps
CPU time	218.14 seconds
Started	Sep 24 05:10:54 AM UTC 24
Finished	Sep 24 05:14:36 AM UTC 24
Peak memory	232524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72717602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.72717602
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.4222269595
Short name	T801
Test name
Test status
Simulation time	566018273 ps
CPU time	17.98 seconds
Started	Sep 24 05:10:40 AM UTC 24
Finished	Sep 24 05:10:59 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222269595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4222269595
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3461131732
Short name	T839
Test name
Test status
Simulation time	1231131978 ps
CPU time	63.76 seconds
Started	Sep 24 05:11:03 AM UTC 24
Finished	Sep 24 05:12:09 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461131732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3461131732
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3251657727
Short name	T884
Test name
Test status
Simulation time	32522497560 ps
CPU time	240.67 seconds
Started	Sep 24 05:11:05 AM UTC 24
Finished	Sep 24 05:15:09 AM UTC 24
Peak memory	217968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251657727 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.3251657727
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2527722595
Short name	T824
Test name
Test status
Simulation time	1152211917 ps
CPU time	18.15 seconds
Started	Sep 24 05:11:14 AM UTC 24
Finished	Sep 24 05:11:34 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527722595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2527722595
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.3128742518
Short name	T823
Test name
Test status
Simulation time	416888060 ps
CPU time	19.79 seconds
Started	Sep 24 05:11:11 AM UTC 24
Finished	Sep 24 05:11:32 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128742518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3128742518
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.780690221
Short name	T247
Test name
Test status
Simulation time	522236136 ps
CPU time	15.49 seconds
Started	Sep 24 05:11:00 AM UTC 24
Finished	Sep 24 05:11:17 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780690221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.780690221
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.3001775264
Short name	T834
Test name
Test status
Simulation time	21470732492 ps
CPU time	59.79 seconds
Started	Sep 24 05:11:02 AM UTC 24
Finished	Sep 24 05:12:03 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001775264 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3001775264
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1676331762
Short name	T885
Test name
Test status
Simulation time	74036560697 ps
CPU time	248.76 seconds
Started	Sep 24 05:11:02 AM UTC 24
Finished	Sep 24 05:15:15 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676331762 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1676331762
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.1207050156
Short name	T807
Test name
Test status
Simulation time	30321284 ps
CPU time	5.48 seconds
Started	Sep 24 05:11:00 AM UTC 24
Finished	Sep 24 05:11:07 AM UTC 24
Peak memory	215764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207050156 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1207050156
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3377639238
Short name	T828
Test name
Test status
Simulation time	11396333282 ps
CPU time	41.24 seconds
Started	Sep 24 05:11:08 AM UTC 24
Finished	Sep 24 05:11:51 AM UTC 24
Peak memory	216100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377639238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3377639238
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.108783408
Short name	T802
Test name
Test status
Simulation time	474000052 ps
CPU time	3.82 seconds
Started	Sep 24 05:10:54 AM UTC 24
Finished	Sep 24 05:10:59 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108783408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.108783408
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2418509233
Short name	T819
Test name
Test status
Simulation time	4121891391 ps
CPU time	31.95 seconds
Started	Sep 24 05:10:55 AM UTC 24
Finished	Sep 24 05:11:28 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418509233 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2418509233
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2759989712
Short name	T822
Test name
Test status
Simulation time	3891448750 ps
CPU time	30.42 seconds
Started	Sep 24 05:11:00 AM UTC 24
Finished	Sep 24 05:11:32 AM UTC 24
Peak memory	215824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759989712 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2759989712
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3001011894
Short name	T729
Test name
Test status
Simulation time	33539911 ps
CPU time	3.39 seconds
Started	Sep 24 05:10:55 AM UTC 24
Finished	Sep 24 05:10:59 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001011894 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3001011894
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.136445343
Short name	T882
Test name
Test status
Simulation time	4572778681 ps
CPU time	206.92 seconds
Started	Sep 24 05:11:16 AM UTC 24
Finished	Sep 24 05:14:47 AM UTC 24
Peak memory	222060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136445343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.136445343
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.122085911
Short name	T847
Test name
Test status
Simulation time	2672049424 ps
CPU time	66.43 seconds
Started	Sep 24 05:11:18 AM UTC 24
Finished	Sep 24 05:12:26 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122085911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.122085911
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3968272208
Short name	T895
Test name
Test status
Simulation time	1858435012 ps
CPU time	332.97 seconds
Started	Sep 24 05:11:16 AM UTC 24
Finished	Sep 24 05:16:54 AM UTC 24
Peak memory	232724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968272208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.3968272208
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.5603684
Short name	T855
Test name
Test status
Simulation time	147122107 ps
CPU time	83.89 seconds
Started	Sep 24 05:11:21 AM UTC 24
Finished	Sep 24 05:12:47 AM UTC 24
Peak memory	219888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5603684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_ TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.5603684
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2553201997
Short name	T825
Test name
Test status
Simulation time	3126950533 ps
CPU time	28.42 seconds
Started	Sep 24 05:11:13 AM UTC 24
Finished	Sep 24 05:11:42 AM UTC 24
Peak memory	218088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553201997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2553201997
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3642541246
Short name	T844
Test name
Test status
Simulation time	440231914 ps
CPU time	44.31 seconds
Started	Sep 24 05:11:33 AM UTC 24
Finished	Sep 24 05:12:19 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642541246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3642541246
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.944337654
Short name	T152
Test name
Test status
Simulation time	125310608502 ps
CPU time	737.58 seconds
Started	Sep 24 05:11:34 AM UTC 24
Finished	Sep 24 05:24:00 AM UTC 24
Peak memory	218156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944337654 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.944337654
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3469831991
Short name	T838
Test name
Test status
Simulation time	520912138 ps
CPU time	17.72 seconds
Started	Sep 24 05:11:49 AM UTC 24
Finished	Sep 24 05:12:08 AM UTC 24
Peak memory	216044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469831991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3469831991
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3274758031
Short name	T830
Test name
Test status
Simulation time	121659139 ps
CPU time	13.92 seconds
Started	Sep 24 05:11:43 AM UTC 24
Finished	Sep 24 05:11:59 AM UTC 24
Peak memory	215768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274758031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3274758031
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.320718904
Short name	T841
Test name
Test status
Simulation time	1106410893 ps
CPU time	42.7 seconds
Started	Sep 24 05:11:28 AM UTC 24
Finished	Sep 24 05:12:12 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320718904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.320718904
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1063234936
Short name	T836
Test name
Test status
Simulation time	6605123271 ps
CPU time	35.95 seconds
Started	Sep 24 05:11:29 AM UTC 24
Finished	Sep 24 05:12:07 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063234936 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1063234936
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2023139013
Short name	T875
Test name
Test status
Simulation time	16609970167 ps
CPU time	163.36 seconds
Started	Sep 24 05:11:33 AM UTC 24
Finished	Sep 24 05:14:20 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023139013 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2023139013
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1335909190
Short name	T827
Test name
Test status
Simulation time	92068583 ps
CPU time	17.04 seconds
Started	Sep 24 05:11:29 AM UTC 24
Finished	Sep 24 05:11:47 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335909190 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1335909190
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.1285777973
Short name	T826
Test name
Test status
Simulation time	94019838 ps
CPU time	11.27 seconds
Started	Sep 24 05:11:35 AM UTC 24
Finished	Sep 24 05:11:47 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285777973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1285777973
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.517959920
Short name	T818
Test name
Test status
Simulation time	124945686 ps
CPU time	4.44 seconds
Started	Sep 24 05:11:22 AM UTC 24
Finished	Sep 24 05:11:27 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517959920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.517959920
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.452106035
Short name	T842
Test name
Test status
Simulation time	7841109913 ps
CPU time	45.43 seconds
Started	Sep 24 05:11:26 AM UTC 24
Finished	Sep 24 05:12:13 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452106035 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.452106035
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4032973717
Short name	T832
Test name
Test status
Simulation time	4889167064 ps
CPU time	32.64 seconds
Started	Sep 24 05:11:28 AM UTC 24
Finished	Sep 24 05:12:02 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032973717 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.4032973717
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2736991358
Short name	T816
Test name
Test status
Simulation time	35413750 ps
CPU time	2.25 seconds
Started	Sep 24 05:11:22 AM UTC 24
Finished	Sep 24 05:11:25 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736991358 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2736991358
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.3872101252
Short name	T886
Test name
Test status
Simulation time	6840503739 ps
CPU time	211.74 seconds
Started	Sep 24 05:11:52 AM UTC 24
Finished	Sep 24 05:15:27 AM UTC 24
Peak memory	222056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872101252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3872101252
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2585618399
Short name	T874
Test name
Test status
Simulation time	6906813887 ps
CPU time	133.61 seconds
Started	Sep 24 05:11:59 AM UTC 24
Finished	Sep 24 05:14:15 AM UTC 24
Peak memory	217896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585618399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2585618399
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.950206574
Short name	T888
Test name
Test status
Simulation time	1292785965 ps
CPU time	220.86 seconds
Started	Sep 24 05:11:52 AM UTC 24
Finished	Sep 24 05:15:36 AM UTC 24
Peak memory	221928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950206574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.950206574
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.869524319
Short name	T873
Test name
Test status
Simulation time	447780490 ps
CPU time	129.67 seconds
Started	Sep 24 05:12:00 AM UTC 24
Finished	Sep 24 05:14:13 AM UTC 24
Peak memory	221932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869524319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.869524319
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.583454419
Short name	T835
Test name
Test status
Simulation time	276056497 ps
CPU time	15.96 seconds
Started	Sep 24 05:11:49 AM UTC 24
Finished	Sep 24 05:12:06 AM UTC 24
Peak memory	218020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583454419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.583454419
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2875483590
Short name	T154
Test name
Test status
Simulation time	3830190396 ps
CPU time	89.19 seconds
Started	Sep 24 05:12:12 AM UTC 24
Finished	Sep 24 05:13:43 AM UTC 24
Peak memory	217828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875483590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2875483590
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3836962970
Short name	T900
Test name
Test status
Simulation time	132253798545 ps
CPU time	982.7 seconds
Started	Sep 24 05:12:12 AM UTC 24
Finished	Sep 24 05:28:47 AM UTC 24
Peak memory	220012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836962970 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.3836962970
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.4014195841
Short name	T857
Test name
Test status
Simulation time	1275220783 ps
CPU time	29.41 seconds
Started	Sep 24 05:12:21 AM UTC 24
Finished	Sep 24 05:12:52 AM UTC 24
Peak memory	215708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014195841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.4014195841
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.996666482
Short name	T854
Test name
Test status
Simulation time	265893145 ps
CPU time	27.35 seconds
Started	Sep 24 05:12:15 AM UTC 24
Finished	Sep 24 05:12:44 AM UTC 24
Peak memory	215832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996666482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.996666482
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2261048686
Short name	T850
Test name
Test status
Simulation time	601671534 ps
CPU time	26.62 seconds
Started	Sep 24 05:12:09 AM UTC 24
Finished	Sep 24 05:12:37 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261048686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2261048686
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.2727296478
Short name	T876
Test name
Test status
Simulation time	38305363791 ps
CPU time	129.06 seconds
Started	Sep 24 05:12:09 AM UTC 24
Finished	Sep 24 05:14:21 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727296478 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2727296478
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2307038237
Short name	T205
Test name
Test status
Simulation time	54538541681 ps
CPU time	251.14 seconds
Started	Sep 24 05:12:10 AM UTC 24
Finished	Sep 24 05:16:25 AM UTC 24
Peak memory	215916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307038237 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2307038237
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3190516666
Short name	T843
Test name
Test status
Simulation time	64813554 ps
CPU time	8.43 seconds
Started	Sep 24 05:12:09 AM UTC 24
Finished	Sep 24 05:12:19 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190516666 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3190516666
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1710783260
Short name	T848
Test name
Test status
Simulation time	1495884153 ps
CPU time	16.62 seconds
Started	Sep 24 05:12:13 AM UTC 24
Finished	Sep 24 05:12:31 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710783260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1710783260
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.2166876432
Short name	T840
Test name
Test status
Simulation time	329690466 ps
CPU time	6.09 seconds
Started	Sep 24 05:12:04 AM UTC 24
Finished	Sep 24 05:12:11 AM UTC 24
Peak memory	215548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166876432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2166876432
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.4065193389
Short name	T860
Test name
Test status
Simulation time	7009865585 ps
CPU time	58.32 seconds
Started	Sep 24 05:12:05 AM UTC 24
Finished	Sep 24 05:13:05 AM UTC 24
Peak memory	216080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065193389 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.4065193389
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.273177114
Short name	T859
Test name
Test status
Simulation time	3094735476 ps
CPU time	50.48 seconds
Started	Sep 24 05:12:05 AM UTC 24
Finished	Sep 24 05:12:57 AM UTC 24
Peak memory	216084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273177114 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.273177114
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.4248437073
Short name	T837
Test name
Test status
Simulation time	26766988 ps
CPU time	3.16 seconds
Started	Sep 24 05:12:04 AM UTC 24
Finished	Sep 24 05:12:08 AM UTC 24
Peak memory	215552 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248437073 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.4248437073
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3894181162
Short name	T861
Test name
Test status
Simulation time	1654956171 ps
CPU time	42.92 seconds
Started	Sep 24 05:12:21 AM UTC 24
Finished	Sep 24 05:13:06 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894181162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3894181162
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2050784914
Short name	T871
Test name
Test status
Simulation time	3246436531 ps
CPU time	98.92 seconds
Started	Sep 24 05:12:28 AM UTC 24
Finished	Sep 24 05:14:09 AM UTC 24
Peak memory	219944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050784914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2050784914
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1563876884
Short name	T44
Test name
Test status
Simulation time	109703729 ps
CPU time	79.29 seconds
Started	Sep 24 05:12:24 AM UTC 24
Finished	Sep 24 05:13:45 AM UTC 24
Peak memory	219884 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563876884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.1563876884
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1821226062
Short name	T866
Test name
Test status
Simulation time	267324550 ps
CPU time	51.4 seconds
Started	Sep 24 05:12:33 AM UTC 24
Finished	Sep 24 05:13:26 AM UTC 24
Peak memory	217836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821226062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.1821226062
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.1106459518
Short name	T851
Test name
Test status
Simulation time	451476315 ps
CPU time	16.16 seconds
Started	Sep 24 05:12:21 AM UTC 24
Finished	Sep 24 05:12:39 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106459518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1106459518
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.1285568079
Short name	T101
Test name
Test status
Simulation time	521103549 ps
CPU time	19.55 seconds
Started	Sep 24 04:44:47 AM UTC 24
Finished	Sep 24 04:45:08 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285568079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1285568079
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2914449573
Short name	T102
Test name
Test status
Simulation time	4283708749 ps
CPU time	39.95 seconds
Started	Sep 24 04:44:48 AM UTC 24
Finished	Sep 24 04:45:30 AM UTC 24
Peak memory	215844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914449573 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.2914449573
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.516291295
Short name	T203
Test name
Test status
Simulation time	680933222 ps
CPU time	16.81 seconds
Started	Sep 24 04:45:08 AM UTC 24
Finished	Sep 24 04:45:26 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516291295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.516291295
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.1797759606
Short name	T33
Test name
Test status
Simulation time	1080562504 ps
CPU time	38.74 seconds
Started	Sep 24 04:44:56 AM UTC 24
Finished	Sep 24 04:45:37 AM UTC 24
Peak memory	215964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797759606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1797759606
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.1250917154
Short name	T82
Test name
Test status
Simulation time	225399271 ps
CPU time	8.3 seconds
Started	Sep 24 04:44:38 AM UTC 24
Finished	Sep 24 04:44:47 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250917154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1250917154
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.4082591201
Short name	T199
Test name
Test status
Simulation time	6020203281 ps
CPU time	33.52 seconds
Started	Sep 24 04:44:44 AM UTC 24
Finished	Sep 24 04:45:19 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082591201 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4082591201
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1360684731
Short name	T104
Test name
Test status
Simulation time	7528005069 ps
CPU time	79.73 seconds
Started	Sep 24 04:44:46 AM UTC 24
Finished	Sep 24 04:46:08 AM UTC 24
Peak memory	215908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360684731 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1360684731
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.13458647
Short name	T279
Test name
Test status
Simulation time	127125482 ps
CPU time	4.21 seconds
Started	Sep 24 04:44:38 AM UTC 24
Finished	Sep 24 04:44:43 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13458647 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.13458647
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.893385454
Short name	T202
Test name
Test status
Simulation time	1364863352 ps
CPU time	35.01 seconds
Started	Sep 24 04:44:48 AM UTC 24
Finished	Sep 24 04:45:25 AM UTC 24
Peak memory	216036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893385454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.893385454
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.1508883679
Short name	T181
Test name
Test status
Simulation time	137242417 ps
CPU time	4.28 seconds
Started	Sep 24 04:44:21 AM UTC 24
Finished	Sep 24 04:44:27 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508883679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1508883679
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.699521291
Short name	T197
Test name
Test status
Simulation time	6209887440 ps
CPU time	49.02 seconds
Started	Sep 24 04:44:26 AM UTC 24
Finished	Sep 24 04:45:17 AM UTC 24
Peak memory	216088 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699521291 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.699521291
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1282409851
Short name	T4
Test name
Test status
Simulation time	4673945129 ps
CPU time	46.13 seconds
Started	Sep 24 04:44:27 AM UTC 24
Finished	Sep 24 04:45:15 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282409851 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1282409851
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.443765754
Short name	T278
Test name
Test status
Simulation time	68621212 ps
CPU time	3.2 seconds
Started	Sep 24 04:44:21 AM UTC 24
Finished	Sep 24 04:44:25 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443765754 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.443765754
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.1198060560
Short name	T91
Test name
Test status
Simulation time	12799964664 ps
CPU time	274.56 seconds
Started	Sep 24 04:45:09 AM UTC 24
Finished	Sep 24 04:49:48 AM UTC 24
Peak memory	220008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198060560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1198060560
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.673435575
Short name	T97
Test name
Test status
Simulation time	10194703197 ps
CPU time	282.43 seconds
Started	Sep 24 04:45:12 AM UTC 24
Finished	Sep 24 04:50:00 AM UTC 24
Peak memory	219944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673435575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.673435575
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3195606399
Short name	T110
Test name
Test status
Simulation time	18695267682 ps
CPU time	672.56 seconds
Started	Sep 24 04:45:10 AM UTC 24
Finished	Sep 24 04:56:33 AM UTC 24
Peak memory	222064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195606399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.3195606399
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3188663321
Short name	T273
Test name
Test status
Simulation time	122649340 ps
CPU time	18.51 seconds
Started	Sep 24 04:45:16 AM UTC 24
Finished	Sep 24 04:45:36 AM UTC 24
Peak memory	217840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188663321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.3188663321
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.334721737
Short name	T187
Test name
Test status
Simulation time	109063225 ps
CPU time	10.7 seconds
Started	Sep 24 04:44:58 AM UTC 24
Finished	Sep 24 04:45:09 AM UTC 24
Peak memory	217824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334721737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.334721737
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.2543012009
Short name	T86
Test name
Test status
Simulation time	3809167671 ps
CPU time	48.3 seconds
Started	Sep 24 04:45:37 AM UTC 24
Finished	Sep 24 04:46:27 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543012009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2543012009
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.97271511
Short name	T253
Test name
Test status
Simulation time	50592421108 ps
CPU time	538.9 seconds
Started	Sep 24 04:45:37 AM UTC 24
Finished	Sep 24 04:54:44 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97271511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.97271511
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2421417562
Short name	T284
Test name
Test status
Simulation time	597066329 ps
CPU time	17.79 seconds
Started	Sep 24 04:45:56 AM UTC 24
Finished	Sep 24 04:46:15 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421417562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2421417562
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.10446462
Short name	T233
Test name
Test status
Simulation time	657006057 ps
CPU time	11.28 seconds
Started	Sep 24 04:45:53 AM UTC 24
Finished	Sep 24 04:46:06 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10446462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.10446462
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.2920058207
Short name	T282
Test name
Test status
Simulation time	860424639 ps
CPU time	27.19 seconds
Started	Sep 24 04:45:24 AM UTC 24
Finished	Sep 24 04:45:52 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920058207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2920058207
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.1429650523
Short name	T58
Test name
Test status
Simulation time	70779545662 ps
CPU time	332.82 seconds
Started	Sep 24 04:45:27 AM UTC 24
Finished	Sep 24 04:51:05 AM UTC 24
Peak memory	218148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429650523 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1429650523
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2378125907
Short name	T175
Test name
Test status
Simulation time	20899545616 ps
CPU time	230.93 seconds
Started	Sep 24 04:45:31 AM UTC 24
Finished	Sep 24 04:49:26 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378125907 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2378125907
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.2153527720
Short name	T281
Test name
Test status
Simulation time	115371764 ps
CPU time	15.79 seconds
Started	Sep 24 04:45:26 AM UTC 24
Finished	Sep 24 04:45:43 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153527720 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2153527720
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.1747010448
Short name	T37
Test name
Test status
Simulation time	262319503 ps
CPU time	16.74 seconds
Started	Sep 24 04:45:44 AM UTC 24
Finished	Sep 24 04:46:02 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747010448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1747010448
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2300996226
Short name	T198
Test name
Test status
Simulation time	42520840 ps
CPU time	2.71 seconds
Started	Sep 24 04:45:18 AM UTC 24
Finished	Sep 24 04:45:22 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300996226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2300996226
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3035198734
Short name	T283
Test name
Test status
Simulation time	3552761444 ps
CPU time	30.09 seconds
Started	Sep 24 04:45:24 AM UTC 24
Finished	Sep 24 04:45:55 AM UTC 24
Peak memory	215828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035198734 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3035198734
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.371750108
Short name	T234
Test name
Test status
Simulation time	5404894691 ps
CPU time	46.31 seconds
Started	Sep 24 04:45:24 AM UTC 24
Finished	Sep 24 04:46:11 AM UTC 24
Peak memory	216084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371750108 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.371750108
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2929020737
Short name	T201
Test name
Test status
Simulation time	30675374 ps
CPU time	2.7 seconds
Started	Sep 24 04:45:19 AM UTC 24
Finished	Sep 24 04:45:23 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929020737 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2929020737
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.1095244244
Short name	T89
Test name
Test status
Simulation time	3595988963 ps
CPU time	67.61 seconds
Started	Sep 24 04:46:02 AM UTC 24
Finished	Sep 24 04:47:11 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095244244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1095244244
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2049013272
Short name	T260
Test name
Test status
Simulation time	626671781 ps
CPU time	76.86 seconds
Started	Sep 24 04:46:04 AM UTC 24
Finished	Sep 24 04:47:23 AM UTC 24
Peak memory	218092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049013272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2049013272
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3874118146
Short name	T274
Test name
Test status
Simulation time	194012187 ps
CPU time	88.56 seconds
Started	Sep 24 04:46:03 AM UTC 24
Finished	Sep 24 04:47:34 AM UTC 24
Peak memory	219880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874118146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.3874118146
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2499354148
Short name	T27
Test name
Test status
Simulation time	544247296 ps
CPU time	111.75 seconds
Started	Sep 24 04:46:07 AM UTC 24
Finished	Sep 24 04:48:01 AM UTC 24
Peak memory	221932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499354148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.2499354148
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.2614430268
Short name	T85
Test name
Test status
Simulation time	1032245376 ps
CPU time	18.52 seconds
Started	Sep 24 04:45:56 AM UTC 24
Finished	Sep 24 04:46:15 AM UTC 24
Peak memory	217824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614430268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2614430268
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.3308840638
Short name	T238
Test name
Test status
Simulation time	444594016 ps
CPU time	19.42 seconds
Started	Sep 24 04:46:16 AM UTC 24
Finished	Sep 24 04:46:37 AM UTC 24
Peak memory	217768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308840638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3308840638
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3772933340
Short name	T241
Test name
Test status
Simulation time	270241395 ps
CPU time	9.05 seconds
Started	Sep 24 04:46:32 AM UTC 24
Finished	Sep 24 04:46:42 AM UTC 24
Peak memory	215720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772933340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3772933340
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.2819593019
Short name	T285
Test name
Test status
Simulation time	157057302 ps
CPU time	13.1 seconds
Started	Sep 24 04:46:28 AM UTC 24
Finished	Sep 24 04:46:43 AM UTC 24
Peak memory	215772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819593019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2819593019
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.3317495803
Short name	T236
Test name
Test status
Simulation time	144277581 ps
CPU time	14.88 seconds
Started	Sep 24 04:46:14 AM UTC 24
Finished	Sep 24 04:46:30 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317495803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3317495803
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.1432149413
Short name	T344
Test name
Test status
Simulation time	170436955943 ps
CPU time	487.44 seconds
Started	Sep 24 04:46:16 AM UTC 24
Finished	Sep 24 04:54:31 AM UTC 24
Peak memory	216100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432149413 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1432149413
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3227698161
Short name	T94
Test name
Test status
Simulation time	24142163918 ps
CPU time	210.76 seconds
Started	Sep 24 04:46:16 AM UTC 24
Finished	Sep 24 04:49:51 AM UTC 24
Peak memory	215340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227698161 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3227698161
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.920816329
Short name	T239
Test name
Test status
Simulation time	447513600 ps
CPU time	22.93 seconds
Started	Sep 24 04:46:15 AM UTC 24
Finished	Sep 24 04:46:39 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920816329 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.920816329
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.3557628247
Short name	T237
Test name
Test status
Simulation time	89310219 ps
CPU time	7.69 seconds
Started	Sep 24 04:46:22 AM UTC 24
Finished	Sep 24 04:46:31 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557628247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3557628247
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.1973464606
Short name	T215
Test name
Test status
Simulation time	202037186 ps
CPU time	4.64 seconds
Started	Sep 24 04:46:08 AM UTC 24
Finished	Sep 24 04:46:14 AM UTC 24
Peak memory	215696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973464606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1973464606
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3965788809
Short name	T288
Test name
Test status
Simulation time	4764083643 ps
CPU time	41.3 seconds
Started	Sep 24 04:46:13 AM UTC 24
Finished	Sep 24 04:46:55 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965788809 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3965788809
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1743220449
Short name	T289
Test name
Test status
Simulation time	7687171818 ps
CPU time	44.77 seconds
Started	Sep 24 04:46:13 AM UTC 24
Finished	Sep 24 04:46:59 AM UTC 24
Peak memory	215892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743220449 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1743220449
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.742047325
Short name	T235
Test name
Test status
Simulation time	34570306 ps
CPU time	2.53 seconds
Started	Sep 24 04:46:09 AM UTC 24
Finished	Sep 24 04:46:13 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742047325 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.742047325
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.4237148849
Short name	T191
Test name
Test status
Simulation time	1292840979 ps
CPU time	24.73 seconds
Started	Sep 24 04:46:38 AM UTC 24
Finished	Sep 24 04:47:04 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237148849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.4237148849
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3951551750
Short name	T267
Test name
Test status
Simulation time	1186659057 ps
CPU time	118.08 seconds
Started	Sep 24 04:46:40 AM UTC 24
Finished	Sep 24 04:48:41 AM UTC 24
Peak memory	217832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951551750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3951551750
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2288176502
Short name	T40
Test name
Test status
Simulation time	227561433 ps
CPU time	125.76 seconds
Started	Sep 24 04:46:40 AM UTC 24
Finished	Sep 24 04:48:48 AM UTC 24
Peak memory	219888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288176502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.2288176502
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3137880442
Short name	T275
Test name
Test status
Simulation time	441272337 ps
CPU time	142.11 seconds
Started	Sep 24 04:46:41 AM UTC 24
Finished	Sep 24 04:49:06 AM UTC 24
Peak memory	222124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137880442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.3137880442
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.3364137273
Short name	T287
Test name
Test status
Simulation time	161090541 ps
CPU time	16.98 seconds
Started	Sep 24 04:46:31 AM UTC 24
Finished	Sep 24 04:46:49 AM UTC 24
Peak memory	215712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364137273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3364137273
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.2606006395
Short name	T290
Test name
Test status
Simulation time	67916926 ps
CPU time	16.08 seconds
Started	Sep 24 04:47:04 AM UTC 24
Finished	Sep 24 04:47:22 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606006395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2606006395
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3591164771
Short name	T297
Test name
Test status
Simulation time	831774360 ps
CPU time	30.86 seconds
Started	Sep 24 04:47:28 AM UTC 24
Finished	Sep 24 04:48:00 AM UTC 24
Peak memory	215980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591164771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3591164771
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.3212037490
Short name	T293
Test name
Test status
Simulation time	254131160 ps
CPU time	19.18 seconds
Started	Sep 24 04:47:24 AM UTC 24
Finished	Sep 24 04:47:44 AM UTC 24
Peak memory	215952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212037490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3212037490
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.4267425544
Short name	T90
Test name
Test status
Simulation time	1492273903 ps
CPU time	35.66 seconds
Started	Sep 24 04:46:50 AM UTC 24
Finished	Sep 24 04:47:27 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267425544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.4267425544
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.1935927542
Short name	T183
Test name
Test status
Simulation time	39834754539 ps
CPU time	351.18 seconds
Started	Sep 24 04:47:00 AM UTC 24
Finished	Sep 24 04:52:57 AM UTC 24
Peak memory	215912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935927542 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1935927542
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.457016277
Short name	T216
Test name
Test status
Simulation time	82659119210 ps
CPU time	319.43 seconds
Started	Sep 24 04:47:04 AM UTC 24
Finished	Sep 24 04:52:29 AM UTC 24
Peak memory	217960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457016277 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.457016277
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.1630294394
Short name	T291
Test name
Test status
Simulation time	742089824 ps
CPU time	26.07 seconds
Started	Sep 24 04:46:56 AM UTC 24
Finished	Sep 24 04:47:23 AM UTC 24
Peak memory	215836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630294394 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1630294394
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.3877937707
Short name	T296
Test name
Test status
Simulation time	1786089910 ps
CPU time	29.37 seconds
Started	Sep 24 04:47:23 AM UTC 24
Finished	Sep 24 04:47:53 AM UTC 24
Peak memory	215968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877937707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3877937707
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.2895782562
Short name	T87
Test name
Test status
Simulation time	174395235 ps
CPU time	3.69 seconds
Started	Sep 24 04:46:42 AM UTC 24
Finished	Sep 24 04:46:47 AM UTC 24
Peak memory	216012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895782562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2895782562
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3592793420
Short name	T54
Test name
Test status
Simulation time	8351362990 ps
CPU time	43.31 seconds
Started	Sep 24 04:46:48 AM UTC 24
Finished	Sep 24 04:47:32 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592793420 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3592793420
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.304955491
Short name	T292
Test name
Test status
Simulation time	4442336577 ps
CPU time	40.91 seconds
Started	Sep 24 04:46:49 AM UTC 24
Finished	Sep 24 04:47:31 AM UTC 24
Peak memory	216020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304955491 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.304955491
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.4273592482
Short name	T286
Test name
Test status
Simulation time	32192292 ps
CPU time	3.12 seconds
Started	Sep 24 04:46:43 AM UTC 24
Finished	Sep 24 04:46:48 AM UTC 24
Peak memory	215948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273592482 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.4273592482
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.1566186111
Short name	T299
Test name
Test status
Simulation time	576018072 ps
CPU time	29.9 seconds
Started	Sep 24 04:47:32 AM UTC 24
Finished	Sep 24 04:48:03 AM UTC 24
Peak memory	215784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566186111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1566186111
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4028078131
Short name	T99
Test name
Test status
Simulation time	12287110657 ps
CPU time	156.32 seconds
Started	Sep 24 04:47:34 AM UTC 24
Finished	Sep 24 04:50:14 AM UTC 24
Peak memory	220012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028078131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4028078131
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.74508918
Short name	T302
Test name
Test status
Simulation time	53841103 ps
CPU time	38.76 seconds
Started	Sep 24 04:47:33 AM UTC 24
Finished	Sep 24 04:48:13 AM UTC 24
Peak memory	217764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74508918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.74508918
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1095141981
Short name	T45
Test name
Test status
Simulation time	11653770304 ps
CPU time	387.27 seconds
Started	Sep 24 04:47:44 AM UTC 24
Finished	Sep 24 04:54:18 AM UTC 24
Peak memory	232652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095141981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.1095141981
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.2122949519
Short name	T251
Test name
Test status
Simulation time	539031010 ps
CPU time	21.51 seconds
Started	Sep 24 04:47:24 AM UTC 24
Finished	Sep 24 04:47:47 AM UTC 24
Peak memory	217824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122949519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2122949519
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.1104894735
Short name	T230
Test name
Test status
Simulation time	430935972 ps
CPU time	11.86 seconds
Started	Sep 24 04:48:03 AM UTC 24
Finished	Sep 24 04:48:16 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104894735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1104894735
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2299717783
Short name	T306
Test name
Test status
Simulation time	322594053 ps
CPU time	17.9 seconds
Started	Sep 24 04:48:17 AM UTC 24
Finished	Sep 24 04:48:36 AM UTC 24
Peak memory	215788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299717783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2299717783
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.1355381880
Short name	T309
Test name
Test status
Simulation time	1060903150 ps
CPU time	29.05 seconds
Started	Sep 24 04:48:11 AM UTC 24
Finished	Sep 24 04:48:42 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355381880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1355381880
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.2966467959
Short name	T298
Test name
Test status
Simulation time	177710279 ps
CPU time	9.63 seconds
Started	Sep 24 04:47:52 AM UTC 24
Finished	Sep 24 04:48:03 AM UTC 24
Peak memory	215972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966467959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2966467959
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.2586544428
Short name	T317
Test name
Test status
Simulation time	70452170751 ps
CPU time	196.22 seconds
Started	Sep 24 04:48:01 AM UTC 24
Finished	Sep 24 04:51:21 AM UTC 24
Peak memory	216100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586544428 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2586544428
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.263528510
Short name	T325
Test name
Test status
Simulation time	30903972607 ps
CPU time	268.02 seconds
Started	Sep 24 04:48:02 AM UTC 24
Finished	Sep 24 04:52:35 AM UTC 24
Peak memory	217956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263528510 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.263528510
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.117217810
Short name	T300
Test name
Test status
Simulation time	77014714 ps
CPU time	11.15 seconds
Started	Sep 24 04:47:54 AM UTC 24
Finished	Sep 24 04:48:06 AM UTC 24
Peak memory	215780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117217810 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.117217810
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.4285539998
Short name	T301
Test name
Test status
Simulation time	50992832 ps
CPU time	2.59 seconds
Started	Sep 24 04:48:07 AM UTC 24
Finished	Sep 24 04:48:11 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285539998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.4285539998
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.2191404069
Short name	T294
Test name
Test status
Simulation time	169446567 ps
CPU time	3.89 seconds
Started	Sep 24 04:47:45 AM UTC 24
Finished	Sep 24 04:47:50 AM UTC 24
Peak memory	215760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191404069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2191404069
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1044680110
Short name	T307
Test name
Test status
Simulation time	6583568879 ps
CPU time	46.66 seconds
Started	Sep 24 04:47:49 AM UTC 24
Finished	Sep 24 04:48:37 AM UTC 24
Peak memory	215888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044680110 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1044680110
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3471494699
Short name	T304
Test name
Test status
Simulation time	3340595014 ps
CPU time	34.3 seconds
Started	Sep 24 04:47:51 AM UTC 24
Finished	Sep 24 04:48:26 AM UTC 24
Peak memory	216024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471494699 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3471494699
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.1916830574
Short name	T295
Test name
Test status
Simulation time	55388433 ps
CPU time	2.59 seconds
Started	Sep 24 04:47:47 AM UTC 24
Finished	Sep 24 04:47:51 AM UTC 24
Peak memory	215756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916830574 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1916830574
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.2565934718
Short name	T106
Test name
Test status
Simulation time	26374236120 ps
CPU time	266.25 seconds
Started	Sep 24 04:48:18 AM UTC 24
Finished	Sep 24 04:52:48 AM UTC 24
Peak memory	220008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565934718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2565934718
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3236348074
Short name	T258
Test name
Test status
Simulation time	27852529470 ps
CPU time	227.84 seconds
Started	Sep 24 04:48:30 AM UTC 24
Finished	Sep 24 04:52:22 AM UTC 24
Peak memory	220012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236348074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3236348074
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.815385133
Short name	T29
Test name
Test status
Simulation time	9050802917 ps
CPU time	315.39 seconds
Started	Sep 24 04:48:27 AM UTC 24
Finished	Sep 24 04:53:48 AM UTC 24
Peak memory	222052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815385133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.815385133
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.835542176
Short name	T28
Test name
Test status
Simulation time	605534558 ps
CPU time	116.69 seconds
Started	Sep 24 04:48:37 AM UTC 24
Finished	Sep 24 04:50:37 AM UTC 24
Peak memory	219820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835542176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.835542176
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.3653256774
Short name	T305
Test name
Test status
Simulation time	83138445 ps
CPU time	13.45 seconds
Started	Sep 24 04:48:15 AM UTC 24
Finished	Sep 24 04:48:29 AM UTC 24
Peak memory	215776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653256774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3653256774
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest