Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1806	1			T8	1		T29	3		T22	2
all_values[1]	1801	1			T29	3		T22	2		T24	2
all_values[2]	1779	1			T8	1		T29	3		T22	1
all_values[3]	1844	1			T8	3		T22	2		T24	2
all_values[4]	1703	1			T29	3		T22	2		T24	1
all_values[5]	1785	1			T8	2		T29	2		T22	2
all_values[6]	1795	1			T8	2		T29	2		T22	3
all_values[7]	1845	1			T8	4		T29	1		T22	6
all_values[8]	1826	1			T8	2		T29	1		T22	2
all_values[9]	1839	1			T29	4		T22	2		T24	6
all_values[10]	1792	1			T8	1		T29	1		T22	2
all_values[11]	1798	1			T8	1		T29	3		T22	2
all_values[12]	1836	1			T8	2		T29	2		T22	3
all_values[13]	1798	1			T8	3		T29	2		T22	2
all_values[14]	1841	1			T8	3		T29	1		T22	2
all_values[15]	1813	1			T8	2		T22	5		T24	1
all_values[16]	1779	1			T8	3		T29	3		T24	3
all_values[17]	1779	1			T8	2		T29	1		T22	4
all_values[18]	1784	1			T8	2		T29	3		T22	2
all_values[19]	1808	1			T29	2		T22	2		T24	5
all_values[20]	1803	1			T8	1		T29	4		T22	1
all_values[21]	1722	1			T8	1		T22	1		T24	1
all_values[22]	1899	1			T8	1		T29	4		T22	2
all_values[23]	1909	1			T8	1		T22	6		T24	3
all_values[24]	1870	1			T29	2		T22	1		T24	1
all_values[25]	1796	1			T8	1		T29	1		T22	3
all_values[26]	1818	1			T8	4		T29	3		T22	2
all_values[27]	1852	1			T29	2		T22	1		T24	3
all_values[28]	1850	1			T8	2		T29	4		T22	3
all_values[29]	1806	1			T8	3		T22	3		T24	4
all_values[30]	1781	1			T8	4		T29	1		T22	1
all_values[31]	1843	1			T8	3		T29	4		T22	3
all_values[32]	1733	1			T8	4		T29	3		T22	2
all_values[33]	1781	1			T8	1		T29	2		T22	3
all_values[34]	1803	1			T8	4		T29	2		T22	4
all_values[35]	1840	1			T8	6		T29	2		T24	3
all_values[36]	1826	1			T8	1		T22	2		T24	1
all_values[37]	1789	1			T8	2		T22	2		T24	2
all_values[38]	1763	1			T8	3		T29	2		T22	3
all_values[39]	1793	1			T8	3		T29	2		T24	1
all_values[40]	1847	1			T8	2		T29	3		T22	2
all_values[41]	1790	1			T8	3		T29	1		T22	3
all_values[42]	1830	1			T8	3		T29	2		T22	2
all_values[43]	1686	1			T8	2		T22	1		T24	6
all_values[44]	1809	1			T29	2		T22	1		T24	3
all_values[45]	1773	1			T8	2		T22	2		T24	2
all_values[46]	1812	1			T8	1		T29	1		T22	1
all_values[47]	1747	1			T8	3		T29	1		T22	1
all_values[48]	1845	1			T8	2		T29	2		T22	7
all_values[49]	1795	1			T29	4		T22	3		T24	2
all_values[50]	1879	1			T8	2		T29	3		T22	2
all_values[51]	1794	1			T8	6		T29	6		T22	1
all_values[52]	1827	1			T8	1		T29	3		T22	2
all_values[53]	1807	1			T8	1		T29	2		T24	4
all_values[54]	1867	1			T8	1		T29	3		T22	4
all_values[55]	1754	1			T8	2		T29	3		T22	3
all_values[56]	1810	1			T8	2		T29	3		T22	2
all_values[57]	1750	1			T29	5		T22	3		T24	6
all_values[58]	1748	1			T8	1		T29	3		T22	1
all_values[59]	1891	1			T8	1		T29	2		T229	1
all_values[60]	1883	1			T8	2		T29	2		T22	2
all_values[61]	1730	1			T8	1		T24	2		T56	1
all_values[62]	1750	1			T8	1		T29	1		T22	3
all_values[63]	1854	1			T8	2		T29	3		T22	4