Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	24	0	24	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	24	0	24	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	450	1			T253	1		T52	4		T53	2
all_values[1]	482	1			T55	1		T52	5		T53	4
all_values[2]	490	1			T9	1		T55	1		T52	3
all_values[3]	489	1			T55	1		T52	2		T53	2
all_values[4]	509	1			T16	1		T76	2		T253	1
all_values[5]	481	1			T55	1		T52	3		T53	2
all_values[6]	501	1			T55	1		T52	1		T53	2
all_values[7]	474	1			T55	1		T52	3		T53	2
all_values[8]	465	1			T253	1		T52	5		T53	2
all_values[9]	501	1			T253	1		T52	1		T53	5
all_values[10]	486	1			T52	4		T53	3		T325	1
all_values[11]	488	1			T9	1		T16	1		T52	1
all_values[12]	472	1			T52	2		T53	2		T325	2
all_values[13]	502	1			T55	3		T92	1		T52	5
all_values[14]	494	1			T55	1		T52	1		T53	5
all_values[15]	499	1			T55	1		T92	1		T52	3
all_values[16]	478	1			T55	3		T92	1		T52	5
all_values[17]	486	1			T52	3		T53	2		T94	1
all_values[18]	492	1			T52	2		T53	2		T317	1
all_values[19]	500	1			T16	1		T92	1		T52	6
all_values[20]	472	1			T52	5		T53	3		T94	1
all_values[21]	461	1			T253	1		T55	1		T52	4
all_values[22]	462	1			T253	1		T55	1		T52	8
all_values[23]	488	1			T16	1		T253	1		T52	1