Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1724	1			T15	4		T205	3		T91	1
all_values[1]	1751	1			T15	1		T205	5		T80	2
all_values[2]	1791	1			T15	3		T205	4		T91	2
all_values[3]	1768	1			T15	2		T205	3		T91	5
all_values[4]	1783	1			T15	1		T205	4		T91	7
all_values[5]	1741	1			T15	1		T205	5		T91	5
all_values[6]	1783	1			T15	3		T205	7		T91	4
all_values[7]	1817	1			T15	2		T91	2		T80	2
all_values[8]	1753	1			T91	2		T80	2		T44	6
all_values[9]	1742	1			T205	3		T80	2		T44	7
all_values[10]	1729	1			T205	3		T91	2		T80	5
all_values[11]	1805	1			T15	2		T205	2		T91	3
all_values[12]	1833	1			T15	2		T205	1		T91	4
all_values[13]	1759	1			T15	3		T205	2		T91	3
all_values[14]	1763	1			T15	2		T205	6		T91	2
all_values[15]	1755	1			T15	1		T205	2		T91	2
all_values[16]	1738	1			T15	4		T205	3		T80	4
all_values[17]	1674	1			T15	4		T205	2		T91	1
all_values[18]	1694	1			T15	1		T205	3		T91	1
all_values[19]	1788	1			T15	4		T205	3		T91	3
all_values[20]	1731	1			T15	1		T205	3		T91	1
all_values[21]	1818	1			T15	1		T205	4		T91	5
all_values[22]	1763	1			T15	1		T205	3		T91	5
all_values[23]	1666	1			T15	2		T205	2		T91	3
all_values[24]	1753	1			T15	2		T205	2		T80	1
all_values[25]	1779	1			T15	5		T205	3		T91	8
all_values[26]	1753	1			T15	2		T205	6		T91	1
all_values[27]	1802	1			T15	3		T205	3		T91	1
all_values[28]	1819	1			T15	3		T205	4		T91	1
all_values[29]	1739	1			T15	3		T205	1		T91	2
all_values[30]	1715	1			T15	2		T205	3		T91	1
all_values[31]	1712	1			T205	1		T91	1		T80	4
all_values[32]	1705	1			T15	2		T205	2		T91	3
all_values[33]	1815	1			T15	1		T205	2		T91	2
all_values[34]	1691	1			T15	1		T205	4		T91	3
all_values[35]	1722	1			T15	2		T205	2		T91	1
all_values[36]	1830	1			T15	3		T205	1		T91	5
all_values[37]	1778	1			T15	2		T205	4		T91	1
all_values[38]	1837	1			T15	3		T205	1		T91	5
all_values[39]	1670	1			T91	4		T85	1		T44	3
all_values[40]	1696	1			T15	1		T205	6		T91	2
all_values[41]	1788	1			T15	1		T91	1		T80	2
all_values[42]	1709	1			T15	7		T205	2		T91	2
all_values[43]	1779	1			T15	1		T205	4		T91	1
all_values[44]	1795	1			T15	1		T205	5		T91	1
all_values[45]	1718	1			T15	2		T205	2		T91	1
all_values[46]	1806	1			T205	2		T91	1		T85	1
all_values[47]	1755	1			T15	1		T205	2		T91	2
all_values[48]	1762	1			T15	4		T205	2		T91	1
all_values[49]	1790	1			T15	4		T205	5		T91	2
all_values[50]	1817	1			T15	2		T205	3		T91	2
all_values[51]	1783	1			T205	4		T91	3		T80	2
all_values[52]	1766	1			T15	1		T205	5		T91	2
all_values[53]	1758	1			T205	5		T91	3		T80	2
all_values[54]	1799	1			T15	1		T205	3		T91	1
all_values[55]	1794	1			T15	1		T205	3		T91	2
all_values[56]	1744	1			T15	2		T205	1		T91	2
all_values[57]	1719	1			T15	3		T205	7		T91	5
all_values[58]	1771	1			T15	1		T205	6		T91	2
all_values[59]	1785	1			T15	4		T205	3		T91	1
all_values[60]	1765	1			T205	2		T91	2		T80	3
all_values[61]	1823	1			T15	1		T205	4		T80	2
all_values[62]	1823	1			T205	2		T91	4		T85	1
all_values[63]	1789	1			T15	3		T205	2		T91	2