Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1893	1			T52	1		T55	3		T116	1
all_values[1]	1905	1			T9	4		T52	1		T55	1
all_values[2]	1855	1			T9	2		T55	2		T95	1
all_values[3]	1931	1			T9	3		T52	1		T55	2
all_values[4]	1928	1			T9	1		T116	3		T123	3
all_values[5]	1901	1			T55	1		T123	1		T172	3
all_values[6]	1985	1			T55	2		T116	3		T172	2
all_values[7]	1942	1			T9	1		T52	2		T116	2
all_values[8]	1895	1			T9	2		T52	1		T55	3
all_values[9]	1878	1			T52	1		T55	2		T116	4
all_values[10]	1926	1			T9	1		T116	2		T123	6
all_values[11]	2025	1			T52	1		T55	2		T116	3
all_values[12]	1919	1			T52	1		T55	1		T95	1
all_values[13]	1866	1			T9	1		T55	1		T95	1
all_values[14]	1918	1			T52	1		T116	5		T123	4
all_values[15]	1936	1			T9	1		T52	3		T55	1
all_values[16]	1929	1			T9	1		T52	3		T116	8
all_values[17]	1900	1			T52	1		T55	1		T116	2
all_values[18]	1919	1			T52	2		T116	5		T123	1
all_values[19]	1843	1			T9	1		T55	1		T95	2
all_values[20]	1876	1			T116	3		T123	2		T178	1
all_values[21]	1917	1			T52	1		T55	1		T116	3
all_values[22]	1965	1			T9	2		T52	1		T55	5
all_values[23]	1910	1			T9	1		T55	2		T116	2
all_values[24]	1946	1			T9	2		T55	2		T116	2
all_values[25]	1933	1			T9	1		T95	1		T116	2
all_values[26]	1897	1			T9	2		T116	4		T123	6
all_values[27]	1938	1			T9	1		T52	1		T55	3
all_values[28]	1862	1			T52	3		T55	1		T95	1
all_values[29]	1835	1			T52	2		T55	2		T116	3
all_values[30]	1929	1			T9	1		T55	2		T116	2
all_values[31]	1858	1			T9	1		T52	2		T55	1
all_values[32]	1986	1			T9	2		T55	1		T116	2
all_values[33]	1908	1			T52	3		T55	1		T95	1
all_values[34]	1929	1			T52	1		T55	1		T95	2
all_values[35]	1942	1			T52	1		T55	8		T116	8
all_values[36]	1846	1			T55	2		T123	3		T172	4
all_values[37]	1869	1			T52	2		T116	4		T123	3
all_values[38]	1845	1			T55	2		T116	2		T123	3
all_values[39]	1994	1			T9	2		T52	1		T55	1
all_values[40]	1983	1			T9	1		T52	3		T55	3
all_values[41]	1912	1			T9	1		T52	1		T116	1
all_values[42]	1937	1			T55	2		T116	6		T172	2
all_values[43]	1935	1			T52	1		T55	3		T116	2
all_values[44]	1974	1			T52	1		T55	1		T178	2
all_values[45]	1926	1			T52	1		T55	1		T116	5
all_values[46]	1915	1			T9	2		T52	4		T55	1
all_values[47]	1883	1			T52	5		T55	2		T116	6
all_values[48]	1912	1			T9	1		T55	2		T95	1
all_values[49]	1873	1			T52	1		T116	4		T123	3
all_values[50]	1910	1			T55	1		T116	4		T123	2
all_values[51]	2011	1			T55	1		T95	2		T116	1
all_values[52]	1958	1			T9	2		T52	2		T55	1
all_values[53]	1919	1			T9	1		T52	1		T55	2
all_values[54]	1868	1			T9	1		T116	2		T172	5
all_values[55]	1989	1			T9	2		T52	2		T55	2
all_values[56]	1891	1			T9	1		T52	3		T55	1
all_values[57]	1961	1			T55	1		T116	2		T123	3
all_values[58]	1959	1			T9	1		T52	2		T55	3
all_values[59]	1913	1			T9	1		T52	2		T55	3
all_values[60]	1888	1			T9	1		T55	3		T116	1
all_values[61]	1837	1			T52	1		T116	4		T172	5
all_values[62]	1947	1			T55	2		T116	1		T123	1
all_values[63]	1921	1			T9	1		T52	1		T116	3