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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.23 99.26 88.94 100.00 95.88 99.28 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T772 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.597968844 Oct 12 12:02:12 AM UTC 24 Oct 12 12:02:34 AM UTC 24 363795598 ps
T773 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.348782233 Oct 12 12:02:15 AM UTC 24 Oct 12 12:02:36 AM UTC 24 132169448 ps
T774 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3551375562 Oct 12 12:02:32 AM UTC 24 Oct 12 12:02:36 AM UTC 24 71598276 ps
T775 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3087039998 Oct 12 12:02:34 AM UTC 24 Oct 12 12:02:39 AM UTC 24 26854852 ps
T776 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1809185201 Oct 11 11:58:27 PM UTC 24 Oct 12 12:02:40 AM UTC 24 68404274836 ps
T777 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3551382819 Oct 12 12:02:08 AM UTC 24 Oct 12 12:02:40 AM UTC 24 4583938872 ps
T778 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3579217965 Oct 12 12:01:04 AM UTC 24 Oct 12 12:02:41 AM UTC 24 1829604948 ps
T779 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3069945455 Oct 12 12:02:24 AM UTC 24 Oct 12 12:02:41 AM UTC 24 117280955 ps
T780 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1641017402 Oct 12 12:02:10 AM UTC 24 Oct 12 12:02:42 AM UTC 24 3477231081 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3096154427 Oct 11 11:54:21 PM UTC 24 Oct 12 12:02:43 AM UTC 24 4727355793 ps
T781 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1844737518 Oct 12 12:02:38 AM UTC 24 Oct 12 12:02:43 AM UTC 24 274504605 ps
T782 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2846401991 Oct 12 12:02:38 AM UTC 24 Oct 12 12:02:44 AM UTC 24 25883843 ps
T783 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2649155074 Oct 12 12:01:38 AM UTC 24 Oct 12 12:02:44 AM UTC 24 7509917451 ps
T784 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3734014825 Oct 12 12:01:51 AM UTC 24 Oct 12 12:02:46 AM UTC 24 10294163597 ps
T785 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2094893867 Oct 11 11:59:43 PM UTC 24 Oct 12 12:02:46 AM UTC 24 5690844138 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.964542501 Oct 12 12:00:37 AM UTC 24 Oct 12 12:02:48 AM UTC 24 404640859 ps
T786 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2333176811 Oct 12 12:01:53 AM UTC 24 Oct 12 12:02:49 AM UTC 24 3979941403 ps
T787 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.2828242563 Oct 12 12:01:35 AM UTC 24 Oct 12 12:02:50 AM UTC 24 2657253583 ps
T788 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1363562850 Oct 11 11:58:11 PM UTC 24 Oct 12 12:02:50 AM UTC 24 118083058889 ps
T789 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3140638122 Oct 12 12:02:45 AM UTC 24 Oct 12 12:02:51 AM UTC 24 58166872 ps
T790 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2708805613 Oct 12 12:02:42 AM UTC 24 Oct 12 12:02:53 AM UTC 24 223200131 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3238537576 Oct 12 12:01:56 AM UTC 24 Oct 12 12:02:53 AM UTC 24 7577966703 ps
T791 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.3490950192 Oct 12 12:02:21 AM UTC 24 Oct 12 12:02:55 AM UTC 24 932030291 ps
T792 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1710011106 Oct 12 12:02:51 AM UTC 24 Oct 12 12:02:55 AM UTC 24 35601999 ps
T793 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3533871786 Oct 12 12:02:51 AM UTC 24 Oct 12 12:02:57 AM UTC 24 240459853 ps
T794 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3415923500 Oct 12 12:02:45 AM UTC 24 Oct 12 12:02:58 AM UTC 24 183493584 ps
T795 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.4147601080 Oct 11 11:57:51 PM UTC 24 Oct 12 12:02:58 AM UTC 24 30304864939 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3616407890 Oct 11 11:59:16 PM UTC 24 Oct 12 12:03:04 AM UTC 24 23133298298 ps
T796 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.2645534364 Oct 12 12:02:45 AM UTC 24 Oct 12 12:03:08 AM UTC 24 1199108602 ps
T797 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.2492921067 Oct 12 12:02:26 AM UTC 24 Oct 12 12:03:08 AM UTC 24 1528153387 ps
T798 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2404531964 Oct 12 12:03:01 AM UTC 24 Oct 12 12:03:08 AM UTC 24 68614442 ps
T799 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.3399978732 Oct 12 12:00:21 AM UTC 24 Oct 12 12:03:10 AM UTC 24 62283799934 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.453963327 Oct 12 12:02:36 AM UTC 24 Oct 12 12:03:11 AM UTC 24 17486128704 ps
T800 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2032403782 Oct 12 12:02:55 AM UTC 24 Oct 12 12:03:11 AM UTC 24 111668505 ps
T801 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2491314538 Oct 12 12:01:35 AM UTC 24 Oct 12 12:03:11 AM UTC 24 41434634616 ps
T802 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3825342434 Oct 12 12:02:48 AM UTC 24 Oct 12 12:03:12 AM UTC 24 236511155 ps
T803 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.1267722910 Oct 12 12:02:58 AM UTC 24 Oct 12 12:03:13 AM UTC 24 1109645691 ps
T804 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3476517112 Oct 12 12:02:53 AM UTC 24 Oct 12 12:03:17 AM UTC 24 3443478801 ps
T805 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.700520892 Oct 12 12:02:53 AM UTC 24 Oct 12 12:03:18 AM UTC 24 781694645 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1747092676 Oct 12 12:02:36 AM UTC 24 Oct 12 12:03:18 AM UTC 24 18718993633 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3368759874 Oct 12 12:03:14 AM UTC 24 Oct 12 12:03:18 AM UTC 24 30045953 ps
T808 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.3879572503 Oct 12 12:03:14 AM UTC 24 Oct 12 12:03:19 AM UTC 24 116163995 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1302903367 Oct 11 11:59:01 PM UTC 24 Oct 12 12:03:22 AM UTC 24 547827273 ps
T809 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3880208852 Oct 12 12:02:45 AM UTC 24 Oct 12 12:03:22 AM UTC 24 1119727251 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4122120366 Oct 11 11:57:20 PM UTC 24 Oct 12 12:03:22 AM UTC 24 1992323453 ps
T810 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.4124439725 Oct 12 12:01:26 AM UTC 24 Oct 12 12:03:26 AM UTC 24 364460105 ps
T811 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.4137315176 Oct 12 12:01:22 AM UTC 24 Oct 12 12:03:26 AM UTC 24 4262974704 ps
T812 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3396084150 Oct 11 11:59:06 PM UTC 24 Oct 12 12:03:27 AM UTC 24 7469053446 ps
T813 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3914321560 Oct 12 12:01:48 AM UTC 24 Oct 12 12:03:27 AM UTC 24 350568548 ps
T814 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.4182927145 Oct 12 12:03:01 AM UTC 24 Oct 12 12:03:28 AM UTC 24 1113129990 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.3665394040 Oct 12 12:03:05 AM UTC 24 Oct 12 12:03:29 AM UTC 24 624616750 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.922370297 Oct 12 12:03:10 AM UTC 24 Oct 12 12:03:29 AM UTC 24 2764706271 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1064002140 Oct 12 12:02:51 AM UTC 24 Oct 12 12:03:36 AM UTC 24 125653606 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1080416268 Oct 12 12:03:31 AM UTC 24 Oct 12 12:03:37 AM UTC 24 239494654 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.4020286188 Oct 12 12:03:38 AM UTC 24 Oct 12 12:03:41 AM UTC 24 36623288 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2404385316 Oct 12 12:02:53 AM UTC 24 Oct 12 12:03:42 AM UTC 24 22406342637 ps
T821 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.1390928171 Oct 12 12:03:23 AM UTC 24 Oct 12 12:03:43 AM UTC 24 329508546 ps
T822 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3542943824 Oct 12 12:03:31 AM UTC 24 Oct 12 12:03:43 AM UTC 24 86438351 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.462937283 Oct 12 12:03:19 AM UTC 24 Oct 12 12:03:46 AM UTC 24 368236381 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1945710287 Oct 11 11:56:11 PM UTC 24 Oct 12 12:03:46 AM UTC 24 12976870103 ps
T824 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1395247875 Oct 12 12:03:26 AM UTC 24 Oct 12 12:03:49 AM UTC 24 162048493 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2138400624 Oct 12 12:03:13 AM UTC 24 Oct 12 12:03:49 AM UTC 24 1815010461 ps
T826 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.742192992 Oct 12 12:03:45 AM UTC 24 Oct 12 12:03:51 AM UTC 24 97581525 ps
T827 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2441529940 Oct 12 12:02:58 AM UTC 24 Oct 12 12:03:55 AM UTC 24 10295090727 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3460976825 Oct 12 12:01:17 AM UTC 24 Oct 12 12:03:55 AM UTC 24 15160542180 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1900768091 Oct 12 12:03:25 AM UTC 24 Oct 12 12:03:59 AM UTC 24 2874812788 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.793432544 Oct 12 12:03:31 AM UTC 24 Oct 12 12:04:01 AM UTC 24 3009082203 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2371379769 Oct 12 12:03:14 AM UTC 24 Oct 12 12:04:02 AM UTC 24 17047780350 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2562726678 Oct 12 12:03:14 AM UTC 24 Oct 12 12:04:02 AM UTC 24 21723180247 ps
T832 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.1451500006 Oct 12 12:01:20 AM UTC 24 Oct 12 12:04:04 AM UTC 24 5424339907 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.519832321 Oct 12 12:02:15 AM UTC 24 Oct 12 12:04:05 AM UTC 24 20070844013 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.167642386 Oct 12 12:00:34 AM UTC 24 Oct 12 12:04:05 AM UTC 24 5627281012 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.1465836386 Oct 12 12:03:19 AM UTC 24 Oct 12 12:04:06 AM UTC 24 1351924049 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.737728699 Oct 12 12:03:21 AM UTC 24 Oct 12 12:04:07 AM UTC 24 739542222 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.3504365428 Oct 12 12:03:51 AM UTC 24 Oct 12 12:04:07 AM UTC 24 215444868 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3652201158 Oct 12 12:03:21 AM UTC 24 Oct 12 12:04:09 AM UTC 24 4092696607 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.362636073 Oct 11 11:59:42 PM UTC 24 Oct 12 12:04:10 AM UTC 24 5553415340 ps
T837 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1548308927 Oct 12 12:01:58 AM UTC 24 Oct 12 12:04:11 AM UTC 24 17762755368 ps
T838 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3587621299 Oct 12 12:01:20 AM UTC 24 Oct 12 12:04:11 AM UTC 24 2530127911 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.4227618968 Oct 12 12:03:53 AM UTC 24 Oct 12 12:04:11 AM UTC 24 427158379 ps
T840 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.411007288 Oct 12 12:04:02 AM UTC 24 Oct 12 12:04:12 AM UTC 24 38260551 ps
T841 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3120558911 Oct 12 12:03:49 AM UTC 24 Oct 12 12:04:13 AM UTC 24 1477198840 ps
T842 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2822330290 Oct 12 12:04:10 AM UTC 24 Oct 12 12:04:14 AM UTC 24 126221924 ps
T843 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1963189537 Oct 12 12:03:38 AM UTC 24 Oct 12 12:04:14 AM UTC 24 9099542980 ps
T844 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.4065849323 Oct 12 12:03:57 AM UTC 24 Oct 12 12:04:14 AM UTC 24 242282176 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.883315486 Oct 12 12:04:10 AM UTC 24 Oct 12 12:04:15 AM UTC 24 34812081 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3922465279 Oct 12 12:02:42 AM UTC 24 Oct 12 12:04:15 AM UTC 24 19546243155 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2372144786 Oct 12 12:03:45 AM UTC 24 Oct 12 12:04:16 AM UTC 24 845420137 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1343297305 Oct 12 12:02:55 AM UTC 24 Oct 12 12:04:17 AM UTC 24 14124906907 ps
T848 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1147439072 Oct 11 11:58:37 PM UTC 24 Oct 12 12:04:17 AM UTC 24 3565848602 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3905212410 Oct 12 12:02:05 AM UTC 24 Oct 12 12:04:18 AM UTC 24 2264686012 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1046843460 Oct 12 12:03:43 AM UTC 24 Oct 12 12:04:19 AM UTC 24 3737572583 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1664026532 Oct 11 11:59:37 PM UTC 24 Oct 12 12:04:20 AM UTC 24 56463658769 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2240016030 Oct 12 12:04:10 AM UTC 24 Oct 12 12:04:21 AM UTC 24 98095891 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2627315584 Oct 12 12:04:15 AM UTC 24 Oct 12 12:04:21 AM UTC 24 131378265 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.1776200464 Oct 12 12:03:57 AM UTC 24 Oct 12 12:04:21 AM UTC 24 1787005188 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.2349095344 Oct 12 12:04:15 AM UTC 24 Oct 12 12:04:26 AM UTC 24 144275583 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.4047266812 Oct 12 12:04:15 AM UTC 24 Oct 12 12:04:27 AM UTC 24 270385146 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1689986802 Oct 12 12:02:15 AM UTC 24 Oct 12 12:04:28 AM UTC 24 22468138471 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.3629301881 Oct 12 12:04:01 AM UTC 24 Oct 12 12:04:31 AM UTC 24 167982253 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2133785400 Oct 12 12:04:16 AM UTC 24 Oct 12 12:04:31 AM UTC 24 1308372218 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.1559856449 Oct 12 12:01:54 AM UTC 24 Oct 12 12:04:37 AM UTC 24 99403219158 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.136662050 Oct 12 12:00:09 AM UTC 24 Oct 12 12:04:37 AM UTC 24 1605947644 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3172676582 Oct 12 12:04:10 AM UTC 24 Oct 12 12:04:38 AM UTC 24 779466281 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1442769959 Oct 12 12:04:15 AM UTC 24 Oct 12 12:04:39 AM UTC 24 1420552019 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1848897546 Oct 12 12:04:10 AM UTC 24 Oct 12 12:04:41 AM UTC 24 5785418318 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2706069818 Oct 12 12:02:00 AM UTC 24 Oct 12 12:04:43 AM UTC 24 7967661016 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3885047113 Oct 12 12:01:00 AM UTC 24 Oct 12 12:04:46 AM UTC 24 686832765 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2997889790 Oct 12 12:04:10 AM UTC 24 Oct 12 12:04:46 AM UTC 24 3594810778 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3950939389 Oct 12 12:02:30 AM UTC 24 Oct 12 12:04:48 AM UTC 24 12115319681 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.726513106 Oct 12 12:02:32 AM UTC 24 Oct 12 12:04:53 AM UTC 24 490628715 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.783192563 Oct 11 11:59:59 PM UTC 24 Oct 12 12:04:56 AM UTC 24 106079063227 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.2283157101 Oct 12 12:03:19 AM UTC 24 Oct 12 12:05:00 AM UTC 24 21363128130 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1799407763 Oct 12 12:00:51 AM UTC 24 Oct 12 12:05:02 AM UTC 24 73345452973 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.70206753 Oct 12 12:04:15 AM UTC 24 Oct 12 12:05:10 AM UTC 24 7666262940 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3956005114 Oct 12 12:02:42 AM UTC 24 Oct 12 12:05:10 AM UTC 24 15624460667 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2661126788 Oct 12 12:01:33 AM UTC 24 Oct 12 12:05:11 AM UTC 24 123849692004 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.224330092 Oct 12 12:02:48 AM UTC 24 Oct 12 12:05:11 AM UTC 24 1983645741 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1653609353 Oct 12 12:04:15 AM UTC 24 Oct 12 12:05:14 AM UTC 24 9922272618 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2769622294 Oct 12 12:04:15 AM UTC 24 Oct 12 12:05:18 AM UTC 24 12898394107 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3612195121 Oct 12 12:02:48 AM UTC 24 Oct 12 12:05:20 AM UTC 24 398715530 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.767410021 Oct 12 12:04:05 AM UTC 24 Oct 12 12:05:27 AM UTC 24 1072224887 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1383488690 Oct 12 12:00:26 AM UTC 24 Oct 12 12:05:27 AM UTC 24 36963641218 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.661289832 Oct 12 12:03:10 AM UTC 24 Oct 12 12:05:37 AM UTC 24 366038097 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.4119508475 Oct 12 12:03:31 AM UTC 24 Oct 12 12:05:40 AM UTC 24 1416754621 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.157320750 Oct 12 12:04:18 AM UTC 24 Oct 12 12:05:42 AM UTC 24 304212253 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.4086519709 Oct 11 11:59:25 PM UTC 24 Oct 12 12:05:45 AM UTC 24 8112076061 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3826620485 Oct 12 12:03:46 AM UTC 24 Oct 12 12:05:47 AM UTC 24 29115240202 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3155225851 Oct 12 12:02:17 AM UTC 24 Oct 12 12:05:48 AM UTC 24 28625166833 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.761223366 Oct 12 12:03:00 AM UTC 24 Oct 12 12:05:49 AM UTC 24 24846858480 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3003339863 Oct 12 12:01:04 AM UTC 24 Oct 12 12:05:56 AM UTC 24 1971933704 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.3631352073 Oct 12 12:03:45 AM UTC 24 Oct 12 12:05:59 AM UTC 24 67291240741 ps
T888 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4102886529 Oct 11 11:58:20 PM UTC 24 Oct 12 12:06:06 AM UTC 24 4203372672 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.748788748 Oct 12 12:02:08 AM UTC 24 Oct 12 12:06:08 AM UTC 24 1605490790 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1450721353 Oct 12 12:03:23 AM UTC 24 Oct 12 12:06:16 AM UTC 24 47935677014 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.812444206 Oct 12 12:03:13 AM UTC 24 Oct 12 12:07:06 AM UTC 24 2314288823 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2884758054 Oct 11 11:57:59 PM UTC 24 Oct 12 12:07:07 AM UTC 24 15860869531 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3130246935 Oct 11 11:59:27 PM UTC 24 Oct 12 12:07:08 AM UTC 24 15130942165 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.298025086 Oct 12 12:03:31 AM UTC 24 Oct 12 12:07:51 AM UTC 24 847156860 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1886285089 Oct 12 12:02:45 AM UTC 24 Oct 12 12:07:53 AM UTC 24 84833877258 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3710541376 Oct 12 12:04:05 AM UTC 24 Oct 12 12:07:54 AM UTC 24 7090098768 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2032725608 Oct 12 12:04:18 AM UTC 24 Oct 12 12:08:05 AM UTC 24 15658478589 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3219834882 Oct 12 12:03:31 AM UTC 24 Oct 12 12:08:11 AM UTC 24 3116942895 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1323733122 Oct 12 12:02:27 AM UTC 24 Oct 12 12:08:15 AM UTC 24 4040183328 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3094866787 Oct 12 12:04:18 AM UTC 24 Oct 12 12:09:03 AM UTC 24 8759081079 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.3186203857 Oct 12 12:03:10 AM UTC 24 Oct 12 12:09:08 AM UTC 24 31957741280 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3587212877 Oct 12 12:04:18 AM UTC 24 Oct 12 12:09:18 AM UTC 24 12403158473 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.316049988 Oct 12 12:00:09 AM UTC 24 Oct 12 12:09:42 AM UTC 24 16286003306 ps
T900 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2070309558 Oct 12 12:03:51 AM UTC 24 Oct 12 12:10:15 AM UTC 24 38388792196 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.292867069 Oct 12 12:02:02 AM UTC 24 Oct 12 12:11:34 AM UTC 24 3074898713 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2090615236
Short name T13
Test name
Test status
Simulation time 474269833 ps
CPU time 19.22 seconds
Started Oct 11 11:46:21 PM UTC 24
Finished Oct 11 11:46:41 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090615236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2090615236
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.3356107573
Short name T88
Test name
Test status
Simulation time 5219352853 ps
CPU time 81.84 seconds
Started Oct 11 11:48:07 PM UTC 24
Finished Oct 11 11:49:31 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356107573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3356107573
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.394263731
Short name T281
Test name
Test status
Simulation time 39219932875 ps
CPU time 292.98 seconds
Started Oct 11 11:49:42 PM UTC 24
Finished Oct 11 11:54:39 PM UTC 24
Peak memory 216936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394263731 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.394263731
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.2463320782
Short name T94
Test name
Test status
Simulation time 11087495615 ps
CPU time 255.43 seconds
Started Oct 11 11:47:39 PM UTC 24
Finished Oct 11 11:51:58 PM UTC 24
Peak memory 220836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463320782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2463320782
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.2993558308
Short name T54
Test name
Test status
Simulation time 1383836371 ps
CPU time 43.97 seconds
Started Oct 11 11:46:18 PM UTC 24
Finished Oct 11 11:47:05 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993558308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2993558308
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.1651458895
Short name T90
Test name
Test status
Simulation time 1470459055 ps
CPU time 52.29 seconds
Started Oct 11 11:48:57 PM UTC 24
Finished Oct 11 11:49:51 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651458895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1651458895
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.712665608
Short name T53
Test name
Test status
Simulation time 2054867836 ps
CPU time 30.8 seconds
Started Oct 11 11:46:31 PM UTC 24
Finished Oct 11 11:47:04 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712665608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.712665608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.1602042018
Short name T9
Test name
Test status
Simulation time 358247140 ps
CPU time 8.17 seconds
Started Oct 11 11:46:19 PM UTC 24
Finished Oct 11 11:46:29 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602042018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1602042018
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.2558496200
Short name T4
Test name
Test status
Simulation time 182522091 ps
CPU time 6.41 seconds
Started Oct 11 11:46:39 PM UTC 24
Finished Oct 11 11:46:46 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558496200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2558496200
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.463182779
Short name T40
Test name
Test status
Simulation time 1866482134 ps
CPU time 94.82 seconds
Started Oct 11 11:46:28 PM UTC 24
Finished Oct 11 11:48:05 PM UTC 24
Peak memory 218832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463182779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.463182779
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3954807456
Short name T27
Test name
Test status
Simulation time 17650935054 ps
CPU time 39.39 seconds
Started Oct 11 11:46:16 PM UTC 24
Finished Oct 11 11:46:57 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954807456 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3954807456
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2162174031
Short name T129
Test name
Test status
Simulation time 17838931557 ps
CPU time 132.49 seconds
Started Oct 11 11:56:49 PM UTC 24
Finished Oct 11 11:59:04 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162174031 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.2162174031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.1680614627
Short name T14
Test name
Test status
Simulation time 2067523729 ps
CPU time 18.97 seconds
Started Oct 11 11:46:30 PM UTC 24
Finished Oct 11 11:46:50 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680614627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1680614627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3754564874
Short name T29
Test name
Test status
Simulation time 617657577 ps
CPU time 140.84 seconds
Started Oct 11 11:48:00 PM UTC 24
Finished Oct 11 11:50:23 PM UTC 24
Peak memory 220780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754564874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.3754564874
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.3373185226
Short name T84
Test name
Test status
Simulation time 1205116458 ps
CPU time 50.77 seconds
Started Oct 11 11:47:52 PM UTC 24
Finished Oct 11 11:48:45 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373185226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3373185226
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.252563283
Short name T49
Test name
Test status
Simulation time 353499603 ps
CPU time 122.17 seconds
Started Oct 11 11:47:45 PM UTC 24
Finished Oct 11 11:49:50 PM UTC 24
Peak memory 220976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252563283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.252563283
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.3398080109
Short name T112
Test name
Test status
Simulation time 5675513744 ps
CPU time 85.69 seconds
Started Oct 11 11:50:53 PM UTC 24
Finished Oct 11 11:52:21 PM UTC 24
Peak memory 218788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398080109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3398080109
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3532115828
Short name T6
Test name
Test status
Simulation time 8367216038 ps
CPU time 79.44 seconds
Started Oct 11 11:46:31 PM UTC 24
Finished Oct 11 11:47:53 PM UTC 24
Peak memory 214888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532115828 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3532115828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3798550750
Short name T297
Test name
Test status
Simulation time 541943754 ps
CPU time 203.59 seconds
Started Oct 11 11:49:34 PM UTC 24
Finished Oct 11 11:53:01 PM UTC 24
Peak memory 221092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798550750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3798550750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.1072646713
Short name T1
Test name
Test status
Simulation time 155436567 ps
CPU time 4.09 seconds
Started Oct 11 11:46:15 PM UTC 24
Finished Oct 11 11:46:20 PM UTC 24
Peak memory 214672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072646713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1072646713
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.859475649
Short name T295
Test name
Test status
Simulation time 432422807 ps
CPU time 113.09 seconds
Started Oct 11 11:53:36 PM UTC 24
Finished Oct 11 11:55:31 PM UTC 24
Peak memory 220784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859475649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.859475649
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2884758054
Short name T32
Test name
Test status
Simulation time 15860869531 ps
CPU time 541.33 seconds
Started Oct 11 11:57:59 PM UTC 24
Finished Oct 12 12:07:07 AM UTC 24
Peak memory 234960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884758054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.2884758054
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1313843088
Short name T186
Test name
Test status
Simulation time 36505790053 ps
CPU time 196.95 seconds
Started Oct 11 11:52:20 PM UTC 24
Finished Oct 11 11:55:39 PM UTC 24
Peak memory 216936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313843088 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.1313843088
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3506889427
Short name T60
Test name
Test status
Simulation time 31983573470 ps
CPU time 250.78 seconds
Started Oct 11 11:46:52 PM UTC 24
Finished Oct 11 11:51:06 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506889427 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.3506889427
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3576085001
Short name T42
Test name
Test status
Simulation time 4531269637 ps
CPU time 431 seconds
Started Oct 11 11:50:09 PM UTC 24
Finished Oct 11 11:57:26 PM UTC 24
Peak memory 232908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576085001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3576085001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1945710287
Short name T45
Test name
Test status
Simulation time 12976870103 ps
CPU time 449.21 seconds
Started Oct 11 11:56:11 PM UTC 24
Finished Oct 12 12:03:46 AM UTC 24
Peak memory 222652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945710287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.1945710287
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.284189569
Short name T123
Test name
Test status
Simulation time 825872027 ps
CPU time 90.55 seconds
Started Oct 11 11:46:22 PM UTC 24
Finished Oct 11 11:47:54 PM UTC 24
Peak memory 218728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284189569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.284189569
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.4186942824
Short name T162
Test name
Test status
Simulation time 27738875827 ps
CPU time 225.53 seconds
Started Oct 11 11:46:18 PM UTC 24
Finished Oct 11 11:50:08 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186942824 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.4186942824
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.2471240088
Short name T7
Test name
Test status
Simulation time 434501840 ps
CPU time 10.01 seconds
Started Oct 11 11:46:19 PM UTC 24
Finished Oct 11 11:46:30 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471240088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2471240088
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.2799688355
Short name T3
Test name
Test status
Simulation time 194601613 ps
CPU time 8.9 seconds
Started Oct 11 11:46:16 PM UTC 24
Finished Oct 11 11:46:26 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799688355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2799688355
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.261656861
Short name T229
Test name
Test status
Simulation time 35605208351 ps
CPU time 106.92 seconds
Started Oct 11 11:46:17 PM UTC 24
Finished Oct 11 11:48:06 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261656861 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.261656861
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1476045050
Short name T155
Test name
Test status
Simulation time 12355068871 ps
CPU time 84.83 seconds
Started Oct 11 11:46:18 PM UTC 24
Finished Oct 11 11:47:46 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476045050 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1476045050
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.361663975
Short name T8
Test name
Test status
Simulation time 259026691 ps
CPU time 10.38 seconds
Started Oct 11 11:46:16 PM UTC 24
Finished Oct 11 11:46:28 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361663975 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.361663975
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3219690497
Short name T25
Test name
Test status
Simulation time 2743095779 ps
CPU time 24.16 seconds
Started Oct 11 11:46:16 PM UTC 24
Finished Oct 11 11:46:42 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219690497 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3219690497
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3965998317
Short name T2
Test name
Test status
Simulation time 40075300 ps
CPU time 3.18 seconds
Started Oct 11 11:46:16 PM UTC 24
Finished Oct 11 11:46:20 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965998317 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3965998317
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.483389512
Short name T214
Test name
Test status
Simulation time 14561048175 ps
CPU time 202.22 seconds
Started Oct 11 11:46:27 PM UTC 24
Finished Oct 11 11:49:52 PM UTC 24
Peak memory 218792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483389512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.483389512
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1604802234
Short name T223
Test name
Test status
Simulation time 389256331 ps
CPU time 135.23 seconds
Started Oct 11 11:46:27 PM UTC 24
Finished Oct 11 11:48:44 PM UTC 24
Peak memory 218852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604802234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.1604802234
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.3566599299
Short name T12
Test name
Test status
Simulation time 567517358 ps
CPU time 15.98 seconds
Started Oct 11 11:46:20 PM UTC 24
Finished Oct 11 11:46:38 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566599299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3566599299
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2524466635
Short name T113
Test name
Test status
Simulation time 43245388795 ps
CPU time 351.99 seconds
Started Oct 11 11:46:33 PM UTC 24
Finished Oct 11 11:52:30 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524466635 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2524466635
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1728008120
Short name T15
Test name
Test status
Simulation time 155468318 ps
CPU time 16.92 seconds
Started Oct 11 11:46:40 PM UTC 24
Finished Oct 11 11:46:58 PM UTC 24
Peak memory 214828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728008120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1728008120
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.3397332064
Short name T101
Test name
Test status
Simulation time 49647496966 ps
CPU time 135.38 seconds
Started Oct 11 11:46:31 PM UTC 24
Finished Oct 11 11:48:49 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397332064 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3397332064
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.1614566997
Short name T16
Test name
Test status
Simulation time 616490091 ps
CPU time 29.95 seconds
Started Oct 11 11:46:31 PM UTC 24
Finished Oct 11 11:47:03 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614566997 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1614566997
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.2113367696
Short name T52
Test name
Test status
Simulation time 542679785 ps
CPU time 15.04 seconds
Started Oct 11 11:46:35 PM UTC 24
Finished Oct 11 11:46:51 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113367696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2113367696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.3717402000
Short name T10
Test name
Test status
Simulation time 163393564 ps
CPU time 3.45 seconds
Started Oct 11 11:46:28 PM UTC 24
Finished Oct 11 11:46:32 PM UTC 24
Peak memory 214564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717402000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3717402000
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.787975688
Short name T98
Test name
Test status
Simulation time 8288061515 ps
CPU time 63.22 seconds
Started Oct 11 11:46:29 PM UTC 24
Finished Oct 11 11:47:34 PM UTC 24
Peak memory 214136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787975688 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.787975688
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.1856164633
Short name T157
Test name
Test status
Simulation time 16824226923 ps
CPU time 29.67 seconds
Started Oct 11 11:46:29 PM UTC 24
Finished Oct 11 11:47:00 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856164633 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1856164633
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1651595871
Short name T11
Test name
Test status
Simulation time 40936233 ps
CPU time 3.39 seconds
Started Oct 11 11:46:29 PM UTC 24
Finished Oct 11 11:46:34 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651595871 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1651595871
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.2053553560
Short name T35
Test name
Test status
Simulation time 685476069 ps
CPU time 109.92 seconds
Started Oct 11 11:46:41 PM UTC 24
Finished Oct 11 11:48:33 PM UTC 24
Peak memory 218728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053553560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2053553560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1051328333
Short name T277
Test name
Test status
Simulation time 3408280149 ps
CPU time 111.44 seconds
Started Oct 11 11:46:42 PM UTC 24
Finished Oct 11 11:48:36 PM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051328333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1051328333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2299775095
Short name T39
Test name
Test status
Simulation time 3444440079 ps
CPU time 285.11 seconds
Started Oct 11 11:46:42 PM UTC 24
Finished Oct 11 11:51:31 PM UTC 24
Peak memory 220840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299775095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.2299775095
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.662373143
Short name T195
Test name
Test status
Simulation time 1510148345 ps
CPU time 207.03 seconds
Started Oct 11 11:46:42 PM UTC 24
Finished Oct 11 11:50:12 PM UTC 24
Peak memory 231340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662373143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.662373143
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.264953514
Short name T37
Test name
Test status
Simulation time 239003842 ps
CPU time 10.53 seconds
Started Oct 11 11:46:40 PM UTC 24
Finished Oct 11 11:46:51 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264953514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.264953514
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.125355112
Short name T58
Test name
Test status
Simulation time 298303141 ps
CPU time 34.29 seconds
Started Oct 11 11:49:41 PM UTC 24
Finished Oct 11 11:50:17 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125355112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.125355112
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2803985907
Short name T217
Test name
Test status
Simulation time 251414381 ps
CPU time 4.88 seconds
Started Oct 11 11:49:49 PM UTC 24
Finished Oct 11 11:49:55 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803985907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2803985907
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.948074546
Short name T218
Test name
Test status
Simulation time 174024664 ps
CPU time 11.14 seconds
Started Oct 11 11:49:43 PM UTC 24
Finished Oct 11 11:49:56 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948074546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.948074546
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.4108150909
Short name T153
Test name
Test status
Simulation time 1049268700 ps
CPU time 30.38 seconds
Started Oct 11 11:49:39 PM UTC 24
Finished Oct 11 11:50:11 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108150909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.4108150909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.2785891519
Short name T348
Test name
Test status
Simulation time 16120057246 ps
CPU time 121.83 seconds
Started Oct 11 11:49:39 PM UTC 24
Finished Oct 11 11:51:43 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785891519 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2785891519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.441089362
Short name T340
Test name
Test status
Simulation time 11496951417 ps
CPU time 77.53 seconds
Started Oct 11 11:49:40 PM UTC 24
Finished Oct 11 11:50:59 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441089362 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.441089362
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.3640128728
Short name T334
Test name
Test status
Simulation time 427405437 ps
CPU time 27.09 seconds
Started Oct 11 11:49:39 PM UTC 24
Finished Oct 11 11:50:07 PM UTC 24
Peak memory 214816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640128728 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3640128728
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.663796877
Short name T170
Test name
Test status
Simulation time 2825975104 ps
CPU time 39.45 seconds
Started Oct 11 11:49:43 PM UTC 24
Finished Oct 11 11:50:24 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663796877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.663796877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.3819212973
Short name T323
Test name
Test status
Simulation time 44294888 ps
CPU time 2.39 seconds
Started Oct 11 11:49:35 PM UTC 24
Finished Oct 11 11:49:39 PM UTC 24
Peak memory 214716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819212973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3819212973
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2205698919
Short name T194
Test name
Test status
Simulation time 4710885414 ps
CPU time 33.03 seconds
Started Oct 11 11:49:37 PM UTC 24
Finished Oct 11 11:50:11 PM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205698919 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2205698919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1285580053
Short name T335
Test name
Test status
Simulation time 9512692906 ps
CPU time 28.68 seconds
Started Oct 11 11:49:38 PM UTC 24
Finished Oct 11 11:50:08 PM UTC 24
Peak memory 214656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285580053 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1285580053
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2080335397
Short name T325
Test name
Test status
Simulation time 113805956 ps
CPU time 3.31 seconds
Started Oct 11 11:49:37 PM UTC 24
Finished Oct 11 11:49:41 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080335397 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2080335397
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.1399627446
Short name T402
Test name
Test status
Simulation time 1550554722 ps
CPU time 213.7 seconds
Started Oct 11 11:49:51 PM UTC 24
Finished Oct 11 11:53:28 PM UTC 24
Peak memory 218984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399627446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1399627446
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.462247433
Short name T333
Test name
Test status
Simulation time 583097790 ps
CPU time 12.46 seconds
Started Oct 11 11:49:53 PM UTC 24
Finished Oct 11 11:50:07 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462247433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.462247433
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2610894799
Short name T542
Test name
Test status
Simulation time 7885120045 ps
CPU time 428.59 seconds
Started Oct 11 11:49:51 PM UTC 24
Finished Oct 11 11:57:05 PM UTC 24
Peak memory 234956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610894799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.2610894799
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1259646688
Short name T381
Test name
Test status
Simulation time 1657160663 ps
CPU time 177.88 seconds
Started Oct 11 11:49:53 PM UTC 24
Finished Oct 11 11:52:54 PM UTC 24
Peak memory 221092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259646688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.1259646688
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.3579853546
Short name T215
Test name
Test status
Simulation time 118361903 ps
CPU time 6.9 seconds
Started Oct 11 11:49:45 PM UTC 24
Finished Oct 11 11:49:53 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579853546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3579853546
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.654161634
Short name T196
Test name
Test status
Simulation time 69293268 ps
CPU time 10.59 seconds
Started Oct 11 11:50:03 PM UTC 24
Finished Oct 11 11:50:15 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654161634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.654161634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.51971165
Short name T280
Test name
Test status
Simulation time 90106280011 ps
CPU time 256.17 seconds
Started Oct 11 11:50:04 PM UTC 24
Finished Oct 11 11:54:24 PM UTC 24
Peak memory 216936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51971165 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.51971165
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3387004931
Short name T339
Test name
Test status
Simulation time 191790000 ps
CPU time 22.59 seconds
Started Oct 11 11:50:09 PM UTC 24
Finished Oct 11 11:50:33 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387004931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3387004931
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.870884644
Short name T193
Test name
Test status
Simulation time 132360174 ps
CPU time 4.03 seconds
Started Oct 11 11:50:06 PM UTC 24
Finished Oct 11 11:50:11 PM UTC 24
Peak memory 214592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870884644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.870884644
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.1795176230
Short name T169
Test name
Test status
Simulation time 175619511 ps
CPU time 19.36 seconds
Started Oct 11 11:49:59 PM UTC 24
Finished Oct 11 11:50:19 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795176230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1795176230
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.3259069144
Short name T197
Test name
Test status
Simulation time 3359096571 ps
CPU time 14.07 seconds
Started Oct 11 11:50:00 PM UTC 24
Finished Oct 11 11:50:15 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259069144 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3259069144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3938474460
Short name T185
Test name
Test status
Simulation time 11704032824 ps
CPU time 84.76 seconds
Started Oct 11 11:50:01 PM UTC 24
Finished Oct 11 11:51:28 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938474460 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3938474460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.1028545378
Short name T320
Test name
Test status
Simulation time 291259411 ps
CPU time 13.3 seconds
Started Oct 11 11:50:00 PM UTC 24
Finished Oct 11 11:50:14 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028545378 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1028545378
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.2487148601
Short name T248
Test name
Test status
Simulation time 912614621 ps
CPU time 28.29 seconds
Started Oct 11 11:50:04 PM UTC 24
Finished Oct 11 11:50:34 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487148601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2487148601
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.363253200
Short name T152
Test name
Test status
Simulation time 280609355 ps
CPU time 5.03 seconds
Started Oct 11 11:49:53 PM UTC 24
Finished Oct 11 11:49:59 PM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363253200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.363253200
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.226712838
Short name T337
Test name
Test status
Simulation time 3740693477 ps
CPU time 31.88 seconds
Started Oct 11 11:49:57 PM UTC 24
Finished Oct 11 11:50:30 PM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226712838 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.226712838
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1662499042
Short name T252
Test name
Test status
Simulation time 16352760353 ps
CPU time 40.98 seconds
Started Oct 11 11:49:59 PM UTC 24
Finished Oct 11 11:50:41 PM UTC 24
Peak memory 214656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662499042 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1662499042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2528758134
Short name T329
Test name
Test status
Simulation time 52547842 ps
CPU time 3.22 seconds
Started Oct 11 11:49:55 PM UTC 24
Finished Oct 11 11:50:00 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528758134 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2528758134
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.3479263596
Short name T232
Test name
Test status
Simulation time 881063561 ps
CPU time 36.39 seconds
Started Oct 11 11:50:09 PM UTC 24
Finished Oct 11 11:50:47 PM UTC 24
Peak memory 216664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479263596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3479263596
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3768541119
Short name T282
Test name
Test status
Simulation time 7657562137 ps
CPU time 241.22 seconds
Started Oct 11 11:50:11 PM UTC 24
Finished Oct 11 11:54:17 PM UTC 24
Peak memory 220844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768541119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3768541119
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1798146326
Short name T270
Test name
Test status
Simulation time 223422256 ps
CPU time 82.45 seconds
Started Oct 11 11:50:11 PM UTC 24
Finished Oct 11 11:51:36 PM UTC 24
Peak memory 220780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798146326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.1798146326
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.208902131
Short name T338
Test name
Test status
Simulation time 103913651 ps
CPU time 22.86 seconds
Started Oct 11 11:50:08 PM UTC 24
Finished Oct 11 11:50:32 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208902131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.208902131
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.1238762848
Short name T200
Test name
Test status
Simulation time 853381118 ps
CPU time 16.74 seconds
Started Oct 11 11:50:20 PM UTC 24
Finished Oct 11 11:50:38 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238762848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1238762848
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2935859052
Short name T291
Test name
Test status
Simulation time 35155008618 ps
CPU time 115.42 seconds
Started Oct 11 11:50:22 PM UTC 24
Finished Oct 11 11:52:20 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935859052 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.2935859052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1274441395
Short name T249
Test name
Test status
Simulation time 80482487 ps
CPU time 4.85 seconds
Started Oct 11 11:50:30 PM UTC 24
Finished Oct 11 11:50:36 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274441395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1274441395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.4208038968
Short name T236
Test name
Test status
Simulation time 1527731320 ps
CPU time 30.74 seconds
Started Oct 11 11:50:24 PM UTC 24
Finished Oct 11 11:50:57 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208038968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.4208038968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.462450860
Short name T226
Test name
Test status
Simulation time 795899638 ps
CPU time 35.13 seconds
Started Oct 11 11:50:16 PM UTC 24
Finished Oct 11 11:50:53 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462450860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.462450860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.4191214937
Short name T62
Test name
Test status
Simulation time 41549128339 ps
CPU time 89.35 seconds
Started Oct 11 11:50:19 PM UTC 24
Finished Oct 11 11:51:50 PM UTC 24
Peak memory 214764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191214937 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.4191214937
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3503480501
Short name T263
Test name
Test status
Simulation time 3736911836 ps
CPU time 35.45 seconds
Started Oct 11 11:50:20 PM UTC 24
Finished Oct 11 11:50:57 PM UTC 24
Peak memory 214952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503480501 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3503480501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.3623115257
Short name T253
Test name
Test status
Simulation time 378127588 ps
CPU time 24.21 seconds
Started Oct 11 11:50:17 PM UTC 24
Finished Oct 11 11:50:43 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623115257 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3623115257
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.2054846922
Short name T336
Test name
Test status
Simulation time 27622163 ps
CPU time 3.1 seconds
Started Oct 11 11:50:24 PM UTC 24
Finished Oct 11 11:50:29 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054846922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2054846922
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.3108533240
Short name T198
Test name
Test status
Simulation time 355829167 ps
CPU time 5.33 seconds
Started Oct 11 11:50:12 PM UTC 24
Finished Oct 11 11:50:18 PM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108533240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3108533240
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3851461969
Short name T233
Test name
Test status
Simulation time 10783967221 ps
CPU time 35.04 seconds
Started Oct 11 11:50:15 PM UTC 24
Finished Oct 11 11:50:52 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851461969 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3851461969
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2721328712
Short name T257
Test name
Test status
Simulation time 4189574940 ps
CPU time 49.85 seconds
Started Oct 11 11:50:16 PM UTC 24
Finished Oct 11 11:51:08 PM UTC 24
Peak memory 214656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721328712 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2721328712
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.744087092
Short name T199
Test name
Test status
Simulation time 61563401 ps
CPU time 3.6 seconds
Started Oct 11 11:50:14 PM UTC 24
Finished Oct 11 11:50:19 PM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744087092 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.744087092
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.241242394
Short name T400
Test name
Test status
Simulation time 3738899602 ps
CPU time 165.74 seconds
Started Oct 11 11:50:31 PM UTC 24
Finished Oct 11 11:53:20 PM UTC 24
Peak memory 220836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241242394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.241242394
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.545719448
Short name T380
Test name
Test status
Simulation time 4098864840 ps
CPU time 133.56 seconds
Started Oct 11 11:50:34 PM UTC 24
Finished Oct 11 11:52:50 PM UTC 24
Peak memory 218792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545719448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.545719448
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.55074474
Short name T239
Test name
Test status
Simulation time 5454940765 ps
CPU time 516.6 seconds
Started Oct 11 11:50:33 PM UTC 24
Finished Oct 11 11:59:16 PM UTC 24
Peak memory 232984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55074474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.55074474
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1192095751
Short name T487
Test name
Test status
Simulation time 6805774135 ps
CPU time 312.85 seconds
Started Oct 11 11:50:35 PM UTC 24
Finished Oct 11 11:55:52 PM UTC 24
Peak memory 231396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192095751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1192095751
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.3695256896
Short name T208
Test name
Test status
Simulation time 397715829 ps
CPU time 17.98 seconds
Started Oct 11 11:50:25 PM UTC 24
Finished Oct 11 11:50:45 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695256896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3695256896
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.3452783870
Short name T234
Test name
Test status
Simulation time 194649505 ps
CPU time 6.79 seconds
Started Oct 11 11:50:44 PM UTC 24
Finished Oct 11 11:50:52 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452783870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3452783870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.833845424
Short name T135
Test name
Test status
Simulation time 87774601445 ps
CPU time 357.19 seconds
Started Oct 11 11:50:44 PM UTC 24
Finished Oct 11 11:56:47 PM UTC 24
Peak memory 216936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833845424 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.833845424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1816832045
Short name T343
Test name
Test status
Simulation time 71769129 ps
CPU time 11.27 seconds
Started Oct 11 11:50:52 PM UTC 24
Finished Oct 11 11:51:04 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816832045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1816832045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.3250367069
Short name T258
Test name
Test status
Simulation time 187809605 ps
CPU time 21.43 seconds
Started Oct 11 11:50:47 PM UTC 24
Finished Oct 11 11:51:09 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250367069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3250367069
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.1329689281
Short name T259
Test name
Test status
Simulation time 285021624 ps
CPU time 29.89 seconds
Started Oct 11 11:50:40 PM UTC 24
Finished Oct 11 11:51:11 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329689281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1329689281
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.3242880449
Short name T269
Test name
Test status
Simulation time 15259482850 ps
CPU time 52.33 seconds
Started Oct 11 11:50:42 PM UTC 24
Finished Oct 11 11:51:36 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242880449 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3242880449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3233780006
Short name T373
Test name
Test status
Simulation time 9090632319 ps
CPU time 115.9 seconds
Started Oct 11 11:50:43 PM UTC 24
Finished Oct 11 11:52:41 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233780006 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3233780006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.802206929
Short name T235
Test name
Test status
Simulation time 97588008 ps
CPU time 11.49 seconds
Started Oct 11 11:50:42 PM UTC 24
Finished Oct 11 11:50:55 PM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802206929 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.802206929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1370555596
Short name T255
Test name
Test status
Simulation time 1219395394 ps
CPU time 35.3 seconds
Started Oct 11 11:50:46 PM UTC 24
Finished Oct 11 11:51:22 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370555596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1370555596
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.1276681251
Short name T250
Test name
Test status
Simulation time 67401145 ps
CPU time 2.93 seconds
Started Oct 11 11:50:35 PM UTC 24
Finished Oct 11 11:50:39 PM UTC 24
Peak memory 214588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276681251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1276681251
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.4048605320
Short name T262
Test name
Test status
Simulation time 8331425990 ps
CPU time 39.6 seconds
Started Oct 11 11:50:39 PM UTC 24
Finished Oct 11 11:51:20 PM UTC 24
Peak memory 214872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048605320 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.4048605320
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.396723604
Short name T61
Test name
Test status
Simulation time 16988223573 ps
CPU time 41.47 seconds
Started Oct 11 11:50:39 PM UTC 24
Finished Oct 11 11:51:21 PM UTC 24
Peak memory 214844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396723604 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.396723604
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2709697398
Short name T251
Test name
Test status
Simulation time 34699791 ps
CPU time 3.15 seconds
Started Oct 11 11:50:36 PM UTC 24
Finished Oct 11 11:50:41 PM UTC 24
Peak memory 214792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709697398 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2709697398
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3612528829
Short name T384
Test name
Test status
Simulation time 4720046975 ps
CPU time 122.48 seconds
Started Oct 11 11:50:53 PM UTC 24
Finished Oct 11 11:52:58 PM UTC 24
Peak memory 214700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612528829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3612528829
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.257991316
Short name T183
Test name
Test status
Simulation time 1521672421 ps
CPU time 302.52 seconds
Started Oct 11 11:50:53 PM UTC 24
Finished Oct 11 11:56:00 PM UTC 24
Peak memory 231292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257991316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.257991316
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.71662658
Short name T293
Test name
Test status
Simulation time 613115282 ps
CPU time 94.66 seconds
Started Oct 11 11:50:56 PM UTC 24
Finished Oct 11 11:52:32 PM UTC 24
Peak memory 220976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71662658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.71662658
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.237254249
Short name T247
Test name
Test status
Simulation time 514542812 ps
CPU time 21.24 seconds
Started Oct 11 11:50:48 PM UTC 24
Finished Oct 11 11:51:10 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237254249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.237254249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.49847230
Short name T261
Test name
Test status
Simulation time 80940565 ps
CPU time 4.22 seconds
Started Oct 11 11:51:07 PM UTC 24
Finished Oct 11 11:51:12 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49847230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.49847230
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2993398999
Short name T420
Test name
Test status
Simulation time 28683957862 ps
CPU time 170.7 seconds
Started Oct 11 11:51:08 PM UTC 24
Finished Oct 11 11:54:02 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993398999 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.2993398999
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3103414913
Short name T266
Test name
Test status
Simulation time 187285914 ps
CPU time 21.7 seconds
Started Oct 11 11:51:10 PM UTC 24
Finished Oct 11 11:51:33 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103414913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3103414913
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.1347381031
Short name T267
Test name
Test status
Simulation time 913659217 ps
CPU time 24.41 seconds
Started Oct 11 11:51:08 PM UTC 24
Finished Oct 11 11:51:34 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347381031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1347381031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.2346604384
Short name T344
Test name
Test status
Simulation time 36841357 ps
CPU time 2.94 seconds
Started Oct 11 11:51:02 PM UTC 24
Finished Oct 11 11:51:06 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346604384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2346604384
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.335478634
Short name T366
Test name
Test status
Simulation time 29419917544 ps
CPU time 80.5 seconds
Started Oct 11 11:51:06 PM UTC 24
Finished Oct 11 11:52:28 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335478634 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.335478634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1045100837
Short name T414
Test name
Test status
Simulation time 25817445970 ps
CPU time 160.53 seconds
Started Oct 11 11:51:07 PM UTC 24
Finished Oct 11 11:53:50 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045100837 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1045100837
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.1810336849
Short name T260
Test name
Test status
Simulation time 57890142 ps
CPU time 7.77 seconds
Started Oct 11 11:51:02 PM UTC 24
Finished Oct 11 11:51:11 PM UTC 24
Peak memory 214876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810336849 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1810336849
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.3028173437
Short name T265
Test name
Test status
Simulation time 1209104910 ps
CPU time 23.07 seconds
Started Oct 11 11:51:08 PM UTC 24
Finished Oct 11 11:51:33 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028173437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3028173437
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.1805501709
Short name T342
Test name
Test status
Simulation time 48875401 ps
CPU time 2.88 seconds
Started Oct 11 11:50:58 PM UTC 24
Finished Oct 11 11:51:02 PM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805501709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1805501709
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1574332436
Short name T268
Test name
Test status
Simulation time 4953110422 ps
CPU time 33.28 seconds
Started Oct 11 11:51:00 PM UTC 24
Finished Oct 11 11:51:35 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574332436 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1574332436
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.1654253513
Short name T355
Test name
Test status
Simulation time 6896508164 ps
CPU time 55.19 seconds
Started Oct 11 11:51:01 PM UTC 24
Finished Oct 11 11:51:58 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654253513 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1654253513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.2441410475
Short name T341
Test name
Test status
Simulation time 27974770 ps
CPU time 2.33 seconds
Started Oct 11 11:50:58 PM UTC 24
Finished Oct 11 11:51:01 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441410475 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2441410475
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.516534108
Short name T390
Test name
Test status
Simulation time 1968618737 ps
CPU time 114.61 seconds
Started Oct 11 11:51:11 PM UTC 24
Finished Oct 11 11:53:08 PM UTC 24
Peak memory 220772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516534108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.516534108
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1690575411
Short name T278
Test name
Test status
Simulation time 6856370120 ps
CPU time 113.74 seconds
Started Oct 11 11:51:12 PM UTC 24
Finished Oct 11 11:53:08 PM UTC 24
Peak memory 218776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690575411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1690575411
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.617184369
Short name T30
Test name
Test status
Simulation time 233212594 ps
CPU time 133.51 seconds
Started Oct 11 11:51:12 PM UTC 24
Finished Oct 11 11:53:28 PM UTC 24
Peak memory 218960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617184369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.617184369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.405246590
Short name T508
Test name
Test status
Simulation time 2357957370 ps
CPU time 291.76 seconds
Started Oct 11 11:51:14 PM UTC 24
Finished Oct 11 11:56:10 PM UTC 24
Peak memory 231592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405246590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.405246590
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.798454080
Short name T164
Test name
Test status
Simulation time 391656135 ps
CPU time 19.39 seconds
Started Oct 11 11:51:10 PM UTC 24
Finished Oct 11 11:51:31 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798454080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.798454080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.2954523435
Short name T34
Test name
Test status
Simulation time 2255499362 ps
CPU time 44.65 seconds
Started Oct 11 11:51:32 PM UTC 24
Finished Oct 11 11:52:18 PM UTC 24
Peak memory 216944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954523435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2954523435
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3131179378
Short name T481
Test name
Test status
Simulation time 29974401694 ps
CPU time 245.7 seconds
Started Oct 11 11:51:32 PM UTC 24
Finished Oct 11 11:55:41 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131179378 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.3131179378
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2454383855
Short name T349
Test name
Test status
Simulation time 597227596 ps
CPU time 8.87 seconds
Started Oct 11 11:51:35 PM UTC 24
Finished Oct 11 11:51:45 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454383855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2454383855
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.4035560080
Short name T352
Test name
Test status
Simulation time 760662388 ps
CPU time 18.57 seconds
Started Oct 11 11:51:34 PM UTC 24
Finished Oct 11 11:51:54 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035560080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.4035560080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.625880713
Short name T356
Test name
Test status
Simulation time 312186413 ps
CPU time 31.91 seconds
Started Oct 11 11:51:28 PM UTC 24
Finished Oct 11 11:52:02 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625880713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.625880713
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.1416143844
Short name T353
Test name
Test status
Simulation time 6010093074 ps
CPU time 23.55 seconds
Started Oct 11 11:51:30 PM UTC 24
Finished Oct 11 11:51:54 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416143844 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1416143844
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3442335127
Short name T404
Test name
Test status
Simulation time 15719157407 ps
CPU time 120.54 seconds
Started Oct 11 11:51:32 PM UTC 24
Finished Oct 11 11:53:35 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442335127 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3442335127
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.3057718139
Short name T63
Test name
Test status
Simulation time 198172414 ps
CPU time 22.74 seconds
Started Oct 11 11:51:28 PM UTC 24
Finished Oct 11 11:51:52 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057718139 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3057718139
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.382823641
Short name T365
Test name
Test status
Simulation time 3141052560 ps
CPU time 51.44 seconds
Started Oct 11 11:51:33 PM UTC 24
Finished Oct 11 11:52:26 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382823641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.382823641
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.1607084453
Short name T345
Test name
Test status
Simulation time 39366713 ps
CPU time 3.31 seconds
Started Oct 11 11:51:21 PM UTC 24
Finished Oct 11 11:51:25 PM UTC 24
Peak memory 214584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607084453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1607084453
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3371129177
Short name T354
Test name
Test status
Simulation time 12227748991 ps
CPU time 32.76 seconds
Started Oct 11 11:51:23 PM UTC 24
Finished Oct 11 11:51:57 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371129177 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3371129177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3490151563
Short name T359
Test name
Test status
Simulation time 3503087245 ps
CPU time 40.53 seconds
Started Oct 11 11:51:26 PM UTC 24
Finished Oct 11 11:52:08 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490151563 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3490151563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.592251815
Short name T346
Test name
Test status
Simulation time 49837779 ps
CPU time 3.13 seconds
Started Oct 11 11:51:23 PM UTC 24
Finished Oct 11 11:51:27 PM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592251815 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.592251815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.133501098
Short name T184
Test name
Test status
Simulation time 5695857172 ps
CPU time 62.9 seconds
Started Oct 11 11:51:36 PM UTC 24
Finished Oct 11 11:52:40 PM UTC 24
Peak memory 216936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133501098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.133501098
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3694577609
Short name T31
Test name
Test status
Simulation time 1132910788 ps
CPU time 110.14 seconds
Started Oct 11 11:51:37 PM UTC 24
Finished Oct 11 11:53:29 PM UTC 24
Peak memory 216684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694577609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3694577609
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3088997357
Short name T191
Test name
Test status
Simulation time 1960159816 ps
CPU time 107.63 seconds
Started Oct 11 11:51:37 PM UTC 24
Finished Oct 11 11:53:27 PM UTC 24
Peak memory 220772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088997357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.3088997357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1715868424
Short name T494
Test name
Test status
Simulation time 3042386717 ps
CPU time 259.02 seconds
Started Oct 11 11:51:37 PM UTC 24
Finished Oct 11 11:56:00 PM UTC 24
Peak memory 221156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715868424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.1715868424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.3922092290
Short name T272
Test name
Test status
Simulation time 505951941 ps
CPU time 20.17 seconds
Started Oct 11 11:51:34 PM UTC 24
Finished Oct 11 11:51:56 PM UTC 24
Peak memory 216672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922092290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3922092290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.4043321144
Short name T65
Test name
Test status
Simulation time 669998688 ps
CPU time 33.17 seconds
Started Oct 11 11:51:53 PM UTC 24
Finished Oct 11 11:52:28 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043321144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.4043321144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1945383207
Short name T446
Test name
Test status
Simulation time 37409220985 ps
CPU time 164.39 seconds
Started Oct 11 11:51:56 PM UTC 24
Finished Oct 11 11:54:42 PM UTC 24
Peak memory 216736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945383207 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.1945383207
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.4231026604
Short name T357
Test name
Test status
Simulation time 91926668 ps
CPU time 3.43 seconds
Started Oct 11 11:51:59 PM UTC 24
Finished Oct 11 11:52:03 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231026604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.4231026604
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.918815001
Short name T368
Test name
Test status
Simulation time 2772124194 ps
CPU time 31.92 seconds
Started Oct 11 11:51:57 PM UTC 24
Finished Oct 11 11:52:30 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918815001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.918815001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.786968099
Short name T351
Test name
Test status
Simulation time 17626574 ps
CPU time 2.73 seconds
Started Oct 11 11:51:47 PM UTC 24
Finished Oct 11 11:51:51 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786968099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.786968099
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.2370370679
Short name T407
Test name
Test status
Simulation time 66923413705 ps
CPU time 105.79 seconds
Started Oct 11 11:51:51 PM UTC 24
Finished Oct 11 11:53:39 PM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370370679 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2370370679
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2194648073
Short name T396
Test name
Test status
Simulation time 6711678811 ps
CPU time 80.76 seconds
Started Oct 11 11:51:52 PM UTC 24
Finished Oct 11 11:53:15 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194648073 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2194648073
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.1785131112
Short name T171
Test name
Test status
Simulation time 627921151 ps
CPU time 29.63 seconds
Started Oct 11 11:51:47 PM UTC 24
Finished Oct 11 11:52:18 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785131112 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1785131112
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.683088429
Short name T371
Test name
Test status
Simulation time 4616608205 ps
CPU time 38.46 seconds
Started Oct 11 11:51:56 PM UTC 24
Finished Oct 11 11:52:36 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683088429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.683088429
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.3815067367
Short name T347
Test name
Test status
Simulation time 108233136 ps
CPU time 4.23 seconds
Started Oct 11 11:51:37 PM UTC 24
Finished Oct 11 11:51:42 PM UTC 24
Peak memory 214584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815067367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3815067367
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2870958080
Short name T363
Test name
Test status
Simulation time 6123737551 ps
CPU time 33.26 seconds
Started Oct 11 11:51:44 PM UTC 24
Finished Oct 11 11:52:18 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870958080 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2870958080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1942444135
Short name T358
Test name
Test status
Simulation time 3897932145 ps
CPU time 22.4 seconds
Started Oct 11 11:51:44 PM UTC 24
Finished Oct 11 11:52:07 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942444135 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1942444135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1578381119
Short name T350
Test name
Test status
Simulation time 28542099 ps
CPU time 3.09 seconds
Started Oct 11 11:51:41 PM UTC 24
Finished Oct 11 11:51:46 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578381119 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1578381119
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.232259510
Short name T287
Test name
Test status
Simulation time 15285034224 ps
CPU time 157.14 seconds
Started Oct 11 11:51:59 PM UTC 24
Finished Oct 11 11:54:39 PM UTC 24
Peak memory 216936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232259510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.232259510
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2743943878
Short name T444
Test name
Test status
Simulation time 5114782435 ps
CPU time 151.13 seconds
Started Oct 11 11:52:04 PM UTC 24
Finished Oct 11 11:54:38 PM UTC 24
Peak memory 218796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743943878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2743943878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1044322492
Short name T364
Test name
Test status
Simulation time 75018315 ps
CPU time 20.36 seconds
Started Oct 11 11:52:02 PM UTC 24
Finished Oct 11 11:52:24 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044322492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.1044322492
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2362579803
Short name T670
Test name
Test status
Simulation time 2489448410 ps
CPU time 468.94 seconds
Started Oct 11 11:52:04 PM UTC 24
Finished Oct 12 12:00:00 AM UTC 24
Peak memory 232788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362579803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.2362579803
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.812287100
Short name T64
Test name
Test status
Simulation time 5008099245 ps
CPU time 28.72 seconds
Started Oct 11 11:51:58 PM UTC 24
Finished Oct 11 11:52:28 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812287100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.812287100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.1481321680
Short name T285
Test name
Test status
Simulation time 2143063467 ps
CPU time 46.63 seconds
Started Oct 11 11:52:20 PM UTC 24
Finished Oct 11 11:53:08 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481321680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1481321680
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3737510887
Short name T367
Test name
Test status
Simulation time 60037896 ps
CPU time 2.92 seconds
Started Oct 11 11:52:25 PM UTC 24
Finished Oct 11 11:52:29 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737510887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3737510887
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.808092519
Short name T372
Test name
Test status
Simulation time 271688208 ps
CPU time 16.06 seconds
Started Oct 11 11:52:22 PM UTC 24
Finished Oct 11 11:52:39 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808092519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.808092519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.657010095
Short name T362
Test name
Test status
Simulation time 26663945 ps
CPU time 3.15 seconds
Started Oct 11 11:52:13 PM UTC 24
Finished Oct 11 11:52:17 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657010095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.657010095
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.2649342405
Short name T440
Test name
Test status
Simulation time 66368100264 ps
CPU time 129.54 seconds
Started Oct 11 11:52:18 PM UTC 24
Finished Oct 11 11:54:30 PM UTC 24
Peak memory 214952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649342405 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2649342405
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3719132442
Short name T388
Test name
Test status
Simulation time 6921739321 ps
CPU time 43.25 seconds
Started Oct 11 11:52:19 PM UTC 24
Finished Oct 11 11:53:04 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719132442 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3719132442
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.4130454597
Short name T374
Test name
Test status
Simulation time 162286355 ps
CPU time 23.86 seconds
Started Oct 11 11:52:17 PM UTC 24
Finished Oct 11 11:52:42 PM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130454597 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.4130454597
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.319333237
Short name T376
Test name
Test status
Simulation time 449550129 ps
CPU time 22.39 seconds
Started Oct 11 11:52:21 PM UTC 24
Finished Oct 11 11:52:44 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319333237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.319333237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.365337030
Short name T360
Test name
Test status
Simulation time 42418333 ps
CPU time 3.03 seconds
Started Oct 11 11:52:07 PM UTC 24
Finished Oct 11 11:52:11 PM UTC 24
Peak memory 214804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365337030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.365337030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.244553675
Short name T378
Test name
Test status
Simulation time 8633232655 ps
CPU time 39.22 seconds
Started Oct 11 11:52:09 PM UTC 24
Finished Oct 11 11:52:50 PM UTC 24
Peak memory 214660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244553675 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.244553675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.490063159
Short name T124
Test name
Test status
Simulation time 5912999300 ps
CPU time 33.94 seconds
Started Oct 11 11:52:12 PM UTC 24
Finished Oct 11 11:52:47 PM UTC 24
Peak memory 214648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490063159 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.490063159
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.467278881
Short name T361
Test name
Test status
Simulation time 33334534 ps
CPU time 3.17 seconds
Started Oct 11 11:52:08 PM UTC 24
Finished Oct 11 11:52:12 PM UTC 24
Peak memory 214804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467278881 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.467278881
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.3096537973
Short name T375
Test name
Test status
Simulation time 829353373 ps
CPU time 16.48 seconds
Started Oct 11 11:52:25 PM UTC 24
Finished Oct 11 11:52:43 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096537973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3096537973
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3968719843
Short name T504
Test name
Test status
Simulation time 10862402955 ps
CPU time 215.12 seconds
Started Oct 11 11:52:29 PM UTC 24
Finished Oct 11 11:56:07 PM UTC 24
Peak memory 216752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968719843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3968719843
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1815929418
Short name T145
Test name
Test status
Simulation time 1367865948 ps
CPU time 74.87 seconds
Started Oct 11 11:52:27 PM UTC 24
Finished Oct 11 11:53:44 PM UTC 24
Peak memory 218984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815929418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.1815929418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3592969923
Short name T50
Test name
Test status
Simulation time 369512647 ps
CPU time 68.6 seconds
Started Oct 11 11:52:29 PM UTC 24
Finished Oct 11 11:53:39 PM UTC 24
Peak memory 218728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592969923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.3592969923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.1012591613
Short name T377
Test name
Test status
Simulation time 2610570038 ps
CPU time 20.65 seconds
Started Oct 11 11:52:24 PM UTC 24
Finished Oct 11 11:52:46 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012591613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1012591613
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.427529243
Short name T115
Test name
Test status
Simulation time 1919876352 ps
CPU time 57.95 seconds
Started Oct 11 11:52:40 PM UTC 24
Finished Oct 11 11:53:40 PM UTC 24
Peak memory 216936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427529243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.427529243
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2894792537
Short name T479
Test name
Test status
Simulation time 26809796496 ps
CPU time 175.47 seconds
Started Oct 11 11:52:42 PM UTC 24
Finished Oct 11 11:55:40 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894792537 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.2894792537
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2132683490
Short name T391
Test name
Test status
Simulation time 1223370939 ps
CPU time 22.12 seconds
Started Oct 11 11:52:45 PM UTC 24
Finished Oct 11 11:53:09 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132683490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2132683490
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.1333658517
Short name T403
Test name
Test status
Simulation time 1100172421 ps
CPU time 44.79 seconds
Started Oct 11 11:52:43 PM UTC 24
Finished Oct 11 11:53:29 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333658517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1333658517
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.4271821438
Short name T383
Test name
Test status
Simulation time 564979884 ps
CPU time 20.51 seconds
Started Oct 11 11:52:34 PM UTC 24
Finished Oct 11 11:52:56 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271821438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.4271821438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.1432369538
Short name T190
Test name
Test status
Simulation time 12255976705 ps
CPU time 23.42 seconds
Started Oct 11 11:52:37 PM UTC 24
Finished Oct 11 11:53:02 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432369538 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1432369538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3747201363
Short name T394
Test name
Test status
Simulation time 6591877015 ps
CPU time 34.46 seconds
Started Oct 11 11:52:37 PM UTC 24
Finished Oct 11 11:53:13 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747201363 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3747201363
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.3159031506
Short name T181
Test name
Test status
Simulation time 486776478 ps
CPU time 19.46 seconds
Started Oct 11 11:52:36 PM UTC 24
Finished Oct 11 11:52:57 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159031506 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3159031506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.2595925526
Short name T256
Test name
Test status
Simulation time 2676346933 ps
CPU time 29.78 seconds
Started Oct 11 11:52:43 PM UTC 24
Finished Oct 11 11:53:14 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595925526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2595925526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.143807967
Short name T370
Test name
Test status
Simulation time 272012494 ps
CPU time 4.25 seconds
Started Oct 11 11:52:30 PM UTC 24
Finished Oct 11 11:52:35 PM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143807967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.143807967
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.789237032
Short name T389
Test name
Test status
Simulation time 7264064116 ps
CPU time 33.61 seconds
Started Oct 11 11:52:31 PM UTC 24
Finished Oct 11 11:53:06 PM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789237032 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.789237032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1422253471
Short name T387
Test name
Test status
Simulation time 5654396184 ps
CPU time 31.15 seconds
Started Oct 11 11:52:31 PM UTC 24
Finished Oct 11 11:53:04 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422253471 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1422253471
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.261200606
Short name T369
Test name
Test status
Simulation time 67859475 ps
CPU time 3.39 seconds
Started Oct 11 11:52:30 PM UTC 24
Finished Oct 11 11:52:34 PM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261200606 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.261200606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.2075289349
Short name T543
Test name
Test status
Simulation time 10942629251 ps
CPU time 256.79 seconds
Started Oct 11 11:52:46 PM UTC 24
Finished Oct 11 11:57:07 PM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075289349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2075289349
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.385900815
Short name T447
Test name
Test status
Simulation time 5422452728 ps
CPU time 109.94 seconds
Started Oct 11 11:52:51 PM UTC 24
Finished Oct 11 11:54:43 PM UTC 24
Peak memory 218796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385900815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.385900815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1166369564
Short name T653
Test name
Test status
Simulation time 1420388999 ps
CPU time 402.2 seconds
Started Oct 11 11:52:49 PM UTC 24
Finished Oct 11 11:59:36 PM UTC 24
Peak memory 221164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166369564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1166369564
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2104435820
Short name T596
Test name
Test status
Simulation time 13455915723 ps
CPU time 315.71 seconds
Started Oct 11 11:52:51 PM UTC 24
Finished Oct 11 11:58:11 PM UTC 24
Peak memory 220844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104435820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.2104435820
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.959274802
Short name T379
Test name
Test status
Simulation time 27910324 ps
CPU time 4.58 seconds
Started Oct 11 11:52:44 PM UTC 24
Finished Oct 11 11:52:50 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959274802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.959274802
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.4057569939
Short name T254
Test name
Test status
Simulation time 315927062 ps
CPU time 14.38 seconds
Started Oct 11 11:53:03 PM UTC 24
Finished Oct 11 11:53:19 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057569939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.4057569939
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2926100850
Short name T290
Test name
Test status
Simulation time 98662920829 ps
CPU time 375.56 seconds
Started Oct 11 11:53:04 PM UTC 24
Finished Oct 11 11:59:24 PM UTC 24
Peak memory 216936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926100850 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2926100850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.196724753
Short name T406
Test name
Test status
Simulation time 730035738 ps
CPU time 27.65 seconds
Started Oct 11 11:53:09 PM UTC 24
Finished Oct 11 11:53:38 PM UTC 24
Peak memory 214828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196724753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.196724753
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1477539538
Short name T395
Test name
Test status
Simulation time 64398148 ps
CPU time 7.19 seconds
Started Oct 11 11:53:05 PM UTC 24
Finished Oct 11 11:53:14 PM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477539538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1477539538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.2932376030
Short name T386
Test name
Test status
Simulation time 80027176 ps
CPU time 4.3 seconds
Started Oct 11 11:52:58 PM UTC 24
Finished Oct 11 11:53:04 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932376030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2932376030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.441391134
Short name T457
Test name
Test status
Simulation time 26170347596 ps
CPU time 110.32 seconds
Started Oct 11 11:53:01 PM UTC 24
Finished Oct 11 11:54:53 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441391134 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.441391134
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2388267570
Short name T423
Test name
Test status
Simulation time 7719504296 ps
CPU time 60.74 seconds
Started Oct 11 11:53:02 PM UTC 24
Finished Oct 11 11:54:04 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388267570 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2388267570
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.2352571024
Short name T392
Test name
Test status
Simulation time 81663889 ps
CPU time 8.46 seconds
Started Oct 11 11:52:59 PM UTC 24
Finished Oct 11 11:53:09 PM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352571024 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2352571024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.143275601
Short name T399
Test name
Test status
Simulation time 218749209 ps
CPU time 12.24 seconds
Started Oct 11 11:53:05 PM UTC 24
Finished Oct 11 11:53:19 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143275601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.143275601
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.3345195689
Short name T382
Test name
Test status
Simulation time 51596817 ps
CPU time 3.28 seconds
Started Oct 11 11:52:51 PM UTC 24
Finished Oct 11 11:52:55 PM UTC 24
Peak memory 214776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345195689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3345195689
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2184660271
Short name T417
Test name
Test status
Simulation time 19509978304 ps
CPU time 54.83 seconds
Started Oct 11 11:52:57 PM UTC 24
Finished Oct 11 11:53:53 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184660271 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2184660271
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3796863889
Short name T408
Test name
Test status
Simulation time 3968710754 ps
CPU time 43.55 seconds
Started Oct 11 11:52:57 PM UTC 24
Finished Oct 11 11:53:42 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796863889 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3796863889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2355245288
Short name T385
Test name
Test status
Simulation time 89968112 ps
CPU time 3.47 seconds
Started Oct 11 11:52:56 PM UTC 24
Finished Oct 11 11:53:00 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355245288 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2355245288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.3905089589
Short name T475
Test name
Test status
Simulation time 4353253170 ps
CPU time 142.03 seconds
Started Oct 11 11:53:09 PM UTC 24
Finished Oct 11 11:55:33 PM UTC 24
Peak memory 220696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905089589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3905089589
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2576298237
Short name T426
Test name
Test status
Simulation time 2021803114 ps
CPU time 55.14 seconds
Started Oct 11 11:53:10 PM UTC 24
Finished Oct 11 11:54:07 PM UTC 24
Peak memory 214640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576298237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2576298237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3288797565
Short name T581
Test name
Test status
Simulation time 5577147778 ps
CPU time 278.98 seconds
Started Oct 11 11:53:09 PM UTC 24
Finished Oct 11 11:57:52 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288797565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.3288797565
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3702488239
Short name T565
Test name
Test status
Simulation time 1089036797 ps
CPU time 263.19 seconds
Started Oct 11 11:53:10 PM UTC 24
Finished Oct 11 11:57:37 PM UTC 24
Peak memory 221092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702488239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.3702488239
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.762667424
Short name T393
Test name
Test status
Simulation time 14024206 ps
CPU time 2.87 seconds
Started Oct 11 11:53:08 PM UTC 24
Finished Oct 11 11:53:12 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762667424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.762667424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.1521377011
Short name T20
Test name
Test status
Simulation time 1874581048 ps
CPU time 26.99 seconds
Started Oct 11 11:46:52 PM UTC 24
Finished Oct 11 11:47:20 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521377011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1521377011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3684696882
Short name T18
Test name
Test status
Simulation time 322098283 ps
CPU time 19.02 seconds
Started Oct 11 11:46:57 PM UTC 24
Finished Oct 11 11:47:18 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684696882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3684696882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.1649820504
Short name T158
Test name
Test status
Simulation time 195755184 ps
CPU time 5.17 seconds
Started Oct 11 11:46:53 PM UTC 24
Finished Oct 11 11:46:59 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649820504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1649820504
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.3175561492
Short name T17
Test name
Test status
Simulation time 199904550 ps
CPU time 25.09 seconds
Started Oct 11 11:46:48 PM UTC 24
Finished Oct 11 11:47:15 PM UTC 24
Peak memory 214892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175561492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3175561492
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.1271081469
Short name T310
Test name
Test status
Simulation time 26520804873 ps
CPU time 143.96 seconds
Started Oct 11 11:46:51 PM UTC 24
Finished Oct 11 11:49:17 PM UTC 24
Peak memory 214700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271081469 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1271081469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2307326238
Short name T160
Test name
Test status
Simulation time 30203030049 ps
CPU time 81.3 seconds
Started Oct 11 11:46:52 PM UTC 24
Finished Oct 11 11:48:15 PM UTC 24
Peak memory 214760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307326238 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2307326238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.4200442301
Short name T19
Test name
Test status
Simulation time 263960519 ps
CPU time 26.45 seconds
Started Oct 11 11:46:50 PM UTC 24
Finished Oct 11 11:47:18 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200442301 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.4200442301
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.2310463063
Short name T55
Test name
Test status
Simulation time 997089690 ps
CPU time 16.99 seconds
Started Oct 11 11:46:53 PM UTC 24
Finished Oct 11 11:47:11 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310463063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2310463063
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.2978715499
Short name T26
Test name
Test status
Simulation time 184503140 ps
CPU time 3.27 seconds
Started Oct 11 11:46:44 PM UTC 24
Finished Oct 11 11:46:49 PM UTC 24
Peak memory 214804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978715499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2978715499
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.4041263743
Short name T80
Test name
Test status
Simulation time 6526862886 ps
CPU time 32.46 seconds
Started Oct 11 11:46:47 PM UTC 24
Finished Oct 11 11:47:21 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041263743 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.4041263743
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4252319581
Short name T283
Test name
Test status
Simulation time 7274221807 ps
CPU time 51.04 seconds
Started Oct 11 11:46:47 PM UTC 24
Finished Oct 11 11:47:40 PM UTC 24
Peak memory 214912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252319581 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4252319581
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1272476040
Short name T51
Test name
Test status
Simulation time 49000345 ps
CPU time 3.24 seconds
Started Oct 11 11:46:45 PM UTC 24
Finished Oct 11 11:46:50 PM UTC 24
Peak memory 214732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272476040 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1272476040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.3979719177
Short name T178
Test name
Test status
Simulation time 824449060 ps
CPU time 64.04 seconds
Started Oct 11 11:46:57 PM UTC 24
Finished Oct 11 11:48:03 PM UTC 24
Peak memory 218920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979719177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3979719177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1693789836
Short name T332
Test name
Test status
Simulation time 2032635216 ps
CPU time 182.36 seconds
Started Oct 11 11:46:58 PM UTC 24
Finished Oct 11 11:50:04 PM UTC 24
Peak memory 220780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693789836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1693789836
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2851894930
Short name T182
Test name
Test status
Simulation time 2403521902 ps
CPU time 485.4 seconds
Started Oct 11 11:46:58 PM UTC 24
Finished Oct 11 11:55:10 PM UTC 24
Peak memory 220504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851894930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.2851894930
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3455830548
Short name T292
Test name
Test status
Simulation time 12453390849 ps
CPU time 408.32 seconds
Started Oct 11 11:47:00 PM UTC 24
Finished Oct 11 11:53:55 PM UTC 24
Peak memory 231384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455830548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.3455830548
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.2628973474
Short name T77
Test name
Test status
Simulation time 10823340 ps
CPU time 2.59 seconds
Started Oct 11 11:46:56 PM UTC 24
Finished Oct 11 11:47:00 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628973474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2628973474
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.4187000093
Short name T125
Test name
Test status
Simulation time 2475344901 ps
CPU time 64.42 seconds
Started Oct 11 11:53:20 PM UTC 24
Finished Oct 11 11:54:26 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187000093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.4187000093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.591019696
Short name T524
Test name
Test status
Simulation time 28676826613 ps
CPU time 191.72 seconds
Started Oct 11 11:53:20 PM UTC 24
Finished Oct 11 11:56:35 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591019696 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.591019696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.3648042255
Short name T405
Test name
Test status
Simulation time 108823875 ps
CPU time 6.8 seconds
Started Oct 11 11:53:29 PM UTC 24
Finished Oct 11 11:53:37 PM UTC 24
Peak memory 214888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648042255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.3648042255
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.3468465881
Short name T424
Test name
Test status
Simulation time 1567910095 ps
CPU time 35.08 seconds
Started Oct 11 11:53:28 PM UTC 24
Finished Oct 11 11:54:04 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468465881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3468465881
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.1489641018
Short name T192
Test name
Test status
Simulation time 218887563 ps
CPU time 26.68 seconds
Started Oct 11 11:53:16 PM UTC 24
Finished Oct 11 11:53:44 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489641018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1489641018
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.283302210
Short name T448
Test name
Test status
Simulation time 48549681370 ps
CPU time 83.88 seconds
Started Oct 11 11:53:19 PM UTC 24
Finished Oct 11 11:54:44 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283302210 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.283302210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1174652878
Short name T209
Test name
Test status
Simulation time 29474702955 ps
CPU time 97.99 seconds
Started Oct 11 11:53:19 PM UTC 24
Finished Oct 11 11:54:59 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174652878 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1174652878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.2822924934
Short name T401
Test name
Test status
Simulation time 42005369 ps
CPU time 8.21 seconds
Started Oct 11 11:53:18 PM UTC 24
Finished Oct 11 11:53:27 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822924934 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2822924934
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.1192433059
Short name T412
Test name
Test status
Simulation time 835824860 ps
CPU time 22.96 seconds
Started Oct 11 11:53:20 PM UTC 24
Finished Oct 11 11:53:45 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192433059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1192433059
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.750796670
Short name T398
Test name
Test status
Simulation time 104279746 ps
CPU time 4.39 seconds
Started Oct 11 11:53:12 PM UTC 24
Finished Oct 11 11:53:18 PM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750796670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.750796670
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1353917594
Short name T415
Test name
Test status
Simulation time 9610589020 ps
CPU time 34.14 seconds
Started Oct 11 11:53:15 PM UTC 24
Finished Oct 11 11:53:50 PM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353917594 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1353917594
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.956384341
Short name T413
Test name
Test status
Simulation time 4049178558 ps
CPU time 32.52 seconds
Started Oct 11 11:53:15 PM UTC 24
Finished Oct 11 11:53:49 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956384341 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.956384341
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2246649727
Short name T397
Test name
Test status
Simulation time 41054489 ps
CPU time 2.87 seconds
Started Oct 11 11:53:14 PM UTC 24
Finished Oct 11 11:53:17 PM UTC 24
Peak memory 214792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246649727 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2246649727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.3187892850
Short name T518
Test name
Test status
Simulation time 14271736709 ps
CPU time 169.15 seconds
Started Oct 11 11:53:29 PM UTC 24
Finished Oct 11 11:56:21 PM UTC 24
Peak memory 218788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187892850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3187892850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3683038114
Short name T428
Test name
Test status
Simulation time 332193364 ps
CPU time 36.46 seconds
Started Oct 11 11:53:31 PM UTC 24
Finished Oct 11 11:54:08 PM UTC 24
Peak memory 216688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683038114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3683038114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1047568063
Short name T238
Test name
Test status
Simulation time 5145856114 ps
CPU time 414.57 seconds
Started Oct 11 11:53:30 PM UTC 24
Finished Oct 12 12:00:30 AM UTC 24
Peak memory 222668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047568063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.1047568063
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.87357444
Short name T411
Test name
Test status
Simulation time 174281840 ps
CPU time 15.52 seconds
Started Oct 11 11:53:28 PM UTC 24
Finished Oct 11 11:53:44 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87357444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.87357444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.1028922261
Short name T419
Test name
Test status
Simulation time 325039615 ps
CPU time 14.33 seconds
Started Oct 11 11:53:45 PM UTC 24
Finished Oct 11 11:54:01 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028922261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1028922261
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1882147135
Short name T288
Test name
Test status
Simulation time 60291203827 ps
CPU time 253.63 seconds
Started Oct 11 11:53:45 PM UTC 24
Finished Oct 11 11:58:03 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882147135 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.1882147135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.561800188
Short name T418
Test name
Test status
Simulation time 89864172 ps
CPU time 4.93 seconds
Started Oct 11 11:53:51 PM UTC 24
Finished Oct 11 11:53:57 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561800188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.561800188
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2247830778
Short name T433
Test name
Test status
Simulation time 787511965 ps
CPU time 37.22 seconds
Started Oct 11 11:53:45 PM UTC 24
Finished Oct 11 11:54:24 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247830778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2247830778
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.3172724069
Short name T416
Test name
Test status
Simulation time 324958370 ps
CPU time 11.57 seconds
Started Oct 11 11:53:41 PM UTC 24
Finished Oct 11 11:53:53 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172724069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3172724069
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.192775663
Short name T496
Test name
Test status
Simulation time 31128042969 ps
CPU time 134.62 seconds
Started Oct 11 11:53:44 PM UTC 24
Finished Oct 11 11:56:01 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192775663 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.192775663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1493631826
Short name T201
Test name
Test status
Simulation time 5068132534 ps
CPU time 17 seconds
Started Oct 11 11:53:45 PM UTC 24
Finished Oct 11 11:54:03 PM UTC 24
Peak memory 214924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493631826 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1493631826
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.508339226
Short name T429
Test name
Test status
Simulation time 161589769 ps
CPU time 24.96 seconds
Started Oct 11 11:53:43 PM UTC 24
Finished Oct 11 11:54:09 PM UTC 24
Peak memory 216664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508339226 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.508339226
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.3537590178
Short name T427
Test name
Test status
Simulation time 1109969857 ps
CPU time 21.12 seconds
Started Oct 11 11:53:45 PM UTC 24
Finished Oct 11 11:54:08 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537590178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3537590178
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.2313510193
Short name T410
Test name
Test status
Simulation time 300427948 ps
CPU time 5.31 seconds
Started Oct 11 11:53:38 PM UTC 24
Finished Oct 11 11:53:44 PM UTC 24
Peak memory 214588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313510193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2313510193
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.4288402566
Short name T432
Test name
Test status
Simulation time 8575104156 ps
CPU time 40.86 seconds
Started Oct 11 11:53:40 PM UTC 24
Finished Oct 11 11:54:23 PM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288402566 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.4288402566
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2778822340
Short name T438
Test name
Test status
Simulation time 5614171162 ps
CPU time 46.58 seconds
Started Oct 11 11:53:40 PM UTC 24
Finished Oct 11 11:54:28 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778822340 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2778822340
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2055801097
Short name T409
Test name
Test status
Simulation time 30861235 ps
CPU time 3.14 seconds
Started Oct 11 11:53:39 PM UTC 24
Finished Oct 11 11:53:43 PM UTC 24
Peak memory 214728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055801097 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2055801097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.4076235939
Short name T483
Test name
Test status
Simulation time 16993721051 ps
CPU time 191.32 seconds
Started Oct 11 11:53:51 PM UTC 24
Finished Oct 11 11:57:05 PM UTC 24
Peak memory 218792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076235939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.4076235939
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1832314890
Short name T639
Test name
Test status
Simulation time 9254627829 ps
CPU time 316.38 seconds
Started Oct 11 11:53:54 PM UTC 24
Finished Oct 11 11:59:15 PM UTC 24
Peak memory 220840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832314890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1832314890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2047398494
Short name T744
Test name
Test status
Simulation time 1607812354 ps
CPU time 474.83 seconds
Started Oct 11 11:53:54 PM UTC 24
Finished Oct 12 12:01:55 AM UTC 24
Peak memory 222600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047398494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.2047398494
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2011204539
Short name T645
Test name
Test status
Simulation time 4255432000 ps
CPU time 326.84 seconds
Started Oct 11 11:53:56 PM UTC 24
Finished Oct 11 11:59:27 PM UTC 24
Peak memory 231396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011204539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.2011204539
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.2723847375
Short name T437
Test name
Test status
Simulation time 1616199535 ps
CPU time 33.75 seconds
Started Oct 11 11:53:50 PM UTC 24
Finished Oct 11 11:54:25 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723847375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2723847375
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.1452509290
Short name T443
Test name
Test status
Simulation time 476423297 ps
CPU time 29.26 seconds
Started Oct 11 11:54:07 PM UTC 24
Finished Oct 11 11:54:38 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452509290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1452509290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.437736308
Short name T527
Test name
Test status
Simulation time 18717790860 ps
CPU time 149.81 seconds
Started Oct 11 11:54:08 PM UTC 24
Finished Oct 11 11:56:41 PM UTC 24
Peak memory 216936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437736308 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.437736308
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3147274622
Short name T445
Test name
Test status
Simulation time 2211852827 ps
CPU time 19.38 seconds
Started Oct 11 11:54:18 PM UTC 24
Finished Oct 11 11:54:39 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147274622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3147274622
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.578816081
Short name T431
Test name
Test status
Simulation time 220664702 ps
CPU time 8.46 seconds
Started Oct 11 11:54:10 PM UTC 24
Finished Oct 11 11:54:19 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578816081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.578816081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.89168770
Short name T434
Test name
Test status
Simulation time 346446346 ps
CPU time 18.22 seconds
Started Oct 11 11:54:05 PM UTC 24
Finished Oct 11 11:54:25 PM UTC 24
Peak memory 214888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89168770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.89168770
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.2088368491
Short name T501
Test name
Test status
Simulation time 17491759657 ps
CPU time 115.11 seconds
Started Oct 11 11:54:06 PM UTC 24
Finished Oct 11 11:56:03 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088368491 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2088368491
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.4059616099
Short name T436
Test name
Test status
Simulation time 2411217239 ps
CPU time 17.66 seconds
Started Oct 11 11:54:06 PM UTC 24
Finished Oct 11 11:54:25 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059616099 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.4059616099
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.3725166890
Short name T202
Test name
Test status
Simulation time 74479127 ps
CPU time 13.51 seconds
Started Oct 11 11:54:05 PM UTC 24
Finished Oct 11 11:54:20 PM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725166890 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3725166890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.2266496836
Short name T442
Test name
Test status
Simulation time 1397989702 ps
CPU time 26.05 seconds
Started Oct 11 11:54:08 PM UTC 24
Finished Oct 11 11:54:36 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266496836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2266496836
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.4224014130
Short name T421
Test name
Test status
Simulation time 62759583 ps
CPU time 2.94 seconds
Started Oct 11 11:53:58 PM UTC 24
Finished Oct 11 11:54:02 PM UTC 24
Peak memory 214584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224014130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.4224014130
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2331374875
Short name T454
Test name
Test status
Simulation time 5190065524 ps
CPU time 46.36 seconds
Started Oct 11 11:54:03 PM UTC 24
Finished Oct 11 11:54:51 PM UTC 24
Peak memory 214872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331374875 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2331374875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1809092752
Short name T460
Test name
Test status
Simulation time 3824452369 ps
CPU time 49.2 seconds
Started Oct 11 11:54:03 PM UTC 24
Finished Oct 11 11:54:54 PM UTC 24
Peak memory 214912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809092752 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1809092752
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3942286454
Short name T425
Test name
Test status
Simulation time 89267245 ps
CPU time 3.39 seconds
Started Oct 11 11:54:02 PM UTC 24
Finished Oct 11 11:54:07 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942286454 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3942286454
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.3693786653
Short name T490
Test name
Test status
Simulation time 1133381001 ps
CPU time 95.67 seconds
Started Oct 11 11:54:19 PM UTC 24
Finished Oct 11 11:55:57 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693786653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3693786653
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1441111858
Short name T539
Test name
Test status
Simulation time 6763585656 ps
CPU time 155.64 seconds
Started Oct 11 11:54:21 PM UTC 24
Finished Oct 11 11:56:59 PM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441111858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1441111858
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3096154427
Short name T48
Test name
Test status
Simulation time 4727355793 ps
CPU time 495.96 seconds
Started Oct 11 11:54:21 PM UTC 24
Finished Oct 12 12:02:43 AM UTC 24
Peak memory 232908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096154427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.3096154427
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1406726857
Short name T540
Test name
Test status
Simulation time 381008876 ps
CPU time 155.59 seconds
Started Oct 11 11:54:24 PM UTC 24
Finished Oct 11 11:57:02 PM UTC 24
Peak memory 221092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406726857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.1406726857
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.2113993477
Short name T435
Test name
Test status
Simulation time 185509495 ps
CPU time 13.06 seconds
Started Oct 11 11:54:11 PM UTC 24
Finished Oct 11 11:54:25 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113993477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2113993477
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.3359673330
Short name T462
Test name
Test status
Simulation time 883350666 ps
CPU time 25.08 seconds
Started Oct 11 11:54:30 PM UTC 24
Finished Oct 11 11:54:56 PM UTC 24
Peak memory 214892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359673330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3359673330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.336707214
Short name T492
Test name
Test status
Simulation time 7849855239 ps
CPU time 84.67 seconds
Started Oct 11 11:54:31 PM UTC 24
Finished Oct 11 11:55:58 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336707214 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.336707214
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.876210959
Short name T455
Test name
Test status
Simulation time 163733102 ps
CPU time 11.16 seconds
Started Oct 11 11:54:40 PM UTC 24
Finished Oct 11 11:54:53 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876210959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.876210959
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.1147922840
Short name T459
Test name
Test status
Simulation time 163825607 ps
CPU time 16.66 seconds
Started Oct 11 11:54:36 PM UTC 24
Finished Oct 11 11:54:54 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147922840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1147922840
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.1638081060
Short name T452
Test name
Test status
Simulation time 240674362 ps
CPU time 21.34 seconds
Started Oct 11 11:54:26 PM UTC 24
Finished Oct 11 11:54:49 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638081060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1638081060
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.1355256787
Short name T495
Test name
Test status
Simulation time 17909696218 ps
CPU time 90.92 seconds
Started Oct 11 11:54:28 PM UTC 24
Finished Oct 11 11:56:00 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355256787 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1355256787
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.2760803724
Short name T489
Test name
Test status
Simulation time 14993005476 ps
CPU time 84.68 seconds
Started Oct 11 11:54:30 PM UTC 24
Finished Oct 11 11:55:56 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760803724 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2760803724
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.2771674122
Short name T450
Test name
Test status
Simulation time 984135254 ps
CPU time 19.77 seconds
Started Oct 11 11:54:26 PM UTC 24
Finished Oct 11 11:54:47 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771674122 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2771674122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.1843371512
Short name T456
Test name
Test status
Simulation time 426345272 ps
CPU time 20.39 seconds
Started Oct 11 11:54:31 PM UTC 24
Finished Oct 11 11:54:53 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843371512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1843371512
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.3208293369
Short name T441
Test name
Test status
Simulation time 307694822 ps
CPU time 4.35 seconds
Started Oct 11 11:54:25 PM UTC 24
Finished Oct 11 11:54:30 PM UTC 24
Peak memory 214560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208293369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3208293369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.986469245
Short name T473
Test name
Test status
Simulation time 7957911670 ps
CPU time 56.49 seconds
Started Oct 11 11:54:25 PM UTC 24
Finished Oct 11 11:55:23 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986469245 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.986469245
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2461742756
Short name T458
Test name
Test status
Simulation time 6864386754 ps
CPU time 25.46 seconds
Started Oct 11 11:54:26 PM UTC 24
Finished Oct 11 11:54:53 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461742756 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2461742756
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3167522767
Short name T439
Test name
Test status
Simulation time 27533431 ps
CPU time 3.17 seconds
Started Oct 11 11:54:25 PM UTC 24
Finished Oct 11 11:54:29 PM UTC 24
Peak memory 214760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167522767 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3167522767
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.1618837785
Short name T523
Test name
Test status
Simulation time 4997474902 ps
CPU time 110.9 seconds
Started Oct 11 11:54:40 PM UTC 24
Finished Oct 11 11:56:33 PM UTC 24
Peak memory 218984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618837785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1618837785
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2958915045
Short name T552
Test name
Test status
Simulation time 5990011231 ps
CPU time 153.05 seconds
Started Oct 11 11:54:40 PM UTC 24
Finished Oct 11 11:57:16 PM UTC 24
Peak memory 218796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958915045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2958915045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.4210903494
Short name T296
Test name
Test status
Simulation time 804598784 ps
CPU time 76.65 seconds
Started Oct 11 11:54:40 PM UTC 24
Finished Oct 11 11:55:59 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210903494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.4210903494
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.329930794
Short name T600
Test name
Test status
Simulation time 1246848466 ps
CPU time 213.35 seconds
Started Oct 11 11:54:40 PM UTC 24
Finished Oct 11 11:58:17 PM UTC 24
Peak memory 231592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329930794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.329930794
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.1769597678
Short name T451
Test name
Test status
Simulation time 103120479 ps
CPU time 8.59 seconds
Started Oct 11 11:54:38 PM UTC 24
Finished Oct 11 11:54:48 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769597678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1769597678
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.370420910
Short name T493
Test name
Test status
Simulation time 2882661715 ps
CPU time 65.36 seconds
Started Oct 11 11:54:53 PM UTC 24
Finished Oct 11 11:56:00 PM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370420910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.370420910
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2593324168
Short name T140
Test name
Test status
Simulation time 10175256591 ps
CPU time 89.48 seconds
Started Oct 11 11:54:53 PM UTC 24
Finished Oct 11 11:56:24 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593324168 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.2593324168
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2222041764
Short name T469
Test name
Test status
Simulation time 729669001 ps
CPU time 17.39 seconds
Started Oct 11 11:54:55 PM UTC 24
Finished Oct 11 11:55:13 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222041764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2222041764
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.4158032719
Short name T470
Test name
Test status
Simulation time 1592762422 ps
CPU time 18.63 seconds
Started Oct 11 11:54:54 PM UTC 24
Finished Oct 11 11:55:14 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158032719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.4158032719
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.471619980
Short name T463
Test name
Test status
Simulation time 1577660807 ps
CPU time 12.81 seconds
Started Oct 11 11:54:48 PM UTC 24
Finished Oct 11 11:55:02 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471619980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.471619980
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.4081117775
Short name T579
Test name
Test status
Simulation time 47906824891 ps
CPU time 175.88 seconds
Started Oct 11 11:54:50 PM UTC 24
Finished Oct 11 11:57:49 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081117775 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.4081117775
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2538817685
Short name T488
Test name
Test status
Simulation time 21796340249 ps
CPU time 61.3 seconds
Started Oct 11 11:54:51 PM UTC 24
Finished Oct 11 11:55:53 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538817685 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2538817685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.4033857354
Short name T472
Test name
Test status
Simulation time 760083770 ps
CPU time 30.53 seconds
Started Oct 11 11:54:49 PM UTC 24
Finished Oct 11 11:55:21 PM UTC 24
Peak memory 214816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033857354 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.4033857354
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.4119688571
Short name T471
Test name
Test status
Simulation time 1043718163 ps
CPU time 21.92 seconds
Started Oct 11 11:54:54 PM UTC 24
Finished Oct 11 11:55:18 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119688571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.4119688571
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.3907334152
Short name T453
Test name
Test status
Simulation time 186396351 ps
CPU time 5.25 seconds
Started Oct 11 11:54:44 PM UTC 24
Finished Oct 11 11:54:50 PM UTC 24
Peak memory 214588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907334152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3907334152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2132068318
Short name T476
Test name
Test status
Simulation time 7750224601 ps
CPU time 48.65 seconds
Started Oct 11 11:54:45 PM UTC 24
Finished Oct 11 11:55:35 PM UTC 24
Peak memory 214872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132068318 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2132068318
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1334305773
Short name T468
Test name
Test status
Simulation time 3865330901 ps
CPU time 22.55 seconds
Started Oct 11 11:54:48 PM UTC 24
Finished Oct 11 11:55:12 PM UTC 24
Peak memory 214656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334305773 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1334305773
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1108372801
Short name T449
Test name
Test status
Simulation time 29556988 ps
CPU time 2.06 seconds
Started Oct 11 11:54:44 PM UTC 24
Finished Oct 11 11:54:47 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108372801 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1108372801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.2789239791
Short name T466
Test name
Test status
Simulation time 93811456 ps
CPU time 10.67 seconds
Started Oct 11 11:54:56 PM UTC 24
Finished Oct 11 11:55:08 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789239791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2789239791
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1985103212
Short name T498
Test name
Test status
Simulation time 1824374858 ps
CPU time 63.3 seconds
Started Oct 11 11:54:57 PM UTC 24
Finished Oct 11 11:56:02 PM UTC 24
Peak memory 216684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985103212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1985103212
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3404366285
Short name T559
Test name
Test status
Simulation time 748665311 ps
CPU time 147.61 seconds
Started Oct 11 11:54:56 PM UTC 24
Finished Oct 11 11:57:26 PM UTC 24
Peak memory 220776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404366285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.3404366285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1573210364
Short name T549
Test name
Test status
Simulation time 579654740 ps
CPU time 132.08 seconds
Started Oct 11 11:54:59 PM UTC 24
Finished Oct 11 11:57:14 PM UTC 24
Peak memory 220784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573210364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.1573210364
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.3890392431
Short name T464
Test name
Test status
Simulation time 116110923 ps
CPU time 7.24 seconds
Started Oct 11 11:54:54 PM UTC 24
Finished Oct 11 11:55:03 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890392431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3890392431
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.3380759453
Short name T474
Test name
Test status
Simulation time 111710739 ps
CPU time 15.04 seconds
Started Oct 11 11:55:16 PM UTC 24
Finished Oct 11 11:55:32 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380759453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3380759453
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2809444111
Short name T585
Test name
Test status
Simulation time 21318635254 ps
CPU time 159.51 seconds
Started Oct 11 11:55:19 PM UTC 24
Finished Oct 11 11:58:01 PM UTC 24
Peak memory 216736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809444111 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.2809444111
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.1424245451
Short name T499
Test name
Test status
Simulation time 2953840000 ps
CPU time 28.48 seconds
Started Oct 11 11:55:32 PM UTC 24
Finished Oct 11 11:56:02 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424245451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.1424245451
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.3619996372
Short name T485
Test name
Test status
Simulation time 568303562 ps
CPU time 18.42 seconds
Started Oct 11 11:55:24 PM UTC 24
Finished Oct 11 11:55:44 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619996372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3619996372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.3145174135
Short name T478
Test name
Test status
Simulation time 814382211 ps
CPU time 24.95 seconds
Started Oct 11 11:55:10 PM UTC 24
Finished Oct 11 11:55:36 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145174135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3145174135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.4053140187
Short name T551
Test name
Test status
Simulation time 35099335901 ps
CPU time 119.65 seconds
Started Oct 11 11:55:13 PM UTC 24
Finished Oct 11 11:57:14 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053140187 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.4053140187
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.551923298
Short name T563
Test name
Test status
Simulation time 40016535510 ps
CPU time 135.23 seconds
Started Oct 11 11:55:14 PM UTC 24
Finished Oct 11 11:57:32 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551923298 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.551923298
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.822888141
Short name T461
Test name
Test status
Simulation time 208278878 ps
CPU time 15.45 seconds
Started Oct 11 11:55:11 PM UTC 24
Finished Oct 11 11:55:28 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822888141 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.822888141
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.1397958481
Short name T477
Test name
Test status
Simulation time 277478550 ps
CPU time 12.32 seconds
Started Oct 11 11:55:22 PM UTC 24
Finished Oct 11 11:55:36 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397958481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1397958481
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.454942887
Short name T467
Test name
Test status
Simulation time 685049536 ps
CPU time 4.44 seconds
Started Oct 11 11:55:03 PM UTC 24
Finished Oct 11 11:55:09 PM UTC 24
Peak memory 214804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454942887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.454942887
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2026070370
Short name T480
Test name
Test status
Simulation time 7954944658 ps
CPU time 30.04 seconds
Started Oct 11 11:55:09 PM UTC 24
Finished Oct 11 11:55:40 PM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026070370 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2026070370
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1048986245
Short name T491
Test name
Test status
Simulation time 8273486177 ps
CPU time 47.13 seconds
Started Oct 11 11:55:09 PM UTC 24
Finished Oct 11 11:55:57 PM UTC 24
Peak memory 214912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048986245 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1048986245
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2527578907
Short name T465
Test name
Test status
Simulation time 26939672 ps
CPU time 3.07 seconds
Started Oct 11 11:55:03 PM UTC 24
Finished Oct 11 11:55:07 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527578907 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2527578907
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.813019580
Short name T526
Test name
Test status
Simulation time 4177789563 ps
CPU time 65.2 seconds
Started Oct 11 11:55:32 PM UTC 24
Finished Oct 11 11:56:40 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813019580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.813019580
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.238299230
Short name T638
Test name
Test status
Simulation time 6153693090 ps
CPU time 213.57 seconds
Started Oct 11 11:55:37 PM UTC 24
Finished Oct 11 11:59:14 PM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238299230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.238299230
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.4012096971
Short name T715
Test name
Test status
Simulation time 1720716592 ps
CPU time 336.17 seconds
Started Oct 11 11:55:35 PM UTC 24
Finished Oct 12 12:01:16 AM UTC 24
Peak memory 218724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012096971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.4012096971
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2144853588
Short name T548
Test name
Test status
Simulation time 5012816399 ps
CPU time 91.64 seconds
Started Oct 11 11:55:37 PM UTC 24
Finished Oct 11 11:57:10 PM UTC 24
Peak memory 216944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144853588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.2144853588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.1494642391
Short name T482
Test name
Test status
Simulation time 1050365979 ps
CPU time 12 seconds
Started Oct 11 11:55:29 PM UTC 24
Finished Oct 11 11:55:42 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494642391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1494642391
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.1305846361
Short name T224
Test name
Test status
Simulation time 595500068 ps
CPU time 28.28 seconds
Started Oct 11 11:55:46 PM UTC 24
Finished Oct 11 11:56:15 PM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305846361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1305846361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1053893198
Short name T633
Test name
Test status
Simulation time 23791359555 ps
CPU time 193.03 seconds
Started Oct 11 11:55:53 PM UTC 24
Finished Oct 11 11:59:10 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053893198 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.1053893198
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1344363883
Short name T503
Test name
Test status
Simulation time 46835368 ps
CPU time 3.51 seconds
Started Oct 11 11:56:00 PM UTC 24
Finished Oct 11 11:56:04 PM UTC 24
Peak memory 214760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344363883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1344363883
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.1299679450
Short name T511
Test name
Test status
Simulation time 699577857 ps
CPU time 16.59 seconds
Started Oct 11 11:55:57 PM UTC 24
Finished Oct 11 11:56:15 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299679450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1299679450
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.4005528644
Short name T502
Test name
Test status
Simulation time 136739817 ps
CPU time 20.08 seconds
Started Oct 11 11:55:42 PM UTC 24
Finished Oct 11 11:56:04 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005528644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.4005528644
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.1617495355
Short name T583
Test name
Test status
Simulation time 30934954290 ps
CPU time 125.81 seconds
Started Oct 11 11:55:46 PM UTC 24
Finished Oct 11 11:57:54 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617495355 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1617495355
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3933035988
Short name T166
Test name
Test status
Simulation time 42719382154 ps
CPU time 101.33 seconds
Started Oct 11 11:55:46 PM UTC 24
Finished Oct 11 11:57:29 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933035988 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3933035988
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.714197230
Short name T497
Test name
Test status
Simulation time 172935350 ps
CPU time 17.12 seconds
Started Oct 11 11:55:44 PM UTC 24
Finished Oct 11 11:56:02 PM UTC 24
Peak memory 214812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714197230 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.714197230
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2738981110
Short name T500
Test name
Test status
Simulation time 267779720 ps
CPU time 7.12 seconds
Started Oct 11 11:55:55 PM UTC 24
Finished Oct 11 11:56:03 PM UTC 24
Peak memory 214812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738981110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2738981110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.65355377
Short name T484
Test name
Test status
Simulation time 168667759 ps
CPU time 4.82 seconds
Started Oct 11 11:55:38 PM UTC 24
Finished Oct 11 11:55:44 PM UTC 24
Peak memory 214800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65355377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.65355377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2894109717
Short name T521
Test name
Test status
Simulation time 23218524501 ps
CPU time 48.22 seconds
Started Oct 11 11:55:42 PM UTC 24
Finished Oct 11 11:56:32 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894109717 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2894109717
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.2066077784
Short name T515
Test name
Test status
Simulation time 5233098821 ps
CPU time 34.82 seconds
Started Oct 11 11:55:42 PM UTC 24
Finished Oct 11 11:56:18 PM UTC 24
Peak memory 214656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066077784 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2066077784
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.463421602
Short name T486
Test name
Test status
Simulation time 32376649 ps
CPU time 3.1 seconds
Started Oct 11 11:55:40 PM UTC 24
Finished Oct 11 11:55:44 PM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463421602 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.463421602
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.374729684
Short name T165
Test name
Test status
Simulation time 6981429463 ps
CPU time 69.77 seconds
Started Oct 11 11:56:00 PM UTC 24
Finished Oct 11 11:57:11 PM UTC 24
Peak memory 218788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374729684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.374729684
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3247561052
Short name T601
Test name
Test status
Simulation time 23464465852 ps
CPU time 133.22 seconds
Started Oct 11 11:56:03 PM UTC 24
Finished Oct 11 11:58:18 PM UTC 24
Peak memory 218796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247561052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3247561052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1478546645
Short name T571
Test name
Test status
Simulation time 290633425 ps
CPU time 95.87 seconds
Started Oct 11 11:56:03 PM UTC 24
Finished Oct 11 11:57:41 PM UTC 24
Peak memory 218720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478546645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.1478546645
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1044238707
Short name T636
Test name
Test status
Simulation time 5615628387 ps
CPU time 187.09 seconds
Started Oct 11 11:56:03 PM UTC 24
Finished Oct 11 11:59:13 PM UTC 24
Peak memory 220844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044238707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.1044238707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.2888236081
Short name T522
Test name
Test status
Simulation time 1017414086 ps
CPU time 32.27 seconds
Started Oct 11 11:55:59 PM UTC 24
Finished Oct 11 11:56:33 PM UTC 24
Peak memory 216932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888236081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2888236081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.3890131111
Short name T528
Test name
Test status
Simulation time 1062158518 ps
CPU time 36.29 seconds
Started Oct 11 11:56:05 PM UTC 24
Finished Oct 11 11:56:43 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890131111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3890131111
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.1259583609
Short name T245
Test name
Test status
Simulation time 3627824256 ps
CPU time 45.05 seconds
Started Oct 11 11:56:05 PM UTC 24
Finished Oct 11 11:56:52 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259583609 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.1259583609
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.39196078
Short name T513
Test name
Test status
Simulation time 110228362 ps
CPU time 5.27 seconds
Started Oct 11 11:56:11 PM UTC 24
Finished Oct 11 11:56:17 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39196078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.39196078
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.2003518526
Short name T520
Test name
Test status
Simulation time 863397415 ps
CPU time 18.04 seconds
Started Oct 11 11:56:09 PM UTC 24
Finished Oct 11 11:56:28 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003518526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2003518526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.709498597
Short name T510
Test name
Test status
Simulation time 184585043 ps
CPU time 6.72 seconds
Started Oct 11 11:56:05 PM UTC 24
Finished Oct 11 11:56:13 PM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709498597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.709498597
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.2401109583
Short name T519
Test name
Test status
Simulation time 5368041594 ps
CPU time 19.58 seconds
Started Oct 11 11:56:05 PM UTC 24
Finished Oct 11 11:56:26 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401109583 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2401109583
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3238260336
Short name T578
Test name
Test status
Simulation time 20044301291 ps
CPU time 100.17 seconds
Started Oct 11 11:56:05 PM UTC 24
Finished Oct 11 11:57:47 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238260336 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3238260336
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.2216125353
Short name T506
Test name
Test status
Simulation time 34030567 ps
CPU time 2.51 seconds
Started Oct 11 11:56:05 PM UTC 24
Finished Oct 11 11:56:09 PM UTC 24
Peak memory 214388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216125353 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2216125353
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.2846509434
Short name T509
Test name
Test status
Simulation time 207703328 ps
CPU time 5.95 seconds
Started Oct 11 11:56:05 PM UTC 24
Finished Oct 11 11:56:12 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846509434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2846509434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.1434863991
Short name T507
Test name
Test status
Simulation time 176392095 ps
CPU time 5.33 seconds
Started Oct 11 11:56:03 PM UTC 24
Finished Oct 11 11:56:09 PM UTC 24
Peak memory 214588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434863991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1434863991
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.788515853
Short name T534
Test name
Test status
Simulation time 20875420788 ps
CPU time 43.59 seconds
Started Oct 11 11:56:03 PM UTC 24
Finished Oct 11 11:56:48 PM UTC 24
Peak memory 214940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788515853 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.788515853
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1405169954
Short name T532
Test name
Test status
Simulation time 4900018168 ps
CPU time 38.66 seconds
Started Oct 11 11:56:05 PM UTC 24
Finished Oct 11 11:56:45 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405169954 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1405169954
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3421693398
Short name T505
Test name
Test status
Simulation time 65219213 ps
CPU time 3.25 seconds
Started Oct 11 11:56:03 PM UTC 24
Finished Oct 11 11:56:07 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421693398 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3421693398
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.70487575
Short name T584
Test name
Test status
Simulation time 863072566 ps
CPU time 103.6 seconds
Started Oct 11 11:56:11 PM UTC 24
Finished Oct 11 11:57:57 PM UTC 24
Peak memory 218728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70487575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-si
m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.70487575
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1403629580
Short name T554
Test name
Test status
Simulation time 2388285536 ps
CPU time 65.6 seconds
Started Oct 11 11:56:11 PM UTC 24
Finished Oct 11 11:57:19 PM UTC 24
Peak memory 216752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403629580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1403629580
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3406428616
Short name T298
Test name
Test status
Simulation time 424709741 ps
CPU time 160.44 seconds
Started Oct 11 11:56:14 PM UTC 24
Finished Oct 11 11:58:57 PM UTC 24
Peak memory 220780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406428616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.3406428616
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.1063788925
Short name T516
Test name
Test status
Simulation time 180452121 ps
CPU time 8.59 seconds
Started Oct 11 11:56:09 PM UTC 24
Finished Oct 11 11:56:18 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063788925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1063788925
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.2362471225
Short name T210
Test name
Test status
Simulation time 228986464 ps
CPU time 23.34 seconds
Started Oct 11 11:56:23 PM UTC 24
Finished Oct 11 11:56:48 PM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362471225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2362471225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2144319641
Short name T707
Test name
Test status
Simulation time 41435401555 ps
CPU time 275.25 seconds
Started Oct 11 11:56:26 PM UTC 24
Finished Oct 12 12:01:05 AM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144319641 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2144319641
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3847106636
Short name T537
Test name
Test status
Simulation time 482112504 ps
CPU time 20.43 seconds
Started Oct 11 11:56:33 PM UTC 24
Finished Oct 11 11:56:55 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847106636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3847106636
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.3301002185
Short name T538
Test name
Test status
Simulation time 287001242 ps
CPU time 25.55 seconds
Started Oct 11 11:56:29 PM UTC 24
Finished Oct 11 11:56:56 PM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301002185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3301002185
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.31917094
Short name T525
Test name
Test status
Simulation time 544130845 ps
CPU time 14.65 seconds
Started Oct 11 11:56:20 PM UTC 24
Finished Oct 11 11:56:36 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31917094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.31917094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.2384021017
Short name T621
Test name
Test status
Simulation time 20483474556 ps
CPU time 145.26 seconds
Started Oct 11 11:56:20 PM UTC 24
Finished Oct 11 11:58:48 PM UTC 24
Peak memory 214892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384021017 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2384021017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.4228212202
Short name T591
Test name
Test status
Simulation time 10730452268 ps
CPU time 104.61 seconds
Started Oct 11 11:56:21 PM UTC 24
Finished Oct 11 11:58:08 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228212202 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4228212202
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.1085614626
Short name T146
Test name
Test status
Simulation time 175948080 ps
CPU time 6.83 seconds
Started Oct 11 11:56:20 PM UTC 24
Finished Oct 11 11:56:28 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085614626 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1085614626
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.2188788343
Short name T529
Test name
Test status
Simulation time 522036570 ps
CPU time 15.73 seconds
Started Oct 11 11:56:27 PM UTC 24
Finished Oct 11 11:56:44 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188788343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2188788343
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.2129917315
Short name T514
Test name
Test status
Simulation time 30094304 ps
CPU time 3.34 seconds
Started Oct 11 11:56:14 PM UTC 24
Finished Oct 11 11:56:18 PM UTC 24
Peak memory 214584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129917315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2129917315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.4255900620
Short name T541
Test name
Test status
Simulation time 5165934024 ps
CPU time 44.82 seconds
Started Oct 11 11:56:17 PM UTC 24
Finished Oct 11 11:57:03 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255900620 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4255900620
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.4160587447
Short name T530
Test name
Test status
Simulation time 2991322298 ps
CPU time 25.24 seconds
Started Oct 11 11:56:18 PM UTC 24
Finished Oct 11 11:56:45 PM UTC 24
Peak memory 214660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160587447 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4160587447
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2853631144
Short name T517
Test name
Test status
Simulation time 22957496 ps
CPU time 2.72 seconds
Started Oct 11 11:56:17 PM UTC 24
Finished Oct 11 11:56:21 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853631144 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2853631144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.1944875319
Short name T212
Test name
Test status
Simulation time 10276333275 ps
CPU time 221.14 seconds
Started Oct 11 11:56:35 PM UTC 24
Finished Oct 12 12:00:20 AM UTC 24
Peak memory 220836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944875319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1944875319
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1007915351
Short name T699
Test name
Test status
Simulation time 20369954492 ps
CPU time 250.88 seconds
Started Oct 11 11:56:37 PM UTC 24
Finished Oct 12 12:00:51 AM UTC 24
Peak memory 220848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007915351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1007915351
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.431950693
Short name T545
Test name
Test status
Simulation time 8492393 ps
CPU time 30.93 seconds
Started Oct 11 11:56:35 PM UTC 24
Finished Oct 11 11:57:08 PM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431950693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.431950693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3334910875
Short name T763
Test name
Test status
Simulation time 1960479930 ps
CPU time 339.21 seconds
Started Oct 11 11:56:37 PM UTC 24
Finished Oct 12 12:02:20 AM UTC 24
Peak memory 231332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334910875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.3334910875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.1415747226
Short name T535
Test name
Test status
Simulation time 563802552 ps
CPU time 18.44 seconds
Started Oct 11 11:56:29 PM UTC 24
Finished Oct 11 11:56:49 PM UTC 24
Peak memory 216868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415747226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1415747226
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.3030331312
Short name T289
Test name
Test status
Simulation time 1903069586 ps
CPU time 83.9 seconds
Started Oct 11 11:56:48 PM UTC 24
Finished Oct 11 11:58:14 PM UTC 24
Peak memory 216876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030331312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3030331312
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1048336968
Short name T544
Test name
Test status
Simulation time 122280488 ps
CPU time 10.94 seconds
Started Oct 11 11:56:55 PM UTC 24
Finished Oct 11 11:57:07 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048336968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1048336968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.2056074486
Short name T558
Test name
Test status
Simulation time 6333805500 ps
CPU time 34.02 seconds
Started Oct 11 11:56:50 PM UTC 24
Finished Oct 11 11:57:25 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056074486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2056074486
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.303591411
Short name T555
Test name
Test status
Simulation time 1642901020 ps
CPU time 32.88 seconds
Started Oct 11 11:56:46 PM UTC 24
Finished Oct 11 11:57:21 PM UTC 24
Peak memory 216308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303591411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.303591411
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.188987801
Short name T598
Test name
Test status
Simulation time 19277462121 ps
CPU time 83.89 seconds
Started Oct 11 11:56:47 PM UTC 24
Finished Oct 11 11:58:12 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188987801 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.188987801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2962372164
Short name T550
Test name
Test status
Simulation time 2889149758 ps
CPU time 26.36 seconds
Started Oct 11 11:56:47 PM UTC 24
Finished Oct 11 11:57:14 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962372164 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2962372164
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.1745512263
Short name T536
Test name
Test status
Simulation time 142505310 ps
CPU time 6.46 seconds
Started Oct 11 11:56:47 PM UTC 24
Finished Oct 11 11:56:54 PM UTC 24
Peak memory 214880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745512263 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1745512263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.281755093
Short name T546
Test name
Test status
Simulation time 579488294 ps
CPU time 18.17 seconds
Started Oct 11 11:56:49 PM UTC 24
Finished Oct 11 11:57:09 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281755093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.281755093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.3659813743
Short name T531
Test name
Test status
Simulation time 39618238 ps
CPU time 2.95 seconds
Started Oct 11 11:56:41 PM UTC 24
Finished Oct 11 11:56:45 PM UTC 24
Peak memory 214584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659813743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3659813743
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3590277674
Short name T573
Test name
Test status
Simulation time 6122189728 ps
CPU time 57.27 seconds
Started Oct 11 11:56:43 PM UTC 24
Finished Oct 11 11:57:42 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590277674 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3590277674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.155820408
Short name T566
Test name
Test status
Simulation time 5379939884 ps
CPU time 49.78 seconds
Started Oct 11 11:56:46 PM UTC 24
Finished Oct 11 11:57:38 PM UTC 24
Peak memory 214224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155820408 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.155820408
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1387918765
Short name T533
Test name
Test status
Simulation time 65393781 ps
CPU time 2.68 seconds
Started Oct 11 11:56:42 PM UTC 24
Finished Oct 11 11:56:46 PM UTC 24
Peak memory 214792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387918765 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1387918765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.2600257249
Short name T148
Test name
Test status
Simulation time 1431203447 ps
CPU time 193.12 seconds
Started Oct 11 11:56:56 PM UTC 24
Finished Oct 12 12:00:13 AM UTC 24
Peak memory 216812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600257249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2600257249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2994927498
Short name T560
Test name
Test status
Simulation time 3713935367 ps
CPU time 25.18 seconds
Started Oct 11 11:57:00 PM UTC 24
Finished Oct 11 11:57:26 PM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994927498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2994927498
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3500073995
Short name T713
Test name
Test status
Simulation time 1300108756 ps
CPU time 254.74 seconds
Started Oct 11 11:56:57 PM UTC 24
Finished Oct 12 12:01:15 AM UTC 24
Peak memory 220772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500073995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.3500073995
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2827591183
Short name T668
Test name
Test status
Simulation time 712857743 ps
CPU time 169.94 seconds
Started Oct 11 11:57:03 PM UTC 24
Finished Oct 11 11:59:56 PM UTC 24
Peak memory 231332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827591183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.2827591183
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.2697023160
Short name T553
Test name
Test status
Simulation time 143031302 ps
CPU time 23.67 seconds
Started Oct 11 11:56:53 PM UTC 24
Finished Oct 11 11:57:18 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697023160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2697023160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.4278281791
Short name T22
Test name
Test status
Simulation time 348554681 ps
CPU time 22.08 seconds
Started Oct 11 11:47:06 PM UTC 24
Finished Oct 11 11:47:30 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278281791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.4278281791
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1795669747
Short name T174
Test name
Test status
Simulation time 3978379001 ps
CPU time 43.54 seconds
Started Oct 11 11:47:10 PM UTC 24
Finished Oct 11 11:47:55 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795669747 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.1795669747
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.314768515
Short name T299
Test name
Test status
Simulation time 178771876 ps
CPU time 20.43 seconds
Started Oct 11 11:47:17 PM UTC 24
Finished Oct 11 11:47:38 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314768515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.314768515
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.1026394656
Short name T21
Test name
Test status
Simulation time 336994521 ps
CPU time 14.46 seconds
Started Oct 11 11:47:13 PM UTC 24
Finished Oct 11 11:47:29 PM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026394656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1026394656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.1851168850
Short name T81
Test name
Test status
Simulation time 846948376 ps
CPU time 29.95 seconds
Started Oct 11 11:47:04 PM UTC 24
Finished Oct 11 11:47:35 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851168850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1851168850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.1182281052
Short name T100
Test name
Test status
Simulation time 36290893020 ps
CPU time 101.88 seconds
Started Oct 11 11:47:05 PM UTC 24
Finished Oct 11 11:48:49 PM UTC 24
Peak memory 216752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182281052 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1182281052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.355357950
Short name T56
Test name
Test status
Simulation time 1075982645 ps
CPU time 10.4 seconds
Started Oct 11 11:47:06 PM UTC 24
Finished Oct 11 11:47:18 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355357950 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.355357950
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.2804325526
Short name T23
Test name
Test status
Simulation time 291784232 ps
CPU time 24.37 seconds
Started Oct 11 11:47:05 PM UTC 24
Finished Oct 11 11:47:31 PM UTC 24
Peak memory 216672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804325526 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2804325526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.1121562695
Short name T116
Test name
Test status
Simulation time 2138831485 ps
CPU time 33.69 seconds
Started Oct 11 11:47:12 PM UTC 24
Finished Oct 11 11:47:47 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121562695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1121562695
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.2822613297
Short name T78
Test name
Test status
Simulation time 41814783 ps
CPU time 2.42 seconds
Started Oct 11 11:47:01 PM UTC 24
Finished Oct 11 11:47:04 PM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822613297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2822613297
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1894269395
Short name T97
Test name
Test status
Simulation time 7440233372 ps
CPU time 31.94 seconds
Started Oct 11 11:47:01 PM UTC 24
Finished Oct 11 11:47:34 PM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894269395 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1894269395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3737579457
Short name T284
Test name
Test status
Simulation time 5504672579 ps
CPU time 32.8 seconds
Started Oct 11 11:47:03 PM UTC 24
Finished Oct 11 11:47:37 PM UTC 24
Peak memory 214656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737579457 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3737579457
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.4112018148
Short name T79
Test name
Test status
Simulation time 28566851 ps
CPU time 3.28 seconds
Started Oct 11 11:47:01 PM UTC 24
Finished Oct 11 11:47:05 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112018148 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.4112018148
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.4266150349
Short name T95
Test name
Test status
Simulation time 231154376 ps
CPU time 6.58 seconds
Started Oct 11 11:47:19 PM UTC 24
Finished Oct 11 11:47:26 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266150349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.4266150349
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1651497534
Short name T220
Test name
Test status
Simulation time 6378507090 ps
CPU time 156.99 seconds
Started Oct 11 11:47:19 PM UTC 24
Finished Oct 11 11:49:58 PM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651497534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1651497534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.258729109
Short name T422
Test name
Test status
Simulation time 7491391391 ps
CPU time 398.99 seconds
Started Oct 11 11:47:19 PM UTC 24
Finished Oct 11 11:54:03 PM UTC 24
Peak memory 218796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258729109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.258729109
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1991226032
Short name T41
Test name
Test status
Simulation time 384130672 ps
CPU time 62.14 seconds
Started Oct 11 11:47:21 PM UTC 24
Finished Oct 11 11:48:25 PM UTC 24
Peak memory 218736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991226032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.1991226032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.2399578568
Short name T82
Test name
Test status
Simulation time 611408201 ps
CPU time 24.66 seconds
Started Oct 11 11:47:14 PM UTC 24
Finished Oct 11 11:47:40 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399578568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2399578568
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.3622514794
Short name T127
Test name
Test status
Simulation time 3220578620 ps
CPU time 45.57 seconds
Started Oct 11 11:57:11 PM UTC 24
Finished Oct 11 11:57:58 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622514794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3622514794
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3347263304
Short name T131
Test name
Test status
Simulation time 62125899399 ps
CPU time 274.27 seconds
Started Oct 11 11:57:13 PM UTC 24
Finished Oct 12 12:01:51 AM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347263304 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.3347263304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1970490203
Short name T556
Test name
Test status
Simulation time 114334477 ps
CPU time 3.81 seconds
Started Oct 11 11:57:16 PM UTC 24
Finished Oct 11 11:57:21 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970490203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.1970490203
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.3936608217
Short name T564
Test name
Test status
Simulation time 2818678610 ps
CPU time 17.01 seconds
Started Oct 11 11:57:16 PM UTC 24
Finished Oct 11 11:57:34 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936608217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3936608217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.931838832
Short name T66
Test name
Test status
Simulation time 480947536 ps
CPU time 22.38 seconds
Started Oct 11 11:57:08 PM UTC 24
Finished Oct 11 11:57:32 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931838832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.931838832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.94065903
Short name T609
Test name
Test status
Simulation time 14704951356 ps
CPU time 74.19 seconds
Started Oct 11 11:57:10 PM UTC 24
Finished Oct 11 11:58:26 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94065903 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.94065903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3837716617
Short name T655
Test name
Test status
Simulation time 22695862086 ps
CPU time 145.57 seconds
Started Oct 11 11:57:11 PM UTC 24
Finished Oct 11 11:59:39 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837716617 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3837716617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.1272058033
Short name T567
Test name
Test status
Simulation time 279906144 ps
CPU time 27.12 seconds
Started Oct 11 11:57:10 PM UTC 24
Finished Oct 11 11:57:39 PM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272058033 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1272058033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.1761915712
Short name T225
Test name
Test status
Simulation time 170406995 ps
CPU time 12.38 seconds
Started Oct 11 11:57:13 PM UTC 24
Finished Oct 11 11:57:26 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761915712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1761915712
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.3448396157
Short name T512
Test name
Test status
Simulation time 201235819 ps
CPU time 4.07 seconds
Started Oct 11 11:57:05 PM UTC 24
Finished Oct 11 11:57:10 PM UTC 24
Peak memory 214844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448396157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3448396157
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.522674475
Short name T580
Test name
Test status
Simulation time 5574265574 ps
CPU time 40.57 seconds
Started Oct 11 11:57:08 PM UTC 24
Finished Oct 11 11:57:50 PM UTC 24
Peak memory 214876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522674475 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.522674475
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2984260384
Short name T570
Test name
Test status
Simulation time 19199503882 ps
CPU time 30.68 seconds
Started Oct 11 11:57:08 PM UTC 24
Finished Oct 11 11:57:40 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984260384 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2984260384
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2276760472
Short name T547
Test name
Test status
Simulation time 28850810 ps
CPU time 2.49 seconds
Started Oct 11 11:57:06 PM UTC 24
Finished Oct 11 11:57:10 PM UTC 24
Peak memory 214792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276760472 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2276760472
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.2334726653
Short name T582
Test name
Test status
Simulation time 308617522 ps
CPU time 33.73 seconds
Started Oct 11 11:57:17 PM UTC 24
Finished Oct 11 11:57:53 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334726653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2334726653
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.612020389
Short name T595
Test name
Test status
Simulation time 1789068851 ps
CPU time 49.72 seconds
Started Oct 11 11:57:20 PM UTC 24
Finished Oct 11 11:58:11 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612020389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.612020389
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4122120366
Short name T204
Test name
Test status
Simulation time 1992323453 ps
CPU time 357.31 seconds
Started Oct 11 11:57:20 PM UTC 24
Finished Oct 12 12:03:22 AM UTC 24
Peak memory 220912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122120366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.4122120366
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.4242505742
Short name T623
Test name
Test status
Simulation time 267998932 ps
CPU time 86.17 seconds
Started Oct 11 11:57:22 PM UTC 24
Finished Oct 11 11:58:50 PM UTC 24
Peak memory 220780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242505742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.4242505742
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.3614692813
Short name T557
Test name
Test status
Simulation time 44459771 ps
CPU time 7.15 seconds
Started Oct 11 11:57:16 PM UTC 24
Finished Oct 11 11:57:24 PM UTC 24
Peak memory 216868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614692813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3614692813
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.2668019258
Short name T156
Test name
Test status
Simulation time 1052595187 ps
CPU time 32.12 seconds
Started Oct 11 11:57:31 PM UTC 24
Finished Oct 11 11:58:05 PM UTC 24
Peak memory 216684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668019258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2668019258
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1751559937
Short name T130
Test name
Test status
Simulation time 48851501579 ps
CPU time 143.47 seconds
Started Oct 11 11:57:31 PM UTC 24
Finished Oct 11 11:59:57 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751559937 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.1751559937
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2675297753
Short name T576
Test name
Test status
Simulation time 208328043 ps
CPU time 5.87 seconds
Started Oct 11 11:57:39 PM UTC 24
Finished Oct 11 11:57:46 PM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675297753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2675297753
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.2788161383
Short name T586
Test name
Test status
Simulation time 1407457254 ps
CPU time 28.73 seconds
Started Oct 11 11:57:34 PM UTC 24
Finished Oct 11 11:58:04 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788161383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2788161383
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.3178677830
Short name T126
Test name
Test status
Simulation time 970457990 ps
CPU time 28.47 seconds
Started Oct 11 11:57:28 PM UTC 24
Finished Oct 11 11:57:58 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178677830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3178677830
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.768990418
Short name T572
Test name
Test status
Simulation time 2966472498 ps
CPU time 11.93 seconds
Started Oct 11 11:57:28 PM UTC 24
Finished Oct 11 11:57:41 PM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768990418 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.768990418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1661103102
Short name T631
Test name
Test status
Simulation time 25611122408 ps
CPU time 96.19 seconds
Started Oct 11 11:57:29 PM UTC 24
Finished Oct 11 11:59:08 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661103102 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1661103102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.2117884068
Short name T574
Test name
Test status
Simulation time 183529976 ps
CPU time 15.07 seconds
Started Oct 11 11:57:28 PM UTC 24
Finished Oct 11 11:57:44 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117884068 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2117884068
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.3822443598
Short name T568
Test name
Test status
Simulation time 217524135 ps
CPU time 4.45 seconds
Started Oct 11 11:57:34 PM UTC 24
Finished Oct 11 11:57:39 PM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822443598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3822443598
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.59409443
Short name T561
Test name
Test status
Simulation time 127077128 ps
CPU time 5.01 seconds
Started Oct 11 11:57:22 PM UTC 24
Finished Oct 11 11:57:28 PM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59409443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs
/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.59409443
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1680104058
Short name T590
Test name
Test status
Simulation time 15569471884 ps
CPU time 38.49 seconds
Started Oct 11 11:57:28 PM UTC 24
Finished Oct 11 11:58:08 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680104058 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1680104058
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2385919446
Short name T607
Test name
Test status
Simulation time 24686085192 ps
CPU time 54.35 seconds
Started Oct 11 11:57:28 PM UTC 24
Finished Oct 11 11:58:24 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385919446 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2385919446
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3382834223
Short name T562
Test name
Test status
Simulation time 32264604 ps
CPU time 3.39 seconds
Started Oct 11 11:57:25 PM UTC 24
Finished Oct 11 11:57:30 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382834223 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3382834223
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.4046071177
Short name T677
Test name
Test status
Simulation time 31791295894 ps
CPU time 154.55 seconds
Started Oct 11 11:57:39 PM UTC 24
Finished Oct 12 12:00:16 AM UTC 24
Peak memory 216916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046071177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.4046071177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1214557972
Short name T587
Test name
Test status
Simulation time 1140201072 ps
CPU time 22.67 seconds
Started Oct 11 11:57:40 PM UTC 24
Finished Oct 11 11:58:04 PM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214557972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1214557972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.4159758478
Short name T143
Test name
Test status
Simulation time 1476870626 ps
CPU time 81.95 seconds
Started Oct 11 11:57:40 PM UTC 24
Finished Oct 11 11:59:04 PM UTC 24
Peak memory 218724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159758478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.4159758478
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3091215859
Short name T686
Test name
Test status
Simulation time 10016700003 ps
CPU time 168.06 seconds
Started Oct 11 11:57:40 PM UTC 24
Finished Oct 12 12:00:31 AM UTC 24
Peak memory 220844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091215859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.3091215859
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.572155184
Short name T569
Test name
Test status
Simulation time 19410905 ps
CPU time 3.32 seconds
Started Oct 11 11:57:35 PM UTC 24
Finished Oct 11 11:57:40 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572155184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.572155184
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.2118365716
Short name T67
Test name
Test status
Simulation time 466482973 ps
CPU time 25.22 seconds
Started Oct 11 11:57:51 PM UTC 24
Finished Oct 11 11:58:17 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118365716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2118365716
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.4147601080
Short name T795
Test name
Test status
Simulation time 30304864939 ps
CPU time 303.48 seconds
Started Oct 11 11:57:51 PM UTC 24
Finished Oct 12 12:02:58 AM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147601080 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.4147601080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.966361724
Short name T588
Test name
Test status
Simulation time 351370526 ps
CPU time 10.29 seconds
Started Oct 11 11:57:55 PM UTC 24
Finished Oct 11 11:58:06 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966361724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.966361724
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.2901296578
Short name T616
Test name
Test status
Simulation time 1067124250 ps
CPU time 40.4 seconds
Started Oct 11 11:57:54 PM UTC 24
Finished Oct 11 11:58:36 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901296578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2901296578
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.3314119640
Short name T589
Test name
Test status
Simulation time 146424021 ps
CPU time 19.64 seconds
Started Oct 11 11:57:46 PM UTC 24
Finished Oct 11 11:58:07 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314119640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3314119640
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.4217665863
Short name T684
Test name
Test status
Simulation time 27192398345 ps
CPU time 158.57 seconds
Started Oct 11 11:57:49 PM UTC 24
Finished Oct 12 12:00:30 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217665863 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.4217665863
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2518047729
Short name T614
Test name
Test status
Simulation time 12431338911 ps
CPU time 41.18 seconds
Started Oct 11 11:57:49 PM UTC 24
Finished Oct 11 11:58:32 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518047729 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2518047729
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.2735343211
Short name T597
Test name
Test status
Simulation time 339625901 ps
CPU time 21.88 seconds
Started Oct 11 11:57:49 PM UTC 24
Finished Oct 11 11:58:12 PM UTC 24
Peak memory 216668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735343211 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2735343211
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.2952843556
Short name T599
Test name
Test status
Simulation time 1312554034 ps
CPU time 22.29 seconds
Started Oct 11 11:57:51 PM UTC 24
Finished Oct 11 11:58:14 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952843556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2952843556
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.1227092610
Short name T575
Test name
Test status
Simulation time 31107793 ps
CPU time 2.36 seconds
Started Oct 11 11:57:42 PM UTC 24
Finished Oct 11 11:57:45 PM UTC 24
Peak memory 214588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227092610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1227092610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.812529140
Short name T603
Test name
Test status
Simulation time 6710262045 ps
CPU time 36.69 seconds
Started Oct 11 11:57:42 PM UTC 24
Finished Oct 11 11:58:20 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812529140 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.812529140
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.761043426
Short name T68
Test name
Test status
Simulation time 19855415274 ps
CPU time 48.36 seconds
Started Oct 11 11:57:43 PM UTC 24
Finished Oct 11 11:58:33 PM UTC 24
Peak memory 214844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761043426 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.761043426
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2774613511
Short name T577
Test name
Test status
Simulation time 69030917 ps
CPU time 2.66 seconds
Started Oct 11 11:57:42 PM UTC 24
Finished Oct 11 11:57:46 PM UTC 24
Peak memory 214792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774613511 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2774613511
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.902045996
Short name T144
Test name
Test status
Simulation time 6201838844 ps
CPU time 195.4 seconds
Started Oct 11 11:57:57 PM UTC 24
Finished Oct 12 12:01:16 AM UTC 24
Peak memory 218788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902045996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.902045996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2468389115
Short name T701
Test name
Test status
Simulation time 2081389341 ps
CPU time 174.28 seconds
Started Oct 11 11:58:00 PM UTC 24
Finished Oct 12 12:00:57 AM UTC 24
Peak memory 221072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468389115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2468389115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3797969143
Short name T612
Test name
Test status
Simulation time 153183731 ps
CPU time 25.09 seconds
Started Oct 11 11:58:02 PM UTC 24
Finished Oct 11 11:58:29 PM UTC 24
Peak memory 218736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797969143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.3797969143
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.3909737794
Short name T594
Test name
Test status
Simulation time 131327680 ps
CPU time 15.62 seconds
Started Oct 11 11:57:54 PM UTC 24
Finished Oct 11 11:58:10 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909737794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3909737794
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.3025227103
Short name T630
Test name
Test status
Simulation time 1755475682 ps
CPU time 54.76 seconds
Started Oct 11 11:58:10 PM UTC 24
Finished Oct 11 11:59:06 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025227103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3025227103
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1363562850
Short name T788
Test name
Test status
Simulation time 118083058889 ps
CPU time 275.14 seconds
Started Oct 11 11:58:11 PM UTC 24
Finished Oct 12 12:02:50 AM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363562850 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.1363562850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.4260940377
Short name T602
Test name
Test status
Simulation time 127803538 ps
CPU time 4.81 seconds
Started Oct 11 11:58:14 PM UTC 24
Finished Oct 11 11:58:20 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260940377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.4260940377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.2242444746
Short name T604
Test name
Test status
Simulation time 554522694 ps
CPU time 6.2 seconds
Started Oct 11 11:58:13 PM UTC 24
Finished Oct 11 11:58:21 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242444746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2242444746
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.2555743190
Short name T611
Test name
Test status
Simulation time 493786759 ps
CPU time 19.08 seconds
Started Oct 11 11:58:08 PM UTC 24
Finished Oct 11 11:58:28 PM UTC 24
Peak memory 214700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555743190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2555743190
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.2218673275
Short name T128
Test name
Test status
Simulation time 3270284327 ps
CPU time 21.69 seconds
Started Oct 11 11:58:10 PM UTC 24
Finished Oct 11 11:58:33 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218673275 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2218673275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.587588789
Short name T664
Test name
Test status
Simulation time 9238815854 ps
CPU time 100.41 seconds
Started Oct 11 11:58:10 PM UTC 24
Finished Oct 11 11:59:52 PM UTC 24
Peak memory 214700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587588789 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.587588789
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.1610491873
Short name T610
Test name
Test status
Simulation time 179529611 ps
CPU time 18.48 seconds
Started Oct 11 11:58:08 PM UTC 24
Finished Oct 11 11:58:28 PM UTC 24
Peak memory 216668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610491873 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1610491873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.2994657582
Short name T613
Test name
Test status
Simulation time 816337503 ps
CPU time 16.37 seconds
Started Oct 11 11:58:11 PM UTC 24
Finished Oct 11 11:58:29 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994657582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2994657582
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.1934746773
Short name T593
Test name
Test status
Simulation time 227955619 ps
CPU time 5.52 seconds
Started Oct 11 11:58:04 PM UTC 24
Finished Oct 11 11:58:10 PM UTC 24
Peak memory 214584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934746773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1934746773
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.486608721
Short name T69
Test name
Test status
Simulation time 4739007599 ps
CPU time 28.42 seconds
Started Oct 11 11:58:05 PM UTC 24
Finished Oct 11 11:58:35 PM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486608721 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.486608721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1403256889
Short name T617
Test name
Test status
Simulation time 6718388908 ps
CPU time 31.51 seconds
Started Oct 11 11:58:06 PM UTC 24
Finished Oct 11 11:58:39 PM UTC 24
Peak memory 214912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403256889 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1403256889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3462377174
Short name T592
Test name
Test status
Simulation time 34458578 ps
CPU time 2.69 seconds
Started Oct 11 11:58:05 PM UTC 24
Finished Oct 11 11:58:09 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462377174 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3462377174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.2641005346
Short name T667
Test name
Test status
Simulation time 1697454279 ps
CPU time 99.68 seconds
Started Oct 11 11:58:14 PM UTC 24
Finished Oct 11 11:59:56 PM UTC 24
Peak memory 218728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641005346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2641005346
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2628712461
Short name T717
Test name
Test status
Simulation time 5506990175 ps
CPU time 179.68 seconds
Started Oct 11 11:58:15 PM UTC 24
Finished Oct 12 12:01:18 AM UTC 24
Peak memory 220612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628712461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2628712461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.323070162
Short name T43
Test name
Test status
Simulation time 764440429 ps
CPU time 229.56 seconds
Started Oct 11 11:58:15 PM UTC 24
Finished Oct 12 12:02:09 AM UTC 24
Peak memory 218520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323070162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.323070162
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4102886529
Short name T888
Test name
Test status
Simulation time 4203372672 ps
CPU time 460.82 seconds
Started Oct 11 11:58:20 PM UTC 24
Finished Oct 12 12:06:06 AM UTC 24
Peak memory 232920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102886529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.4102886529
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.1575899431
Short name T605
Test name
Test status
Simulation time 170796866 ps
CPU time 6.47 seconds
Started Oct 11 11:58:14 PM UTC 24
Finished Oct 11 11:58:21 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575899431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1575899431
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.1809397320
Short name T642
Test name
Test status
Simulation time 2212355389 ps
CPU time 54.71 seconds
Started Oct 11 11:58:26 PM UTC 24
Finished Oct 11 11:59:23 PM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809397320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1809397320
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1809185201
Short name T776
Test name
Test status
Simulation time 68404274836 ps
CPU time 248.31 seconds
Started Oct 11 11:58:27 PM UTC 24
Finished Oct 12 12:02:40 AM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809185201 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.1809185201
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1184902953
Short name T615
Test name
Test status
Simulation time 41954858 ps
CPU time 2.68 seconds
Started Oct 11 11:58:31 PM UTC 24
Finished Oct 11 11:58:35 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184902953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1184902953
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.818207769
Short name T625
Test name
Test status
Simulation time 161396638 ps
CPU time 22.45 seconds
Started Oct 11 11:58:31 PM UTC 24
Finished Oct 11 11:58:55 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818207769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.818207769
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.3335981165
Short name T147
Test name
Test status
Simulation time 456467071 ps
CPU time 18.16 seconds
Started Oct 11 11:58:23 PM UTC 24
Finished Oct 11 11:58:42 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335981165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3335981165
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.159648237
Short name T652
Test name
Test status
Simulation time 23065421935 ps
CPU time 68.41 seconds
Started Oct 11 11:58:25 PM UTC 24
Finished Oct 11 11:59:35 PM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159648237 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.159648237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1421443929
Short name T211
Test name
Test status
Simulation time 16410522083 ps
CPU time 63.45 seconds
Started Oct 11 11:58:25 PM UTC 24
Finished Oct 11 11:59:30 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421443929 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1421443929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.3434155376
Short name T624
Test name
Test status
Simulation time 202016965 ps
CPU time 26.88 seconds
Started Oct 11 11:58:23 PM UTC 24
Finished Oct 11 11:58:51 PM UTC 24
Peak memory 216732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434155376 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3434155376
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.4206917179
Short name T620
Test name
Test status
Simulation time 1129469360 ps
CPU time 14.59 seconds
Started Oct 11 11:58:29 PM UTC 24
Finished Oct 11 11:58:45 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206917179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4206917179
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.2918948249
Short name T606
Test name
Test status
Simulation time 40929434 ps
CPU time 2.34 seconds
Started Oct 11 11:58:20 PM UTC 24
Finished Oct 11 11:58:23 PM UTC 24
Peak memory 214588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918948249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2918948249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2366322642
Short name T627
Test name
Test status
Simulation time 10241014667 ps
CPU time 36.18 seconds
Started Oct 11 11:58:21 PM UTC 24
Finished Oct 11 11:58:59 PM UTC 24
Peak memory 214872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366322642 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2366322642
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1066873637
Short name T640
Test name
Test status
Simulation time 10062232991 ps
CPU time 54.99 seconds
Started Oct 11 11:58:21 PM UTC 24
Finished Oct 11 11:59:18 PM UTC 24
Peak memory 214656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066873637 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1066873637
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1882810573
Short name T608
Test name
Test status
Simulation time 126265086 ps
CPU time 3.35 seconds
Started Oct 11 11:58:20 PM UTC 24
Finished Oct 11 11:58:24 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882810573 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1882810573
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.2267135921
Short name T654
Test name
Test status
Simulation time 866913780 ps
CPU time 61.06 seconds
Started Oct 11 11:58:33 PM UTC 24
Finished Oct 11 11:59:36 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267135921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2267135921
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3059933981
Short name T673
Test name
Test status
Simulation time 2870618336 ps
CPU time 88.18 seconds
Started Oct 11 11:58:35 PM UTC 24
Finished Oct 12 12:00:05 AM UTC 24
Peak memory 218796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059933981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3059933981
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2817452788
Short name T769
Test name
Test status
Simulation time 634417122 ps
CPU time 233.31 seconds
Started Oct 11 11:58:33 PM UTC 24
Finished Oct 12 12:02:30 AM UTC 24
Peak memory 218920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817452788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.2817452788
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1147439072
Short name T848
Test name
Test status
Simulation time 3565848602 ps
CPU time 335.63 seconds
Started Oct 11 11:58:37 PM UTC 24
Finished Oct 12 12:04:17 AM UTC 24
Peak memory 231396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147439072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.1147439072
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.785636133
Short name T628
Test name
Test status
Simulation time 1130803266 ps
CPU time 27.85 seconds
Started Oct 11 11:58:31 PM UTC 24
Finished Oct 11 11:59:00 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785636133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.785636133
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.4349560
Short name T648
Test name
Test status
Simulation time 573832076 ps
CPU time 38.62 seconds
Started Oct 11 11:58:49 PM UTC 24
Finished Oct 11 11:59:30 PM UTC 24
Peak memory 216668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4349560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T
EST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.4349560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3987753899
Short name T246
Test name
Test status
Simulation time 22109925682 ps
CPU time 113.45 seconds
Started Oct 11 11:58:52 PM UTC 24
Finished Oct 12 12:00:48 AM UTC 24
Peak memory 216736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987753899 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.3987753899
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1080558542
Short name T637
Test name
Test status
Simulation time 1298202890 ps
CPU time 14.09 seconds
Started Oct 11 11:58:58 PM UTC 24
Finished Oct 11 11:59:14 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080558542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1080558542
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.4227843330
Short name T641
Test name
Test status
Simulation time 1363517012 ps
CPU time 22.17 seconds
Started Oct 11 11:58:56 PM UTC 24
Finished Oct 11 11:59:20 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227843330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.4227843330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.2237371310
Short name T626
Test name
Test status
Simulation time 81429732 ps
CPU time 13.15 seconds
Started Oct 11 11:58:42 PM UTC 24
Finished Oct 11 11:58:56 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237371310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2237371310
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.1194205119
Short name T632
Test name
Test status
Simulation time 3801899432 ps
CPU time 20.92 seconds
Started Oct 11 11:58:46 PM UTC 24
Finished Oct 11 11:59:09 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194205119 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1194205119
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2994314171
Short name T237
Test name
Test status
Simulation time 4120290029 ps
CPU time 45.84 seconds
Started Oct 11 11:58:49 PM UTC 24
Finished Oct 11 11:59:37 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994314171 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2994314171
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.961998298
Short name T622
Test name
Test status
Simulation time 30488745 ps
CPU time 4.14 seconds
Started Oct 11 11:58:43 PM UTC 24
Finished Oct 11 11:58:48 PM UTC 24
Peak memory 214816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961998298 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.961998298
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.1605928453
Short name T647
Test name
Test status
Simulation time 1560907670 ps
CPU time 35 seconds
Started Oct 11 11:58:52 PM UTC 24
Finished Oct 11 11:59:29 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605928453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1605928453
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.3727165984
Short name T619
Test name
Test status
Simulation time 26185723 ps
CPU time 2.7 seconds
Started Oct 11 11:58:37 PM UTC 24
Finished Oct 11 11:58:40 PM UTC 24
Peak memory 214584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727165984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3727165984
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1023818328
Short name T644
Test name
Test status
Simulation time 4976867786 ps
CPU time 42.06 seconds
Started Oct 11 11:58:40 PM UTC 24
Finished Oct 11 11:59:24 PM UTC 24
Peak memory 214872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023818328 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1023818328
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3963612262
Short name T643
Test name
Test status
Simulation time 3378128451 ps
CPU time 40.27 seconds
Started Oct 11 11:58:42 PM UTC 24
Finished Oct 11 11:59:24 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963612262 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3963612262
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1996205077
Short name T618
Test name
Test status
Simulation time 38465649 ps
CPU time 2.56 seconds
Started Oct 11 11:58:37 PM UTC 24
Finished Oct 11 11:58:40 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996205077 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1996205077
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2732547537
Short name T752
Test name
Test status
Simulation time 3808337555 ps
CPU time 181.56 seconds
Started Oct 11 11:59:00 PM UTC 24
Finished Oct 12 12:02:04 AM UTC 24
Peak memory 220836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732547537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2732547537
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1065653336
Short name T766
Test name
Test status
Simulation time 8180425899 ps
CPU time 198.06 seconds
Started Oct 11 11:59:04 PM UTC 24
Finished Oct 12 12:02:26 AM UTC 24
Peak memory 221104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065653336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1065653336
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1302903367
Short name T203
Test name
Test status
Simulation time 547827273 ps
CPU time 256.85 seconds
Started Oct 11 11:59:01 PM UTC 24
Finished Oct 12 12:03:22 AM UTC 24
Peak memory 220772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302903367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.1302903367
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3396084150
Short name T812
Test name
Test status
Simulation time 7469053446 ps
CPU time 256.85 seconds
Started Oct 11 11:59:06 PM UTC 24
Finished Oct 12 12:03:27 AM UTC 24
Peak memory 231400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396084150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.3396084150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.2768100866
Short name T629
Test name
Test status
Simulation time 27801322 ps
CPU time 4.2 seconds
Started Oct 11 11:58:58 PM UTC 24
Finished Oct 11 11:59:04 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768100866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2768100866
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.2295404328
Short name T671
Test name
Test status
Simulation time 337282480 ps
CPU time 45.64 seconds
Started Oct 11 11:59:16 PM UTC 24
Finished Oct 12 12:00:03 AM UTC 24
Peak memory 216580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295404328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2295404328
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3616407890
Short name T136
Test name
Test status
Simulation time 23133298298 ps
CPU time 224.16 seconds
Started Oct 11 11:59:16 PM UTC 24
Finished Oct 12 12:03:04 AM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616407890 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.3616407890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.4147601627
Short name T646
Test name
Test status
Simulation time 35331266 ps
CPU time 6.39 seconds
Started Oct 11 11:59:21 PM UTC 24
Finished Oct 11 11:59:28 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147601627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.4147601627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.1320198323
Short name T656
Test name
Test status
Simulation time 152216244 ps
CPU time 20.92 seconds
Started Oct 11 11:59:18 PM UTC 24
Finished Oct 11 11:59:40 PM UTC 24
Peak memory 214828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320198323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1320198323
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.4222642273
Short name T662
Test name
Test status
Simulation time 1022331547 ps
CPU time 35.19 seconds
Started Oct 11 11:59:12 PM UTC 24
Finished Oct 11 11:59:48 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222642273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.4222642273
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.3259243436
Short name T722
Test name
Test status
Simulation time 40347687940 ps
CPU time 129.42 seconds
Started Oct 11 11:59:13 PM UTC 24
Finished Oct 12 12:01:25 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259243436 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3259243436
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1370487802
Short name T731
Test name
Test status
Simulation time 78642942792 ps
CPU time 138.44 seconds
Started Oct 11 11:59:16 PM UTC 24
Finished Oct 12 12:01:37 AM UTC 24
Peak memory 216612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370487802 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1370487802
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.1655832128
Short name T657
Test name
Test status
Simulation time 151540301 ps
CPU time 25.89 seconds
Started Oct 11 11:59:13 PM UTC 24
Finished Oct 11 11:59:40 PM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655832128 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1655832128
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.826295696
Short name T651
Test name
Test status
Simulation time 1582404211 ps
CPU time 14.16 seconds
Started Oct 11 11:59:18 PM UTC 24
Finished Oct 11 11:59:33 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826295696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.826295696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.3376733234
Short name T635
Test name
Test status
Simulation time 539829828 ps
CPU time 5 seconds
Started Oct 11 11:59:06 PM UTC 24
Finished Oct 11 11:59:12 PM UTC 24
Peak memory 214584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376733234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3376733234
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2253932375
Short name T672
Test name
Test status
Simulation time 9907257338 ps
CPU time 54.44 seconds
Started Oct 11 11:59:09 PM UTC 24
Finished Oct 12 12:00:05 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253932375 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2253932375
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.422557831
Short name T659
Test name
Test status
Simulation time 5358565155 ps
CPU time 30.12 seconds
Started Oct 11 11:59:10 PM UTC 24
Finished Oct 11 11:59:42 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422557831 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.422557831
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2288912973
Short name T634
Test name
Test status
Simulation time 41154564 ps
CPU time 3.46 seconds
Started Oct 11 11:59:07 PM UTC 24
Finished Oct 11 11:59:12 PM UTC 24
Peak memory 214792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288912973 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2288912973
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.2387774731
Short name T723
Test name
Test status
Simulation time 23229814963 ps
CPU time 117.76 seconds
Started Oct 11 11:59:25 PM UTC 24
Finished Oct 12 12:01:25 AM UTC 24
Peak memory 218788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387774731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2387774731
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3828111560
Short name T716
Test name
Test status
Simulation time 9464319803 ps
CPU time 109.67 seconds
Started Oct 11 11:59:25 PM UTC 24
Finished Oct 12 12:01:17 AM UTC 24
Peak memory 218796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828111560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3828111560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.4086519709
Short name T137
Test name
Test status
Simulation time 8112076061 ps
CPU time 374.51 seconds
Started Oct 11 11:59:25 PM UTC 24
Finished Oct 12 12:05:45 AM UTC 24
Peak memory 221164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086519709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.4086519709
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3130246935
Short name T891
Test name
Test status
Simulation time 15130942165 ps
CPU time 454.91 seconds
Started Oct 11 11:59:27 PM UTC 24
Finished Oct 12 12:07:08 AM UTC 24
Peak memory 232916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130246935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3130246935
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.1989094517
Short name T660
Test name
Test status
Simulation time 781605809 ps
CPU time 22.41 seconds
Started Oct 11 11:59:19 PM UTC 24
Finished Oct 11 11:59:43 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989094517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1989094517
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.761083766
Short name T149
Test name
Test status
Simulation time 406387074 ps
CPU time 37.44 seconds
Started Oct 11 11:59:37 PM UTC 24
Finished Oct 12 12:00:16 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761083766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.761083766
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1664026532
Short name T851
Test name
Test status
Simulation time 56463658769 ps
CPU time 278.96 seconds
Started Oct 11 11:59:37 PM UTC 24
Finished Oct 12 12:04:20 AM UTC 24
Peak memory 217000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664026532 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.1664026532
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2169238938
Short name T674
Test name
Test status
Simulation time 1762242816 ps
CPU time 22.24 seconds
Started Oct 11 11:59:42 PM UTC 24
Finished Oct 12 12:00:06 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169238938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2169238938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.3199560905
Short name T661
Test name
Test status
Simulation time 109048271 ps
CPU time 5.32 seconds
Started Oct 11 11:59:40 PM UTC 24
Finished Oct 11 11:59:46 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199560905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3199560905
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1626629775
Short name T70
Test name
Test status
Simulation time 477162566 ps
CPU time 15.92 seconds
Started Oct 11 11:59:32 PM UTC 24
Finished Oct 11 11:59:49 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626629775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1626629775
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2169871801
Short name T669
Test name
Test status
Simulation time 4068675939 ps
CPU time 21.16 seconds
Started Oct 11 11:59:35 PM UTC 24
Finished Oct 11 11:59:57 PM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169871801 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2169871801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2032385332
Short name T725
Test name
Test status
Simulation time 12562586576 ps
CPU time 111.55 seconds
Started Oct 11 11:59:35 PM UTC 24
Finished Oct 12 12:01:29 AM UTC 24
Peak memory 216940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032385332 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2032385332
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.2612607512
Short name T658
Test name
Test status
Simulation time 113017995 ps
CPU time 4.53 seconds
Started Oct 11 11:59:35 PM UTC 24
Finished Oct 11 11:59:41 PM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612607512 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2612607512
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.4053892846
Short name T675
Test name
Test status
Simulation time 1194559965 ps
CPU time 26.14 seconds
Started Oct 11 11:59:39 PM UTC 24
Finished Oct 12 12:00:07 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053892846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.4053892846
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.496169571
Short name T649
Test name
Test status
Simulation time 35474368 ps
CPU time 3.2 seconds
Started Oct 11 11:59:29 PM UTC 24
Finished Oct 11 11:59:33 PM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496169571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.496169571
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2191901255
Short name T71
Test name
Test status
Simulation time 4291252579 ps
CPU time 27.88 seconds
Started Oct 11 11:59:30 PM UTC 24
Finished Oct 12 12:00:00 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191901255 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2191901255
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3596079610
Short name T691
Test name
Test status
Simulation time 17635214015 ps
CPU time 66.92 seconds
Started Oct 11 11:59:31 PM UTC 24
Finished Oct 12 12:00:39 AM UTC 24
Peak memory 214660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596079610 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3596079610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.828698481
Short name T650
Test name
Test status
Simulation time 26172990 ps
CPU time 3.31 seconds
Started Oct 11 11:59:29 PM UTC 24
Finished Oct 11 11:59:33 PM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828698481 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.828698481
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.362636073
Short name T132
Test name
Test status
Simulation time 5553415340 ps
CPU time 263.67 seconds
Started Oct 11 11:59:42 PM UTC 24
Finished Oct 12 12:04:10 AM UTC 24
Peak memory 220844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362636073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.362636073
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2537394893
Short name T746
Test name
Test status
Simulation time 12260745469 ps
CPU time 129.16 seconds
Started Oct 11 11:59:44 PM UTC 24
Finished Oct 12 12:01:56 AM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537394893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2537394893
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2094893867
Short name T785
Test name
Test status
Simulation time 5690844138 ps
CPU time 180.63 seconds
Started Oct 11 11:59:43 PM UTC 24
Finished Oct 12 12:02:46 AM UTC 24
Peak memory 218788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094893867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.2094893867
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3593841024
Short name T690
Test name
Test status
Simulation time 116645174 ps
CPU time 53.09 seconds
Started Oct 11 11:59:44 PM UTC 24
Finished Oct 12 12:00:39 AM UTC 24
Peak memory 218728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593841024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3593841024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.836942224
Short name T663
Test name
Test status
Simulation time 22480011 ps
CPU time 4.9 seconds
Started Oct 11 11:59:42 PM UTC 24
Finished Oct 11 11:59:48 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836942224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.836942224
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.3865181605
Short name T695
Test name
Test status
Simulation time 400706473 ps
CPU time 47.04 seconds
Started Oct 11 11:59:57 PM UTC 24
Finished Oct 12 12:00:46 AM UTC 24
Peak memory 216876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865181605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3865181605
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.783192563
Short name T870
Test name
Test status
Simulation time 106079063227 ps
CPU time 292.97 seconds
Started Oct 11 11:59:59 PM UTC 24
Finished Oct 12 12:04:56 AM UTC 24
Peak memory 217000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783192563 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.783192563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3048330376
Short name T676
Test name
Test status
Simulation time 33139880 ps
CPU time 4.44 seconds
Started Oct 12 12:00:09 AM UTC 24
Finished Oct 12 12:00:14 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048330376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3048330376
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.1421674800
Short name T682
Test name
Test status
Simulation time 225024977 ps
CPU time 18.47 seconds
Started Oct 12 12:00:02 AM UTC 24
Finished Oct 12 12:00:25 AM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421674800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1421674800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.2859980875
Short name T685
Test name
Test status
Simulation time 1281950420 ps
CPU time 36.01 seconds
Started Oct 11 11:59:53 PM UTC 24
Finished Oct 12 12:00:31 AM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859980875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2859980875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.2128268905
Short name T683
Test name
Test status
Simulation time 5017543618 ps
CPU time 28.09 seconds
Started Oct 11 11:59:57 PM UTC 24
Finished Oct 12 12:00:26 AM UTC 24
Peak memory 214700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128268905 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2128268905
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3445072041
Short name T692
Test name
Test status
Simulation time 9859344272 ps
CPU time 43.8 seconds
Started Oct 11 11:59:57 PM UTC 24
Finished Oct 12 12:00:43 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445072041 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3445072041
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.3558870690
Short name T679
Test name
Test status
Simulation time 241915407 ps
CPU time 22.14 seconds
Started Oct 11 11:59:55 PM UTC 24
Finished Oct 12 12:00:19 AM UTC 24
Peak memory 214880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558870690 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3558870690
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.462702309
Short name T678
Test name
Test status
Simulation time 174825952 ps
CPU time 17.42 seconds
Started Oct 11 11:59:59 PM UTC 24
Finished Oct 12 12:00:18 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462702309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.462702309
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.818965825
Short name T666
Test name
Test status
Simulation time 1003192279 ps
CPU time 6.72 seconds
Started Oct 11 11:59:47 PM UTC 24
Finished Oct 11 11:59:55 PM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818965825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.818965825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3968568983
Short name T687
Test name
Test status
Simulation time 21818183179 ps
CPU time 44.8 seconds
Started Oct 11 11:59:50 PM UTC 24
Finished Oct 12 12:00:36 AM UTC 24
Peak memory 214936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968568983 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3968568983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2535941386
Short name T689
Test name
Test status
Simulation time 12739100425 ps
CPU time 45.04 seconds
Started Oct 11 11:59:51 PM UTC 24
Finished Oct 12 12:00:38 AM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535941386 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2535941386
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2994927076
Short name T665
Test name
Test status
Simulation time 131198451 ps
CPU time 3.5 seconds
Started Oct 11 11:59:50 PM UTC 24
Finished Oct 11 11:59:54 PM UTC 24
Peak memory 214792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994927076 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2994927076
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.2045102487
Short name T753
Test name
Test status
Simulation time 1826449180 ps
CPU time 113.91 seconds
Started Oct 12 12:00:09 AM UTC 24
Finished Oct 12 12:02:05 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045102487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2045102487
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2728477287
Short name T735
Test name
Test status
Simulation time 1861862036 ps
CPU time 91.26 seconds
Started Oct 12 12:00:09 AM UTC 24
Finished Oct 12 12:01:42 AM UTC 24
Peak memory 218732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728477287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2728477287
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.316049988
Short name T899
Test name
Test status
Simulation time 16286003306 ps
CPU time 565.91 seconds
Started Oct 12 12:00:09 AM UTC 24
Finished Oct 12 12:09:42 AM UTC 24
Peak memory 232912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316049988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.316049988
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.136662050
Short name T861
Test name
Test status
Simulation time 1605947644 ps
CPU time 264.54 seconds
Started Oct 12 12:00:09 AM UTC 24
Finished Oct 12 12:04:37 AM UTC 24
Peak memory 231528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136662050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.136662050
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.2417643364
Short name T688
Test name
Test status
Simulation time 186056371 ps
CPU time 29.71 seconds
Started Oct 12 12:00:02 AM UTC 24
Finished Oct 12 12:00:37 AM UTC 24
Peak memory 216868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417643364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2417643364
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.1765167786
Short name T724
Test name
Test status
Simulation time 7135037292 ps
CPU time 63.08 seconds
Started Oct 12 12:00:23 AM UTC 24
Finished Oct 12 12:01:28 AM UTC 24
Peak memory 218988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765167786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1765167786
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1383488690
Short name T881
Test name
Test status
Simulation time 36963641218 ps
CPU time 297.09 seconds
Started Oct 12 12:00:26 AM UTC 24
Finished Oct 12 12:05:27 AM UTC 24
Peak memory 218984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383488690 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.1383488690
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3236602745
Short name T696
Test name
Test status
Simulation time 215038404 ps
CPU time 11.03 seconds
Started Oct 12 12:00:34 AM UTC 24
Finished Oct 12 12:00:47 AM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236602745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3236602745
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.184954115
Short name T700
Test name
Test status
Simulation time 550590832 ps
CPU time 17.12 seconds
Started Oct 12 12:00:34 AM UTC 24
Finished Oct 12 12:00:53 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184954115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.184954115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.3927040991
Short name T698
Test name
Test status
Simulation time 1048787165 ps
CPU time 29.21 seconds
Started Oct 12 12:00:19 AM UTC 24
Finished Oct 12 12:00:50 AM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927040991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3927040991
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.3399978732
Short name T799
Test name
Test status
Simulation time 62283799934 ps
CPU time 166.54 seconds
Started Oct 12 12:00:21 AM UTC 24
Finished Oct 12 12:03:10 AM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399978732 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3399978732
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1131425105
Short name T240
Test name
Test status
Simulation time 6724635700 ps
CPU time 65.41 seconds
Started Oct 12 12:00:21 AM UTC 24
Finished Oct 12 12:01:28 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131425105 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1131425105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.2702470649
Short name T697
Test name
Test status
Simulation time 183133563 ps
CPU time 25.03 seconds
Started Oct 12 12:00:21 AM UTC 24
Finished Oct 12 12:00:47 AM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702470649 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2702470649
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.2456015261
Short name T693
Test name
Test status
Simulation time 960756233 ps
CPU time 13.77 seconds
Started Oct 12 12:00:28 AM UTC 24
Finished Oct 12 12:00:43 AM UTC 24
Peak memory 214884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456015261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2456015261
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.2254837048
Short name T681
Test name
Test status
Simulation time 159193116 ps
CPU time 3.62 seconds
Started Oct 12 12:00:15 AM UTC 24
Finished Oct 12 12:00:20 AM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254837048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2254837048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1895151069
Short name T709
Test name
Test status
Simulation time 6181589063 ps
CPU time 48.33 seconds
Started Oct 12 12:00:19 AM UTC 24
Finished Oct 12 12:01:09 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895151069 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1895151069
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1309800080
Short name T702
Test name
Test status
Simulation time 3513639058 ps
CPU time 38.64 seconds
Started Oct 12 12:00:19 AM UTC 24
Finished Oct 12 12:00:59 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309800080 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1309800080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2130693977
Short name T680
Test name
Test status
Simulation time 129818365 ps
CPU time 3.36 seconds
Started Oct 12 12:00:15 AM UTC 24
Finished Oct 12 12:00:19 AM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130693977 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2130693977
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.167642386
Short name T834
Test name
Test status
Simulation time 5627281012 ps
CPU time 206.6 seconds
Started Oct 12 12:00:34 AM UTC 24
Finished Oct 12 12:04:05 AM UTC 24
Peak memory 221148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167642386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.167642386
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.4019567443
Short name T736
Test name
Test status
Simulation time 1795992484 ps
CPU time 66.07 seconds
Started Oct 12 12:00:38 AM UTC 24
Finished Oct 12 12:01:46 AM UTC 24
Peak memory 216684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019567443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.4019567443
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.964542501
Short name T241
Test name
Test status
Simulation time 404640859 ps
CPU time 128.47 seconds
Started Oct 12 12:00:37 AM UTC 24
Finished Oct 12 12:02:48 AM UTC 24
Peak memory 218920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964542501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.964542501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2593149570
Short name T704
Test name
Test status
Simulation time 84034095 ps
CPU time 20.95 seconds
Started Oct 12 12:00:39 AM UTC 24
Finished Oct 12 12:01:02 AM UTC 24
Peak memory 216684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593149570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.2593149570
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.2807691585
Short name T213
Test name
Test status
Simulation time 2238971520 ps
CPU time 15.06 seconds
Started Oct 12 12:00:34 AM UTC 24
Finished Oct 12 12:00:51 AM UTC 24
Peak memory 216736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807691585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2807691585
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.3403163461
Short name T83
Test name
Test status
Simulation time 1247023759 ps
CPU time 13.13 seconds
Started Oct 11 11:47:32 PM UTC 24
Finished Oct 11 11:47:46 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403163461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3403163461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3696896905
Short name T86
Test name
Test status
Simulation time 22204814730 ps
CPU time 101.61 seconds
Started Oct 11 11:47:34 PM UTC 24
Finished Oct 11 11:49:17 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696896905 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.3696896905
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3226337991
Short name T177
Test name
Test status
Simulation time 430121308 ps
CPU time 22.62 seconds
Started Oct 11 11:47:38 PM UTC 24
Finished Oct 11 11:48:02 PM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226337991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3226337991
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.731686559
Short name T117
Test name
Test status
Simulation time 464834221 ps
CPU time 11.5 seconds
Started Oct 11 11:47:35 PM UTC 24
Finished Oct 11 11:47:47 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731686559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.731686559
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.950254385
Short name T173
Test name
Test status
Simulation time 132243210 ps
CPU time 23.28 seconds
Started Oct 11 11:47:30 PM UTC 24
Finished Oct 11 11:47:55 PM UTC 24
Peak memory 216868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950254385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.950254385
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.1143390798
Short name T108
Test name
Test status
Simulation time 50537982014 ps
CPU time 116.29 seconds
Started Oct 11 11:47:32 PM UTC 24
Finished Oct 11 11:49:30 PM UTC 24
Peak memory 214704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143390798 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1143390798
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.497795079
Short name T167
Test name
Test status
Simulation time 1069096834 ps
CPU time 12.02 seconds
Started Oct 11 11:47:32 PM UTC 24
Finished Oct 11 11:47:45 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497795079 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.497795079
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.3510222383
Short name T24
Test name
Test status
Simulation time 56667030 ps
CPU time 11.72 seconds
Started Oct 11 11:47:31 PM UTC 24
Finished Oct 11 11:47:44 PM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510222383 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3510222383
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.1298359074
Short name T172
Test name
Test status
Simulation time 549155813 ps
CPU time 18.29 seconds
Started Oct 11 11:47:35 PM UTC 24
Finished Oct 11 11:47:54 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298359074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1298359074
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.1185381682
Short name T96
Test name
Test status
Simulation time 119393392 ps
CPU time 4.91 seconds
Started Oct 11 11:47:22 PM UTC 24
Finished Oct 11 11:47:28 PM UTC 24
Peak memory 214804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185381682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1185381682
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.163595914
Short name T179
Test name
Test status
Simulation time 10254294142 ps
CPU time 33.73 seconds
Started Oct 11 11:47:29 PM UTC 24
Finished Oct 11 11:48:04 PM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163595914 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.163595914
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2656438555
Short name T119
Test name
Test status
Simulation time 2292086054 ps
CPU time 18.28 seconds
Started Oct 11 11:47:30 PM UTC 24
Finished Oct 11 11:47:50 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656438555 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2656438555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3772495176
Short name T5
Test name
Test status
Simulation time 28432990 ps
CPU time 2.92 seconds
Started Oct 11 11:47:27 PM UTC 24
Finished Oct 11 11:47:31 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772495176 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3772495176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2950731472
Short name T279
Test name
Test status
Simulation time 7408138312 ps
CPU time 100.26 seconds
Started Oct 11 11:47:41 PM UTC 24
Finished Oct 11 11:49:24 PM UTC 24
Peak memory 217004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950731472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2950731472
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3995746118
Short name T47
Test name
Test status
Simulation time 7995912251 ps
CPU time 202.05 seconds
Started Oct 11 11:47:41 PM UTC 24
Finished Oct 11 11:51:07 PM UTC 24
Peak memory 218792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995746118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.3995746118
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.3529077642
Short name T159
Test name
Test status
Simulation time 830437211 ps
CPU time 22.34 seconds
Started Oct 11 11:47:36 PM UTC 24
Finished Oct 11 11:48:00 PM UTC 24
Peak memory 216680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529077642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3529077642
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.1341988415
Short name T703
Test name
Test status
Simulation time 54019498 ps
CPU time 10.37 seconds
Started Oct 12 12:00:49 AM UTC 24
Finished Oct 12 12:01:01 AM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341988415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1341988415
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1799407763
Short name T872
Test name
Test status
Simulation time 73345452973 ps
CPU time 247.35 seconds
Started Oct 12 12:00:51 AM UTC 24
Finished Oct 12 12:05:02 AM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799407763 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.1799407763
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.4117405046
Short name T711
Test name
Test status
Simulation time 2236594970 ps
CPU time 15.05 seconds
Started Oct 12 12:00:55 AM UTC 24
Finished Oct 12 12:01:11 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117405046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.4117405046
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.3601137199
Short name T719
Test name
Test status
Simulation time 1663465080 ps
CPU time 22.84 seconds
Started Oct 12 12:00:54 AM UTC 24
Finished Oct 12 12:01:18 AM UTC 24
Peak memory 214796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601137199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3601137199
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.2512873984
Short name T720
Test name
Test status
Simulation time 343012982 ps
CPU time 32.86 seconds
Started Oct 12 12:00:47 AM UTC 24
Finished Oct 12 12:01:21 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512873984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2512873984
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.651839607
Short name T760
Test name
Test status
Simulation time 12173471766 ps
CPU time 83.24 seconds
Started Oct 12 12:00:49 AM UTC 24
Finished Oct 12 12:02:15 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651839607 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.651839607
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1334090357
Short name T712
Test name
Test status
Simulation time 2120322213 ps
CPU time 20.81 seconds
Started Oct 12 12:00:49 AM UTC 24
Finished Oct 12 12:01:12 AM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334090357 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1334090357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.3419294517
Short name T714
Test name
Test status
Simulation time 131649264 ps
CPU time 24.74 seconds
Started Oct 12 12:00:49 AM UTC 24
Finished Oct 12 12:01:16 AM UTC 24
Peak memory 216668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419294517 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3419294517
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.1063865414
Short name T706
Test name
Test status
Simulation time 665371530 ps
CPU time 11.52 seconds
Started Oct 12 12:00:51 AM UTC 24
Finished Oct 12 12:01:04 AM UTC 24
Peak memory 214828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063865414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1063865414
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.468625927
Short name T72
Test name
Test status
Simulation time 286288402 ps
CPU time 3.96 seconds
Started Oct 12 12:00:41 AM UTC 24
Finished Oct 12 12:00:46 AM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468625927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.468625927
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2764441633
Short name T718
Test name
Test status
Simulation time 7605532283 ps
CPU time 33.28 seconds
Started Oct 12 12:00:44 AM UTC 24
Finished Oct 12 12:01:18 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764441633 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2764441633
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1263501599
Short name T727
Test name
Test status
Simulation time 5084523883 ps
CPU time 47.12 seconds
Started Oct 12 12:00:45 AM UTC 24
Finished Oct 12 12:01:34 AM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263501599 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1263501599
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1709947436
Short name T694
Test name
Test status
Simulation time 26878622 ps
CPU time 3.22 seconds
Started Oct 12 12:00:41 AM UTC 24
Finished Oct 12 12:00:46 AM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709947436 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1709947436
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.1839834252
Short name T758
Test name
Test status
Simulation time 2541570973 ps
CPU time 72.12 seconds
Started Oct 12 12:00:59 AM UTC 24
Finished Oct 12 12:02:13 AM UTC 24
Peak memory 216936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839834252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1839834252
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3579217965
Short name T778
Test name
Test status
Simulation time 1829604948 ps
CPU time 95.63 seconds
Started Oct 12 12:01:04 AM UTC 24
Finished Oct 12 12:02:41 AM UTC 24
Peak memory 216880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579217965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3579217965
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3885047113
Short name T866
Test name
Test status
Simulation time 686832765 ps
CPU time 222.42 seconds
Started Oct 12 12:01:00 AM UTC 24
Finished Oct 12 12:04:46 AM UTC 24
Peak memory 218728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885047113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.3885047113
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3003339863
Short name T886
Test name
Test status
Simulation time 1971933704 ps
CPU time 287.95 seconds
Started Oct 12 12:01:04 AM UTC 24
Finished Oct 12 12:05:56 AM UTC 24
Peak memory 231528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003339863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3003339863
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.536656116
Short name T705
Test name
Test status
Simulation time 139532392 ps
CPU time 6.78 seconds
Started Oct 12 12:00:54 AM UTC 24
Finished Oct 12 12:01:02 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536656116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.536656116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.869035731
Short name T732
Test name
Test status
Simulation time 124130866 ps
CPU time 19.63 seconds
Started Oct 12 12:01:17 AM UTC 24
Finished Oct 12 12:01:38 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869035731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.869035731
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3460976825
Short name T141
Test name
Test status
Simulation time 15160542180 ps
CPU time 155.95 seconds
Started Oct 12 12:01:17 AM UTC 24
Finished Oct 12 12:03:55 AM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460976825 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.3460976825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.4044499584
Short name T721
Test name
Test status
Simulation time 49151540 ps
CPU time 3.4 seconds
Started Oct 12 12:01:19 AM UTC 24
Finished Oct 12 12:01:24 AM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044499584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.4044499584
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.1613643626
Short name T733
Test name
Test status
Simulation time 172951832 ps
CPU time 18.95 seconds
Started Oct 12 12:01:19 AM UTC 24
Finished Oct 12 12:01:40 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613643626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1613643626
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.201111626
Short name T729
Test name
Test status
Simulation time 337057768 ps
CPU time 23.88 seconds
Started Oct 12 12:01:11 AM UTC 24
Finished Oct 12 12:01:36 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201111626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.201111626
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.3373826097
Short name T74
Test name
Test status
Simulation time 5461592750 ps
CPU time 33.9 seconds
Started Oct 12 12:01:12 AM UTC 24
Finished Oct 12 12:01:47 AM UTC 24
Peak memory 214700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373826097 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3373826097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2043586721
Short name T730
Test name
Test status
Simulation time 7555608764 ps
CPU time 21.17 seconds
Started Oct 12 12:01:14 AM UTC 24
Finished Oct 12 12:01:36 AM UTC 24
Peak memory 214668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043586721 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2043586721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.1821987669
Short name T737
Test name
Test status
Simulation time 344463985 ps
CPU time 34.13 seconds
Started Oct 12 12:01:11 AM UTC 24
Finished Oct 12 12:01:46 AM UTC 24
Peak memory 216864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821987669 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1821987669
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.3805549011
Short name T734
Test name
Test status
Simulation time 358586338 ps
CPU time 19.14 seconds
Started Oct 12 12:01:19 AM UTC 24
Finished Oct 12 12:01:40 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805549011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3805549011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.2633512391
Short name T708
Test name
Test status
Simulation time 39208712 ps
CPU time 2.95 seconds
Started Oct 12 12:01:04 AM UTC 24
Finished Oct 12 12:01:08 AM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633512391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2633512391
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1664766582
Short name T742
Test name
Test status
Simulation time 8950259730 ps
CPU time 46 seconds
Started Oct 12 12:01:07 AM UTC 24
Finished Oct 12 12:01:54 AM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664766582 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1664766582
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1156550875
Short name T75
Test name
Test status
Simulation time 5423705937 ps
CPU time 37.42 seconds
Started Oct 12 12:01:09 AM UTC 24
Finished Oct 12 12:01:48 AM UTC 24
Peak memory 214660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156550875 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1156550875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1015992981
Short name T710
Test name
Test status
Simulation time 35233037 ps
CPU time 3.32 seconds
Started Oct 12 12:01:05 AM UTC 24
Finished Oct 12 12:01:09 AM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015992981 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1015992981
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.1451500006
Short name T832
Test name
Test status
Simulation time 5424339907 ps
CPU time 162.22 seconds
Started Oct 12 12:01:20 AM UTC 24
Finished Oct 12 12:04:04 AM UTC 24
Peak memory 219052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451500006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1451500006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.4137315176
Short name T811
Test name
Test status
Simulation time 4262974704 ps
CPU time 121.36 seconds
Started Oct 12 12:01:22 AM UTC 24
Finished Oct 12 12:03:26 AM UTC 24
Peak memory 216752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137315176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.4137315176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3587621299
Short name T838
Test name
Test status
Simulation time 2530127911 ps
CPU time 168.87 seconds
Started Oct 12 12:01:20 AM UTC 24
Finished Oct 12 12:04:11 AM UTC 24
Peak memory 218788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587621299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.3587621299
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.4124439725
Short name T810
Test name
Test status
Simulation time 364460105 ps
CPU time 117.63 seconds
Started Oct 12 12:01:26 AM UTC 24
Finished Oct 12 12:03:26 AM UTC 24
Peak memory 220784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124439725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.4124439725
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.3644034124
Short name T73
Test name
Test status
Simulation time 292583897 ps
CPU time 6.75 seconds
Started Oct 12 12:01:19 AM UTC 24
Finished Oct 12 12:01:27 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644034124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3644034124
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.2828242563
Short name T787
Test name
Test status
Simulation time 2657253583 ps
CPU time 73.12 seconds
Started Oct 12 12:01:35 AM UTC 24
Finished Oct 12 12:02:50 AM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828242563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2828242563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2649155074
Short name T783
Test name
Test status
Simulation time 7509917451 ps
CPU time 65 seconds
Started Oct 12 12:01:38 AM UTC 24
Finished Oct 12 12:02:44 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649155074 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.2649155074
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3074007469
Short name T745
Test name
Test status
Simulation time 280975667 ps
CPU time 13.28 seconds
Started Oct 12 12:01:41 AM UTC 24
Finished Oct 12 12:01:56 AM UTC 24
Peak memory 214284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074007469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3074007469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.360856567
Short name T748
Test name
Test status
Simulation time 1898990518 ps
CPU time 18.59 seconds
Started Oct 12 12:01:39 AM UTC 24
Finished Oct 12 12:01:59 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360856567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.360856567
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.3280356469
Short name T747
Test name
Test status
Simulation time 430964647 ps
CPU time 24.41 seconds
Started Oct 12 12:01:30 AM UTC 24
Finished Oct 12 12:01:56 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280356469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3280356469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2661126788
Short name T875
Test name
Test status
Simulation time 123849692004 ps
CPU time 214 seconds
Started Oct 12 12:01:33 AM UTC 24
Finished Oct 12 12:05:11 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661126788 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2661126788
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2491314538
Short name T801
Test name
Test status
Simulation time 41434634616 ps
CPU time 94.27 seconds
Started Oct 12 12:01:35 AM UTC 24
Finished Oct 12 12:03:11 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491314538 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2491314538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.2154099688
Short name T738
Test name
Test status
Simulation time 125361774 ps
CPU time 14.23 seconds
Started Oct 12 12:01:32 AM UTC 24
Finished Oct 12 12:01:47 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154099688 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2154099688
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.1801722688
Short name T739
Test name
Test status
Simulation time 839657946 ps
CPU time 11.17 seconds
Started Oct 12 12:01:38 AM UTC 24
Finished Oct 12 12:01:50 AM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801722688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1801722688
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.2696066163
Short name T728
Test name
Test status
Simulation time 357600885 ps
CPU time 5.59 seconds
Started Oct 12 12:01:27 AM UTC 24
Finished Oct 12 12:01:34 AM UTC 24
Peak memory 214584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696066163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2696066163
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3797544968
Short name T755
Test name
Test status
Simulation time 5168718609 ps
CPU time 39.52 seconds
Started Oct 12 12:01:30 AM UTC 24
Finished Oct 12 12:02:11 AM UTC 24
Peak memory 214872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797544968 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3797544968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1288667843
Short name T751
Test name
Test status
Simulation time 3635831118 ps
CPU time 32.02 seconds
Started Oct 12 12:01:30 AM UTC 24
Finished Oct 12 12:02:03 AM UTC 24
Peak memory 214656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288667843 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1288667843
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1331878197
Short name T726
Test name
Test status
Simulation time 30059840 ps
CPU time 2.72 seconds
Started Oct 12 12:01:28 AM UTC 24
Finished Oct 12 12:01:31 AM UTC 24
Peak memory 214792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331878197 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1331878197
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.817673059
Short name T750
Test name
Test status
Simulation time 169944839 ps
CPU time 18.1 seconds
Started Oct 12 12:01:41 AM UTC 24
Finished Oct 12 12:02:01 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817673059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.817673059
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2681728952
Short name T767
Test name
Test status
Simulation time 4942216185 ps
CPU time 39.16 seconds
Started Oct 12 12:01:48 AM UTC 24
Finished Oct 12 12:02:29 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681728952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2681728952
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.77077366
Short name T740
Test name
Test status
Simulation time 61697067 ps
CPU time 7.35 seconds
Started Oct 12 12:01:43 AM UTC 24
Finished Oct 12 12:01:51 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77077366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.77077366
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3914321560
Short name T813
Test name
Test status
Simulation time 350568548 ps
CPU time 96.55 seconds
Started Oct 12 12:01:48 AM UTC 24
Finished Oct 12 12:03:27 AM UTC 24
Peak memory 220780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914321560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.3914321560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.1697421987
Short name T749
Test name
Test status
Simulation time 196005465 ps
CPU time 18.93 seconds
Started Oct 12 12:01:39 AM UTC 24
Finished Oct 12 12:02:00 AM UTC 24
Peak memory 214888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697421987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1697421987
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.1603245814
Short name T761
Test name
Test status
Simulation time 431753803 ps
CPU time 21.63 seconds
Started Oct 12 12:01:56 AM UTC 24
Finished Oct 12 12:02:18 AM UTC 24
Peak memory 214828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603245814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1603245814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1548308927
Short name T837
Test name
Test status
Simulation time 17762755368 ps
CPU time 130.37 seconds
Started Oct 12 12:01:58 AM UTC 24
Finished Oct 12 12:04:11 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548308927 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.1548308927
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1311232101
Short name T762
Test name
Test status
Simulation time 143385470 ps
CPU time 17.09 seconds
Started Oct 12 12:02:00 AM UTC 24
Finished Oct 12 12:02:19 AM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311232101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1311232101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.2450314100
Short name T764
Test name
Test status
Simulation time 740045981 ps
CPU time 21.62 seconds
Started Oct 12 12:01:59 AM UTC 24
Finished Oct 12 12:02:21 AM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450314100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2450314100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.1231509546
Short name T76
Test name
Test status
Simulation time 723127109 ps
CPU time 11.17 seconds
Started Oct 12 12:01:54 AM UTC 24
Finished Oct 12 12:02:06 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231509546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1231509546
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.1559856449
Short name T860
Test name
Test status
Simulation time 99403219158 ps
CPU time 160.73 seconds
Started Oct 12 12:01:54 AM UTC 24
Finished Oct 12 12:04:37 AM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559856449 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1559856449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3238537576
Short name T242
Test name
Test status
Simulation time 7577966703 ps
CPU time 56.24 seconds
Started Oct 12 12:01:56 AM UTC 24
Finished Oct 12 12:02:53 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238537576 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3238537576
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.34848057
Short name T759
Test name
Test status
Simulation time 195348500 ps
CPU time 19.83 seconds
Started Oct 12 12:01:54 AM UTC 24
Finished Oct 12 12:02:15 AM UTC 24
Peak memory 216872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34848057 -assert nopostproc +UVM_TESTNAME=xbar_
base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.34848057
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.4056370142
Short name T768
Test name
Test status
Simulation time 1178584741 ps
CPU time 30.11 seconds
Started Oct 12 12:01:59 AM UTC 24
Finished Oct 12 12:02:30 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056370142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.4056370142
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.2125428671
Short name T741
Test name
Test status
Simulation time 97563231 ps
CPU time 2.96 seconds
Started Oct 12 12:01:48 AM UTC 24
Finished Oct 12 12:01:52 AM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125428671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2125428671
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3734014825
Short name T784
Test name
Test status
Simulation time 10294163597 ps
CPU time 53.56 seconds
Started Oct 12 12:01:51 AM UTC 24
Finished Oct 12 12:02:46 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734014825 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3734014825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2333176811
Short name T786
Test name
Test status
Simulation time 3979941403 ps
CPU time 53.57 seconds
Started Oct 12 12:01:53 AM UTC 24
Finished Oct 12 12:02:49 AM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333176811 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2333176811
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3222937525
Short name T743
Test name
Test status
Simulation time 25116817 ps
CPU time 2.87 seconds
Started Oct 12 12:01:50 AM UTC 24
Finished Oct 12 12:01:54 AM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222937525 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3222937525
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2706069818
Short name T865
Test name
Test status
Simulation time 7967661016 ps
CPU time 160.26 seconds
Started Oct 12 12:02:00 AM UTC 24
Finished Oct 12 12:04:43 AM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706069818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2706069818
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3905212410
Short name T849
Test name
Test status
Simulation time 2264686012 ps
CPU time 130.75 seconds
Started Oct 12 12:02:05 AM UTC 24
Finished Oct 12 12:04:18 AM UTC 24
Peak memory 218796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905212410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3905212410
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.292867069
Short name T205
Test name
Test status
Simulation time 3074898713 ps
CPU time 564.85 seconds
Started Oct 12 12:02:02 AM UTC 24
Finished Oct 12 12:11:34 AM UTC 24
Peak memory 232908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292867069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.292867069
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.748788748
Short name T889
Test name
Test status
Simulation time 1605490790 ps
CPU time 236.13 seconds
Started Oct 12 12:02:08 AM UTC 24
Finished Oct 12 12:06:08 AM UTC 24
Peak memory 220920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748788748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.748788748
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.2166241823
Short name T754
Test name
Test status
Simulation time 302393593 ps
CPU time 6.87 seconds
Started Oct 12 12:01:59 AM UTC 24
Finished Oct 12 12:02:07 AM UTC 24
Peak memory 216868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166241823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2166241823
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.85745843
Short name T765
Test name
Test status
Simulation time 192974429 ps
CPU time 5.76 seconds
Started Oct 12 12:02:17 AM UTC 24
Finished Oct 12 12:02:24 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85745843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_
TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar
_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.85745843
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3155225851
Short name T884
Test name
Test status
Simulation time 28625166833 ps
CPU time 207.38 seconds
Started Oct 12 12:02:17 AM UTC 24
Finished Oct 12 12:05:48 AM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155225851 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.3155225851
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3069945455
Short name T779
Test name
Test status
Simulation time 117280955 ps
CPU time 16.42 seconds
Started Oct 12 12:02:24 AM UTC 24
Finished Oct 12 12:02:41 AM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069945455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3069945455
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.3490950192
Short name T791
Test name
Test status
Simulation time 932030291 ps
CPU time 32.62 seconds
Started Oct 12 12:02:21 AM UTC 24
Finished Oct 12 12:02:55 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490950192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3490950192
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.597968844
Short name T772
Test name
Test status
Simulation time 363795598 ps
CPU time 20.72 seconds
Started Oct 12 12:02:12 AM UTC 24
Finished Oct 12 12:02:34 AM UTC 24
Peak memory 216872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597968844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.597968844
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.519832321
Short name T833
Test name
Test status
Simulation time 20070844013 ps
CPU time 107.3 seconds
Started Oct 12 12:02:15 AM UTC 24
Finished Oct 12 12:04:05 AM UTC 24
Peak memory 216928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519832321 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.519832321
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1689986802
Short name T857
Test name
Test status
Simulation time 22468138471 ps
CPU time 129.91 seconds
Started Oct 12 12:02:15 AM UTC 24
Finished Oct 12 12:04:28 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689986802 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1689986802
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.348782233
Short name T773
Test name
Test status
Simulation time 132169448 ps
CPU time 19.62 seconds
Started Oct 12 12:02:15 AM UTC 24
Finished Oct 12 12:02:36 AM UTC 24
Peak memory 216668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348782233 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.348782233
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.1284598322
Short name T771
Test name
Test status
Simulation time 687794225 ps
CPU time 11.83 seconds
Started Oct 12 12:02:21 AM UTC 24
Finished Oct 12 12:02:34 AM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284598322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1284598322
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.612377662
Short name T757
Test name
Test status
Simulation time 112042886 ps
CPU time 3.57 seconds
Started Oct 12 12:02:08 AM UTC 24
Finished Oct 12 12:02:13 AM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612377662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.612377662
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3551382819
Short name T777
Test name
Test status
Simulation time 4583938872 ps
CPU time 30.28 seconds
Started Oct 12 12:02:08 AM UTC 24
Finished Oct 12 12:02:40 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551382819 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3551382819
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1641017402
Short name T780
Test name
Test status
Simulation time 3477231081 ps
CPU time 30.4 seconds
Started Oct 12 12:02:10 AM UTC 24
Finished Oct 12 12:02:42 AM UTC 24
Peak memory 214848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641017402 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1641017402
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2072235112
Short name T756
Test name
Test status
Simulation time 142924528 ps
CPU time 3.38 seconds
Started Oct 12 12:02:08 AM UTC 24
Finished Oct 12 12:02:13 AM UTC 24
Peak memory 214792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072235112 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2072235112
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.2492921067
Short name T797
Test name
Test status
Simulation time 1528153387 ps
CPU time 40.51 seconds
Started Oct 12 12:02:26 AM UTC 24
Finished Oct 12 12:03:08 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492921067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2492921067
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3950939389
Short name T868
Test name
Test status
Simulation time 12115319681 ps
CPU time 135.65 seconds
Started Oct 12 12:02:30 AM UTC 24
Finished Oct 12 12:04:48 AM UTC 24
Peak memory 218800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950939389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3950939389
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1323733122
Short name T896
Test name
Test status
Simulation time 4040183328 ps
CPU time 343.18 seconds
Started Oct 12 12:02:27 AM UTC 24
Finished Oct 12 12:08:15 AM UTC 24
Peak memory 220836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323733122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.1323733122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.726513106
Short name T869
Test name
Test status
Simulation time 490628715 ps
CPU time 138.42 seconds
Started Oct 12 12:02:32 AM UTC 24
Finished Oct 12 12:04:53 AM UTC 24
Peak memory 220784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726513106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.726513106
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.1076632894
Short name T770
Test name
Test status
Simulation time 289142899 ps
CPU time 8.28 seconds
Started Oct 12 12:02:24 AM UTC 24
Finished Oct 12 12:02:33 AM UTC 24
Peak memory 216672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076632894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1076632894
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.2708805613
Short name T790
Test name
Test status
Simulation time 223200131 ps
CPU time 9.59 seconds
Started Oct 12 12:02:42 AM UTC 24
Finished Oct 12 12:02:53 AM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708805613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2708805613
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1886285089
Short name T142
Test name
Test status
Simulation time 84833877258 ps
CPU time 304.48 seconds
Started Oct 12 12:02:45 AM UTC 24
Finished Oct 12 12:07:53 AM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886285089 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.1886285089
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3880208852
Short name T809
Test name
Test status
Simulation time 1119727251 ps
CPU time 35.38 seconds
Started Oct 12 12:02:45 AM UTC 24
Finished Oct 12 12:03:22 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880208852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3880208852
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3140638122
Short name T789
Test name
Test status
Simulation time 58166872 ps
CPU time 5.08 seconds
Started Oct 12 12:02:45 AM UTC 24
Finished Oct 12 12:02:51 AM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140638122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3140638122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1844737518
Short name T781
Test name
Test status
Simulation time 274504605 ps
CPU time 3.59 seconds
Started Oct 12 12:02:38 AM UTC 24
Finished Oct 12 12:02:43 AM UTC 24
Peak memory 214564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844737518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1844737518
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3922465279
Short name T846
Test name
Test status
Simulation time 19546243155 ps
CPU time 91.14 seconds
Started Oct 12 12:02:42 AM UTC 24
Finished Oct 12 12:04:15 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922465279 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3922465279
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3956005114
Short name T874
Test name
Test status
Simulation time 15624460667 ps
CPU time 145.73 seconds
Started Oct 12 12:02:42 AM UTC 24
Finished Oct 12 12:05:10 AM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956005114 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3956005114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2846401991
Short name T782
Test name
Test status
Simulation time 25883843 ps
CPU time 4.19 seconds
Started Oct 12 12:02:38 AM UTC 24
Finished Oct 12 12:02:44 AM UTC 24
Peak memory 214564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846401991 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2846401991
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.2645534364
Short name T796
Test name
Test status
Simulation time 1199108602 ps
CPU time 21.81 seconds
Started Oct 12 12:02:45 AM UTC 24
Finished Oct 12 12:03:08 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645534364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2645534364
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.3551375562
Short name T774
Test name
Test status
Simulation time 71598276 ps
CPU time 3.29 seconds
Started Oct 12 12:02:32 AM UTC 24
Finished Oct 12 12:02:36 AM UTC 24
Peak memory 214584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551375562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3551375562
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1747092676
Short name T806
Test name
Test status
Simulation time 18718993633 ps
CPU time 39.69 seconds
Started Oct 12 12:02:36 AM UTC 24
Finished Oct 12 12:03:18 AM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747092676 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1747092676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.453963327
Short name T222
Test name
Test status
Simulation time 17486128704 ps
CPU time 32.71 seconds
Started Oct 12 12:02:36 AM UTC 24
Finished Oct 12 12:03:11 AM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453963327 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.453963327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3087039998
Short name T775
Test name
Test status
Simulation time 26854852 ps
CPU time 3.13 seconds
Started Oct 12 12:02:34 AM UTC 24
Finished Oct 12 12:02:39 AM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087039998 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3087039998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.224330092
Short name T876
Test name
Test status
Simulation time 1983645741 ps
CPU time 141.27 seconds
Started Oct 12 12:02:48 AM UTC 24
Finished Oct 12 12:05:11 AM UTC 24
Peak memory 218728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224330092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.224330092
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3825342434
Short name T802
Test name
Test status
Simulation time 236511155 ps
CPU time 23.16 seconds
Started Oct 12 12:02:48 AM UTC 24
Finished Oct 12 12:03:12 AM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825342434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3825342434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3612195121
Short name T879
Test name
Test status
Simulation time 398715530 ps
CPU time 150.07 seconds
Started Oct 12 12:02:48 AM UTC 24
Finished Oct 12 12:05:20 AM UTC 24
Peak memory 218920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612195121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.3612195121
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1064002140
Short name T817
Test name
Test status
Simulation time 125653606 ps
CPU time 44.1 seconds
Started Oct 12 12:02:51 AM UTC 24
Finished Oct 12 12:03:36 AM UTC 24
Peak memory 218864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064002140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.1064002140
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.3415923500
Short name T794
Test name
Test status
Simulation time 183493584 ps
CPU time 11.86 seconds
Started Oct 12 12:02:45 AM UTC 24
Finished Oct 12 12:02:58 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415923500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3415923500
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.1267722910
Short name T803
Test name
Test status
Simulation time 1109645691 ps
CPU time 13.8 seconds
Started Oct 12 12:02:58 AM UTC 24
Finished Oct 12 12:03:13 AM UTC 24
Peak memory 214636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267722910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1267722910
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.761223366
Short name T885
Test name
Test status
Simulation time 24846858480 ps
CPU time 165.97 seconds
Started Oct 12 12:03:00 AM UTC 24
Finished Oct 12 12:05:49 AM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761223366 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.761223366
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.922370297
Short name T816
Test name
Test status
Simulation time 2764706271 ps
CPU time 18.4 seconds
Started Oct 12 12:03:10 AM UTC 24
Finished Oct 12 12:03:29 AM UTC 24
Peak memory 214700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922370297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.922370297
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.2404531964
Short name T798
Test name
Test status
Simulation time 68614442 ps
CPU time 6.44 seconds
Started Oct 12 12:03:01 AM UTC 24
Finished Oct 12 12:03:08 AM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404531964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2404531964
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.700520892
Short name T805
Test name
Test status
Simulation time 781694645 ps
CPU time 23.02 seconds
Started Oct 12 12:02:53 AM UTC 24
Finished Oct 12 12:03:18 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700520892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.700520892
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1343297305
Short name T847
Test name
Test status
Simulation time 14124906907 ps
CPU time 79.12 seconds
Started Oct 12 12:02:55 AM UTC 24
Finished Oct 12 12:04:17 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343297305 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1343297305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2441529940
Short name T827
Test name
Test status
Simulation time 10295090727 ps
CPU time 55.74 seconds
Started Oct 12 12:02:58 AM UTC 24
Finished Oct 12 12:03:55 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441529940 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2441529940
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2032403782
Short name T800
Test name
Test status
Simulation time 111668505 ps
CPU time 14.22 seconds
Started Oct 12 12:02:55 AM UTC 24
Finished Oct 12 12:03:11 AM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032403782 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2032403782
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.4182927145
Short name T814
Test name
Test status
Simulation time 1113129990 ps
CPU time 26.32 seconds
Started Oct 12 12:03:01 AM UTC 24
Finished Oct 12 12:03:28 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182927145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.4182927145
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3533871786
Short name T793
Test name
Test status
Simulation time 240459853 ps
CPU time 5 seconds
Started Oct 12 12:02:51 AM UTC 24
Finished Oct 12 12:02:57 AM UTC 24
Peak memory 214040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533871786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3533871786
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2404385316
Short name T820
Test name
Test status
Simulation time 22406342637 ps
CPU time 47.51 seconds
Started Oct 12 12:02:53 AM UTC 24
Finished Oct 12 12:03:42 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404385316 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2404385316
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3476517112
Short name T804
Test name
Test status
Simulation time 3443478801 ps
CPU time 22.58 seconds
Started Oct 12 12:02:53 AM UTC 24
Finished Oct 12 12:03:17 AM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476517112 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3476517112
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1710011106
Short name T792
Test name
Test status
Simulation time 35601999 ps
CPU time 3.35 seconds
Started Oct 12 12:02:51 AM UTC 24
Finished Oct 12 12:02:55 AM UTC 24
Peak memory 214080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710011106 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1710011106
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.3186203857
Short name T898
Test name
Test status
Simulation time 31957741280 ps
CPU time 354.13 seconds
Started Oct 12 12:03:10 AM UTC 24
Finished Oct 12 12:09:08 AM UTC 24
Peak memory 221472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186203857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3186203857
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2138400624
Short name T825
Test name
Test status
Simulation time 1815010461 ps
CPU time 33.86 seconds
Started Oct 12 12:03:13 AM UTC 24
Finished Oct 12 12:03:49 AM UTC 24
Peak memory 216684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138400624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2138400624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.661289832
Short name T882
Test name
Test status
Simulation time 366038097 ps
CPU time 144.39 seconds
Started Oct 12 12:03:10 AM UTC 24
Finished Oct 12 12:05:37 AM UTC 24
Peak memory 218724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661289832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.661289832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.812444206
Short name T890
Test name
Test status
Simulation time 2314288823 ps
CPU time 228.8 seconds
Started Oct 12 12:03:13 AM UTC 24
Finished Oct 12 12:07:06 AM UTC 24
Peak memory 221132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812444206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.812444206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.3665394040
Short name T815
Test name
Test status
Simulation time 624616750 ps
CPU time 21.99 seconds
Started Oct 12 12:03:05 AM UTC 24
Finished Oct 12 12:03:29 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665394040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3665394040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.737728699
Short name T206
Test name
Test status
Simulation time 739542222 ps
CPU time 44.06 seconds
Started Oct 12 12:03:21 AM UTC 24
Finished Oct 12 12:04:07 AM UTC 24
Peak memory 214828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737728699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.737728699
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1450721353
Short name T138
Test name
Test status
Simulation time 47935677014 ps
CPU time 170.53 seconds
Started Oct 12 12:03:23 AM UTC 24
Finished Oct 12 12:06:16 AM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450721353 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.1450721353
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3542943824
Short name T822
Test name
Test status
Simulation time 86438351 ps
CPU time 10.87 seconds
Started Oct 12 12:03:31 AM UTC 24
Finished Oct 12 12:03:43 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542943824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3542943824
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1900768091
Short name T828
Test name
Test status
Simulation time 2874812788 ps
CPU time 32.4 seconds
Started Oct 12 12:03:25 AM UTC 24
Finished Oct 12 12:03:59 AM UTC 24
Peak memory 214688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900768091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1900768091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.1465836386
Short name T150
Test name
Test status
Simulation time 1351924049 ps
CPU time 45.41 seconds
Started Oct 12 12:03:19 AM UTC 24
Finished Oct 12 12:04:06 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465836386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1465836386
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.2283157101
Short name T871
Test name
Test status
Simulation time 21363128130 ps
CPU time 98.59 seconds
Started Oct 12 12:03:19 AM UTC 24
Finished Oct 12 12:05:00 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283157101 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2283157101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3652201158
Short name T836
Test name
Test status
Simulation time 4092696607 ps
CPU time 46.59 seconds
Started Oct 12 12:03:21 AM UTC 24
Finished Oct 12 12:04:09 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652201158 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3652201158
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.462937283
Short name T823
Test name
Test status
Simulation time 368236381 ps
CPU time 25.29 seconds
Started Oct 12 12:03:19 AM UTC 24
Finished Oct 12 12:03:46 AM UTC 24
Peak memory 214816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462937283 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.462937283
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.1390928171
Short name T821
Test name
Test status
Simulation time 329508546 ps
CPU time 18.72 seconds
Started Oct 12 12:03:23 AM UTC 24
Finished Oct 12 12:03:43 AM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390928171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1390928171
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.3879572503
Short name T808
Test name
Test status
Simulation time 116163995 ps
CPU time 4.83 seconds
Started Oct 12 12:03:14 AM UTC 24
Finished Oct 12 12:03:19 AM UTC 24
Peak memory 214568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879572503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3879572503
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2562726678
Short name T831
Test name
Test status
Simulation time 21723180247 ps
CPU time 47.16 seconds
Started Oct 12 12:03:14 AM UTC 24
Finished Oct 12 12:04:02 AM UTC 24
Peak memory 214368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562726678 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2562726678
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2371379769
Short name T830
Test name
Test status
Simulation time 17047780350 ps
CPU time 46.87 seconds
Started Oct 12 12:03:14 AM UTC 24
Finished Oct 12 12:04:02 AM UTC 24
Peak memory 214492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371379769 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2371379769
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3368759874
Short name T807
Test name
Test status
Simulation time 30045953 ps
CPU time 3.49 seconds
Started Oct 12 12:03:14 AM UTC 24
Finished Oct 12 12:03:18 AM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368759874 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3368759874
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.4119508475
Short name T221
Test name
Test status
Simulation time 1416754621 ps
CPU time 126.71 seconds
Started Oct 12 12:03:31 AM UTC 24
Finished Oct 12 12:05:40 AM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119508475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.4119508475
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.793432544
Short name T829
Test name
Test status
Simulation time 3009082203 ps
CPU time 28.69 seconds
Started Oct 12 12:03:31 AM UTC 24
Finished Oct 12 12:04:01 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793432544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.793432544
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.298025086
Short name T892
Test name
Test status
Simulation time 847156860 ps
CPU time 255.63 seconds
Started Oct 12 12:03:31 AM UTC 24
Finished Oct 12 12:07:51 AM UTC 24
Peak memory 220772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298025086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.298025086
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3219834882
Short name T895
Test name
Test status
Simulation time 3116942895 ps
CPU time 275.33 seconds
Started Oct 12 12:03:31 AM UTC 24
Finished Oct 12 12:08:11 AM UTC 24
Peak memory 231528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219834882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.3219834882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1395247875
Short name T824
Test name
Test status
Simulation time 162048493 ps
CPU time 20.86 seconds
Started Oct 12 12:03:26 AM UTC 24
Finished Oct 12 12:03:49 AM UTC 24
Peak memory 216868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395247875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1395247875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3120558911
Short name T841
Test name
Test status
Simulation time 1477198840 ps
CPU time 22.56 seconds
Started Oct 12 12:03:49 AM UTC 24
Finished Oct 12 12:04:13 AM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120558911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3120558911
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2070309558
Short name T900
Test name
Test status
Simulation time 38388792196 ps
CPU time 379.34 seconds
Started Oct 12 12:03:51 AM UTC 24
Finished Oct 12 12:10:15 AM UTC 24
Peak memory 218264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070309558 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.2070309558
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.4065849323
Short name T844
Test name
Test status
Simulation time 242282176 ps
CPU time 16.32 seconds
Started Oct 12 12:03:57 AM UTC 24
Finished Oct 12 12:04:14 AM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065849323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.4065849323
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.4227618968
Short name T839
Test name
Test status
Simulation time 427158379 ps
CPU time 17.49 seconds
Started Oct 12 12:03:53 AM UTC 24
Finished Oct 12 12:04:11 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227618968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.4227618968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2372144786
Short name T243
Test name
Test status
Simulation time 845420137 ps
CPU time 29.51 seconds
Started Oct 12 12:03:45 AM UTC 24
Finished Oct 12 12:04:16 AM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372144786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2372144786
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.3631352073
Short name T887
Test name
Test status
Simulation time 67291240741 ps
CPU time 131.27 seconds
Started Oct 12 12:03:45 AM UTC 24
Finished Oct 12 12:05:59 AM UTC 24
Peak memory 214952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631352073 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3631352073
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3826620485
Short name T133
Test name
Test status
Simulation time 29115240202 ps
CPU time 118.34 seconds
Started Oct 12 12:03:46 AM UTC 24
Finished Oct 12 12:05:47 AM UTC 24
Peak memory 214888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826620485 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3826620485
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.742192992
Short name T826
Test name
Test status
Simulation time 97581525 ps
CPU time 4.88 seconds
Started Oct 12 12:03:45 AM UTC 24
Finished Oct 12 12:03:51 AM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742192992 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.742192992
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.3504365428
Short name T835
Test name
Test status
Simulation time 215444868 ps
CPU time 14.59 seconds
Started Oct 12 12:03:51 AM UTC 24
Finished Oct 12 12:04:07 AM UTC 24
Peak memory 214756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504365428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3504365428
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1080416268
Short name T818
Test name
Test status
Simulation time 239494654 ps
CPU time 4.92 seconds
Started Oct 12 12:03:31 AM UTC 24
Finished Oct 12 12:03:37 AM UTC 24
Peak memory 214588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080416268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1080416268
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1963189537
Short name T843
Test name
Test status
Simulation time 9099542980 ps
CPU time 34.81 seconds
Started Oct 12 12:03:38 AM UTC 24
Finished Oct 12 12:04:14 AM UTC 24
Peak memory 214872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963189537 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1963189537
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1046843460
Short name T850
Test name
Test status
Simulation time 3737572583 ps
CPU time 34.34 seconds
Started Oct 12 12:03:43 AM UTC 24
Finished Oct 12 12:04:19 AM UTC 24
Peak memory 214848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046843460 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1046843460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.4020286188
Short name T819
Test name
Test status
Simulation time 36623288 ps
CPU time 2.29 seconds
Started Oct 12 12:03:38 AM UTC 24
Finished Oct 12 12:03:41 AM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020286188 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.4020286188
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.3629301881
Short name T858
Test name
Test status
Simulation time 167982253 ps
CPU time 28.07 seconds
Started Oct 12 12:04:01 AM UTC 24
Finished Oct 12 12:04:31 AM UTC 24
Peak memory 216876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629301881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3629301881
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.767410021
Short name T880
Test name
Test status
Simulation time 1072224887 ps
CPU time 80.09 seconds
Started Oct 12 12:04:05 AM UTC 24
Finished Oct 12 12:05:27 AM UTC 24
Peak memory 216808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767410021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.767410021
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.411007288
Short name T840
Test name
Test status
Simulation time 38260551 ps
CPU time 8.25 seconds
Started Oct 12 12:04:02 AM UTC 24
Finished Oct 12 12:04:12 AM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411007288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.411007288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3710541376
Short name T893
Test name
Test status
Simulation time 7090098768 ps
CPU time 225.37 seconds
Started Oct 12 12:04:05 AM UTC 24
Finished Oct 12 12:07:54 AM UTC 24
Peak memory 231396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710541376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.3710541376
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.1776200464
Short name T854
Test name
Test status
Simulation time 1787005188 ps
CPU time 23.38 seconds
Started Oct 12 12:03:57 AM UTC 24
Finished Oct 12 12:04:21 AM UTC 24
Peak memory 216872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776200464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1776200464
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.4047266812
Short name T856
Test name
Test status
Simulation time 270385146 ps
CPU time 10.74 seconds
Started Oct 12 12:04:15 AM UTC 24
Finished Oct 12 12:04:27 AM UTC 24
Peak memory 216876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047266812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.4047266812
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1653609353
Short name T877
Test name
Test status
Simulation time 9922272618 ps
CPU time 56.67 seconds
Started Oct 12 12:04:15 AM UTC 24
Finished Oct 12 12:05:14 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653609353 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.1653609353
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2133785400
Short name T859
Test name
Test status
Simulation time 1308372218 ps
CPU time 14.31 seconds
Started Oct 12 12:04:16 AM UTC 24
Finished Oct 12 12:04:31 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133785400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2133785400
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.2349095344
Short name T855
Test name
Test status
Simulation time 144275583 ps
CPU time 9.32 seconds
Started Oct 12 12:04:15 AM UTC 24
Finished Oct 12 12:04:26 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349095344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2349095344
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3172676582
Short name T862
Test name
Test status
Simulation time 779466281 ps
CPU time 26.51 seconds
Started Oct 12 12:04:10 AM UTC 24
Finished Oct 12 12:04:38 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172676582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3172676582
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.70206753
Short name T873
Test name
Test status
Simulation time 7666262940 ps
CPU time 53.24 seconds
Started Oct 12 12:04:15 AM UTC 24
Finished Oct 12 12:05:10 AM UTC 24
Peak memory 214876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70206753 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.70206753
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2769622294
Short name T878
Test name
Test status
Simulation time 12898394107 ps
CPU time 61.44 seconds
Started Oct 12 12:04:15 AM UTC 24
Finished Oct 12 12:05:18 AM UTC 24
Peak memory 216728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769622294 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2769622294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2240016030
Short name T852
Test name
Test status
Simulation time 98095891 ps
CPU time 9.75 seconds
Started Oct 12 12:04:10 AM UTC 24
Finished Oct 12 12:04:21 AM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240016030 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2240016030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1442769959
Short name T863
Test name
Test status
Simulation time 1420552019 ps
CPU time 22.22 seconds
Started Oct 12 12:04:15 AM UTC 24
Finished Oct 12 12:04:39 AM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442769959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1442769959
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.883315486
Short name T845
Test name
Test status
Simulation time 34812081 ps
CPU time 3.68 seconds
Started Oct 12 12:04:10 AM UTC 24
Finished Oct 12 12:04:15 AM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883315486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.883315486
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1848897546
Short name T864
Test name
Test status
Simulation time 5785418318 ps
CPU time 29.78 seconds
Started Oct 12 12:04:10 AM UTC 24
Finished Oct 12 12:04:41 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848897546 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1848897546
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2997889790
Short name T867
Test name
Test status
Simulation time 3594810778 ps
CPU time 34.38 seconds
Started Oct 12 12:04:10 AM UTC 24
Finished Oct 12 12:04:46 AM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997889790 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2997889790
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2822330290
Short name T842
Test name
Test status
Simulation time 126221924 ps
CPU time 3.12 seconds
Started Oct 12 12:04:10 AM UTC 24
Finished Oct 12 12:04:14 AM UTC 24
Peak memory 214728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822330290 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2822330290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3587212877
Short name T134
Test name
Test status
Simulation time 12403158473 ps
CPU time 295.35 seconds
Started Oct 12 12:04:18 AM UTC 24
Finished Oct 12 12:09:18 AM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587212877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3587212877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2032725608
Short name T894
Test name
Test status
Simulation time 15658478589 ps
CPU time 223.49 seconds
Started Oct 12 12:04:18 AM UTC 24
Finished Oct 12 12:08:05 AM UTC 24
Peak memory 219036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032725608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2032725608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.157320750
Short name T883
Test name
Test status
Simulation time 304212253 ps
CPU time 81.91 seconds
Started Oct 12 12:04:18 AM UTC 24
Finished Oct 12 12:05:42 AM UTC 24
Peak memory 216652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157320750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.157320750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3094866787
Short name T897
Test name
Test status
Simulation time 8759081079 ps
CPU time 280.14 seconds
Started Oct 12 12:04:18 AM UTC 24
Finished Oct 12 12:09:03 AM UTC 24
Peak memory 221156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094866787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.3094866787
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2627315584
Short name T853
Test name
Test status
Simulation time 131378265 ps
CPU time 4.59 seconds
Started Oct 12 12:04:15 AM UTC 24
Finished Oct 12 12:04:21 AM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627315584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2627315584
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.367999438
Short name T111
Test name
Test status
Simulation time 25077477892 ps
CPU time 216.81 seconds
Started Oct 11 11:47:52 PM UTC 24
Finished Oct 11 11:51:32 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367999438 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.367999438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1839642712
Short name T176
Test name
Test status
Simulation time 31665811 ps
CPU time 4.7 seconds
Started Oct 11 11:47:56 PM UTC 24
Finished Oct 11 11:48:02 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839642712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1839642712
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.1540604699
Short name T304
Test name
Test status
Simulation time 298553664 ps
CPU time 19.79 seconds
Started Oct 11 11:47:55 PM UTC 24
Finished Oct 11 11:48:16 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540604699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1540604699
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.3420140749
Short name T121
Test name
Test status
Simulation time 18978467 ps
CPU time 2.07 seconds
Started Oct 11 11:47:48 PM UTC 24
Finished Oct 11 11:47:51 PM UTC 24
Peak memory 214796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420140749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3420140749
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.3687022835
Short name T318
Test name
Test status
Simulation time 22348371496 ps
CPU time 100.05 seconds
Started Oct 11 11:47:51 PM UTC 24
Finished Oct 11 11:49:33 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687022835 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3687022835
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1395995179
Short name T161
Test name
Test status
Simulation time 14431554246 ps
CPU time 47.59 seconds
Started Oct 11 11:47:52 PM UTC 24
Finished Oct 11 11:48:41 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395995179 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1395995179
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.1305072100
Short name T300
Test name
Test status
Simulation time 107067537 ps
CPU time 14.82 seconds
Started Oct 11 11:47:51 PM UTC 24
Finished Oct 11 11:48:07 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305072100 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1305072100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.2372589878
Short name T175
Test name
Test status
Simulation time 23278310 ps
CPU time 3.22 seconds
Started Oct 11 11:47:53 PM UTC 24
Finished Oct 11 11:47:58 PM UTC 24
Peak memory 214796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372589878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2372589878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.3211703221
Short name T118
Test name
Test status
Simulation time 114177680 ps
CPU time 3.12 seconds
Started Oct 11 11:47:46 PM UTC 24
Finished Oct 11 11:47:50 PM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211703221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3211703221
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2123384795
Short name T244
Test name
Test status
Simulation time 12373748145 ps
CPU time 53.54 seconds
Started Oct 11 11:47:47 PM UTC 24
Finished Oct 11 11:48:42 PM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123384795 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2123384795
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.80212426
Short name T57
Test name
Test status
Simulation time 4332781487 ps
CPU time 36.32 seconds
Started Oct 11 11:47:48 PM UTC 24
Finished Oct 11 11:48:26 PM UTC 24
Peak memory 214648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80212426 -assert nopostproc +UVM_TESTNAME=xbar_base_test
+UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-s
im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.80212426
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3231812753
Short name T120
Test name
Test status
Simulation time 39681317 ps
CPU time 3.13 seconds
Started Oct 11 11:47:47 PM UTC 24
Finished Oct 11 11:47:51 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231812753 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3231812753
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.2105051842
Short name T93
Test name
Test status
Simulation time 6954050350 ps
CPU time 173.52 seconds
Started Oct 11 11:47:56 PM UTC 24
Finished Oct 11 11:50:52 PM UTC 24
Peak memory 220840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105051842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2105051842
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2533629845
Short name T275
Test name
Test status
Simulation time 1777849054 ps
CPU time 61.65 seconds
Started Oct 11 11:48:00 PM UTC 24
Finished Oct 11 11:49:03 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533629845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2533629845
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3325386688
Short name T36
Test name
Test status
Simulation time 233291116 ps
CPU time 86.08 seconds
Started Oct 11 11:47:59 PM UTC 24
Finished Oct 11 11:49:27 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325386688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.3325386688
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.1503101284
Short name T303
Test name
Test status
Simulation time 1396294003 ps
CPU time 17.05 seconds
Started Oct 11 11:47:56 PM UTC 24
Finished Oct 11 11:48:14 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503101284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1503101284
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2030894410
Short name T110
Test name
Test status
Simulation time 64206100731 ps
CPU time 152.31 seconds
Started Oct 11 11:48:08 PM UTC 24
Finished Oct 11 11:50:43 PM UTC 24
Peak memory 216740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030894410 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.2030894410
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3843167507
Short name T44
Test name
Test status
Simulation time 284340644 ps
CPU time 11.42 seconds
Started Oct 11 11:48:16 PM UTC 24
Finished Oct 11 11:48:28 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843167507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3843167507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.2248856319
Short name T305
Test name
Test status
Simulation time 163423528 ps
CPU time 17.43 seconds
Started Oct 11 11:48:11 PM UTC 24
Finished Oct 11 11:48:30 PM UTC 24
Peak memory 214816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248856319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2248856319
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.1071706515
Short name T302
Test name
Test status
Simulation time 91377219 ps
CPU time 3.85 seconds
Started Oct 11 11:48:06 PM UTC 24
Finished Oct 11 11:48:11 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071706515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1071706515
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.456772510
Short name T59
Test name
Test status
Simulation time 59053237446 ps
CPU time 154.08 seconds
Started Oct 11 11:48:06 PM UTC 24
Finished Oct 11 11:50:42 PM UTC 24
Peak memory 214888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456772510 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.456772510
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3766397372
Short name T306
Test name
Test status
Simulation time 4702146012 ps
CPU time 23.66 seconds
Started Oct 11 11:48:07 PM UTC 24
Finished Oct 11 11:48:32 PM UTC 24
Peak memory 214664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766397372 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3766397372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.3696063956
Short name T122
Test name
Test status
Simulation time 371090762 ps
CPU time 23.15 seconds
Started Oct 11 11:48:06 PM UTC 24
Finished Oct 11 11:48:30 PM UTC 24
Peak memory 214812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696063956 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3696063956
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.3554539278
Short name T230
Test name
Test status
Simulation time 1872372564 ps
CPU time 23.09 seconds
Started Oct 11 11:48:08 PM UTC 24
Finished Oct 11 11:48:33 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554539278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3554539278
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2292938559
Short name T28
Test name
Test status
Simulation time 251049393 ps
CPU time 3.05 seconds
Started Oct 11 11:48:02 PM UTC 24
Finished Oct 11 11:48:06 PM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292938559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2292938559
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3329019752
Short name T106
Test name
Test status
Simulation time 6580040376 ps
CPU time 49.45 seconds
Started Oct 11 11:48:04 PM UTC 24
Finished Oct 11 11:48:55 PM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329019752 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3329019752
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.585959136
Short name T286
Test name
Test status
Simulation time 6240197590 ps
CPU time 37.7 seconds
Started Oct 11 11:48:05 PM UTC 24
Finished Oct 11 11:48:44 PM UTC 24
Peak memory 214912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585959136 -assert nopostproc +UVM_TESTNAME=xbar_base_tes
t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.585959136
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1119916224
Short name T301
Test name
Test status
Simulation time 86793305 ps
CPU time 2.84 seconds
Started Oct 11 11:48:03 PM UTC 24
Finished Oct 11 11:48:07 PM UTC 24
Peak memory 214860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119916224 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1119916224
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.1357122699
Short name T91
Test name
Test status
Simulation time 21489963258 ps
CPU time 121.3 seconds
Started Oct 11 11:48:17 PM UTC 24
Finished Oct 11 11:50:21 PM UTC 24
Peak memory 216936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357122699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1357122699
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.615513611
Short name T271
Test name
Test status
Simulation time 20033969900 ps
CPU time 186.24 seconds
Started Oct 11 11:48:27 PM UTC 24
Finished Oct 11 11:51:36 PM UTC 24
Peak memory 220840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615513611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.615513611
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1051441657
Short name T114
Test name
Test status
Simulation time 927611425 ps
CPU time 285.18 seconds
Started Oct 11 11:48:26 PM UTC 24
Finished Oct 11 11:53:16 PM UTC 24
Peak memory 218728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051441657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.1051441657
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3856530035
Short name T38
Test name
Test status
Simulation time 424844431 ps
CPU time 91.85 seconds
Started Oct 11 11:48:29 PM UTC 24
Finished Oct 11 11:50:03 PM UTC 24
Peak memory 218796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856530035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.3856530035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.2534473958
Short name T151
Test name
Test status
Simulation time 845339676 ps
CPU time 12.8 seconds
Started Oct 11 11:48:15 PM UTC 24
Finished Oct 11 11:48:28 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534473958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2534473958
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.710680327
Short name T187
Test name
Test status
Simulation time 503812727 ps
CPU time 42.18 seconds
Started Oct 11 11:48:37 PM UTC 24
Finished Oct 11 11:49:21 PM UTC 24
Peak memory 216872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710680327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xba
r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.710680327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2525025496
Short name T227
Test name
Test status
Simulation time 5940743583 ps
CPU time 55.55 seconds
Started Oct 11 11:48:39 PM UTC 24
Finished Oct 11 11:49:36 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525025496 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.2525025496
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.713405860
Short name T274
Test name
Test status
Simulation time 894605368 ps
CPU time 16.38 seconds
Started Oct 11 11:48:44 PM UTC 24
Finished Oct 11 11:49:02 PM UTC 24
Peak memory 214624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713405860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.713405860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.527489345
Short name T105
Test name
Test status
Simulation time 200588910 ps
CPU time 10.92 seconds
Started Oct 11 11:48:42 PM UTC 24
Finished Oct 11 11:48:55 PM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527489345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.527489345
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.1063641287
Short name T85
Test name
Test status
Simulation time 1324079151 ps
CPU time 23.31 seconds
Started Oct 11 11:48:34 PM UTC 24
Finished Oct 11 11:48:59 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063641287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1063641287
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.3693536969
Short name T319
Test name
Test status
Simulation time 27646131000 ps
CPU time 57.81 seconds
Started Oct 11 11:48:35 PM UTC 24
Finished Oct 11 11:49:35 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693536969 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3693536969
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1430222975
Short name T163
Test name
Test status
Simulation time 32606180049 ps
CPU time 146.57 seconds
Started Oct 11 11:48:37 PM UTC 24
Finished Oct 11 11:51:06 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430222975 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1430222975
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.3639151762
Short name T99
Test name
Test status
Simulation time 67818351 ps
CPU time 10.48 seconds
Started Oct 11 11:48:34 PM UTC 24
Finished Oct 11 11:48:46 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639151762 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3639151762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.2300427104
Short name T107
Test name
Test status
Simulation time 670148300 ps
CPU time 12.06 seconds
Started Oct 11 11:48:42 PM UTC 24
Finished Oct 11 11:48:56 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300427104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2300427104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.329937871
Short name T168
Test name
Test status
Simulation time 36677609 ps
CPU time 3.12 seconds
Started Oct 11 11:48:29 PM UTC 24
Finished Oct 11 11:48:34 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329937871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.329937871
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2219768402
Short name T327
Test name
Test status
Simulation time 5879958787 ps
CPU time 69.69 seconds
Started Oct 11 11:48:31 PM UTC 24
Finished Oct 11 11:49:43 PM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219768402 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2219768402
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1484095354
Short name T315
Test name
Test status
Simulation time 4262382860 ps
CPU time 45.85 seconds
Started Oct 11 11:48:32 PM UTC 24
Finished Oct 11 11:49:20 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484095354 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1484095354
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.1257752051
Short name T307
Test name
Test status
Simulation time 61723178 ps
CPU time 2.98 seconds
Started Oct 11 11:48:31 PM UTC 24
Finished Oct 11 11:48:36 PM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257752051 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.1257752051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.3219683618
Short name T33
Test name
Test status
Simulation time 7314171711 ps
CPU time 196.45 seconds
Started Oct 11 11:48:46 PM UTC 24
Finished Oct 11 11:52:06 PM UTC 24
Peak memory 218788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219683618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3219683618
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2153932521
Short name T216
Test name
Test status
Simulation time 1521624749 ps
CPU time 63.75 seconds
Started Oct 11 11:48:47 PM UTC 24
Finished Oct 11 11:49:53 PM UTC 24
Peak memory 216684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153932521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2153932521
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.623147075
Short name T228
Test name
Test status
Simulation time 4304241703 ps
CPU time 159.28 seconds
Started Oct 11 11:48:46 PM UTC 24
Finished Oct 11 11:51:28 PM UTC 24
Peak memory 218988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623147075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.623147075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2011495947
Short name T46
Test name
Test status
Simulation time 472177326 ps
CPU time 135.57 seconds
Started Oct 11 11:48:50 PM UTC 24
Finished Oct 11 11:51:08 PM UTC 24
Peak memory 220780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011495947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.2011495947
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.2608316646
Short name T102
Test name
Test status
Simulation time 310848584 ps
CPU time 4.16 seconds
Started Oct 11 11:48:44 PM UTC 24
Finished Oct 11 11:48:49 PM UTC 24
Peak memory 214888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608316646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2608316646
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.31058583
Short name T139
Test name
Test status
Simulation time 36472397040 ps
CPU time 98.3 seconds
Started Oct 11 11:48:57 PM UTC 24
Finished Oct 11 11:50:37 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31058583 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.31058583
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1934203627
Short name T314
Test name
Test status
Simulation time 106098363 ps
CPU time 14.72 seconds
Started Oct 11 11:49:04 PM UTC 24
Finished Oct 11 11:49:20 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934203627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1934203627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.2496965813
Short name T312
Test name
Test status
Simulation time 279814298 ps
CPU time 15.96 seconds
Started Oct 11 11:49:01 PM UTC 24
Finished Oct 11 11:49:18 PM UTC 24
Peak memory 214816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496965813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2496965813
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.1123192611
Short name T309
Test name
Test status
Simulation time 757965102 ps
CPU time 17.1 seconds
Started Oct 11 11:48:54 PM UTC 24
Finished Oct 11 11:49:13 PM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123192611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-
vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1123192611
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.2073731509
Short name T276
Test name
Test status
Simulation time 17838996781 ps
CPU time 152.68 seconds
Started Oct 11 11:48:56 PM UTC 24
Finished Oct 11 11:51:31 PM UTC 24
Peak memory 214700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073731509 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2073731509
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2209634268
Short name T317
Test name
Test status
Simulation time 5652879712 ps
CPU time 33.08 seconds
Started Oct 11 11:48:57 PM UTC 24
Finished Oct 11 11:49:31 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209634268 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2209634268
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.3261115008
Short name T308
Test name
Test status
Simulation time 187498855 ps
CPU time 9.49 seconds
Started Oct 11 11:48:54 PM UTC 24
Finished Oct 11 11:49:05 PM UTC 24
Peak memory 214620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261115008 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3261115008
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.2073609731
Short name T311
Test name
Test status
Simulation time 207021723 ps
CPU time 16.34 seconds
Started Oct 11 11:49:00 PM UTC 24
Finished Oct 11 11:49:17 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073609731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2073609731
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.350736493
Short name T104
Test name
Test status
Simulation time 53736540 ps
CPU time 2.63 seconds
Started Oct 11 11:48:50 PM UTC 24
Finished Oct 11 11:48:54 PM UTC 24
Peak memory 214580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350736493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vc
s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.350736493
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.268733983
Short name T313
Test name
Test status
Simulation time 6316047906 ps
CPU time 28.36 seconds
Started Oct 11 11:48:50 PM UTC 24
Finished Oct 11 11:49:20 PM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268733983 -assert nopostproc +UVM_TESTNAME=xbar_base
_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.268733983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1558663563
Short name T109
Test name
Test status
Simulation time 3282345526 ps
CPU time 38.99 seconds
Started Oct 11 11:48:51 PM UTC 24
Finished Oct 11 11:49:32 PM UTC 24
Peak memory 214912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558663563 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1558663563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3207811125
Short name T103
Test name
Test status
Simulation time 41495542 ps
CPU time 2.42 seconds
Started Oct 11 11:48:50 PM UTC 24
Finished Oct 11 11:48:54 PM UTC 24
Peak memory 214580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207811125 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3207811125
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.4280039452
Short name T180
Test name
Test status
Simulation time 1673074545 ps
CPU time 151.85 seconds
Started Oct 11 11:49:06 PM UTC 24
Finished Oct 11 11:51:41 PM UTC 24
Peak memory 220776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280039452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4280039452
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2021253064
Short name T321
Test name
Test status
Simulation time 418591826 ps
CPU time 21.88 seconds
Started Oct 11 11:49:13 PM UTC 24
Finished Oct 11 11:49:37 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021253064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2021253064
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.4019791229
Short name T430
Test name
Test status
Simulation time 2368924238 ps
CPU time 300.87 seconds
Started Oct 11 11:49:12 PM UTC 24
Finished Oct 11 11:54:18 PM UTC 24
Peak memory 221160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019791229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.4019791229
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1727153729
Short name T294
Test name
Test status
Simulation time 9947984597 ps
CPU time 315.17 seconds
Started Oct 11 11:49:19 PM UTC 24
Finished Oct 11 11:54:38 PM UTC 24
Peak memory 231400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727153729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.1727153729
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.692526072
Short name T87
Test name
Test status
Simulation time 315019030 ps
CPU time 14.81 seconds
Started Oct 11 11:49:03 PM UTC 24
Finished Oct 11 11:49:19 PM UTC 24
Peak memory 216676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692526072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_mai
n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.692526072
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.2184038607
Short name T92
Test name
Test status
Simulation time 4240084004 ps
CPU time 68.64 seconds
Started Oct 11 11:49:23 PM UTC 24
Finished Oct 11 11:50:34 PM UTC 24
Peak memory 216744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184038607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xb
ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2184038607
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_access_same_device/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1238498815
Short name T188
Test name
Test status
Simulation time 3769865224 ps
CPU time 32.2 seconds
Started Oct 11 11:49:24 PM UTC 24
Finished Oct 11 11:49:58 PM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238498815 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.1238498815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3643635104
Short name T328
Test name
Test status
Simulation time 788188918 ps
CPU time 14.86 seconds
Started Oct 11 11:49:32 PM UTC 24
Finished Oct 11 11:49:48 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643635104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_m
ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3643635104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.2738408754
Short name T322
Test name
Test status
Simulation time 61057305 ps
CPU time 9.51 seconds
Started Oct 11 11:49:28 PM UTC 24
Finished Oct 11 11:49:38 PM UTC 24
Peak memory 214592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738408754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim
-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2738408754
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_error_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.839080814
Short name T189
Test name
Test status
Simulation time 1146022800 ps
CPU time 13.69 seconds
Started Oct 11 11:49:21 PM UTC 24
Finished Oct 11 11:49:36 PM UTC 24
Peak memory 214468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839080814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.839080814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.3744156520
Short name T273
Test name
Test status
Simulation time 19225470914 ps
CPU time 132.78 seconds
Started Oct 11 11:49:21 PM UTC 24
Finished Oct 11 11:51:36 PM UTC 24
Peak memory 214700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744156520 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3744156520
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_random_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3824576729
Short name T154
Test name
Test status
Simulation time 17448081423 ps
CPU time 97.27 seconds
Started Oct 11 11:49:21 PM UTC 24
Finished Oct 11 11:51:01 PM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824576729 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3824576729
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.2213676740
Short name T324
Test name
Test status
Simulation time 196188198 ps
CPU time 17.93 seconds
Started Oct 11 11:49:21 PM UTC 24
Finished Oct 11 11:49:40 PM UTC 24
Peak memory 214428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213676740 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2213676740
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.1179713176
Short name T326
Test name
Test status
Simulation time 599499067 ps
CPU time 15.42 seconds
Started Oct 11 11:49:26 PM UTC 24
Finished Oct 11 11:49:42 PM UTC 24
Peak memory 214888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179713176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1179713176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_same_source/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.3575382825
Short name T207
Test name
Test status
Simulation time 749747114 ps
CPU time 4.55 seconds
Started Oct 11 11:49:19 PM UTC 24
Finished Oct 11 11:49:24 PM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575382825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-v
cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3575382825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1110127967
Short name T219
Test name
Test status
Simulation time 5825033505 ps
CPU time 37.47 seconds
Started Oct 11 11:49:19 PM UTC 24
Finished Oct 11 11:49:58 PM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device
_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110127967 -assert nopostproc +UVM_TESTNAME=xbar_bas
e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_
main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1110127967
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2693061884
Short name T330
Test name
Test status
Simulation time 9252891563 ps
CPU time 40.66 seconds
Started Oct 11 11:49:20 PM UTC 24
Finished Oct 11 11:50:02 PM UTC 24
Peak memory 214652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r
eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693061884 -assert nopostproc +UVM_TESTNAME=xbar_base_te
st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2693061884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.172953694
Short name T316
Test name
Test status
Simulation time 27774253 ps
CPU time 2.27 seconds
Started Oct 11 11:49:19 PM UTC 24
Finished Oct 11 11:49:22 PM UTC 24
Peak memory 214580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172953694 -assert nopostproc +UVM_TESTNAME=xbar
_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/x
bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.172953694
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.1681570060
Short name T231
Test name
Test status
Simulation time 2569172924 ps
CPU time 71.89 seconds
Started Oct 11 11:49:32 PM UTC 24
Finished Oct 11 11:50:46 PM UTC 24
Peak memory 216940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681570060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-
sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1681570060
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3189245108
Short name T331
Test name
Test status
Simulation time 704749915 ps
CPU time 28.88 seconds
Started Oct 11 11:49:33 PM UTC 24
Finished Oct 11 11:50:04 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189245108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U
VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main
-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3189245108
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.474358697
Short name T264
Test name
Test status
Simulation time 9019902675 ps
CPU time 382.83 seconds
Started Oct 11 11:49:32 PM UTC 24
Finished Oct 11 11:56:00 PM UTC 24
Peak memory 222364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474358697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM
_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.474358697
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.1928115836
Short name T89
Test name
Test status
Simulation time 180741141 ps
CPU time 10.21 seconds
Started Oct 11 11:49:31 PM UTC 24
Finished Oct 11 11:49:42 PM UTC 24
Peak memory 214824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928115836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV
M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/xbar_ma
in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1928115836
Directory /workspaces/repo/scratch/os_regression_2024_10_11/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest
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