Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_27.fifo_h.reqfifo

Module Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.62	97.50	84.09			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	106667812	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	106667812	0	0
T1	2081	328	0	0
T2	7952	881	0	0
T3	826	281	0	0
T7	21253	5187	0	0
T8	47942	2581	0	0
T9	2384	309	0	0
T10	3214	1506	0	0
T11	2614	1435	0	0
T12	1724	400	0	0
T13	2135	341	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	39625999	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	39625999	0	0
T1	2081	116	0	0
T2	7952	297	0	0
T3	826	103	0	0
T7	21253	1874	0	0
T8	47942	6802	0	0
T9	2384	107	0	0
T10	3214	604	0	0
T11	2614	489	0	0
T12	1724	142	0	0
T13	2135	118	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	1349297	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1349297	0	0
T1	2081	40	0	0
T2	7952	23	0	0
T3	826	29	0	0
T7	21253	188	0	0
T8	47942	222	0	0
T9	2384	26	0	0
T10	3214	86	0	0
T11	2614	121	0	0
T12	1724	42	0	0
T13	2135	29	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	9528658	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	9528658	0	0
T1	2081	40	0	0
T2	7952	82	0	0
T3	826	28	0	0
T7	21253	367	0	0
T8	47942	1612	0	0
T9	2384	26	0	0
T10	3214	86	0	0
T11	2614	118	0	0
T12	1724	42	0	0
T13	2135	29	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	1437900	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1437900	0	0
T1	2081	41	0	0
T2	7952	59	0	0
T3	826	48	0	0
T7	21253	173	0	0
T8	47942	236	0	0
T9	2384	32	0	0
T10	3214	81	0	0
T11	2614	180	0	0
T12	1724	46	0	0
T13	2135	42	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	9607061	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	9607061	0	0
T1	2081	31	0	0
T2	7952	90	0	0
T3	826	32	0	0
T7	21253	347	0	0
T8	47942	1728	0	0
T9	2384	26	0	0
T10	3214	68	0	0
T11	2614	137	0	0
T12	1724	36	0	0
T13	2135	33	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	6751243	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	6751243	0	0
T1	2081	17	0	0
T2	7952	180	0	0
T3	826	31	0	0
T7	21253	893	0	0
T8	47942	1877	0	0
T9	2384	23	0	0
T10	3214	79	0	0
T11	2614	100	0	0
T12	1724	32	0	0
T13	2135	25	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	9900066	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	9900066	0	0
T1	2081	17	0	0
T2	7952	54	0	0
T3	826	30	0	0
T7	21253	404	0	0
T8	47942	1915	0	0
T9	2384	23	0	0
T10	3214	75	0	0
T11	2614	99	0	0
T12	1724	32	0	0
T13	2135	25	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	1479744	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1479744	0	0
T1	2081	37	0	0
T2	7952	22	0	0
T3	826	15	0	0
T7	21253	203	0	0
T8	47942	241	0	0
T9	2384	41	0	0
T10	3214	101	0	0
T11	2614	181	0	0
T12	1724	42	0	0
T13	2135	41	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	9629297	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	9629297	0	0
T1	2081	28	0	0
T2	7952	71	0	0
T3	826	13	0	0
T7	21253	298	0	0
T8	47942	1542	0	0
T9	2384	32	0	0
T10	3214	81	0	0
T11	2614	135	0	0
T12	1724	32	0	0
T13	2135	31	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T2 T3 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	24	21	87.50
Logical	24	21	87.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	2	2	100.00
IF	111	1	1	100.00

130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==> (Excluded)
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Excluded	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==> (Excluded)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	9149861	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	259629478	9149861	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	9149861	0	0
T1	2081	55	0	0
T2	7952	191	0	0
T3	826	37	0	0
T7	21253	1205	0	0
T8	47942	2219	0	0
T9	2384	42	0	0
T10	3214	115	0	0
T11	2614	172	0	0
T12	1724	50	0	0
T13	2135	45	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	9149861	0	0
T1	2081	55	0	0
T2	7952	191	0	0
T3	826	37	0	0
T7	21253	1205	0	0
T8	47942	2219	0	0
T9	2384	42	0	0
T10	3214	115	0	0
T11	2614	172	0	0
T12	1724	50	0	0
T13	2135	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T2 T3 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T2 T3 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T3 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T11
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==> (Excluded)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	11691246	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	259629478	11691246	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	11691246	0	0
T1	2081	55	0	0
T2	7952	95	0	0
T3	826	37	0	0
T7	21253	457	0	0
T8	47942	2032	0	0
T9	2384	42	0	0
T10	3214	115	0	0
T11	2614	172	0	0
T12	1724	50	0	0
T13	2135	45	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	11691246	0	0
T1	2081	55	0	0
T2	7952	95	0	0
T3	826	37	0	0
T7	21253	457	0	0
T8	47942	2032	0	0
T9	2384	42	0	0
T10	3214	115	0	0
T11	2614	172	0	0
T12	1724	50	0	0
T13	2135	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	1349297	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1349297	0	0
T1	2081	40	0	0
T2	7952	23	0	0
T3	826	29	0	0
T7	21253	188	0	0
T8	47942	222	0	0
T9	2384	26	0	0
T10	3214	86	0	0
T11	2614	121	0	0
T12	1724	42	0	0
T13	2135	29	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	9528658	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	9528658	0	0
T1	2081	40	0	0
T2	7952	82	0	0
T3	826	28	0	0
T7	21253	367	0	0
T8	47942	1612	0	0
T9	2384	26	0	0
T10	3214	86	0	0
T11	2614	118	0	0
T12	1724	42	0	0
T13	2135	29	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0