Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_32.fifo_h.reqfifo

Module Instance : tb.dut.u_s1n_32.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_32.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	82151243	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	82151243	0	0
T1	2081	585	0	0
T2	7952	1400	0	0
T3	826	579	0	0
T7	21253	7527	0	0
T8	47942	1319	0	0
T9	2384	767	0	0
T10	3214	2274	0	0
T11	2614	2497	0	0
T12	1724	395	0	0
T13	2135	816	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	50391400	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	50391400	0	0
T1	2081	131	0	0
T2	7952	352	0	0
T3	826	130	0	0
T7	21253	1890	0	0
T8	47942	7477	0	0
T9	2384	173	0	0
T10	3214	622	0	0
T11	2614	576	0	0
T12	1724	99	0	0
T13	2135	194	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	350050	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	350050	0	0
T1	2081	8	0	0
T2	7952	5	0	0
T3	826	2	0	0
T7	21253	44	0	0
T8	47942	62	0	0
T9	2384	9	0	0
T10	3214	10	0	0
T11	2614	32	0	0
T12	1724	4	0	0
T13	2135	10	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	1765984	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1765984	0	0
T1	2081	8	0	0
T2	7952	11	0	0
T3	826	2	0	0
T7	21253	54	0	0
T8	47942	375	0	0
T9	2384	9	0	0
T10	3214	10	0	0
T11	2614	31	0	0
T12	1724	4	0	0
T13	2135	10	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	249060	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	249060	0	0
T1	2081	9	0	0
T2	7952	5	0	0
T3	826	9	0	0
T7	21253	23	0	0
T8	47942	41	0	0
T9	2384	11	0	0
T10	3214	13	0	0
T11	2614	26	0	0
T12	1724	2	0	0
T13	2135	7	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	2034983	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2034983	0	0
T1	2081	7	0	0
T2	7952	19	0	0
T3	826	7	0	0
T7	21253	72	0	0
T8	47942	372	0	0
T9	2384	10	0	0
T10	3214	13	0	0
T11	2614	25	0	0
T12	1724	2	0	0
T13	2135	7	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	370365	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	370365	0	0
T1	2081	10	0	0
T2	7952	10	0	0
T3	826	12	0	0
T7	21253	20	0	0
T8	47942	41	0	0
T9	2384	8	0	0
T10	3214	11	0	0
T11	2614	28	0	0
T12	1724	4	0	0
T13	2135	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	1809163	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1809163	0	0
T1	2081	9	0	0
T2	7952	28	0	0
T3	826	8	0	0
T7	21253	33	0	0
T8	47942	225	0	0
T9	2384	8	0	0
T10	3214	11	0	0
T11	2614	22	0	0
T12	1724	3	0	0
T13	2135	11	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	253428	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	253428	0	0
T1	2081	4	0	0
T2	7952	12	0	0
T3	826	6	0	0
T7	21253	38	0	0
T8	47942	41	0	0
T9	2384	5	0	0
T10	3214	13	0	0
T11	2614	23	0	0
T12	1724	3	0	0
T13	2135	5	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	2130755	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2130755	0	0
T1	2081	4	0	0
T2	7952	5	0	0
T3	826	6	0	0
T7	21253	42	0	0
T8	47942	281	0	0
T9	2384	5	0	0
T10	3214	12	0	0
T11	2614	22	0	0
T12	1724	3	0	0
T13	2135	4	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	1235045	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1235045	0	0
T1	2081	6	0	0
T2	7952	47	0	0
T3	826	7	0	0
T7	21253	165	0	0
T8	47942	314	0	0
T9	2384	7	0	0
T10	3214	15	0	0
T11	2614	19	0	0
T12	1724	7	0	0
T13	2135	4	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	2329606	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2329606	0	0
T1	2081	6	0	0
T2	7952	14	0	0
T3	826	7	0	0
T7	21253	58	0	0
T8	47942	316	0	0
T9	2384	7	0	0
T10	3214	14	0	0
T11	2614	19	0	0
T12	1724	7	0	0
T13	2135	4	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	754888	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	754888	0	0
T1	2081	5	0	0
T2	7952	12	0	0
T3	826	5	0	0
T7	21253	41	0	0
T8	47942	33	0	0
T9	2384	6	0	0
T10	3214	26	0	0
T11	2614	30	0	0
T12	1724	16	0	0
T13	2135	5	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	2227639	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2227639	0	0
T1	2081	5	0	0
T2	7952	2	0	0
T3	826	4	0	0
T7	21253	88	0	0
T8	47942	227	0	0
T9	2384	6	0	0
T10	3214	16	0	0
T11	2614	23	0	0
T12	1724	6	0	0
T13	2135	5	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0