Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
278633 |
0 |
0 |
T1 |
2081 |
8 |
0 |
0 |
T2 |
7952 |
13 |
0 |
0 |
T3 |
826 |
9 |
0 |
0 |
T7 |
21253 |
53 |
0 |
0 |
T8 |
47942 |
60 |
0 |
0 |
T9 |
2384 |
6 |
0 |
0 |
T10 |
3214 |
10 |
0 |
0 |
T11 |
2614 |
31 |
0 |
0 |
T12 |
1724 |
1 |
0 |
0 |
T13 |
2135 |
5 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
2230128 |
0 |
0 |
T1 |
2081 |
7 |
0 |
0 |
T2 |
7952 |
3 |
0 |
0 |
T3 |
826 |
8 |
0 |
0 |
T7 |
21253 |
110 |
0 |
0 |
T8 |
47942 |
392 |
0 |
0 |
T9 |
2384 |
6 |
0 |
0 |
T10 |
3214 |
10 |
0 |
0 |
T11 |
2614 |
28 |
0 |
0 |
T12 |
1724 |
1 |
0 |
0 |
T13 |
2135 |
5 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
251656 |
0 |
0 |
T1 |
2081 |
7 |
0 |
0 |
T2 |
7952 |
8 |
0 |
0 |
T3 |
826 |
9 |
0 |
0 |
T7 |
21253 |
17 |
0 |
0 |
T8 |
47942 |
62 |
0 |
0 |
T9 |
2384 |
15 |
0 |
0 |
T10 |
3214 |
12 |
0 |
0 |
T11 |
2614 |
22 |
0 |
0 |
T12 |
1724 |
4 |
0 |
0 |
T13 |
2135 |
14 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
1654338 |
0 |
0 |
T1 |
2081 |
6 |
0 |
0 |
T2 |
7952 |
38 |
0 |
0 |
T3 |
826 |
8 |
0 |
0 |
T7 |
21253 |
38 |
0 |
0 |
T8 |
47942 |
425 |
0 |
0 |
T9 |
2384 |
12 |
0 |
0 |
T10 |
3214 |
11 |
0 |
0 |
T11 |
2614 |
20 |
0 |
0 |
T12 |
1724 |
4 |
0 |
0 |
T13 |
2135 |
11 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
240218 |
0 |
0 |
T1 |
2081 |
6 |
0 |
0 |
T2 |
7952 |
2 |
0 |
0 |
T3 |
826 |
10 |
0 |
0 |
T7 |
21253 |
45 |
0 |
0 |
T8 |
47942 |
36 |
0 |
0 |
T9 |
2384 |
9 |
0 |
0 |
T10 |
3214 |
20 |
0 |
0 |
T11 |
2614 |
24 |
0 |
0 |
T12 |
1724 |
6 |
0 |
0 |
T13 |
2135 |
7 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
1826395 |
0 |
0 |
T1 |
2081 |
6 |
0 |
0 |
T2 |
7952 |
12 |
0 |
0 |
T3 |
826 |
10 |
0 |
0 |
T7 |
21253 |
108 |
0 |
0 |
T8 |
47942 |
315 |
0 |
0 |
T9 |
2384 |
9 |
0 |
0 |
T10 |
3214 |
19 |
0 |
0 |
T11 |
2614 |
23 |
0 |
0 |
T12 |
1724 |
5 |
0 |
0 |
T13 |
2135 |
6 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
254394 |
0 |
0 |
T1 |
2081 |
7 |
0 |
0 |
T2 |
7952 |
10 |
0 |
0 |
T3 |
826 |
3 |
0 |
0 |
T7 |
21253 |
28 |
0 |
0 |
T8 |
47942 |
34 |
0 |
0 |
T9 |
2384 |
10 |
0 |
0 |
T10 |
3214 |
14 |
0 |
0 |
T11 |
2614 |
26 |
0 |
0 |
T12 |
1724 |
2 |
0 |
0 |
T13 |
2135 |
5 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
2241722 |
0 |
0 |
T1 |
2081 |
7 |
0 |
0 |
T2 |
7952 |
29 |
0 |
0 |
T3 |
826 |
3 |
0 |
0 |
T7 |
21253 |
54 |
0 |
0 |
T8 |
47942 |
271 |
0 |
0 |
T9 |
2384 |
8 |
0 |
0 |
T10 |
3214 |
12 |
0 |
0 |
T11 |
2614 |
26 |
0 |
0 |
T12 |
1724 |
2 |
0 |
0 |
T13 |
2135 |
5 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
249503 |
0 |
0 |
T1 |
2081 |
7 |
0 |
0 |
T2 |
7952 |
23 |
0 |
0 |
T3 |
826 |
5 |
0 |
0 |
T7 |
21253 |
16 |
0 |
0 |
T8 |
47942 |
42 |
0 |
0 |
T9 |
2384 |
8 |
0 |
0 |
T10 |
3214 |
12 |
0 |
0 |
T11 |
2614 |
34 |
0 |
0 |
T12 |
1724 |
4 |
0 |
0 |
T13 |
2135 |
5 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
2074935 |
0 |
0 |
T1 |
2081 |
6 |
0 |
0 |
T2 |
7952 |
19 |
0 |
0 |
T3 |
826 |
5 |
0 |
0 |
T7 |
21253 |
32 |
0 |
0 |
T8 |
47942 |
305 |
0 |
0 |
T9 |
2384 |
8 |
0 |
0 |
T10 |
3214 |
12 |
0 |
0 |
T11 |
2614 |
29 |
0 |
0 |
T12 |
1724 |
4 |
0 |
0 |
T13 |
2135 |
5 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
268516 |
0 |
0 |
T1 |
2081 |
2 |
0 |
0 |
T2 |
7952 |
9 |
0 |
0 |
T3 |
826 |
5 |
0 |
0 |
T7 |
21253 |
33 |
0 |
0 |
T8 |
47942 |
43 |
0 |
0 |
T9 |
2384 |
8 |
0 |
0 |
T10 |
3214 |
15 |
0 |
0 |
T11 |
2614 |
30 |
0 |
0 |
T12 |
1724 |
2 |
0 |
0 |
T13 |
2135 |
5 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
2113552 |
0 |
0 |
T1 |
2081 |
2 |
0 |
0 |
T2 |
7952 |
25 |
0 |
0 |
T3 |
826 |
5 |
0 |
0 |
T7 |
21253 |
79 |
0 |
0 |
T8 |
47942 |
351 |
0 |
0 |
T9 |
2384 |
7 |
0 |
0 |
T10 |
3214 |
15 |
0 |
0 |
T11 |
2614 |
25 |
0 |
0 |
T12 |
1724 |
2 |
0 |
0 |
T13 |
2135 |
4 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
289414 |
0 |
0 |
T1 |
2081 |
4 |
0 |
0 |
T2 |
7952 |
5 |
0 |
0 |
T3 |
826 |
2 |
0 |
0 |
T7 |
21253 |
22 |
0 |
0 |
T8 |
47942 |
32 |
0 |
0 |
T9 |
2384 |
2 |
0 |
0 |
T10 |
3214 |
12 |
0 |
0 |
T11 |
2614 |
16 |
0 |
0 |
T12 |
1724 |
2 |
0 |
0 |
T13 |
2135 |
2 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
2244905 |
0 |
0 |
T1 |
2081 |
4 |
0 |
0 |
T2 |
7952 |
12 |
0 |
0 |
T3 |
826 |
2 |
0 |
0 |
T7 |
21253 |
70 |
0 |
0 |
T8 |
47942 |
286 |
0 |
0 |
T9 |
2384 |
2 |
0 |
0 |
T10 |
3214 |
11 |
0 |
0 |
T11 |
2614 |
15 |
0 |
0 |
T12 |
1724 |
2 |
0 |
0 |
T13 |
2135 |
2 |
0 |
0 |
DataKnown_AKnownEnable
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
259629478 |
259512400 |
0 |
0 |
T1 |
2081 |
2029 |
0 |
0 |
T2 |
7952 |
7933 |
0 |
0 |
T3 |
826 |
797 |
0 |
0 |
T7 |
21253 |
21173 |
0 |
0 |
T8 |
47942 |
47933 |
0 |
0 |
T9 |
2384 |
2334 |
0 |
0 |
T10 |
3214 |
3135 |
0 |
0 |
T11 |
2614 |
2601 |
0 |
0 |
T12 |
1724 |
1677 |
0 |
0 |
T13 |
2135 |
2101 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |