Unified Coverage Report :: Module Instance :: tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.reqfifo

Module Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_42.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_42.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	591228	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	591228	0	0
T1	2081	2	0	0
T2	7952	4	0	0
T3	826	5	0	0
T7	21253	23	0	0
T8	47942	39	0	0
T9	2384	6	0	0
T10	3214	12	0	0
T11	2614	20	0	0
T12	1724	2	0	0
T13	2135	10	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	2284850	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2284850	0	0
T1	2081	2	0	0
T2	7952	4	0	0
T3	826	5	0	0
T7	21253	49	0	0
T8	47942	236	0	0
T9	2384	6	0	0
T10	3214	12	0	0
T11	2614	16	0	0
T12	1724	2	0	0
T13	2135	10	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	654838	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	654838	0	0
T1	2081	4	0	0
T2	7952	4	0	0
T3	826	13	0	0
T7	21253	67	0	0
T8	47942	42	0	0
T9	2384	16	0	0
T10	3214	14	0	0
T11	2614	35	0	0
T12	1724	16	0	0
T13	2135	11	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	686839	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	686839	0	0
T1	2081	4	0	0
T2	7952	4	0	0
T3	826	8	0	0
T7	21253	21	0	0
T8	47942	42	0	0
T9	2384	10	0	0
T10	3214	8	0	0
T11	2614	25	0	0
T12	1724	8	0	0
T13	2135	7	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_40.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	855869	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	855869	0	0
T1	2081	12	0	0
T2	7952	15	0	0
T3	826	9	0	0
T7	21253	50	0	0
T8	47942	90	0	0
T9	2384	26	0	0
T10	3214	70	0	0
T11	2614	78	0	0
T12	1724	10	0	0
T13	2135	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_40.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	2565369	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2565369	0	0
T1	2081	12	0	0
T2	7952	19	0	0
T3	826	4	0	0
T7	21253	81	0	0
T8	47942	286	0	0
T9	2384	22	0	0
T10	3214	24	0	0
T11	2614	48	0	0
T12	1724	10	0	0
T13	2135	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	518650	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	518650	0	0
T1	2081	4	0	0
T2	7952	12	0	0
T3	826	9	0	0
T7	21253	20	0	0
T8	47942	36	0	0
T9	2384	7	0	0
T10	3214	40	0	0
T11	2614	40	0	0
T12	1724	2	0	0
T13	2135	9	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	2032912	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2032912	0	0
T1	2081	4	0	0
T2	7952	16	0	0
T3	826	4	0	0
T7	21253	61	0	0
T8	47942	237	0	0
T9	2384	7	0	0
T10	3214	15	0	0
T11	2614	24	0	0
T12	1724	2	0	0
T13	2135	9	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	600031	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	600031	0	0
T1	2081	8	0	0
T2	7952	3	0	0
T3	826	0	0	0
T7	21253	30	0	0
T8	47942	55	0	0
T9	2384	19	0	0
T10	3214	30	0	0
T11	2614	38	0	0
T12	1724	8	0	0
T13	2135	4	0	0
T22	0	72	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	532457	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	532457	0	0
T1	2081	8	0	0
T2	7952	3	0	0
T3	826	0	0	0
T7	21253	20	0	0
T8	47942	49	0	0
T9	2384	15	0	0
T10	3214	9	0	0
T11	2614	24	0	0
T12	1724	8	0	0
T13	2135	4	0	0
T22	0	38	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_42.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	947825	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	947825	0	0
T1	2081	29	0	0
T2	7952	6	0	0
T3	826	42	0	0
T7	21253	94	0	0
T8	47942	90	0	0
T9	2384	17	0	0
T10	3214	37	0	0
T11	2614	85	0	0
T12	1724	5	0	0
T13	2135	24	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_42.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	2590516	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2590516	0	0
T1	2081	16	0	0
T2	7952	6	0	0
T3	826	15	0	0
T7	21253	61	0	0
T8	47942	416	0	0
T9	2384	11	0	0
T10	3214	27	0	0
T11	2614	50	0	0
T12	1724	5	0	0
T13	2135	17	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	614316	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	614316	0	0
T1	2081	6	0	0
T2	7952	3	0	0
T3	826	15	0	0
T7	21253	48	0	0
T8	47942	49	0	0
T9	2384	5	0	0
T10	3214	22	0	0
T11	2614	57	0	0
T12	1724	2	0	0
T13	2135	7	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	259629478	2095798	0	0
DataKnown_AKnownEnable	259629478	259512400	0	0
DepthKnown_A	259629478	259512400	0	0
RvalidKnown_A	259629478	259512400	0	0
WreadyKnown_A	259629478	259512400	0	0
gen_passthru_fifo.paramCheckPass	899	899	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2095798	0	0
T1	2081	6	0	0
T2	7952	3	0	0
T3	826	4	0	0
T7	21253	41	0	0
T8	47942	375	0	0
T9	2384	5	0	0
T10	3214	14	0	0
T11	2614	32	0	0
T12	1724	2	0	0
T13	2135	7	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0