Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21576	21576	0	0
GntImpliesReady_A	2147483647	7280406	0	0
GntImpliesValid_A	2147483647	7280406	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7280406	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	284557884	0	0
ReadyAndValidImplyGrant_A	2147483647	7280406	0	0
ReqAndReadyImplyGrant_A	2147483647	7280406	0	0
ReqImpliesValid_A	2147483647	26040376	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	50902	0	21576
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7280406	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	49944	48696	0	0
T2	190848	190392	0	0
T3	19824	19128	0	0
T7	510072	508152	0	0
T8	1150608	1150392	0	0
T9	57216	56016	0	0
T10	77136	75240	0	0
T11	62736	62424	0	0
T12	41376	40248	0	0
T13	51240	50424	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21576	21576	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7280406	0	0
T1	49944	394	0	0
T2	190848	358	0	0
T3	19824	349	0	0
T7	510072	1473	0	0
T8	1150608	2882	0	0
T9	57216	465	0	0
T10	77136	934	0	0
T11	62736	1537	0	0
T12	41376	354	0	0
T13	51240	491	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7280406	0	0
T1	49944	394	0	0
T2	190848	358	0	0
T3	19824	349	0	0
T7	510072	1473	0	0
T8	1150608	2882	0	0
T9	57216	465	0	0
T10	77136	934	0	0
T11	62736	1537	0	0
T12	41376	354	0	0
T13	51240	491	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	49944	48696	0	0
T2	190848	190392	0	0
T3	19824	19128	0	0
T7	510072	508152	0	0
T8	1150608	1150392	0	0
T9	57216	56016	0	0
T10	77136	75240	0	0
T11	62736	62424	0	0
T12	41376	40248	0	0
T13	51240	50424	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	49944	48696	0	0
T2	190848	190392	0	0
T3	19824	19128	0	0
T7	510072	508152	0	0
T8	1150608	1150392	0	0
T9	57216	56016	0	0
T10	77136	75240	0	0
T11	62736	62424	0	0
T12	41376	40248	0	0
T13	51240	50424	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7280406	0	0
T1	49944	394	0	0
T2	190848	358	0	0
T3	19824	349	0	0
T7	510072	1473	0	0
T8	1150608	2882	0	0
T9	57216	465	0	0
T10	77136	934	0	0
T11	62736	1537	0	0
T12	41376	354	0	0
T13	51240	491	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	284557884	0	0
T1	49944	562	0	0
T2	190848	9500	0	0
T3	19824	447	0	0
T7	510072	30170	0	0
T8	1150608	59892	0	0
T9	57216	705	0	0
T10	77136	1426	0	0
T11	62736	1797	0	0
T12	41376	422	0	0
T13	51240	637	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7280406	0	0
T1	49944	394	0	0
T2	190848	358	0	0
T3	19824	349	0	0
T7	510072	1473	0	0
T8	1150608	2882	0	0
T9	57216	465	0	0
T10	77136	934	0	0
T11	62736	1537	0	0
T12	41376	354	0	0
T13	51240	491	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7280406	0	0
T1	49944	394	0	0
T2	190848	358	0	0
T3	19824	349	0	0
T7	510072	1473	0	0
T8	1150608	2882	0	0
T9	57216	465	0	0
T10	77136	934	0	0
T11	62736	1537	0	0
T12	41376	354	0	0
T13	51240	491	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	26040376	0	0
T1	49944	433	0	0
T2	190848	789	0	0
T3	19824	412	0	0
T7	510072	3298	0	0
T8	1150608	5231	0	0
T9	57216	506	0	0
T10	77136	1059	0	0
T11	62736	1759	0	0
T12	41376	401	0	0
T13	51240	538	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50902	0	21576
T3	1652	2	0	2
T7	42506	0	0	2
T8	95884	0	0	2
T9	4768	0	0	2
T10	6428	5	0	2
T11	5228	8	0	2
T12	3448	0	0	2
T13	4270	0	0	2
T14	23522	27	0	2
T15	0	10	0	0
T16	0	21	0	0
T17	0	15	0	0
T18	0	30	0	0
T19	0	2	0	0
T20	0	14	0	0
T21	0	1	0	0
T22	81272	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	49944	48696	0	0
T2	190848	190392	0	0
T3	19824	19128	0	0
T7	510072	508152	0	0
T8	1150608	1150392	0	0
T9	57216	56016	0	0
T10	77136	75240	0	0
T11	62736	62424	0	0
T12	41376	40248	0	0
T13	51240	50424	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7280406	0	0
T1	49944	394	0	0
T2	190848	358	0	0
T3	19824	349	0	0
T7	510072	1473	0	0
T8	1150608	2882	0	0
T9	57216	465	0	0
T10	77136	934	0	0
T11	62736	1537	0	0
T12	41376	354	0	0
T13	51240	491	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	803009	0	0
GntImpliesValid_A	259629478	803009	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	803009	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	8032340	0	0
ReadyAndValidImplyGrant_A	259629478	803009	0	0
ReqAndReadyImplyGrant_A	259629478	803009	0	0
ReqImpliesValid_A	259629478	1895704	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	803009	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803009	0	0
T1	2081	46	0	0
T2	7952	47	0	0
T3	826	46	0	0
T7	21253	163	0	0
T8	47942	298	0	0
T9	2384	46	0	0
T10	3214	86	0	0
T11	2614	178	0	0
T12	1724	43	0	0
T13	2135	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803009	0	0
T1	2081	46	0	0
T2	7952	47	0	0
T3	826	46	0	0
T7	21253	163	0	0
T8	47942	298	0	0
T9	2384	46	0	0
T10	3214	86	0	0
T11	2614	178	0	0
T12	1724	43	0	0
T13	2135	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803009	0	0
T1	2081	46	0	0
T2	7952	47	0	0
T3	826	46	0	0
T7	21253	163	0	0
T8	47942	298	0	0
T9	2384	46	0	0
T10	3214	86	0	0
T11	2614	178	0	0
T12	1724	43	0	0
T13	2135	53	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	8032340	0	0
T1	2081	36	0	0
T2	7952	348	0	0
T3	826	32	0	0
T7	21253	1257	0	0
T8	47942	2232	0	0
T9	2384	41	0	0
T10	3214	74	0	0
T11	2614	132	0	0
T12	1724	33	0	0
T13	2135	43	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803009	0	0
T1	2081	46	0	0
T2	7952	47	0	0
T3	826	46	0	0
T7	21253	163	0	0
T8	47942	298	0	0
T9	2384	46	0	0
T10	3214	86	0	0
T11	2614	178	0	0
T12	1724	43	0	0
T13	2135	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803009	0	0
T1	2081	46	0	0
T2	7952	47	0	0
T3	826	46	0	0
T7	21253	163	0	0
T8	47942	298	0	0
T9	2384	46	0	0
T10	3214	86	0	0
T11	2614	178	0	0
T12	1724	43	0	0
T13	2135	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1895704	0	0
T1	2081	57	0	0
T2	7952	82	0	0
T3	826	61	0	0
T7	21253	252	0	0
T8	47942	322	0	0
T9	2384	52	0	0
T10	3214	99	0	0
T11	2614	225	0	0
T12	1724	54	0	0
T13	2135	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803009	0	0
T1	2081	46	0	0
T2	7952	47	0	0
T3	826	46	0	0
T7	21253	163	0	0
T8	47942	298	0	0
T9	2384	46	0	0
T10	3214	86	0	0
T11	2614	178	0	0
T12	1724	43	0	0
T13	2135	53	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	815882	0	0
GntImpliesValid_A	259629478	815882	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	815882	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	8078478	0	0
ReadyAndValidImplyGrant_A	259629478	815882	0	0
ReqAndReadyImplyGrant_A	259629478	815882	0	0
ReqImpliesValid_A	259629478	1979496	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	815882	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	815882	0	0
T1	2081	37	0	0
T2	7952	27	0	0
T3	826	21	0	0
T7	21253	154	0	0
T8	47942	301	0	0
T9	2384	50	0	0
T10	3214	113	0	0
T11	2614	181	0	0
T12	1724	42	0	0
T13	2135	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	815882	0	0
T1	2081	37	0	0
T2	7952	27	0	0
T3	826	21	0	0
T7	21253	154	0	0
T8	47942	301	0	0
T9	2384	50	0	0
T10	3214	113	0	0
T11	2614	181	0	0
T12	1724	42	0	0
T13	2135	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	815882	0	0
T1	2081	37	0	0
T2	7952	27	0	0
T3	826	21	0	0
T7	21253	154	0	0
T8	47942	301	0	0
T9	2384	50	0	0
T10	3214	113	0	0
T11	2614	181	0	0
T12	1724	42	0	0
T13	2135	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	8078478	0	0
T1	2081	29	0	0
T2	7952	204	0	0
T3	826	19	0	0
T7	21253	1150	0	0
T8	47942	2212	0	0
T9	2384	40	0	0
T10	3214	92	0	0
T11	2614	132	0	0
T12	1724	33	0	0
T13	2135	37	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	815882	0	0
T1	2081	37	0	0
T2	7952	27	0	0
T3	826	21	0	0
T7	21253	154	0	0
T8	47942	301	0	0
T9	2384	50	0	0
T10	3214	113	0	0
T11	2614	181	0	0
T12	1724	42	0	0
T13	2135	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	815882	0	0
T1	2081	37	0	0
T2	7952	27	0	0
T3	826	21	0	0
T7	21253	154	0	0
T8	47942	301	0	0
T9	2384	50	0	0
T10	3214	113	0	0
T11	2614	181	0	0
T12	1724	42	0	0
T13	2135	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1979496	0	0
T1	2081	46	0	0
T2	7952	30	0	0
T3	826	24	0	0
T7	21253	285	0	0
T8	47942	345	0	0
T9	2384	61	0	0
T10	3214	135	0	0
T11	2614	231	0	0
T12	1724	52	0	0
T13	2135	56	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	815882	0	0
T1	2081	37	0	0
T2	7952	27	0	0
T3	826	21	0	0
T7	21253	154	0	0
T8	47942	301	0	0
T9	2384	50	0	0
T10	3214	113	0	0
T11	2614	181	0	0
T12	1724	42	0	0
T13	2135	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	200268	0	0
GntImpliesValid_A	259629478	200268	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	200268	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	1969659	0	0
ReadyAndValidImplyGrant_A	259629478	200268	0	0
ReqAndReadyImplyGrant_A	259629478	200268	0	0
ReqImpliesValid_A	259629478	468757	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	200268	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200268	0	0
T1	2081	18	0	0
T2	7952	9	0	0
T3	826	16	0	0
T7	21253	49	0	0
T8	47942	83	0	0
T9	2384	20	0	0
T10	3214	31	0	0
T11	2614	50	0	0
T12	1724	9	0	0
T13	2135	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200268	0	0
T1	2081	18	0	0
T2	7952	9	0	0
T3	826	16	0	0
T7	21253	49	0	0
T8	47942	83	0	0
T9	2384	20	0	0
T10	3214	31	0	0
T11	2614	50	0	0
T12	1724	9	0	0
T13	2135	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200268	0	0
T1	2081	18	0	0
T2	7952	9	0	0
T3	826	16	0	0
T7	21253	49	0	0
T8	47942	83	0	0
T9	2384	20	0	0
T10	3214	31	0	0
T11	2614	50	0	0
T12	1724	9	0	0
T13	2135	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1969659	0	0
T1	2081	17	0	0
T2	7952	87	0	0
T3	826	15	0	0
T7	21253	320	0	0
T8	47942	646	0	0
T9	2384	20	0	0
T10	3214	32	0	0
T11	2614	49	0	0
T12	1724	10	0	0
T13	2135	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200268	0	0
T1	2081	18	0	0
T2	7952	9	0	0
T3	826	16	0	0
T7	21253	49	0	0
T8	47942	83	0	0
T9	2384	20	0	0
T10	3214	31	0	0
T11	2614	50	0	0
T12	1724	9	0	0
T13	2135	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200268	0	0
T1	2081	18	0	0
T2	7952	9	0	0
T3	826	16	0	0
T7	21253	49	0	0
T8	47942	83	0	0
T9	2384	20	0	0
T10	3214	31	0	0
T11	2614	50	0	0
T12	1724	9	0	0
T13	2135	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	468757	0	0
T1	2081	20	0	0
T2	7952	9	0	0
T3	826	18	0	0
T7	21253	87	0	0
T8	47942	83	0	0
T9	2384	21	0	0
T10	3214	31	0	0
T11	2614	52	0	0
T12	1724	9	0	0
T13	2135	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200268	0	0
T1	2081	18	0	0
T2	7952	9	0	0
T3	826	16	0	0
T7	21253	49	0	0
T8	47942	83	0	0
T9	2384	20	0	0
T10	3214	31	0	0
T11	2614	50	0	0
T12	1724	9	0	0
T13	2135	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T10 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T10,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	199586	0	0
GntImpliesValid_A	259629478	199586	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	199586	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	1951556	0	0
ReadyAndValidImplyGrant_A	259629478	199586	0	0
ReqAndReadyImplyGrant_A	259629478	199586	0	0
ReqImpliesValid_A	259629478	461312	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	199586	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199586	0	0
T1	2081	8	0	0
T2	7952	9	0	0
T3	826	10	0	0
T7	21253	41	0	0
T8	47942	73	0	0
T9	2384	17	0	0
T10	3214	22	0	0
T11	2614	40	0	0
T12	1724	7	0	0
T13	2135	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199586	0	0
T1	2081	8	0	0
T2	7952	9	0	0
T3	826	10	0	0
T7	21253	41	0	0
T8	47942	73	0	0
T9	2384	17	0	0
T10	3214	22	0	0
T11	2614	40	0	0
T12	1724	7	0	0
T13	2135	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199586	0	0
T1	2081	8	0	0
T2	7952	9	0	0
T3	826	10	0	0
T7	21253	41	0	0
T8	47942	73	0	0
T9	2384	17	0	0
T10	3214	22	0	0
T11	2614	40	0	0
T12	1724	7	0	0
T13	2135	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1951556	0	0
T1	2081	9	0	0
T2	7952	59	0	0
T3	826	11	0	0
T7	21253	321	0	0
T8	47942	487	0	0
T9	2384	18	0	0
T10	3214	22	0	0
T11	2614	40	0	0
T12	1724	8	0	0
T13	2135	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199586	0	0
T1	2081	8	0	0
T2	7952	9	0	0
T3	826	10	0	0
T7	21253	41	0	0
T8	47942	73	0	0
T9	2384	17	0	0
T10	3214	22	0	0
T11	2614	40	0	0
T12	1724	7	0	0
T13	2135	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199586	0	0
T1	2081	8	0	0
T2	7952	9	0	0
T3	826	10	0	0
T7	21253	41	0	0
T8	47942	73	0	0
T9	2384	17	0	0
T10	3214	22	0	0
T11	2614	40	0	0
T12	1724	7	0	0
T13	2135	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	461312	0	0
T1	2081	8	0	0
T2	7952	16	0	0
T3	826	10	0	0
T7	21253	62	0	0
T8	47942	76	0	0
T9	2384	17	0	0
T10	3214	23	0	0
T11	2614	41	0	0
T12	1724	7	0	0
T13	2135	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199586	0	0
T1	2081	8	0	0
T2	7952	9	0	0
T3	826	10	0	0
T7	21253	41	0	0
T8	47942	73	0	0
T9	2384	17	0	0
T10	3214	22	0	0
T11	2614	40	0	0
T12	1724	7	0	0
T13	2135	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	207774	0	0
GntImpliesValid_A	259629478	207774	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	207774	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	3175003	0	0
ReadyAndValidImplyGrant_A	259629478	207774	0	0
ReqAndReadyImplyGrant_A	259629478	207774	0	0
ReqImpliesValid_A	259629478	1133874	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	207774	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	207774	0	0
T1	2081	11	0	0
T2	7952	5	0	0
T3	826	7	0	0
T7	21253	38	0	0
T8	47942	94	0	0
T9	2384	11	0	0
T10	3214	28	0	0
T11	2614	45	0	0
T12	1724	8	0	0
T13	2135	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	207774	0	0
T1	2081	11	0	0
T2	7952	5	0	0
T3	826	7	0	0
T7	21253	38	0	0
T8	47942	94	0	0
T9	2384	11	0	0
T10	3214	28	0	0
T11	2614	45	0	0
T12	1724	8	0	0
T13	2135	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	207774	0	0
T1	2081	11	0	0
T2	7952	5	0	0
T3	826	7	0	0
T7	21253	38	0	0
T8	47942	94	0	0
T9	2384	11	0	0
T10	3214	28	0	0
T11	2614	45	0	0
T12	1724	8	0	0
T13	2135	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	3175003	0	0
T1	2081	85	0	0
T2	7952	62	0	0
T3	826	37	0	0
T7	21253	1101	0	0
T8	47942	465	0	0
T9	2384	122	0	0
T10	3214	162	0	0
T11	2614	145	0	0
T12	1724	32	0	0
T13	2135	62	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	207774	0	0
T1	2081	11	0	0
T2	7952	5	0	0
T3	826	7	0	0
T7	21253	38	0	0
T8	47942	94	0	0
T9	2384	11	0	0
T10	3214	28	0	0
T11	2614	45	0	0
T12	1724	8	0	0
T13	2135	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	207774	0	0
T1	2081	11	0	0
T2	7952	5	0	0
T3	826	7	0	0
T7	21253	38	0	0
T8	47942	94	0	0
T9	2384	11	0	0
T10	3214	28	0	0
T11	2614	45	0	0
T12	1724	8	0	0
T13	2135	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1133874	0	0
T1	2081	11	0	0
T2	7952	33	0	0
T3	826	8	0	0
T7	21253	147	0	0
T8	47942	94	0	0
T9	2384	11	0	0
T10	3214	42	0	0
T11	2614	54	0	0
T12	1724	18	0	0
T13	2135	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	207774	0	0
T1	2081	11	0	0
T2	7952	5	0	0
T3	826	7	0	0
T7	21253	38	0	0
T8	47942	94	0	0
T9	2384	11	0	0
T10	3214	28	0	0
T11	2614	45	0	0
T12	1724	8	0	0
T13	2135	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T9 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	202745	0	0
GntImpliesValid_A	259629478	202745	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	202745	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	3299294	0	0
ReadyAndValidImplyGrant_A	259629478	202745	0	0
ReqAndReadyImplyGrant_A	259629478	202745	0	0
ReqImpliesValid_A	259629478	937353	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	202745	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202745	0	0
T1	2081	6	0	0
T2	7952	8	0	0
T3	826	13	0	0
T7	21253	44	0	0
T8	47942	81	0	0
T9	2384	16	0	0
T10	3214	20	0	0
T11	2614	41	0	0
T12	1724	10	0	0
T13	2135	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202745	0	0
T1	2081	6	0	0
T2	7952	8	0	0
T3	826	13	0	0
T7	21253	44	0	0
T8	47942	81	0	0
T9	2384	16	0	0
T10	3214	20	0	0
T11	2614	41	0	0
T12	1724	10	0	0
T13	2135	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202745	0	0
T1	2081	6	0	0
T2	7952	8	0	0
T3	826	13	0	0
T7	21253	44	0	0
T8	47942	81	0	0
T9	2384	16	0	0
T10	3214	20	0	0
T11	2614	41	0	0
T12	1724	10	0	0
T13	2135	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	3299294	0	0
T1	2081	62	0	0
T2	7952	70	0	0
T3	826	70	0	0
T7	21253	990	0	0
T8	47942	532	0	0
T9	2384	84	0	0
T10	3214	147	0	0
T11	2614	161	0	0
T12	1724	43	0	0
T13	2135	106	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202745	0	0
T1	2081	6	0	0
T2	7952	8	0	0
T3	826	13	0	0
T7	21253	44	0	0
T8	47942	81	0	0
T9	2384	16	0	0
T10	3214	20	0	0
T11	2614	41	0	0
T12	1724	10	0	0
T13	2135	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202745	0	0
T1	2081	6	0	0
T2	7952	8	0	0
T3	826	13	0	0
T7	21253	44	0	0
T8	47942	81	0	0
T9	2384	16	0	0
T10	3214	20	0	0
T11	2614	41	0	0
T12	1724	10	0	0
T13	2135	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	937353	0	0
T1	2081	6	0	0
T2	7952	8	0	0
T3	826	18	0	0
T7	21253	90	0	0
T8	47942	81	0	0
T9	2384	22	0	0
T10	3214	26	0	0
T11	2614	55	0	0
T12	1724	18	0	0
T13	2135	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202745	0	0
T1	2081	6	0	0
T2	7952	8	0	0
T3	826	13	0	0
T7	21253	44	0	0
T8	47942	81	0	0
T9	2384	16	0	0
T10	3214	20	0	0
T11	2614	41	0	0
T12	1724	10	0	0
T13	2135	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	197203	0	0
GntImpliesValid_A	259629478	197203	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	197203	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	3274481	0	0
ReadyAndValidImplyGrant_A	259629478	197203	0	0
ReqAndReadyImplyGrant_A	259629478	197203	0	0
ReqImpliesValid_A	259629478	855869	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	197203	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	197203	0	0
T1	2081	12	0	0
T2	7952	12	0	0
T3	826	4	0	0
T7	21253	40	0	0
T8	47942	85	0	0
T9	2384	22	0	0
T10	3214	24	0	0
T11	2614	48	0	0
T12	1724	10	0	0
T13	2135	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	197203	0	0
T1	2081	12	0	0
T2	7952	12	0	0
T3	826	4	0	0
T7	21253	40	0	0
T8	47942	85	0	0
T9	2384	22	0	0
T10	3214	24	0	0
T11	2614	48	0	0
T12	1724	10	0	0
T13	2135	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	197203	0	0
T1	2081	12	0	0
T2	7952	12	0	0
T3	826	4	0	0
T7	21253	40	0	0
T8	47942	85	0	0
T9	2384	22	0	0
T10	3214	24	0	0
T11	2614	48	0	0
T12	1724	10	0	0
T13	2135	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	3274481	0	0
T1	2081	68	0	0
T2	7952	93	0	0
T3	826	15	0	0
T7	21253	546	0	0
T8	47942	378	0	0
T9	2384	131	0	0
T10	3214	371	0	0
T11	2614	205	0	0
T12	1724	107	0	0
T13	2135	75	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	197203	0	0
T1	2081	12	0	0
T2	7952	12	0	0
T3	826	4	0	0
T7	21253	40	0	0
T8	47942	85	0	0
T9	2384	22	0	0
T10	3214	24	0	0
T11	2614	48	0	0
T12	1724	10	0	0
T13	2135	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	197203	0	0
T1	2081	12	0	0
T2	7952	12	0	0
T3	826	4	0	0
T7	21253	40	0	0
T8	47942	85	0	0
T9	2384	22	0	0
T10	3214	24	0	0
T11	2614	48	0	0
T12	1724	10	0	0
T13	2135	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	855869	0	0
T1	2081	12	0	0
T2	7952	15	0	0
T3	826	9	0	0
T7	21253	50	0	0
T8	47942	90	0	0
T9	2384	26	0	0
T10	3214	70	0	0
T11	2614	78	0	0
T12	1724	10	0	0
T13	2135	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	197203	0	0
T1	2081	12	0	0
T2	7952	12	0	0
T3	826	4	0	0
T7	21253	40	0	0
T8	47942	85	0	0
T9	2384	22	0	0
T10	3214	24	0	0
T11	2614	48	0	0
T12	1724	10	0	0
T13	2135	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	201386	0	0
GntImpliesValid_A	259629478	201386	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	201386	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	3291362	0	0
ReadyAndValidImplyGrant_A	259629478	201386	0	0
ReqAndReadyImplyGrant_A	259629478	201386	0	0
ReqImpliesValid_A	259629478	947825	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	201386	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201386	0	0
T1	2081	16	0	0
T2	7952	6	0	0
T3	826	15	0	0
T7	21253	39	0	0
T8	47942	90	0	0
T9	2384	11	0	0
T10	3214	27	0	0
T11	2614	50	0	0
T12	1724	5	0	0
T13	2135	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201386	0	0
T1	2081	16	0	0
T2	7952	6	0	0
T3	826	15	0	0
T7	21253	39	0	0
T8	47942	90	0	0
T9	2384	11	0	0
T10	3214	27	0	0
T11	2614	50	0	0
T12	1724	5	0	0
T13	2135	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201386	0	0
T1	2081	16	0	0
T2	7952	6	0	0
T3	826	15	0	0
T7	21253	39	0	0
T8	47942	90	0	0
T9	2384	11	0	0
T10	3214	27	0	0
T11	2614	50	0	0
T12	1724	5	0	0
T13	2135	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	3291362	0	0
T1	2081	87	0	0
T2	7952	105	0	0
T3	826	99	0	0
T7	21253	566	0	0
T8	47942	646	0	0
T9	2384	49	0	0
T10	3214	152	0	0
T11	2614	359	0	0
T12	1724	24	0	0
T13	2135	69	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201386	0	0
T1	2081	16	0	0
T2	7952	6	0	0
T3	826	15	0	0
T7	21253	39	0	0
T8	47942	90	0	0
T9	2384	11	0	0
T10	3214	27	0	0
T11	2614	50	0	0
T12	1724	5	0	0
T13	2135	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201386	0	0
T1	2081	16	0	0
T2	7952	6	0	0
T3	826	15	0	0
T7	21253	39	0	0
T8	47942	90	0	0
T9	2384	11	0	0
T10	3214	27	0	0
T11	2614	50	0	0
T12	1724	5	0	0
T13	2135	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	947825	0	0
T1	2081	29	0	0
T2	7952	6	0	0
T3	826	42	0	0
T7	21253	94	0	0
T8	47942	90	0	0
T9	2384	17	0	0
T10	3214	37	0	0
T11	2614	85	0	0
T12	1724	5	0	0
T13	2135	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201386	0	0
T1	2081	16	0	0
T2	7952	6	0	0
T3	826	15	0	0
T7	21253	39	0	0
T8	47942	90	0	0
T9	2384	11	0	0
T10	3214	27	0	0
T11	2614	50	0	0
T12	1724	5	0	0
T13	2135	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T10 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T10,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	201571	0	0
GntImpliesValid_A	259629478	201571	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	201571	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	1983295	0	0
ReadyAndValidImplyGrant_A	259629478	201571	0	0
ReqAndReadyImplyGrant_A	259629478	201571	0	0
ReqImpliesValid_A	259629478	458413	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	201571	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201571	0	0
T1	2081	14	0	0
T2	7952	10	0	0
T3	826	14	0	0
T7	21253	38	0	0
T8	47942	82	0	0
T9	2384	9	0	0
T10	3214	26	0	0
T11	2614	43	0	0
T12	1724	8	0	0
T13	2135	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201571	0	0
T1	2081	14	0	0
T2	7952	10	0	0
T3	826	14	0	0
T7	21253	38	0	0
T8	47942	82	0	0
T9	2384	9	0	0
T10	3214	26	0	0
T11	2614	43	0	0
T12	1724	8	0	0
T13	2135	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201571	0	0
T1	2081	14	0	0
T2	7952	10	0	0
T3	826	14	0	0
T7	21253	38	0	0
T8	47942	82	0	0
T9	2384	9	0	0
T10	3214	26	0	0
T11	2614	43	0	0
T12	1724	8	0	0
T13	2135	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1983295	0	0
T1	2081	15	0	0
T2	7952	81	0	0
T3	826	15	0	0
T7	21253	292	0	0
T8	47942	588	0	0
T9	2384	10	0	0
T10	3214	24	0	0
T11	2614	39	0	0
T12	1724	9	0	0
T13	2135	23	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201571	0	0
T1	2081	14	0	0
T2	7952	10	0	0
T3	826	14	0	0
T7	21253	38	0	0
T8	47942	82	0	0
T9	2384	9	0	0
T10	3214	26	0	0
T11	2614	43	0	0
T12	1724	8	0	0
T13	2135	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201571	0	0
T1	2081	14	0	0
T2	7952	10	0	0
T3	826	14	0	0
T7	21253	38	0	0
T8	47942	82	0	0
T9	2384	9	0	0
T10	3214	26	0	0
T11	2614	43	0	0
T12	1724	8	0	0
T13	2135	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	458413	0	0
T1	2081	14	0	0
T2	7952	25	0	0
T3	826	14	0	0
T7	21253	52	0	0
T8	47942	93	0	0
T9	2384	9	0	0
T10	3214	29	0	0
T11	2614	48	0	0
T12	1724	8	0	0
T13	2135	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201571	0	0
T1	2081	14	0	0
T2	7952	10	0	0
T3	826	14	0	0
T7	21253	38	0	0
T8	47942	82	0	0
T9	2384	9	0	0
T10	3214	26	0	0
T11	2614	43	0	0
T12	1724	8	0	0
T13	2135	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T10 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T10,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	199196	0	0
GntImpliesValid_A	259629478	199196	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	199196	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	1958280	0	0
ReadyAndValidImplyGrant_A	259629478	199196	0	0
ReqAndReadyImplyGrant_A	259629478	199196	0	0
ReqImpliesValid_A	259629478	436675	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	199196	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199196	0	0
T1	2081	9	0	0
T2	7952	7	0	0
T3	826	12	0	0
T7	21253	33	0	0
T8	47942	70	0	0
T9	2384	16	0	0
T10	3214	22	0	0
T11	2614	50	0	0
T12	1724	14	0	0
T13	2135	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199196	0	0
T1	2081	9	0	0
T2	7952	7	0	0
T3	826	12	0	0
T7	21253	33	0	0
T8	47942	70	0	0
T9	2384	16	0	0
T10	3214	22	0	0
T11	2614	50	0	0
T12	1724	14	0	0
T13	2135	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199196	0	0
T1	2081	9	0	0
T2	7952	7	0	0
T3	826	12	0	0
T7	21253	33	0	0
T8	47942	70	0	0
T9	2384	16	0	0
T10	3214	22	0	0
T11	2614	50	0	0
T12	1724	14	0	0
T13	2135	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1958280	0	0
T1	2081	9	0	0
T2	7952	26	0	0
T3	826	13	0	0
T7	21253	286	0	0
T8	47942	504	0	0
T9	2384	17	0	0
T10	3214	20	0	0
T11	2614	49	0	0
T12	1724	13	0	0
T13	2135	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199196	0	0
T1	2081	9	0	0
T2	7952	7	0	0
T3	826	12	0	0
T7	21253	33	0	0
T8	47942	70	0	0
T9	2384	16	0	0
T10	3214	22	0	0
T11	2614	50	0	0
T12	1724	14	0	0
T13	2135	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199196	0	0
T1	2081	9	0	0
T2	7952	7	0	0
T3	826	12	0	0
T7	21253	33	0	0
T8	47942	70	0	0
T9	2384	16	0	0
T10	3214	22	0	0
T11	2614	50	0	0
T12	1724	14	0	0
T13	2135	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	436675	0	0
T1	2081	10	0	0
T2	7952	7	0	0
T3	826	12	0	0
T7	21253	38	0	0
T8	47942	70	0	0
T9	2384	16	0	0
T10	3214	25	0	0
T11	2614	52	0	0
T12	1724	16	0	0
T13	2135	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199196	0	0
T1	2081	9	0	0
T2	7952	7	0	0
T3	826	12	0	0
T7	21253	33	0	0
T8	47942	70	0	0
T9	2384	16	0	0
T10	3214	22	0	0
T11	2614	50	0	0
T12	1724	14	0	0
T13	2135	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T11 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T11,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	187611	0	0
GntImpliesValid_A	259629478	187611	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	187611	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	1971697	0	0
ReadyAndValidImplyGrant_A	259629478	187611	0	0
ReqAndReadyImplyGrant_A	259629478	187611	0	0
ReqImpliesValid_A	259629478	440325	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	187611	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	187611	0	0
T1	2081	16	0	0
T2	7952	11	0	0
T3	826	7	0	0
T7	21253	41	0	0
T8	47942	75	0	0
T9	2384	10	0	0
T10	3214	24	0	0
T11	2614	41	0	0
T12	1724	15	0	0
T13	2135	29	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	187611	0	0
T1	2081	16	0	0
T2	7952	11	0	0
T3	826	7	0	0
T7	21253	41	0	0
T8	47942	75	0	0
T9	2384	10	0	0
T10	3214	24	0	0
T11	2614	41	0	0
T12	1724	15	0	0
T13	2135	29	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	187611	0	0
T1	2081	16	0	0
T2	7952	11	0	0
T3	826	7	0	0
T7	21253	41	0	0
T8	47942	75	0	0
T9	2384	10	0	0
T10	3214	24	0	0
T11	2614	41	0	0
T12	1724	15	0	0
T13	2135	29	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1971697	0	0
T1	2081	17	0	0
T2	7952	110	0	0
T3	826	8	0	0
T7	21253	324	0	0
T8	47942	544	0	0
T9	2384	11	0	0
T10	3214	25	0	0
T11	2614	40	0	0
T12	1724	15	0	0
T13	2135	28	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	187611	0	0
T1	2081	16	0	0
T2	7952	11	0	0
T3	826	7	0	0
T7	21253	41	0	0
T8	47942	75	0	0
T9	2384	10	0	0
T10	3214	24	0	0
T11	2614	41	0	0
T12	1724	15	0	0
T13	2135	29	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	187611	0	0
T1	2081	16	0	0
T2	7952	11	0	0
T3	826	7	0	0
T7	21253	41	0	0
T8	47942	75	0	0
T9	2384	10	0	0
T10	3214	24	0	0
T11	2614	41	0	0
T12	1724	15	0	0
T13	2135	29	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	440325	0	0
T1	2081	16	0	0
T2	7952	18	0	0
T3	826	7	0	0
T7	21253	49	0	0
T8	47942	75	0	0
T9	2384	10	0	0
T10	3214	24	0	0
T11	2614	43	0	0
T12	1724	16	0	0
T13	2135	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	187611	0	0
T1	2081	16	0	0
T2	7952	11	0	0
T3	826	7	0	0
T7	21253	41	0	0
T8	47942	75	0	0
T9	2384	10	0	0
T10	3214	24	0	0
T11	2614	41	0	0
T12	1724	15	0	0
T13	2135	29	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	206819	0	0
GntImpliesValid_A	259629478	206819	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	206819	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	2012287	0	0
ReadyAndValidImplyGrant_A	259629478	206819	0	0
ReqAndReadyImplyGrant_A	259629478	206819	0	0
ReqImpliesValid_A	259629478	498718	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	206819	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	206819	0	0
T1	2081	15	0	0
T2	7952	10	0	0
T3	826	10	0	0
T7	21253	60	0	0
T8	47942	100	0	0
T9	2384	11	0	0
T10	3214	32	0	0
T11	2614	47	0	0
T12	1724	5	0	0
T13	2135	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	206819	0	0
T1	2081	15	0	0
T2	7952	10	0	0
T3	826	10	0	0
T7	21253	60	0	0
T8	47942	100	0	0
T9	2384	11	0	0
T10	3214	32	0	0
T11	2614	47	0	0
T12	1724	5	0	0
T13	2135	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	206819	0	0
T1	2081	15	0	0
T2	7952	10	0	0
T3	826	10	0	0
T7	21253	60	0	0
T8	47942	100	0	0
T9	2384	11	0	0
T10	3214	32	0	0
T11	2614	47	0	0
T12	1724	5	0	0
T13	2135	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2012287	0	0
T1	2081	15	0	0
T2	7952	69	0	0
T3	826	10	0	0
T7	21253	442	0	0
T8	47942	792	0	0
T9	2384	12	0	0
T10	3214	33	0	0
T11	2614	45	0	0
T12	1724	6	0	0
T13	2135	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	206819	0	0
T1	2081	15	0	0
T2	7952	10	0	0
T3	826	10	0	0
T7	21253	60	0	0
T8	47942	100	0	0
T9	2384	11	0	0
T10	3214	32	0	0
T11	2614	47	0	0
T12	1724	5	0	0
T13	2135	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	206819	0	0
T1	2081	15	0	0
T2	7952	10	0	0
T3	826	10	0	0
T7	21253	60	0	0
T8	47942	100	0	0
T9	2384	11	0	0
T10	3214	32	0	0
T11	2614	47	0	0
T12	1724	5	0	0
T13	2135	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	498718	0	0
T1	2081	16	0	0
T2	7952	33	0	0
T3	826	11	0	0
T7	21253	103	0	0
T8	47942	104	0	0
T9	2384	11	0	0
T10	3214	32	0	0
T11	2614	50	0	0
T12	1724	5	0	0
T13	2135	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	206819	0	0
T1	2081	15	0	0
T2	7952	10	0	0
T3	826	10	0	0
T7	21253	60	0	0
T8	47942	100	0	0
T9	2384	11	0	0
T10	3214	32	0	0
T11	2614	47	0	0
T12	1724	5	0	0
T13	2135	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	194975	0	0
GntImpliesValid_A	259629478	194975	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	194975	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	2000365	0	0
ReadyAndValidImplyGrant_A	259629478	194975	0	0
ReqAndReadyImplyGrant_A	259629478	194975	0	0
ReqImpliesValid_A	259629478	472549	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	194975	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	194975	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	35	0	0
T8	47942	81	0	0
T9	2384	21	0	0
T10	3214	23	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	194975	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	35	0	0
T8	47942	81	0	0
T9	2384	21	0	0
T10	3214	23	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	194975	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	35	0	0
T8	47942	81	0	0
T9	2384	21	0	0
T10	3214	23	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2000365	0	0
T1	2081	11	0	0
T2	7952	97	0	0
T3	826	12	0	0
T7	21253	258	0	0
T8	47942	695	0	0
T9	2384	19	0	0
T10	3214	23	0	0
T11	2614	39	0	0
T12	1724	10	0	0
T13	2135	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	194975	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	35	0	0
T8	47942	81	0	0
T9	2384	21	0	0
T10	3214	23	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	194975	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	35	0	0
T8	47942	81	0	0
T9	2384	21	0	0
T10	3214	23	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	472549	0	0
T1	2081	12	0	0
T2	7952	26	0	0
T3	826	13	0	0
T7	21253	35	0	0
T8	47942	109	0	0
T9	2384	24	0	0
T10	3214	24	0	0
T11	2614	44	0	0
T12	1724	9	0	0
T13	2135	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	194975	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	35	0	0
T8	47942	81	0	0
T9	2384	21	0	0
T10	3214	23	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T10 T11 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T11,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	200266	0	0
GntImpliesValid_A	259629478	200266	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	200266	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	1969920	0	0
ReadyAndValidImplyGrant_A	259629478	200266	0	0
ReqAndReadyImplyGrant_A	259629478	200266	0	0
ReqImpliesValid_A	259629478	447733	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	200266	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200266	0	0
T1	2081	10	0	0
T2	7952	7	0	0
T3	826	13	0	0
T7	21253	53	0	0
T8	47942	92	0	0
T9	2384	16	0	0
T10	3214	32	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200266	0	0
T1	2081	10	0	0
T2	7952	7	0	0
T3	826	13	0	0
T7	21253	53	0	0
T8	47942	92	0	0
T9	2384	16	0	0
T10	3214	32	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200266	0	0
T1	2081	10	0	0
T2	7952	7	0	0
T3	826	13	0	0
T7	21253	53	0	0
T8	47942	92	0	0
T9	2384	16	0	0
T10	3214	32	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1969920	0	0
T1	2081	11	0	0
T2	7952	60	0	0
T3	826	14	0	0
T7	21253	442	0	0
T8	47942	746	0	0
T9	2384	17	0	0
T10	3214	32	0	0
T11	2614	40	0	0
T12	1724	9	0	0
T13	2135	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200266	0	0
T1	2081	10	0	0
T2	7952	7	0	0
T3	826	13	0	0
T7	21253	53	0	0
T8	47942	92	0	0
T9	2384	16	0	0
T10	3214	32	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200266	0	0
T1	2081	10	0	0
T2	7952	7	0	0
T3	826	13	0	0
T7	21253	53	0	0
T8	47942	92	0	0
T9	2384	16	0	0
T10	3214	32	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	447733	0	0
T1	2081	10	0	0
T2	7952	7	0	0
T3	826	13	0	0
T7	21253	103	0	0
T8	47942	92	0	0
T9	2384	16	0	0
T10	3214	33	0	0
T11	2614	43	0	0
T12	1724	10	0	0
T13	2135	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	200266	0	0
T1	2081	10	0	0
T2	7952	7	0	0
T3	826	13	0	0
T7	21253	53	0	0
T8	47942	92	0	0
T9	2384	16	0	0
T10	3214	32	0	0
T11	2614	41	0	0
T12	1724	9	0	0
T13	2135	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T9 T10 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T9,T10
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	201781	0	0
GntImpliesValid_A	259629478	201781	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	201781	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	1979528	0	0
ReadyAndValidImplyGrant_A	259629478	201781	0	0
ReqAndReadyImplyGrant_A	259629478	201781	0	0
ReqImpliesValid_A	259629478	492434	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	201781	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201781	0	0
T1	2081	11	0	0
T2	7952	21	0	0
T3	826	7	0	0
T7	21253	55	0	0
T8	47942	71	0	0
T9	2384	17	0	0
T10	3214	18	0	0
T11	2614	47	0	0
T12	1724	6	0	0
T13	2135	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201781	0	0
T1	2081	11	0	0
T2	7952	21	0	0
T3	826	7	0	0
T7	21253	55	0	0
T8	47942	71	0	0
T9	2384	17	0	0
T10	3214	18	0	0
T11	2614	47	0	0
T12	1724	6	0	0
T13	2135	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201781	0	0
T1	2081	11	0	0
T2	7952	21	0	0
T3	826	7	0	0
T7	21253	55	0	0
T8	47942	71	0	0
T9	2384	17	0	0
T10	3214	18	0	0
T11	2614	47	0	0
T12	1724	6	0	0
T13	2135	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1979528	0	0
T1	2081	12	0	0
T2	7952	166	0	0
T3	826	8	0	0
T7	21253	405	0	0
T8	47942	526	0	0
T9	2384	16	0	0
T10	3214	17	0	0
T11	2614	48	0	0
T12	1724	7	0	0
T13	2135	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201781	0	0
T1	2081	11	0	0
T2	7952	21	0	0
T3	826	7	0	0
T7	21253	55	0	0
T8	47942	71	0	0
T9	2384	17	0	0
T10	3214	18	0	0
T11	2614	47	0	0
T12	1724	6	0	0
T13	2135	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201781	0	0
T1	2081	11	0	0
T2	7952	21	0	0
T3	826	7	0	0
T7	21253	55	0	0
T8	47942	71	0	0
T9	2384	17	0	0
T10	3214	18	0	0
T11	2614	47	0	0
T12	1724	6	0	0
T13	2135	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	492434	0	0
T1	2081	11	0	0
T2	7952	48	0	0
T3	826	7	0	0
T7	21253	84	0	0
T8	47942	71	0	0
T9	2384	19	0	0
T10	3214	20	0	0
T11	2614	47	0	0
T12	1724	6	0	0
T13	2135	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201781	0	0
T1	2081	11	0	0
T2	7952	21	0	0
T3	826	7	0	0
T7	21253	55	0	0
T8	47942	71	0	0
T9	2384	17	0	0
T10	3214	18	0	0
T11	2614	47	0	0
T12	1724	6	0	0
T13	2135	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	199281	0	0
GntImpliesValid_A	259629478	199281	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	199281	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	1938284	0	0
ReadyAndValidImplyGrant_A	259629478	199281	0	0
ReqAndReadyImplyGrant_A	259629478	199281	0	0
ReqImpliesValid_A	259629478	456193	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	199281	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199281	0	0
T1	2081	15	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	30	0	0
T8	47942	83	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	44	0	0
T12	1724	5	0	0
T13	2135	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199281	0	0
T1	2081	15	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	30	0	0
T8	47942	83	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	44	0	0
T12	1724	5	0	0
T13	2135	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199281	0	0
T1	2081	15	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	30	0	0
T8	47942	83	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	44	0	0
T12	1724	5	0	0
T13	2135	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1938284	0	0
T1	2081	15	0	0
T2	7952	108	0	0
T3	826	10	0	0
T7	21253	261	0	0
T8	47942	749	0	0
T9	2384	16	0	0
T10	3214	25	0	0
T11	2614	40	0	0
T12	1724	6	0	0
T13	2135	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199281	0	0
T1	2081	15	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	30	0	0
T8	47942	83	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	44	0	0
T12	1724	5	0	0
T13	2135	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199281	0	0
T1	2081	15	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	30	0	0
T8	47942	83	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	44	0	0
T12	1724	5	0	0
T13	2135	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	456193	0	0
T1	2081	16	0	0
T2	7952	27	0	0
T3	826	9	0	0
T7	21253	39	0	0
T8	47942	83	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	49	0	0
T12	1724	5	0	0
T13	2135	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	199281	0	0
T1	2081	15	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	30	0	0
T8	47942	83	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	44	0	0
T12	1724	5	0	0
T13	2135	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T9 T11 T13 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T11,T13
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T11,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T11,T13
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	222538	0	0
GntImpliesValid_A	259629478	222538	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	222538	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	2108625	0	0
ReadyAndValidImplyGrant_A	259629478	222538	0	0
ReqAndReadyImplyGrant_A	259629478	222538	0	0
ReqImpliesValid_A	259629478	503210	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	222538	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	222538	0	0
T1	2081	3	0	0
T2	7952	15	0	0
T3	826	7	0	0
T7	21253	64	0	0
T8	47942	85	0	0
T9	2384	13	0	0
T10	3214	42	0	0
T11	2614	38	0	0
T12	1724	6	0	0
T13	2135	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	222538	0	0
T1	2081	3	0	0
T2	7952	15	0	0
T3	826	7	0	0
T7	21253	64	0	0
T8	47942	85	0	0
T9	2384	13	0	0
T10	3214	42	0	0
T11	2614	38	0	0
T12	1724	6	0	0
T13	2135	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	222538	0	0
T1	2081	3	0	0
T2	7952	15	0	0
T3	826	7	0	0
T7	21253	64	0	0
T8	47942	85	0	0
T9	2384	13	0	0
T10	3214	42	0	0
T11	2614	38	0	0
T12	1724	6	0	0
T13	2135	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2108625	0	0
T1	2081	4	0	0
T2	7952	116	0	0
T3	826	8	0	0
T7	21253	445	0	0
T8	47942	684	0	0
T9	2384	13	0	0
T10	3214	43	0	0
T11	2614	35	0	0
T12	1724	7	0	0
T13	2135	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	222538	0	0
T1	2081	3	0	0
T2	7952	15	0	0
T3	826	7	0	0
T7	21253	64	0	0
T8	47942	85	0	0
T9	2384	13	0	0
T10	3214	42	0	0
T11	2614	38	0	0
T12	1724	6	0	0
T13	2135	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	222538	0	0
T1	2081	3	0	0
T2	7952	15	0	0
T3	826	7	0	0
T7	21253	64	0	0
T8	47942	85	0	0
T9	2384	13	0	0
T10	3214	42	0	0
T11	2614	38	0	0
T12	1724	6	0	0
T13	2135	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	503210	0	0
T1	2081	3	0	0
T2	7952	15	0	0
T3	826	7	0	0
T7	21253	86	0	0
T8	47942	85	0	0
T9	2384	14	0	0
T10	3214	42	0	0
T11	2614	42	0	0
T12	1724	6	0	0
T13	2135	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	222538	0	0
T1	2081	3	0	0
T2	7952	15	0	0
T3	826	7	0	0
T7	21253	64	0	0
T8	47942	85	0	0
T9	2384	13	0	0
T10	3214	42	0	0
T11	2614	38	0	0
T12	1724	6	0	0
T13	2135	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T10 T11 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T10,T11
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	204817	0	0
GntImpliesValid_A	259629478	204817	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	204817	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	2027107	0	0
ReadyAndValidImplyGrant_A	259629478	204817	0	0
ReqAndReadyImplyGrant_A	259629478	204817	0	0
ReqImpliesValid_A	259629478	523153	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	204817	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	204817	0	0
T1	2081	7	0	0
T2	7952	14	0	0
T3	826	5	0	0
T7	21253	36	0	0
T8	47942	83	0	0
T9	2384	7	0	0
T10	3214	24	0	0
T11	2614	30	0	0
T12	1724	6	0	0
T13	2135	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	204817	0	0
T1	2081	7	0	0
T2	7952	14	0	0
T3	826	5	0	0
T7	21253	36	0	0
T8	47942	83	0	0
T9	2384	7	0	0
T10	3214	24	0	0
T11	2614	30	0	0
T12	1724	6	0	0
T13	2135	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	204817	0	0
T1	2081	7	0	0
T2	7952	14	0	0
T3	826	5	0	0
T7	21253	36	0	0
T8	47942	83	0	0
T9	2384	7	0	0
T10	3214	24	0	0
T11	2614	30	0	0
T12	1724	6	0	0
T13	2135	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2027107	0	0
T1	2081	8	0	0
T2	7952	80	0	0
T3	826	6	0	0
T7	21253	250	0	0
T8	47942	589	0	0
T9	2384	8	0	0
T10	3214	24	0	0
T11	2614	30	0	0
T12	1724	7	0	0
T13	2135	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	204817	0	0
T1	2081	7	0	0
T2	7952	14	0	0
T3	826	5	0	0
T7	21253	36	0	0
T8	47942	83	0	0
T9	2384	7	0	0
T10	3214	24	0	0
T11	2614	30	0	0
T12	1724	6	0	0
T13	2135	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	204817	0	0
T1	2081	7	0	0
T2	7952	14	0	0
T3	826	5	0	0
T7	21253	36	0	0
T8	47942	83	0	0
T9	2384	7	0	0
T10	3214	24	0	0
T11	2614	30	0	0
T12	1724	6	0	0
T13	2135	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	523153	0	0
T1	2081	7	0	0
T2	7952	31	0	0
T3	826	5	0	0
T7	21253	36	0	0
T8	47942	96	0	0
T9	2384	7	0	0
T10	3214	25	0	0
T11	2614	31	0	0
T12	1724	6	0	0
T13	2135	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	204817	0	0
T1	2081	7	0	0
T2	7952	14	0	0
T3	826	5	0	0
T7	21253	36	0	0
T8	47942	83	0	0
T9	2384	7	0	0
T10	3214	24	0	0
T11	2614	30	0	0
T12	1724	6	0	0
T13	2135	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T11 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T11,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	208052	0	0
GntImpliesValid_A	259629478	208052	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	208052	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	2013098	0	0
ReadyAndValidImplyGrant_A	259629478	208052	0	0
ReqAndReadyImplyGrant_A	259629478	208052	0	0
ReqImpliesValid_A	259629478	513147	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	208052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	208052	0	0
T1	2081	10	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	36	0	0
T8	47942	81	0	0
T9	2384	8	0	0
T10	3214	29	0	0
T11	2614	52	0	0
T12	1724	8	0	0
T13	2135	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	208052	0	0
T1	2081	10	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	36	0	0
T8	47942	81	0	0
T9	2384	8	0	0
T10	3214	29	0	0
T11	2614	52	0	0
T12	1724	8	0	0
T13	2135	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	208052	0	0
T1	2081	10	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	36	0	0
T8	47942	81	0	0
T9	2384	8	0	0
T10	3214	29	0	0
T11	2614	52	0	0
T12	1724	8	0	0
T13	2135	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2013098	0	0
T1	2081	11	0	0
T2	7952	108	0	0
T3	826	10	0	0
T7	21253	325	0	0
T8	47942	644	0	0
T9	2384	9	0	0
T10	3214	30	0	0
T11	2614	49	0	0
T12	1724	7	0	0
T13	2135	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	208052	0	0
T1	2081	10	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	36	0	0
T8	47942	81	0	0
T9	2384	8	0	0
T10	3214	29	0	0
T11	2614	52	0	0
T12	1724	8	0	0
T13	2135	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	208052	0	0
T1	2081	10	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	36	0	0
T8	47942	81	0	0
T9	2384	8	0	0
T10	3214	29	0	0
T11	2614	52	0	0
T12	1724	8	0	0
T13	2135	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	513147	0	0
T1	2081	10	0	0
T2	7952	22	0	0
T3	826	9	0	0
T7	21253	43	0	0
T8	47942	90	0	0
T9	2384	8	0	0
T10	3214	29	0	0
T11	2614	56	0	0
T12	1724	10	0	0
T13	2135	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	208052	0	0
T1	2081	10	0	0
T2	7952	14	0	0
T3	826	9	0	0
T7	21253	36	0	0
T8	47942	81	0	0
T9	2384	8	0	0
T10	3214	29	0	0
T11	2614	52	0	0
T12	1724	8	0	0
T13	2135	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T3 T9 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	202833	0	0
GntImpliesValid_A	259629478	202833	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	202833	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	2035425	0	0
ReadyAndValidImplyGrant_A	259629478	202833	0	0
ReqAndReadyImplyGrant_A	259629478	202833	0	0
ReqImpliesValid_A	259629478	515982	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	202833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202833	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	46	0	0
T8	47942	90	0	0
T9	2384	16	0	0
T10	3214	25	0	0
T11	2614	44	0	0
T12	1724	7	0	0
T13	2135	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202833	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	46	0	0
T8	47942	90	0	0
T9	2384	16	0	0
T10	3214	25	0	0
T11	2614	44	0	0
T12	1724	7	0	0
T13	2135	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202833	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	46	0	0
T8	47942	90	0	0
T9	2384	16	0	0
T10	3214	25	0	0
T11	2614	44	0	0
T12	1724	7	0	0
T13	2135	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	2035425	0	0
T1	2081	12	0	0
T2	7952	69	0	0
T3	826	12	0	0
T7	21253	375	0	0
T8	47942	697	0	0
T9	2384	16	0	0
T10	3214	25	0	0
T11	2614	43	0	0
T12	1724	8	0	0
T13	2135	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202833	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	46	0	0
T8	47942	90	0	0
T9	2384	16	0	0
T10	3214	25	0	0
T11	2614	44	0	0
T12	1724	7	0	0
T13	2135	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202833	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	46	0	0
T8	47942	90	0	0
T9	2384	16	0	0
T10	3214	25	0	0
T11	2614	44	0	0
T12	1724	7	0	0
T13	2135	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	515982	0	0
T1	2081	11	0	0
T2	7952	33	0	0
T3	826	13	0	0
T7	21253	50	0	0
T8	47942	94	0	0
T9	2384	17	0	0
T10	3214	26	0	0
T11	2614	46	0	0
T12	1724	7	0	0
T13	2135	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	202833	0	0
T1	2081	11	0	0
T2	7952	14	0	0
T3	826	12	0	0
T7	21253	46	0	0
T8	47942	90	0	0
T9	2384	16	0	0
T10	3214	25	0	0
T11	2614	44	0	0
T12	1724	7	0	0
T13	2135	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T11 T12 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T11,T12
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	201917	0	0
GntImpliesValid_A	259629478	201917	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	201917	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	1988548	0	0
ReadyAndValidImplyGrant_A	259629478	201917	0	0
ReqAndReadyImplyGrant_A	259629478	201917	0	0
ReqImpliesValid_A	259629478	498050	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	201917	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201917	0	0
T1	2081	9	0	0
T2	7952	14	0	0
T3	826	10	0	0
T7	21253	38	0	0
T8	47942	79	0	0
T9	2384	17	0	0
T10	3214	26	0	0
T11	2614	32	0	0
T12	1724	9	0	0
T13	2135	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201917	0	0
T1	2081	9	0	0
T2	7952	14	0	0
T3	826	10	0	0
T7	21253	38	0	0
T8	47942	79	0	0
T9	2384	17	0	0
T10	3214	26	0	0
T11	2614	32	0	0
T12	1724	9	0	0
T13	2135	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201917	0	0
T1	2081	9	0	0
T2	7952	14	0	0
T3	826	10	0	0
T7	21253	38	0	0
T8	47942	79	0	0
T9	2384	17	0	0
T10	3214	26	0	0
T11	2614	32	0	0
T12	1724	9	0	0
T13	2135	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1988548	0	0
T1	2081	10	0	0
T2	7952	105	0	0
T3	826	10	0	0
T7	21253	319	0	0
T8	47942	584	0	0
T9	2384	18	0	0
T10	3214	27	0	0
T11	2614	32	0	0
T12	1724	8	0	0
T13	2135	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201917	0	0
T1	2081	9	0	0
T2	7952	14	0	0
T3	826	10	0	0
T7	21253	38	0	0
T8	47942	79	0	0
T9	2384	17	0	0
T10	3214	26	0	0
T11	2614	32	0	0
T12	1724	9	0	0
T13	2135	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201917	0	0
T1	2081	9	0	0
T2	7952	14	0	0
T3	826	10	0	0
T7	21253	38	0	0
T8	47942	79	0	0
T9	2384	17	0	0
T10	3214	26	0	0
T11	2614	32	0	0
T12	1724	9	0	0
T13	2135	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	498050	0	0
T1	2081	9	0	0
T2	7952	14	0	0
T3	826	11	0	0
T7	21253	38	0	0
T8	47942	81	0	0
T9	2384	17	0	0
T10	3214	26	0	0
T11	2614	33	0	0
T12	1724	11	0	0
T13	2135	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201917	0	0
T1	2081	9	0	0
T2	7952	14	0	0
T3	826	10	0	0
T7	21253	38	0	0
T8	47942	79	0	0
T9	2384	17	0	0
T10	3214	26	0	0
T11	2614	32	0	0
T12	1724	9	0	0
T13	2135	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T3 T10 T13 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T13
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T10,T13
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	201355	0	0
GntImpliesValid_A	259629478	201355	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	201355	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	1983934	0	0
ReadyAndValidImplyGrant_A	259629478	201355	0	0
ReqAndReadyImplyGrant_A	259629478	201355	0	0
ReqImpliesValid_A	259629478	502068	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	0	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	201355	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201355	0	0
T1	2081	16	0	0
T2	7952	12	0	0
T3	826	11	0	0
T7	21253	43	0	0
T8	47942	85	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	42	0	0
T12	1724	17	0	0
T13	2135	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201355	0	0
T1	2081	16	0	0
T2	7952	12	0	0
T3	826	11	0	0
T7	21253	43	0	0
T8	47942	85	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	42	0	0
T12	1724	17	0	0
T13	2135	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201355	0	0
T1	2081	16	0	0
T2	7952	12	0	0
T3	826	11	0	0
T7	21253	43	0	0
T8	47942	85	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	42	0	0
T12	1724	17	0	0
T13	2135	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1983934	0	0
T1	2081	17	0	0
T2	7952	103	0	0
T3	826	11	0	0
T7	21253	311	0	0
T8	47942	690	0	0
T9	2384	16	0	0
T10	3214	24	0	0
T11	2614	43	0	0
T12	1724	18	0	0
T13	2135	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201355	0	0
T1	2081	16	0	0
T2	7952	12	0	0
T3	826	11	0	0
T7	21253	43	0	0
T8	47942	85	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	42	0	0
T12	1724	17	0	0
T13	2135	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201355	0	0
T1	2081	16	0	0
T2	7952	12	0	0
T3	826	11	0	0
T7	21253	43	0	0
T8	47942	85	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	42	0	0
T12	1724	17	0	0
T13	2135	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	502068	0	0
T1	2081	16	0	0
T2	7952	12	0	0
T3	826	12	0	0
T7	21253	60	0	0
T8	47942	91	0	0
T9	2384	15	0	0
T10	3214	25	0	0
T11	2614	42	0	0
T12	1724	17	0	0
T13	2135	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	201355	0	0
T1	2081	16	0	0
T2	7952	12	0	0
T3	826	11	0	0
T7	21253	43	0	0
T8	47942	85	0	0
T9	2384	15	0	0
T10	3214	24	0	0
T11	2614	42	0	0
T12	1724	17	0	0
T13	2135	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T7 T8 T22 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T22
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T22

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T22
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	816404	0	0
GntImpliesValid_A	259629478	816404	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	816404	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	7332415	0	0
ReadyAndValidImplyGrant_A	259629478	816404	0	0
ReqAndReadyImplyGrant_A	259629478	816404	0	0
ReqImpliesValid_A	259629478	1819462	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	19687	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	816404	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	816404	0	0
T1	2081	55	0	0
T2	7952	30	0	0
T3	826	37	0	0
T7	21253	148	0	0
T8	47942	293	0	0
T9	2384	42	0	0
T10	3214	115	0	0
T11	2614	172	0	0
T12	1724	50	0	0
T13	2135	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	816404	0	0
T1	2081	55	0	0
T2	7952	30	0	0
T3	826	37	0	0
T7	21253	148	0	0
T8	47942	293	0	0
T9	2384	42	0	0
T10	3214	115	0	0
T11	2614	172	0	0
T12	1724	50	0	0
T13	2135	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	816404	0	0
T1	2081	55	0	0
T2	7952	30	0	0
T3	826	37	0	0
T7	21253	148	0	0
T8	47942	293	0	0
T9	2384	42	0	0
T10	3214	115	0	0
T11	2614	172	0	0
T12	1724	50	0	0
T13	2135	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	7332415	0	0
T1	2081	1	0	0
T2	7952	162	0	0
T3	826	1	0	0
T7	21253	949	0	0
T8	47942	1868	0	0
T9	2384	1	0	0
T10	3214	1	0	0
T11	2614	1	0	0
T12	1724	1	0	0
T13	2135	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	816404	0	0
T1	2081	55	0	0
T2	7952	30	0	0
T3	826	37	0	0
T7	21253	148	0	0
T8	47942	293	0	0
T9	2384	42	0	0
T10	3214	115	0	0
T11	2614	172	0	0
T12	1724	50	0	0
T13	2135	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	816404	0	0
T1	2081	55	0	0
T2	7952	30	0	0
T3	826	37	0	0
T7	21253	148	0	0
T8	47942	293	0	0
T9	2384	42	0	0
T10	3214	115	0	0
T11	2614	172	0	0
T12	1724	50	0	0
T13	2135	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	1819462	0	0
T1	2081	55	0	0
T2	7952	30	0	0
T3	826	37	0	0
T7	21253	257	0	0
T8	47942	352	0	0
T9	2384	42	0	0
T10	3214	115	0	0
T11	2614	172	0	0
T12	1724	50	0	0
T13	2135	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	19687	0	899
T3	826	1	0	1
T7	21253	0	0	1
T8	47942	0	0	1
T9	2384	0	0	1
T10	3214	2	0	1
T11	2614	2	0	1
T12	1724	0	0	1
T13	2135	0	0	1
T14	11761	12	0	1
T15	0	5	0	0
T16	0	13	0	0
T17	0	7	0	0
T18	0	8	0	0
T19	0	2	0	0
T20	0	4	0	0
T22	40636	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	816404	0	0
T1	2081	55	0	0
T2	7952	30	0	0
T3	826	37	0	0
T7	21253	148	0	0
T8	47942	293	0	0
T9	2384	42	0	0
T10	3214	115	0	0
T11	2614	172	0	0
T12	1724	50	0	0
T13	2135	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T2 T7 T8 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T1 T2 T3 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	259629478	259512400	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	259629478	803137	0	0
GntImpliesValid_A	259629478	803137	0	0
GrantKnown_A	259629478	259512400	0	0
IdxKnown_A	259629478	259512400	0	0
IndexIsCorrect_A	259629478	803137	0	0
LockArbDecision_A	259629478	0	0	0
NoReadyValidNoGrant_A	259629478	216182903	0	0
ReadyAndValidImplyGrant_A	259629478	803137	0	0
ReqAndReadyImplyGrant_A	259629478	803137	0	0
ReqImpliesValid_A	259629478	8782074	0	0
ReqStaysHighUntilGranted0_M	259629478	0	0	0
RoundRobin_A	259629478	31215	0	899
ValidKnown_A	259629478	259512400	0	0
gen_data_port_assertion.DataFlow_A	259629478	803137	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803137	0	0
T1	2081	28	0	0
T2	7952	28	0	0
T3	826	42	0	0
T7	21253	149	0	0
T8	47942	327	0	0
T9	2384	39	0	0
T10	3214	97	0	0
T11	2614	140	0	0
T12	1724	46	0	0
T13	2135	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803137	0	0
T1	2081	28	0	0
T2	7952	28	0	0
T3	826	42	0	0
T7	21253	149	0	0
T8	47942	327	0	0
T9	2384	39	0	0
T10	3214	97	0	0
T11	2614	140	0	0
T12	1724	46	0	0
T13	2135	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803137	0	0
T1	2081	28	0	0
T2	7952	28	0	0
T3	826	42	0	0
T7	21253	149	0	0
T8	47942	327	0	0
T9	2384	39	0	0
T10	3214	97	0	0
T11	2614	140	0	0
T12	1724	46	0	0
T13	2135	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	216182903	0	0
T1	2081	1	0	0
T2	7952	7012	0	0
T3	826	1	0	0
T7	21253	18235	0	0
T8	47942	41394	0	0
T9	2384	1	0	0
T10	3214	1	0	0
T11	2614	1	0	0
T12	1724	1	0	0
T13	2135	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803137	0	0
T1	2081	28	0	0
T2	7952	28	0	0
T3	826	42	0	0
T7	21253	149	0	0
T8	47942	327	0	0
T9	2384	39	0	0
T10	3214	97	0	0
T11	2614	140	0	0
T12	1724	46	0	0
T13	2135	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803137	0	0
T1	2081	28	0	0
T2	7952	28	0	0
T3	826	42	0	0
T7	21253	149	0	0
T8	47942	327	0	0
T9	2384	39	0	0
T10	3214	97	0	0
T11	2614	140	0	0
T12	1724	46	0	0
T13	2135	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	8782074	0	0
T1	2081	28	0	0
T2	7952	242	0	0
T3	826	42	0	0
T7	21253	1158	0	0
T8	47942	2464	0	0
T9	2384	39	0	0
T10	3214	97	0	0
T11	2614	140	0	0
T12	1724	46	0	0
T13	2135	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	31215	0	899
T3	826	1	0	1
T7	21253	0	0	1
T8	47942	0	0	1
T9	2384	0	0	1
T10	3214	3	0	1
T11	2614	6	0	1
T12	1724	0	0	1
T13	2135	0	0	1
T14	11761	15	0	1
T15	0	5	0	0
T16	0	8	0	0
T17	0	8	0	0
T18	0	22	0	0
T20	0	10	0	0
T21	0	1	0	0
T22	40636	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	259512400	0	0
T1	2081	2029	0	0
T2	7952	7933	0	0
T3	826	797	0	0
T7	21253	21173	0	0
T8	47942	47933	0	0
T9	2384	2334	0	0
T10	3214	3135	0	0
T11	2614	2601	0	0
T12	1724	1677	0	0
T13	2135	2101	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259629478	803137	0	0
T1	2081	28	0	0
T2	7952	28	0	0
T3	826	42	0	0
T7	21253	149	0	0
T8	47942	327	0	0
T9	2384	39	0	0
T10	3214	97	0	0
T11	2614	140	0	0
T12	1724	46	0	0
T13	2135	44	0	0