Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1400	1			T1	11		T2	2		T7	2
all_values[1]	1000	1			T1	9		T2	1		T7	1
all_values[2]	1000	1			T1	8		T2	1		T7	1
all_values[3]	900	1			T1	5		T5	4		T6	5
all_values[4]	800	1			T1	6		T2	1		T7	1
all_values[5]	700	1			T1	7		T6	7		T13	7
all_values[6]	1200	1			T1	8		T5	4		T6	8
all_values[7]	700	1			T1	5		T5	2		T6	5
all_values[8]	500	1			T1	3		T2	1		T7	1
all_values[9]	1200	1			T1	10		T2	1		T7	1
all_values[10]	1000	1			T1	10		T6	10		T13	10
all_values[11]	1400	1			T1	10		T2	1		T7	1
all_values[12]	1300	1			T1	8		T2	2		T7	2
all_values[13]	500	1			T1	2		T5	3		T6	2
all_values[14]	800	1			T1	7		T2	1		T7	1
all_values[15]	1000	1			T1	8		T2	1		T7	1
all_values[16]	1300	1			T1	12		T5	1		T6	12
all_values[17]	1100	1			T1	9		T5	2		T6	9
all_values[18]	1200	1			T1	9		T2	1		T7	1
all_values[19]	1100	1			T1	11		T6	11		T13	11
all_values[20]	800	1			T1	6		T5	2		T6	6
all_values[21]	1000	1			T1	7		T2	2		T7	2
all_values[22]	800	1			T1	6		T2	1		T7	1
all_values[23]	800	1			T1	6		T2	2		T7	2
all_values[24]	1100	1			T1	9		T5	2		T6	9
all_values[25]	1000	1			T1	8		T5	2		T6	8
all_values[26]	900	1			T1	8		T5	1		T6	8