Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.71 100.00 94.78 100.00 100.00 99.61 55.89


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T751 /workspace/coverage/xbar_build_mode/2.xbar_error_random.32360733970414643819114056216694525945691505229184163671859101818684879869450 Nov 22 01:40:04 PM PST 23 Nov 22 01:40:19 PM PST 23 4923670935 ps
T752 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.31439361403929945940874740767245091393652517916112094810414965598557407824866 Nov 22 01:40:27 PM PST 23 Nov 22 01:40:45 PM PST 23 4712795935 ps
T753 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.81810161453298218189250345561489966149300413216606194381185622268969388882043 Nov 22 01:40:04 PM PST 23 Nov 22 01:42:47 PM PST 23 13716459184 ps
T754 /workspace/coverage/xbar_build_mode/49.xbar_stress_all.10788071223562272222007175876855212138331523664891466654967266289207437735985 Nov 22 01:42:00 PM PST 23 Nov 22 01:44:13 PM PST 23 46147859184 ps
T755 /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.16771002475387766227866700995496617845226832748073429731580651719697828405284 Nov 22 01:41:20 PM PST 23 Nov 22 01:41:31 PM PST 23 3423420935 ps
T756 /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.65610007207790949216355549110350252752945949137170437201220621327865530979491 Nov 22 01:40:28 PM PST 23 Nov 22 01:40:42 PM PST 23 10098608435 ps
T757 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.78860495982113881841157217362535374249448515043725148353351312542249406173252 Nov 22 01:40:27 PM PST 23 Nov 22 01:43:11 PM PST 23 13716459184 ps
T758 /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.62679239036064099149042257875607411902912066629474873857886929169740419552292 Nov 22 01:41:30 PM PST 23 Nov 22 01:41:49 PM PST 23 4712795935 ps
T759 /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.94321734279133328317638863664721789581560659940349428548179733835381637529758 Nov 22 01:40:44 PM PST 23 Nov 22 01:40:52 PM PST 23 360920935 ps
T760 /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.100173522617229998887872140754392039663939915381518394894200238364414963850829 Nov 22 01:41:56 PM PST 23 Nov 22 01:42:10 PM PST 23 3423420935 ps
T761 /workspace/coverage/xbar_build_mode/0.xbar_smoke.38968194730463126867376996223082327565192142441054897702434319405440590744281 Nov 22 01:39:51 PM PST 23 Nov 22 01:39:54 PM PST 23 331233435 ps
T762 /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.41674681400767571160594171555985347413761130759737736770428836307085549048887 Nov 22 01:41:49 PM PST 23 Nov 22 01:41:53 PM PST 23 27670935 ps
T763 /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.58241005905756686840244790220747689369143218884886013569775968622396565386596 Nov 22 01:40:14 PM PST 23 Nov 22 01:40:23 PM PST 23 360920935 ps
T764 /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.59838057998320450459112637159985109180233668867736795071187078002182845553542 Nov 22 01:40:10 PM PST 23 Nov 22 01:42:15 PM PST 23 46147859184 ps
T765 /workspace/coverage/xbar_build_mode/23.xbar_error_random.77636253526057783084893880335650696076653638189897671538541742252725668510339 Nov 22 01:40:43 PM PST 23 Nov 22 01:40:58 PM PST 23 4923670935 ps
T766 /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.22830466804757355087876012952214915281063680400740896302927462841866640447794 Nov 22 01:40:00 PM PST 23 Nov 22 01:45:41 PM PST 23 260306045935 ps
T767 /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.49948520864885018460341069150608990149728847732640531536367658957628448100363 Nov 22 01:40:37 PM PST 23 Nov 22 01:40:56 PM PST 23 4712795935 ps
T768 /workspace/coverage/xbar_build_mode/40.xbar_random.112651938623464934279770756018216749381077579147286370344569882658341551464597 Nov 22 01:41:42 PM PST 23 Nov 22 01:41:58 PM PST 23 4923670935 ps
T769 /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.328784259515916267458357796813516822632263046023838735826688339135615691430 Nov 22 01:41:14 PM PST 23 Nov 22 01:41:34 PM PST 23 4712795935 ps
T770 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.103342688915219972932909598052539160992574005036696112838492394603801029182993 Nov 22 01:40:08 PM PST 23 Nov 22 01:42:09 PM PST 23 46147859184 ps
T771 /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.87591196219569552364474588329554975413650756107830562676064065991644474337920 Nov 22 01:40:30 PM PST 23 Nov 22 01:40:43 PM PST 23 3423420935 ps
T772 /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.115497849124201801755337668347798682752971174212861080706422726191637471715283 Nov 22 01:40:42 PM PST 23 Nov 22 01:43:27 PM PST 23 13716459184 ps
T773 /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.54281058244229441666338599052742300532595676300006090346749573146109909838041 Nov 22 01:40:13 PM PST 23 Nov 22 01:40:28 PM PST 23 15405233435 ps
T774 /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.33145121110942331932889716978566461099925087274594971591519657755005174218653 Nov 22 01:41:44 PM PST 23 Nov 22 01:41:48 PM PST 23 27670935 ps
T775 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.54251259042882617772488844539700698923506556142979250226767199063161449980338 Nov 22 01:41:17 PM PST 23 Nov 22 01:43:19 PM PST 23 46147859184 ps
T776 /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.30085235223775150783621055994625538438654025344549628357423820606557987537582 Nov 22 01:41:26 PM PST 23 Nov 22 01:43:22 PM PST 23 46147859184 ps
T777 /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.88309669923599275083509113652437143410337068151520161101913211367250941671784 Nov 22 01:40:25 PM PST 23 Nov 22 01:40:28 PM PST 23 27670935 ps
T778 /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.36215753888038566397544311863323051204034548647349557414628044417265485807276 Nov 22 01:41:50 PM PST 23 Nov 22 01:42:06 PM PST 23 15405233435 ps
T779 /workspace/coverage/xbar_build_mode/8.xbar_same_source.76301503241293827901697439369453304446687195414124788311987746302689558291505 Nov 22 01:40:26 PM PST 23 Nov 22 01:40:39 PM PST 23 5235733435 ps
T780 /workspace/coverage/xbar_build_mode/19.xbar_same_source.48030556664138874633984223546613166934417797085930989585646656787890258315963 Nov 22 01:40:03 PM PST 23 Nov 22 01:40:17 PM PST 23 5235733435 ps
T781 /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.48668087194792131229928713026735720699093532860530551586478754689462228255188 Nov 22 01:41:24 PM PST 23 Nov 22 01:41:33 PM PST 23 360920935 ps
T782 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.41199229305002287317518572272698260657972516713366563796535200867869712573078 Nov 22 01:41:28 PM PST 23 Nov 22 01:47:06 PM PST 23 260306045935 ps
T783 /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.90559862654529584351735375737412898573307893145815130423922175229243410489380 Nov 22 01:41:13 PM PST 23 Nov 22 01:43:54 PM PST 23 13716459184 ps
T784 /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.5343672134394699527359465176151735059878276955103234824336385275427307967101 Nov 22 01:39:46 PM PST 23 Nov 22 01:45:22 PM PST 23 260306045935 ps
T785 /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.32327111230381088029890560179650090312719950978026572475356267375879212476548 Nov 22 01:41:15 PM PST 23 Nov 22 01:44:27 PM PST 23 160909483435 ps
T786 /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.101952501821991967101791391701402144394658297082175203062672783292355976244717 Nov 22 01:42:38 PM PST 23 Nov 22 01:42:57 PM PST 23 4712795935 ps
T787 /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.6723012985306139314537177464302407372705322062487902399896703343953965361380 Nov 22 01:40:12 PM PST 23 Nov 22 01:40:27 PM PST 23 10098608435 ps
T788 /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.59831919600361316145434197049518301108384455531434939885301326910473211401473 Nov 22 01:40:35 PM PST 23 Nov 22 01:43:46 PM PST 23 237556670935 ps
T789 /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.5575037780542176096952596157716041372302836701424407384991333723559580620700 Nov 22 01:41:44 PM PST 23 Nov 22 01:41:58 PM PST 23 3423420935 ps
T790 /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.104124096354718058155254998602072639493555479523917508901541605779263306625759 Nov 22 01:41:43 PM PST 23 Nov 22 01:41:54 PM PST 23 3423420935 ps
T791 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.41575708875373308238620075928279284460643450957968870338243689573732279049998 Nov 22 01:41:37 PM PST 23 Nov 22 01:47:19 PM PST 23 260306045935 ps
T792 /workspace/coverage/xbar_build_mode/31.xbar_same_source.72365810489591636151869593713816453916391201245836749769038864653248578687821 Nov 22 01:41:25 PM PST 23 Nov 22 01:41:38 PM PST 23 5235733435 ps
T793 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.45760337097212072679341274512897880577878980352318213950129574243385642779567 Nov 22 01:41:49 PM PST 23 Nov 22 01:44:33 PM PST 23 13716459184 ps
T794 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.6293426999086563586579956496044446637078727478849639851135014056003236305053 Nov 22 01:41:11 PM PST 23 Nov 22 01:43:19 PM PST 23 46147859184 ps
T795 /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.100552833923784894826133852309276522670707322168124011232345897346558950581399 Nov 22 01:39:53 PM PST 23 Nov 22 01:42:08 PM PST 23 13716459184 ps
T796 /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.71586549265559539342264472757399817538236424094268059299597436106264438763303 Nov 22 01:41:46 PM PST 23 Nov 22 01:41:55 PM PST 23 360920935 ps
T797 /workspace/coverage/xbar_build_mode/3.xbar_smoke.47733103432926789201945249585729106151536385838382082597343973562544432531772 Nov 22 01:39:54 PM PST 23 Nov 22 01:39:56 PM PST 23 331233435 ps
T798 /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.100976643472992566233580505270203078931332544848154168780330857711902191853398 Nov 22 01:41:48 PM PST 23 Nov 22 01:44:58 PM PST 23 237556670935 ps
T799 /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.74744908274153157489929934238724152479444477332492097250031959719223990812951 Nov 22 01:41:30 PM PST 23 Nov 22 01:47:10 PM PST 23 260306045935 ps
T800 /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.36595907420246427565278350781811748875788415002499224315850901905510528980790 Nov 22 01:41:37 PM PST 23 Nov 22 01:41:51 PM PST 23 3423420935 ps
T801 /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.105271457272204301285408262626427678186981115976358879288478244526165472499428 Nov 22 01:41:20 PM PST 23 Nov 22 01:43:36 PM PST 23 13716459184 ps
T802 /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.13722342847677623779045321994726141706537725949951664241144700522332743090723 Nov 22 01:41:16 PM PST 23 Nov 22 01:44:32 PM PST 23 160909483435 ps
T803 /workspace/coverage/xbar_build_mode/32.xbar_stress_all.25579460058638063508346938279464107697966587339204515663342004587031916076393 Nov 22 01:41:29 PM PST 23 Nov 22 01:43:39 PM PST 23 46147859184 ps
T804 /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.19756918244318244250122302925311254168570742084078531259118263796125925357642 Nov 22 01:40:58 PM PST 23 Nov 22 01:46:41 PM PST 23 260306045935 ps
T805 /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.31955859239936384486480238731013309990589328291702063823082605957843225707160 Nov 22 01:41:35 PM PST 23 Nov 22 01:43:54 PM PST 23 13716459184 ps
T806 /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.102431732702477562667781135956425703785450605255425149859633983376183782691040 Nov 22 01:41:29 PM PST 23 Nov 22 01:43:45 PM PST 23 13716459184 ps
T807 /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.76320320449949460045570859347832500866002771466587086018258293335125132219494 Nov 22 01:41:37 PM PST 23 Nov 22 01:41:41 PM PST 23 27670935 ps
T808 /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.10552700539710236065177864610701047779441921963849801327232547396074476803743 Nov 22 01:40:35 PM PST 23 Nov 22 01:43:20 PM PST 23 13716459184 ps
T809 /workspace/coverage/xbar_build_mode/9.xbar_error_random.45150413606418823082868632444960753342833376077820237935564146697611834181693 Nov 22 01:41:15 PM PST 23 Nov 22 01:41:30 PM PST 23 4923670935 ps
T810 /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2975828989146053428136383669464292981234642038823760148219554056270161917463 Nov 22 01:40:11 PM PST 23 Nov 22 01:42:32 PM PST 23 13716459184 ps
T811 /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.66505117915433459543484899652419111358720015297233412452912313570985403553664 Nov 22 01:40:35 PM PST 23 Nov 22 01:43:48 PM PST 23 237556670935 ps
T812 /workspace/coverage/xbar_build_mode/14.xbar_error_random.62954906399465484459285703926563547325342768301061982319769136159867083297370 Nov 22 01:40:56 PM PST 23 Nov 22 01:41:10 PM PST 23 4923670935 ps
T813 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.49974168648462369655133139070981727682869304018329651830671579005903970390507 Nov 22 01:42:03 PM PST 23 Nov 22 01:44:26 PM PST 23 13716459184 ps
T814 /workspace/coverage/xbar_build_mode/28.xbar_random.17553522986059541417922503324554160449893379517475515689785454400512293670439 Nov 22 01:41:21 PM PST 23 Nov 22 01:41:36 PM PST 23 4923670935 ps
T815 /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.85124147933730856460365787461096322402937848672256183592475853870340247468706 Nov 22 01:41:20 PM PST 23 Nov 22 01:41:31 PM PST 23 3423420935 ps
T816 /workspace/coverage/xbar_build_mode/10.xbar_same_source.47056169351047524897962464832690444070873028359866999539362217073836353634587 Nov 22 01:40:26 PM PST 23 Nov 22 01:40:40 PM PST 23 5235733435 ps
T817 /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.101224471034093306806132574743305071561551685964702506317361978636123915461174 Nov 22 01:40:20 PM PST 23 Nov 22 01:43:26 PM PST 23 237556670935 ps
T818 /workspace/coverage/xbar_build_mode/11.xbar_random.100380974290421767071650361136652288374392299885864134338449427569463874610947 Nov 22 01:40:11 PM PST 23 Nov 22 01:40:26 PM PST 23 4923670935 ps
T819 /workspace/coverage/xbar_build_mode/36.xbar_same_source.57707018589274052513302326178153863888993394324540125008361801158646780843893 Nov 22 01:41:11 PM PST 23 Nov 22 01:41:24 PM PST 23 5235733435 ps
T820 /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.56737337518298031304796740800622762027595378288388518514865083850459331273436 Nov 22 01:41:21 PM PST 23 Nov 22 01:41:32 PM PST 23 3423420935 ps
T821 /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.83289070601254267413602423233015763217221771145605824799533634610242853760224 Nov 22 01:41:24 PM PST 23 Nov 22 01:44:38 PM PST 23 237556670935 ps
T822 /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.21715427791153955987914527882790142915678820962892605828075848380914629912317 Nov 22 01:41:45 PM PST 23 Nov 22 01:41:49 PM PST 23 27670935 ps
T823 /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.4934094609838060834170453850529879456929112894223605420336153033867861321806 Nov 22 01:41:17 PM PST 23 Nov 22 01:43:31 PM PST 23 13716459184 ps
T824 /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.25747879663689018142930688870090903621392394380323605488268649865115996046250 Nov 22 01:41:14 PM PST 23 Nov 22 01:41:29 PM PST 23 10098608435 ps
T825 /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.46797661944494279248348574961494709072572431958683186769174490704408054863925 Nov 22 01:40:07 PM PST 23 Nov 22 01:40:19 PM PST 23 3423420935 ps
T826 /workspace/coverage/xbar_build_mode/46.xbar_stress_all.115368337018724956954339081164671546374321367278722760134472368021613214723662 Nov 22 01:41:44 PM PST 23 Nov 22 01:43:53 PM PST 23 46147859184 ps
T827 /workspace/coverage/xbar_build_mode/17.xbar_error_random.53216061874299789063454787151468610184785557715621744829564690746209703983505 Nov 22 01:40:37 PM PST 23 Nov 22 01:40:52 PM PST 23 4923670935 ps
T828 /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.53277461653828069755788319961189121996388935900436309544802058895137603618164 Nov 22 01:41:40 PM PST 23 Nov 22 01:44:48 PM PST 23 237556670935 ps
T829 /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.26996899833651654122875799857607767313256615667920410048830219924702284724392 Nov 22 01:41:16 PM PST 23 Nov 22 01:41:28 PM PST 23 360920935 ps
T830 /workspace/coverage/xbar_build_mode/44.xbar_error_random.14124219938857384059202969366403818457970007085888149342832237296422052834770 Nov 22 01:41:37 PM PST 23 Nov 22 01:41:53 PM PST 23 4923670935 ps
T831 /workspace/coverage/xbar_build_mode/29.xbar_error_random.55816065774783123287159832011973156957891135946763881360234413182638304661163 Nov 22 01:41:46 PM PST 23 Nov 22 01:42:02 PM PST 23 4923670935 ps
T832 /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.34863019862715191170044145788904687047767627592628138724368348358430714946832 Nov 22 01:41:17 PM PST 23 Nov 22 01:41:32 PM PST 23 10098608435 ps
T833 /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.108177404964227103909808525748497552940128112859885060103218645238355009329273 Nov 22 01:41:19 PM PST 23 Nov 22 01:41:34 PM PST 23 15405233435 ps
T834 /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.20599884094670704768318131578638087094628139153494688441106709808768402761063 Nov 22 01:41:24 PM PST 23 Nov 22 01:46:55 PM PST 23 260306045935 ps
T835 /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.23630374199279427421801539055516619220966146470344195828143406550756949036706 Nov 22 01:41:50 PM PST 23 Nov 22 01:42:03 PM PST 23 3423420935 ps
T836 /workspace/coverage/xbar_build_mode/34.xbar_error_random.105992241644933935604680045689131684279598235618284135281296432046545839903977 Nov 22 01:41:27 PM PST 23 Nov 22 01:41:41 PM PST 23 4923670935 ps
T837 /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.89882181496560619751377737472370114536700151710374247899131891086322168130301 Nov 22 01:40:11 PM PST 23 Nov 22 01:40:24 PM PST 23 3423420935 ps
T838 /workspace/coverage/xbar_build_mode/2.xbar_random.10166730624372003982692459344047909282383710681995530051406550129957184034646 Nov 22 01:40:02 PM PST 23 Nov 22 01:40:19 PM PST 23 4923670935 ps
T839 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.103786943349300767416774661321645838389303171836541876446872063899760734487788 Nov 22 01:40:25 PM PST 23 Nov 22 01:43:12 PM PST 23 13716459184 ps
T840 /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.7860702086385161961141154238477914749848790475668718943937468856407213724922 Nov 22 01:41:13 PM PST 23 Nov 22 01:41:26 PM PST 23 3423420935 ps
T841 /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.31828700117273222196622855978892989481547837926353819558931985357143911393318 Nov 22 01:41:43 PM PST 23 Nov 22 01:41:54 PM PST 23 3423420935 ps
T842 /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.27659897902807284218079292909964941677030526847123657694358354661726360404305 Nov 22 01:40:06 PM PST 23 Nov 22 01:40:08 PM PST 23 27670935 ps
T843 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.98780842499860107860445562697163900793303113885717196377502513422432833686113 Nov 22 01:40:25 PM PST 23 Nov 22 01:42:47 PM PST 23 13716459184 ps
T844 /workspace/coverage/xbar_build_mode/3.xbar_same_source.74386435382378902213452418002136159605845208990511921883043184648631992806107 Nov 22 01:40:02 PM PST 23 Nov 22 01:40:18 PM PST 23 5235733435 ps
T845 /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.76112608146612342670268158570235040908720442664895771851653374948592054712878 Nov 22 01:41:45 PM PST 23 Nov 22 01:41:58 PM PST 23 3423420935 ps
T846 /workspace/coverage/xbar_build_mode/4.xbar_error_random.96864104877069187730325405916701656641132004503135199216243196207872640970023 Nov 22 01:40:36 PM PST 23 Nov 22 01:40:51 PM PST 23 4923670935 ps
T847 /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.22098693681637348173116278981718541162013429287657353147578007941068117044459 Nov 22 01:41:14 PM PST 23 Nov 22 01:44:32 PM PST 23 160909483435 ps
T848 /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.72728818499150729008598078477816954501214242692111234923124794373695486965986 Nov 22 01:40:03 PM PST 23 Nov 22 01:45:36 PM PST 23 260306045935 ps
T849 /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.99380218454312627173054916040819170689563336617076687648130772815179255842641 Nov 22 01:41:49 PM PST 23 Nov 22 01:42:05 PM PST 23 15405233435 ps
T850 /workspace/coverage/xbar_build_mode/1.xbar_smoke.18589220836343689983246967401975361792237353242860496934668223199905853227107 Nov 22 01:39:55 PM PST 23 Nov 22 01:39:57 PM PST 23 331233435 ps
T851 /workspace/coverage/xbar_build_mode/5.xbar_stress_all.103911246850716748308915390366266736538929604859108013257225885026189574589875 Nov 22 01:40:23 PM PST 23 Nov 22 01:42:23 PM PST 23 46147859184 ps
T852 /workspace/coverage/xbar_build_mode/1.xbar_same_source.56066030932626508928277366953467202712510730594185425801928902981438635602620 Nov 22 01:39:52 PM PST 23 Nov 22 01:40:05 PM PST 23 5235733435 ps
T853 /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.4002722389861819167123028390692698874100504568123863550865781737290200083356 Nov 22 01:40:14 PM PST 23 Nov 22 01:40:23 PM PST 23 360920935 ps
T854 /workspace/coverage/xbar_build_mode/16.xbar_same_source.44912270061634985277743728900174046436024962428117827477677984365670078059796 Nov 22 01:41:30 PM PST 23 Nov 22 01:41:45 PM PST 23 5235733435 ps
T855 /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.39704779501985367922588527191230686281464465163921884893470524114383766393503 Nov 22 01:41:50 PM PST 23 Nov 22 01:42:06 PM PST 23 15405233435 ps
T856 /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.7427761063959587280177982733843057246910244929941760001188033942343190705036 Nov 22 01:41:16 PM PST 23 Nov 22 01:44:25 PM PST 23 237556670935 ps
T857 /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.22475054661138883450468843545975330413224347599744303412621983498376547191575 Nov 22 01:41:27 PM PST 23 Nov 22 01:41:29 PM PST 23 27670935 ps
T858 /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.14907180419225758263482284307883277166503028216457637930617178165753963460019 Nov 22 01:41:14 PM PST 23 Nov 22 01:43:35 PM PST 23 13716459184 ps
T859 /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.107275534286645164104781884690240377015040982301204571387414197297639901572100 Nov 22 01:41:33 PM PST 23 Nov 22 01:41:52 PM PST 23 4712795935 ps
T860 /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.99350769299908341836070486879165508511345328416960039252309576201751529401481 Nov 22 01:41:01 PM PST 23 Nov 22 01:43:44 PM PST 23 13716459184 ps
T861 /workspace/coverage/xbar_build_mode/4.xbar_smoke.19617190239174837240802036642856850773134528324116031275681217293685421747991 Nov 22 01:40:23 PM PST 23 Nov 22 01:40:26 PM PST 23 331233435 ps
T862 /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.17196608620318389173115421660515858384599064124443738562306400497512016752309 Nov 22 01:40:41 PM PST 23 Nov 22 01:40:50 PM PST 23 360920935 ps
T863 /workspace/coverage/xbar_build_mode/22.xbar_random.25706941656984553335800399262014397119727004994116841172634606028819017517711 Nov 22 01:40:46 PM PST 23 Nov 22 01:41:01 PM PST 23 4923670935 ps
T864 /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.60214557195055953912763444075634865584773921075066096701566067312326822193260 Nov 22 01:41:17 PM PST 23 Nov 22 01:41:32 PM PST 23 15405233435 ps
T865 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.33095992667242274775877871365882319047168442212237818107388595866430974120296 Nov 22 01:40:19 PM PST 23 Nov 22 01:42:39 PM PST 23 13716459184 ps
T866 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.112249098060549909824410301032866082836566149401293530206112667644857177163850 Nov 22 01:41:34 PM PST 23 Nov 22 01:44:19 PM PST 23 13716459184 ps
T867 /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.102572735888378329700290938860318323280016310431073548457891616282711948646431 Nov 22 01:42:01 PM PST 23 Nov 22 01:45:25 PM PST 23 160909483435 ps
T868 /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.101933056932638905041194265871517228568187497344545369519938438005088431854872 Nov 22 01:41:52 PM PST 23 Nov 22 01:47:35 PM PST 23 260306045935 ps
T869 /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.11726035403571772062035130076989992119251169606275005354243356123388641824100 Nov 22 01:41:48 PM PST 23 Nov 22 01:45:03 PM PST 23 160909483435 ps
T870 /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1009357913345182244245523452091913817277351368135565170194254784219322785565 Nov 22 01:40:18 PM PST 23 Nov 22 01:40:33 PM PST 23 15405233435 ps
T871 /workspace/coverage/xbar_build_mode/12.xbar_random.36899783440188964536389293683183160324085361147967325070569764592814554954680 Nov 22 01:41:15 PM PST 23 Nov 22 01:41:31 PM PST 23 4923670935 ps
T872 /workspace/coverage/xbar_build_mode/45.xbar_random.69351731592446717667331274890509267033872747295880300835666058328098765157323 Nov 22 01:41:43 PM PST 23 Nov 22 01:41:59 PM PST 23 4923670935 ps
T873 /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.80015941643580178946319746072373948721265397015252072609904941902753248078339 Nov 22 01:40:09 PM PST 23 Nov 22 01:45:44 PM PST 23 260306045935 ps
T874 /workspace/coverage/xbar_build_mode/31.xbar_random.30717732944793978890210577508732305404139112243088670080531858161748834508189 Nov 22 01:41:21 PM PST 23 Nov 22 01:41:36 PM PST 23 4923670935 ps
T875 /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.16270693645246862668018223348731055874952042545234000589832779392504981192279 Nov 22 01:41:46 PM PST 23 Nov 22 01:41:56 PM PST 23 360920935 ps
T876 /workspace/coverage/xbar_build_mode/1.xbar_error_random.89241112813122710952734626203520112889159910272135107904099735096058645638327 Nov 22 01:40:03 PM PST 23 Nov 22 01:40:19 PM PST 23 4923670935 ps
T877 /workspace/coverage/xbar_build_mode/38.xbar_smoke.76376097051777960797685906669285033341998354687189701998234434069429887211136 Nov 22 01:41:34 PM PST 23 Nov 22 01:41:39 PM PST 23 331233435 ps
T878 /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.90648424242603805548507763101835339531081020222450384126365017450047581102573 Nov 22 01:41:42 PM PST 23 Nov 22 01:47:26 PM PST 23 260306045935 ps
T879 /workspace/coverage/xbar_build_mode/27.xbar_same_source.1678737150847873297637741507282872540460582173114425880110635007084868725268 Nov 22 01:40:58 PM PST 23 Nov 22 01:41:12 PM PST 23 5235733435 ps
T880 /workspace/coverage/xbar_build_mode/18.xbar_same_source.10229218324532876409773715399270076050851975954794263337045677078561970383694 Nov 22 01:41:49 PM PST 23 Nov 22 01:42:04 PM PST 23 5235733435 ps
T881 /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.46398531805023376595107231783297725916572253050379652004801560954990795697525 Nov 22 01:41:20 PM PST 23 Nov 22 01:41:38 PM PST 23 4712795935 ps
T882 /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.68673154095578146570863319952957186998491151272210259853974943128940658691236 Nov 22 01:40:11 PM PST 23 Nov 22 01:40:29 PM PST 23 4712795935 ps
T883 /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.15456013835504260588385243766289027226803167048747381736725079542340981443187 Nov 22 01:41:34 PM PST 23 Nov 22 01:41:45 PM PST 23 360920935 ps
T884 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.31632478712012185636237239551174330324341593278284335701071661887341654194366 Nov 22 01:41:50 PM PST 23 Nov 22 01:44:09 PM PST 23 13716459184 ps
T885 /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.77783057072940031357194764113127122734793098803551514607938049170412803685974 Nov 22 01:40:40 PM PST 23 Nov 22 01:40:58 PM PST 23 4712795935 ps
T886 /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.52708088033977090942020980633617784276627787999450183591540758056218030006913 Nov 22 01:41:48 PM PST 23 Nov 22 01:47:22 PM PST 23 260306045935 ps
T887 /workspace/coverage/xbar_build_mode/6.xbar_same_source.13222075236368051935799329078334632570733668370957690726269042730122035595722 Nov 22 01:40:21 PM PST 23 Nov 22 01:40:33 PM PST 23 5235733435 ps
T888 /workspace/coverage/xbar_build_mode/34.xbar_same_source.28019300940679991520186749619796792252752869672370113010218580356664494240300 Nov 22 01:41:42 PM PST 23 Nov 22 01:41:55 PM PST 23 5235733435 ps
T889 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.4267384540395086852726384615343653235832199230178699881229543321632625702844 Nov 22 01:40:12 PM PST 23 Nov 22 01:42:19 PM PST 23 46147859184 ps
T890 /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.85395797482519533068555424980163219121929931084337792125092707833211666302722 Nov 22 01:41:42 PM PST 23 Nov 22 01:43:37 PM PST 23 46147859184 ps
T891 /workspace/coverage/xbar_build_mode/43.xbar_random.96026979344589212206203243740256484178317761411258310339242823268068819403193 Nov 22 01:42:00 PM PST 23 Nov 22 01:42:21 PM PST 23 4923670935 ps
T892 /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.31099266447878032779619912047197224307570323775371384276273640167598795319875 Nov 22 01:41:26 PM PST 23 Nov 22 01:44:34 PM PST 23 237556670935 ps
T893 /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.76033061871386770376022031987261530746304619026854427714883686809636715080161 Nov 22 01:40:35 PM PST 23 Nov 22 01:43:16 PM PST 23 13716459184 ps
T894 /workspace/coverage/xbar_build_mode/40.xbar_smoke.84518695110585271091286512066297629289857454232137918534386870123702417613973 Nov 22 01:42:03 PM PST 23 Nov 22 01:42:12 PM PST 23 331233435 ps
T895 /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.24584428076210625022096933105626297209058822509530689355315824485105950553696 Nov 22 01:41:42 PM PST 23 Nov 22 01:44:51 PM PST 23 237556670935 ps
T896 /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.9398802396142712262853602573350063118352096758137412721202265294610157138190 Nov 22 01:40:28 PM PST 23 Nov 22 01:43:39 PM PST 23 237556670935 ps
T897 /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.15557918559592918526030870380074977797044591065066064924974101311614125452243 Nov 22 01:41:36 PM PST 23 Nov 22 01:41:56 PM PST 23 4712795935 ps
T898 /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.109355456233508728948762894086013034803026967760691268444527584267063496683413 Nov 22 01:40:13 PM PST 23 Nov 22 01:40:33 PM PST 23 4712795935 ps
T899 /workspace/coverage/xbar_build_mode/48.xbar_same_source.108414143170354334829928638793068059034757102767785580433283858119247033078973 Nov 22 01:41:48 PM PST 23 Nov 22 01:42:04 PM PST 23 5235733435 ps
T900 /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.79853452424591926486317414395993382074731071321560909621277790171032901738287 Nov 22 01:41:28 PM PST 23 Nov 22 01:41:47 PM PST 23 4712795935 ps

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.5805828665256921779305699518718961190776580931482990190389107452173711672325
Short name T6
Test name
Test status
Simulation time 13716459184 ps
CPU time 135.18 seconds
Started Nov 22 01:41:23 PM PST 23
Finished Nov 22 01:43:40 PM PST 23
Peak memory 206240 kb
Host smart-f83c1afa-48b6-4240-b8ce-8a1186e779d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5805828665256921779305699518718961190776580931482990190389107452173711672325 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.5805828665256921779305699518718961190776580931482990190389107452173711672325
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.30929866293661072658547528258476394371198065591629717459342718764302741907325
Short name T7
Test name
Test status
Simulation time 260306045935 ps
CPU time 333.47 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:46:51 PM PST 23
Peak memory 203020 kb
Host smart-0c799a3c-612f-49c3-a797-73920b3d1c26
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=30929866293661072658547528258476394371198065591629717459342718764302741907325 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.30929866293661072658547528258476394371198065591629717459342718764302741907325
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.20373492478576095375656637195889403719445646688820558881901868534055610428062
Short name T8
Test name
Test status
Simulation time 360920935 ps
CPU time 7.86 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:40:35 PM PST 23
Peak memory 202032 kb
Host smart-3ae6e333-4692-49b0-bdb0-11d7ab20629f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20373492478576095375656637195889403719445646688820558881901868534055610428062 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.20373492478576095375656637195889403719445646688820558881901868534055610428062
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.66385089181237402871031475582103208652271615631158521316786689976169617895264
Short name T21
Test name
Test status
Simulation time 237556670935 ps
CPU time 189.4 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:44:27 PM PST 23
Peak memory 202008 kb
Host smart-788582c2-9307-4070-a13e-3925bfae82a1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=66385089181237402871031475582103208652271615631158521316786689976169617895264 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 24.xbar_random_large_delays.66385089181237402871031475582103208652271615631158521316786689976169617895264
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.66023699079187593546748101428508419494672532851699703700298468654522133667046
Short name T5
Test name
Test status
Simulation time 46147859184 ps
CPU time 114.69 seconds
Started Nov 22 01:40:37 PM PST 23
Finished Nov 22 01:42:33 PM PST 23
Peak memory 204876 kb
Host smart-1c80ea19-f9b5-4764-bfa6-a4db044135c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=66023699079187593546748101428508419494672532851699703700298468654522133667046 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 11.xbar_stress_all_with_error.66023699079187593546748101428508419494672532851699703700298468654522133667046
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.23142112563611442239712972173948918053571472418041381840386542019267097236665
Short name T51
Test name
Test status
Simulation time 160909483435 ps
CPU time 191.09 seconds
Started Nov 22 01:40:01 PM PST 23
Finished Nov 22 01:43:14 PM PST 23
Peak memory 201928 kb
Host smart-21e26bdc-0b8a-420e-b266-554cafaffb62
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=23142112563611442239712972173948918053571472418041381840386542019267097236665 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.23142112563611442239712972173948918053571472418041381840386542019267097236665
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.62015840407890956406606768925450831347143255530900528789941493284525244611314
Short name T64
Test name
Test status
Simulation time 4923670935 ps
CPU time 15.08 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:17 PM PST 23
Peak memory 202028 kb
Host smart-e7f7e8d7-03f2-4d0a-b014-b3c856190d56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62015840407890956406606768925450831347143255530900528789941493284525244611314 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 0.xbar_random.62015840407890956406606768925450831347143255530900528789941493284525244611314
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2937030842731585534709594531275618408990289626168360917285002509614675164610
Short name T394
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.15 seconds
Started Nov 22 01:39:55 PM PST 23
Finished Nov 22 01:40:14 PM PST 23
Peak memory 201980 kb
Host smart-770675a3-aa22-4925-bbe4-adf035d6abb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2937030842731585534709594531275618408990289626168360917285002509614675164610 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2937030842731585534709594531275618408990289626168360917285002509614675164610
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.10677746566728070957888758465273585698268936289750223673560336312248912849031
Short name T559
Test name
Test status
Simulation time 260306045935 ps
CPU time 335.11 seconds
Started Nov 22 01:40:04 PM PST 23
Finished Nov 22 01:45:41 PM PST 23
Peak memory 203032 kb
Host smart-07ea8c8e-af8b-4c3e-a053-7532d162f682
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=10677746566728070957888758465273585698268936289750223673560336312248912849031 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.10677746566728070957888758465273585698268936289750223673560336312248912849031
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.55816967966931839305583773838703532354964359308451518957080059174576841635722
Short name T401
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.42 seconds
Started Nov 22 01:39:52 PM PST 23
Finished Nov 22 01:40:03 PM PST 23
Peak memory 201916 kb
Host smart-169bd555-51db-4194-bdb8-4e718ca31a37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55816967966931839305583773838703532354964359308451518957080059174576841635722 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.55816967966931839305583773838703532354964359308451518957080059174576841635722
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.76630534881842245612922766644301390979097931239649874508117583763493033074369
Short name T339
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.68 seconds
Started Nov 22 01:39:51 PM PST 23
Finished Nov 22 01:40:04 PM PST 23
Peak memory 201980 kb
Host smart-a1ad0b08-aa2e-4c46-8ae1-583798e16616
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76630534881842245612922766644301390979097931239649874508117583763493033074369 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 0.xbar_error_random.76630534881842245612922766644301390979097931239649874508117583763493033074369
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.26783895248860338035316564947852706669924848230999151006266901805735886836551
Short name T309
Test name
Test status
Simulation time 237556670935 ps
CPU time 187.07 seconds
Started Nov 22 01:39:59 PM PST 23
Finished Nov 22 01:43:07 PM PST 23
Peak memory 201904 kb
Host smart-3fe96a9b-616f-445d-9d02-e6cb8ea98846
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=26783895248860338035316564947852706669924848230999151006266901805735886836551 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 0.xbar_random_large_delays.26783895248860338035316564947852706669924848230999151006266901805735886836551
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.99314368366108998257549582260277633607676731013155586821991534852383881165069
Short name T679
Test name
Test status
Simulation time 360920935 ps
CPU time 7.72 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:40:12 PM PST 23
Peak memory 201928 kb
Host smart-817d2551-2ae9-4724-a22c-c028301f59d3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99314368366108998257549582260277633607676731013155586821991534852383881165069 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.99314368366108998257549582260277633607676731013155586821991534852383881165069
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.40459539212691682990242770181820590639142643599844207749828305795307321000455
Short name T731
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.07 seconds
Started Nov 22 01:39:56 PM PST 23
Finished Nov 22 01:40:08 PM PST 23
Peak memory 201976 kb
Host smart-854158d5-139a-42d6-aa9f-1a45b71a1cd1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40459539212691682990242770181820590639142643599844207749828305795307321000455 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 0.xbar_same_source.40459539212691682990242770181820590639142643599844207749828305795307321000455
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.38968194730463126867376996223082327565192142441054897702434319405440590744281
Short name T761
Test name
Test status
Simulation time 331233435 ps
CPU time 1.57 seconds
Started Nov 22 01:39:51 PM PST 23
Finished Nov 22 01:39:54 PM PST 23
Peak memory 201880 kb
Host smart-dfb2aa8e-635b-4114-9197-0261ca564f79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=38968194730463126867376996223082327565192142441054897702434319405440590744281 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 0.xbar_smoke.38968194730463126867376996223082327565192142441054897702434319405440590744281
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.60598975706884912279935448673908658747921204241816193479728307777853125631444
Short name T566
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.73 seconds
Started Nov 22 01:40:04 PM PST 23
Finished Nov 22 01:40:19 PM PST 23
Peak memory 202000 kb
Host smart-2cd33294-f748-4d60-95e8-69914abad56c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=60598975706884912279935448673908658747921204241816193479728307777853125631444 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.60598975706884912279935448673908658747921204241816193479728307777853125631444
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.31552951169850647237665683403845745430928225048621091591766821993314110466454
Short name T616
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.75 seconds
Started Nov 22 01:39:56 PM PST 23
Finished Nov 22 01:40:10 PM PST 23
Peak memory 201980 kb
Host smart-88b44c43-0918-4631-a4a7-acce28e4662f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=31552951169850647237665683403845745430928225048621091591766821993314110466454 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.31552951169850647237665683403845745430928225048621091591766821993314110466454
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.114104763911828893846555950744970679459044331539630307854233837861732109630173
Short name T392
Test name
Test status
Simulation time 27670935 ps
CPU time 1.17 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:02 PM PST 23
Peak memory 201860 kb
Host smart-436e23f8-a11f-4377-a1ef-08adbb5f06d1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114104763911828893846555950744970679459044331539630307854233837861732109630173 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.114104763911828893846555950744970679459044331539630307854233837861732109630173
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.81608190122505285950351956641284919918730832382634987012567906807541372220951
Short name T689
Test name
Test status
Simulation time 46147859184 ps
CPU time 129.97 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:42:11 PM PST 23
Peak memory 203216 kb
Host smart-9b32c76b-5155-48d2-a04d-f9f6e35957bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81608190122505285950351956641284919918730832382634987012567906807541372220951 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 0.xbar_stress_all.81608190122505285950351956641284919918730832382634987012567906807541372220951
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.233808745284029345091099257258326456526621126578097642331416784389600336802
Short name T193
Test name
Test status
Simulation time 46147859184 ps
CPU time 118.83 seconds
Started Nov 22 01:40:04 PM PST 23
Finished Nov 22 01:42:05 PM PST 23
Peak memory 204940 kb
Host smart-86234463-a883-4f79-87fe-09976cdbe32b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=233808745284029345091099257258326456526621126578097642331416784389600336802 -assert nopostproc +UVM_TESTNAME=xba
r_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_
log /dev/null -cm_name 0.xbar_stress_all_with_error.233808745284029345091099257258326456526621126578097642331416784389600336802
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.14637284728945535327267013371035152863518760430553943982367196782333921098894
Short name T732
Test name
Test status
Simulation time 13716459184 ps
CPU time 162.25 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:42:52 PM PST 23
Peak memory 205132 kb
Host smart-6e225962-4808-4b47-8098-948755d9a169
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14637284728945535327267013371035152863518760430553943982367196782333921098894 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.14637284728945535327267013371035152863518760430553943982367196782333921098894
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.100552833923784894826133852309276522670707322168124011232345897346558950581399
Short name T795
Test name
Test status
Simulation time 13716459184 ps
CPU time 134.26 seconds
Started Nov 22 01:39:53 PM PST 23
Finished Nov 22 01:42:08 PM PST 23
Peak memory 206200 kb
Host smart-0d42074c-ca30-4f8f-8cd4-7cd9307ec494
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100552833923784894826133852309276522670707322168124011232345897346558950581399 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.100552833923784894826133852309276522670707322168124011232345897346558950581399
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.89314392618326179286380485608743471905693180973885870766082456261639140334924
Short name T189
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.08 seconds
Started Nov 22 01:39:50 PM PST 23
Finished Nov 22 01:40:02 PM PST 23
Peak memory 201952 kb
Host smart-0cba6a0b-95c6-4a28-9143-b93c4ceeb8df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=89314392618326179286380485608743471905693180973885870766082456261639140334924 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 0.xbar_unmapped_addr.89314392618326179286380485608743471905693180973885870766082456261639140334924
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.105595222909581857448591768507467535891977971466169493684793041461217843823491
Short name T641
Test name
Test status
Simulation time 4712795935 ps
CPU time 19.03 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:40:29 PM PST 23
Peak memory 201964 kb
Host smart-4508cc05-3187-4cda-9a95-7ce4e60142c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105595222909581857448591768507467535891977971466169493684793041461217843823491 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.105595222909581857448591768507467535891977971466169493684793041461217843823491
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.5343672134394699527359465176151735059878276955103234824336385275427307967101
Short name T784
Test name
Test status
Simulation time 260306045935 ps
CPU time 335.12 seconds
Started Nov 22 01:39:46 PM PST 23
Finished Nov 22 01:45:22 PM PST 23
Peak memory 203024 kb
Host smart-26989f28-f8fb-4ce8-82ff-3fe3fa717dbd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=5343672134394699527359465176151735059878276955103234824336385275427307967101 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build
_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.5343672134394699527359465176151735059878276955103234824336385275427307967101
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.76004735656712206266593674596951856075944600298410548501837766969424595464331
Short name T245
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.53 seconds
Started Nov 22 01:39:52 PM PST 23
Finished Nov 22 01:40:03 PM PST 23
Peak memory 201976 kb
Host smart-008061a4-ff29-4722-ad92-810fa8497b34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76004735656712206266593674596951856075944600298410548501837766969424595464331 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.76004735656712206266593674596951856075944600298410548501837766969424595464331
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.89241112813122710952734626203520112889159910272135107904099735096058645638327
Short name T876
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.05 seconds
Started Nov 22 01:40:03 PM PST 23
Finished Nov 22 01:40:19 PM PST 23
Peak memory 201968 kb
Host smart-48918b46-a323-40a8-a7d5-e053a05f44b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=89241112813122710952734626203520112889159910272135107904099735096058645638327 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 1.xbar_error_random.89241112813122710952734626203520112889159910272135107904099735096058645638327
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.112362822024813732836596798837727764395875683504669230051622596270944218942947
Short name T461
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.81 seconds
Started Nov 22 01:40:01 PM PST 23
Finished Nov 22 01:40:18 PM PST 23
Peak memory 201996 kb
Host smart-6b4250c4-a9d3-4f70-931c-cfe9fe9a2ba9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112362822024813732836596798837727764395875683504669230051622596270944218942947 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 1.xbar_random.112362822024813732836596798837727764395875683504669230051622596270944218942947
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.4142454754453279627988207366861991723803745554889086764381800757947301094595
Short name T46
Test name
Test status
Simulation time 237556670935 ps
CPU time 188.7 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:43:09 PM PST 23
Peak memory 201976 kb
Host smart-3c98083a-fd81-41c3-95ae-100ba22186d3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142454754453279627988207366861991723803745554889086764381800757947301094595 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 1.xbar_random_large_delays.4142454754453279627988207366861991723803745554889086764381800757947301094595
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.102906780578979284995393546752153335530390236941460517411945902488738902044792
Short name T194
Test name
Test status
Simulation time 160909483435 ps
CPU time 196.32 seconds
Started Nov 22 01:39:55 PM PST 23
Finished Nov 22 01:43:12 PM PST 23
Peak memory 201944 kb
Host smart-dbffed3c-cce8-4440-89e5-a486b9d4eb42
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=102906780578979284995393546752153335530390236941460517411945902488738902044792 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.102906780578979284995393546752153335530390236941460517411945902488738902044792
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.82944145177805682555107670760348102749244211361898541691826799879078095350889
Short name T33
Test name
Test status
Simulation time 360920935 ps
CPU time 8.19 seconds
Started Nov 22 01:39:55 PM PST 23
Finished Nov 22 01:40:04 PM PST 23
Peak memory 201920 kb
Host smart-75283d76-df50-405f-87f2-11494f4b2a6a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82944145177805682555107670760348102749244211361898541691826799879078095350889 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.82944145177805682555107670760348102749244211361898541691826799879078095350889
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.56066030932626508928277366953467202712510730594185425801928902981438635602620
Short name T852
Test name
Test status
Simulation time 5235733435 ps
CPU time 13.03 seconds
Started Nov 22 01:39:52 PM PST 23
Finished Nov 22 01:40:05 PM PST 23
Peak memory 201988 kb
Host smart-28ee9f78-9ba2-4470-a492-c198dd2de4e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56066030932626508928277366953467202712510730594185425801928902981438635602620 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 1.xbar_same_source.56066030932626508928277366953467202712510730594185425801928902981438635602620
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.18589220836343689983246967401975361792237353242860496934668223199905853227107
Short name T850
Test name
Test status
Simulation time 331233435 ps
CPU time 1.66 seconds
Started Nov 22 01:39:55 PM PST 23
Finished Nov 22 01:39:57 PM PST 23
Peak memory 201916 kb
Host smart-26389736-7fce-44b8-a759-841e336fd86f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18589220836343689983246967401975361792237353242860496934668223199905853227107 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 1.xbar_smoke.18589220836343689983246967401975361792237353242860496934668223199905853227107
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.113479124089107273371544112918237964204402950489951501229924818744248325987005
Short name T267
Test name
Test status
Simulation time 15405233435 ps
CPU time 13.02 seconds
Started Nov 22 01:40:07 PM PST 23
Finished Nov 22 01:40:21 PM PST 23
Peak memory 201900 kb
Host smart-4ef4dc8a-5ded-4f40-869c-76d063903b8b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=113479124089107273371544112918237964204402950489951501229924818744248325987005 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.113479124089107273371544112918237964204402950489951501229924818744248325987005
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.11444225189555995512726040132922121413691271692149485109895288158993915789385
Short name T96
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.72 seconds
Started Nov 22 01:39:55 PM PST 23
Finished Nov 22 01:40:08 PM PST 23
Peak memory 201980 kb
Host smart-3353532b-e881-4ca9-af5f-0519e47ccbd0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=11444225189555995512726040132922121413691271692149485109895288158993915789385 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.11444225189555995512726040132922121413691271692149485109895288158993915789385
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.27659897902807284218079292909964941677030526847123657694358354661726360404305
Short name T842
Test name
Test status
Simulation time 27670935 ps
CPU time 1.2 seconds
Started Nov 22 01:40:06 PM PST 23
Finished Nov 22 01:40:08 PM PST 23
Peak memory 201908 kb
Host smart-e62728e0-f8fd-4e02-bc03-c1e56fd97ceb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27659897902807284218079292909964941677030526847123657694358354661726360404305 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.27659897902807284218079292909964941677030526847123657694358354661726360404305
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.104016191295004675715317095044720615095784528015416992165641652049024229501825
Short name T529
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.1 seconds
Started Nov 22 01:40:20 PM PST 23
Finished Nov 22 01:42:27 PM PST 23
Peak memory 203124 kb
Host smart-6b7d94e1-a21d-4b29-ba49-33b17b000aee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104016191295004675715317095044720615095784528015416992165641652049024229501825 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 1.xbar_stress_all.104016191295004675715317095044720615095784528015416992165641652049024229501825
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.101355620166951593428073479815539955289367321434334656202213015274616508620741
Short name T264
Test name
Test status
Simulation time 46147859184 ps
CPU time 108.47 seconds
Started Nov 22 01:40:24 PM PST 23
Finished Nov 22 01:42:15 PM PST 23
Peak memory 202996 kb
Host smart-e9b3dab7-7ca3-4e9b-b119-477da7db87ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=101355620166951593428073479815539955289367321434334656202213015274616508620741 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.101355620166951593428073479815539955289367321434334656202213015274616508620741
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.81810161453298218189250345561489966149300413216606194381185622268969388882043
Short name T753
Test name
Test status
Simulation time 13716459184 ps
CPU time 160.3 seconds
Started Nov 22 01:40:04 PM PST 23
Finished Nov 22 01:42:47 PM PST 23
Peak memory 205148 kb
Host smart-dab32ea3-3b08-487e-9ec3-9238113a04ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81810161453298218189250345561489966149300413216606194381185622268969388882043 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.81810161453298218189250345561489966149300413216606194381185622268969388882043
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.71235926510411799117396640743813527230416435628787816571883571936703738732878
Short name T299
Test name
Test status
Simulation time 13716459184 ps
CPU time 138.54 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:42:20 PM PST 23
Peak memory 206204 kb
Host smart-ad74cd88-6b0b-4516-9f57-4dc2632a9e07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=71235926510411799117396640743813527230416435628787816571883571936703738732878 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.71235926510411799117396640743813527230416435628787816571883571936703738732878
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.104465431842398979476993280920189971248714512485773626710692685331944420864882
Short name T548
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.08 seconds
Started Nov 22 01:40:09 PM PST 23
Finished Nov 22 01:40:21 PM PST 23
Peak memory 201960 kb
Host smart-50f1969a-2ec0-4fa0-bf23-d1cfcf9a0d67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104465431842398979476993280920189971248714512485773626710692685331944420864882 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 1.xbar_unmapped_addr.104465431842398979476993280920189971248714512485773626710692685331944420864882
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.8549983432512201943512275206258535940230558496104095833941257638439609720575
Short name T584
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.66 seconds
Started Nov 22 01:40:14 PM PST 23
Finished Nov 22 01:40:34 PM PST 23
Peak memory 202004 kb
Host smart-e22ab4ac-71ee-43eb-857a-67e1e9959476
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=8549983432512201943512275206258535940230558496104095833941257638439609720575 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.8549983432512201943512275206258535940230558496104095833941257638439609720575
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.80015941643580178946319746072373948721265397015252072609904941902753248078339
Short name T873
Test name
Test status
Simulation time 260306045935 ps
CPU time 334.45 seconds
Started Nov 22 01:40:09 PM PST 23
Finished Nov 22 01:45:44 PM PST 23
Peak memory 202960 kb
Host smart-42d43b86-2114-4959-8bfe-6f3d237c1c18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=80015941643580178946319746072373948721265397015252072609904941902753248078339 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.80015941643580178946319746072373948721265397015252072609904941902753248078339
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.12043280323004078957518865354667663783862091532065027898720259736966885110104
Short name T120
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.53 seconds
Started Nov 22 01:40:04 PM PST 23
Finished Nov 22 01:40:16 PM PST 23
Peak memory 201960 kb
Host smart-5673dd4f-b963-45d8-80dd-46cf3fd861a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12043280323004078957518865354667663783862091532065027898720259736966885110104 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.12043280323004078957518865354667663783862091532065027898720259736966885110104
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.94411974321781665009476903529689547330491007423958964502167894959405037762847
Short name T465
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.21 seconds
Started Nov 22 01:40:23 PM PST 23
Finished Nov 22 01:40:38 PM PST 23
Peak memory 201984 kb
Host smart-5873ca36-dcfa-4f27-a705-42afac2f734e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94411974321781665009476903529689547330491007423958964502167894959405037762847 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 10.xbar_error_random.94411974321781665009476903529689547330491007423958964502167894959405037762847
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.81359443215794962665422885631551906809253522347906445443919737830013076089618
Short name T430
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.72 seconds
Started Nov 22 01:41:27 PM PST 23
Finished Nov 22 01:41:42 PM PST 23
Peak memory 201972 kb
Host smart-49af08c6-3e24-4072-87d0-4e502687667c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81359443215794962665422885631551906809253522347906445443919737830013076089618 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 10.xbar_random.81359443215794962665422885631551906809253522347906445443919737830013076089618
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.58214808570958648712561522104998686820175676617371412135596794627354971262232
Short name T72
Test name
Test status
Simulation time 237556670935 ps
CPU time 188.73 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:43:35 PM PST 23
Peak memory 202000 kb
Host smart-75ae05f2-d230-4396-837a-444567923e2f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=58214808570958648712561522104998686820175676617371412135596794627354971262232 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 10.xbar_random_large_delays.58214808570958648712561522104998686820175676617371412135596794627354971262232
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.75398080585295256682440113228678737385145211940301567754736057005754953939950
Short name T666
Test name
Test status
Simulation time 160909483435 ps
CPU time 193.37 seconds
Started Nov 22 01:41:25 PM PST 23
Finished Nov 22 01:44:39 PM PST 23
Peak memory 201928 kb
Host smart-6b091ab6-b563-4117-ac45-a2e2f48668a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=75398080585295256682440113228678737385145211940301567754736057005754953939950 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.75398080585295256682440113228678737385145211940301567754736057005754953939950
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.32449854934917426957101259029069774295224822951712088360121795499463110158478
Short name T671
Test name
Test status
Simulation time 360920935 ps
CPU time 8.23 seconds
Started Nov 22 01:41:36 PM PST 23
Finished Nov 22 01:41:47 PM PST 23
Peak memory 201920 kb
Host smart-bb852010-28a7-440c-aa6e-2118de990f11
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32449854934917426957101259029069774295224822951712088360121795499463110158478 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.32449854934917426957101259029069774295224822951712088360121795499463110158478
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.47056169351047524897962464832690444070873028359866999539362217073836353634587
Short name T816
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.7 seconds
Started Nov 22 01:40:26 PM PST 23
Finished Nov 22 01:40:40 PM PST 23
Peak memory 202004 kb
Host smart-8337ad0f-58b8-4aaa-ac1f-2d5a95413385
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47056169351047524897962464832690444070873028359866999539362217073836353634587 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 10.xbar_same_source.47056169351047524897962464832690444070873028359866999539362217073836353634587
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.62186829742727489810270592970108428272584154239474934621753780940451114752371
Short name T463
Test name
Test status
Simulation time 331233435 ps
CPU time 1.63 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:41:23 PM PST 23
Peak memory 201904 kb
Host smart-790ed38c-c9b3-447e-b114-8eddc459bb1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62186829742727489810270592970108428272584154239474934621753780940451114752371 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 10.xbar_smoke.62186829742727489810270592970108428272584154239474934621753780940451114752371
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.90067954796681160693819994718932479176752682861184670377742276326705012921143
Short name T108
Test name
Test status
Simulation time 15405233435 ps
CPU time 13.04 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:41:51 PM PST 23
Peak memory 202000 kb
Host smart-6917324b-f1a0-4d97-86d8-2bfad1f038fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=90067954796681160693819994718932479176752682861184670377742276326705012921143 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.90067954796681160693819994718932479176752682861184670377742276326705012921143
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.79481285394914341939771752182460722411011721313241706585935197336848620077858
Short name T208
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.87 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:15 PM PST 23
Peak memory 202008 kb
Host smart-6a69cd38-15be-45b9-af1b-7e69d67b3fd7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=79481285394914341939771752182460722411011721313241706585935197336848620077858 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.79481285394914341939771752182460722411011721313241706585935197336848620077858
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.7293374272684459662507817659291017809263239757775081205821732387519850857751
Short name T160
Test name
Test status
Simulation time 27670935 ps
CPU time 1.17 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:41:38 PM PST 23
Peak memory 201908 kb
Host smart-b3618fdc-1609-4d49-9502-f4d6eada73e8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7293374272684459662507817659291017809263239757775081205821732387519850857751 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.7293374272684459662507817659291017809263239757775081205821732387519850857751
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.65856117464486482973319917748258375281953470055974494629050998246300749423123
Short name T201
Test name
Test status
Simulation time 46147859184 ps
CPU time 130.21 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:42:23 PM PST 23
Peak memory 203272 kb
Host smart-2894297f-5b27-476e-9cf6-057018b455cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65856117464486482973319917748258375281953470055974494629050998246300749423123 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 10.xbar_stress_all.65856117464486482973319917748258375281953470055974494629050998246300749423123
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.65348526229416807623249108491097928763883189695756335317362885132665305812139
Short name T367
Test name
Test status
Simulation time 46147859184 ps
CPU time 116.14 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:42:08 PM PST 23
Peak memory 204976 kb
Host smart-e56d7625-18f1-466f-958e-190dc4487b62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65348526229416807623249108491097928763883189695756335317362885132665305812139 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 10.xbar_stress_all_with_error.65348526229416807623249108491097928763883189695756335317362885132665305812139
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.14081892713576427355010586676068247942815582288576516560800396839501919799981
Short name T191
Test name
Test status
Simulation time 13716459184 ps
CPU time 162.89 seconds
Started Nov 22 01:40:19 PM PST 23
Finished Nov 22 01:43:03 PM PST 23
Peak memory 205184 kb
Host smart-2494c871-5615-4fde-9f06-d53487a99bff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14081892713576427355010586676068247942815582288576516560800396839501919799981 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.14081892713576427355010586676068247942815582288576516560800396839501919799981
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.69591374006450204715470044816774978315743993375293465726538330083557544314682
Short name T163
Test name
Test status
Simulation time 13716459184 ps
CPU time 136.79 seconds
Started Nov 22 01:40:26 PM PST 23
Finished Nov 22 01:42:44 PM PST 23
Peak memory 206164 kb
Host smart-87190add-2490-4a0b-b731-8ab75452f276
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69591374006450204715470044816774978315743993375293465726538330083557544314682 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.69591374006450204715470044816774978315743993375293465726538330083557544314682
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.64648991578929462364510778082858064532232487401580616792203963877102221572471
Short name T77
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.54 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:40:15 PM PST 23
Peak memory 201948 kb
Host smart-31589936-9b8c-4107-aa02-59396afad8ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64648991578929462364510778082858064532232487401580616792203963877102221572471 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 10.xbar_unmapped_addr.64648991578929462364510778082858064532232487401580616792203963877102221572471
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.49948520864885018460341069150608990149728847732640531536367658957628448100363
Short name T767
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.64 seconds
Started Nov 22 01:40:37 PM PST 23
Finished Nov 22 01:40:56 PM PST 23
Peak memory 201940 kb
Host smart-7db04937-e773-45e2-832d-13c048f92d2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49948520864885018460341069150608990149728847732640531536367658957628448100363 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.49948520864885018460341069150608990149728847732640531536367658957628448100363
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.54728741182523790984779970234892144823601443832970695206076029229477108365827
Short name T728
Test name
Test status
Simulation time 260306045935 ps
CPU time 331.05 seconds
Started Nov 22 01:40:59 PM PST 23
Finished Nov 22 01:46:32 PM PST 23
Peak memory 202896 kb
Host smart-df1c6c37-2c7f-4788-a94a-dd7e4e5883bf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=54728741182523790984779970234892144823601443832970695206076029229477108365827 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.54728741182523790984779970234892144823601443832970695206076029229477108365827
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.18660482480188132013352683428557709784113074199664183990613568617981913758893
Short name T282
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.33 seconds
Started Nov 22 01:40:36 PM PST 23
Finished Nov 22 01:40:48 PM PST 23
Peak memory 201852 kb
Host smart-60cd613b-2736-4199-b3bf-f19faf830435
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18660482480188132013352683428557709784113074199664183990613568617981913758893 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.18660482480188132013352683428557709784113074199664183990613568617981913758893
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.68418951669864900297618020660446198277826855681115252940361861179330573539672
Short name T474
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.73 seconds
Started Nov 22 01:40:31 PM PST 23
Finished Nov 22 01:40:45 PM PST 23
Peak memory 201944 kb
Host smart-7db3d387-cf39-47e9-97bd-b96493059076
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=68418951669864900297618020660446198277826855681115252940361861179330573539672 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 11.xbar_error_random.68418951669864900297618020660446198277826855681115252940361861179330573539672
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.100380974290421767071650361136652288374392299885864134338449427569463874610947
Short name T818
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.77 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:40:26 PM PST 23
Peak memory 201816 kb
Host smart-67b70619-6800-49a1-999f-1b7fd335953a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100380974290421767071650361136652288374392299885864134338449427569463874610947 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 11.xbar_random.100380974290421767071650361136652288374392299885864134338449427569463874610947
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.9398802396142712262853602573350063118352096758137412721202265294610157138190
Short name T896
Test name
Test status
Simulation time 237556670935 ps
CPU time 189.23 seconds
Started Nov 22 01:40:28 PM PST 23
Finished Nov 22 01:43:39 PM PST 23
Peak memory 202000 kb
Host smart-09a21dff-250b-477f-83a8-46ef7a34c86e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=9398802396142712262853602573350063118352096758137412721202265294610157138190 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 11.xbar_random_large_delays.9398802396142712262853602573350063118352096758137412721202265294610157138190
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.33666158530970582294231833430329714493864534225317762525949838688901223240334
Short name T4
Test name
Test status
Simulation time 160909483435 ps
CPU time 192.61 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:43:50 PM PST 23
Peak memory 201992 kb
Host smart-08bbe31b-1d92-4cd5-86c7-961f4c9342c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=33666158530970582294231833430329714493864534225317762525949838688901223240334 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.33666158530970582294231833430329714493864534225317762525949838688901223240334
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.63354364327162803727422876894814954341096258364527090279223445009431146513135
Short name T519
Test name
Test status
Simulation time 360920935 ps
CPU time 7.41 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:40:19 PM PST 23
Peak memory 201752 kb
Host smart-665eeabf-7600-42ad-b0be-032a59c2b061
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63354364327162803727422876894814954341096258364527090279223445009431146513135 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.63354364327162803727422876894814954341096258364527090279223445009431146513135
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.72700478322188527039182885766176628923040695388726275358975360827659249939761
Short name T154
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.22 seconds
Started Nov 22 01:41:10 PM PST 23
Finished Nov 22 01:41:23 PM PST 23
Peak memory 201988 kb
Host smart-a927ca1a-a0ed-42a4-87a3-9839bc8e3bca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72700478322188527039182885766176628923040695388726275358975360827659249939761 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 11.xbar_same_source.72700478322188527039182885766176628923040695388726275358975360827659249939761
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.6688982664243066514572826762017544843523727377425515873808673187694343779459
Short name T361
Test name
Test status
Simulation time 331233435 ps
CPU time 1.73 seconds
Started Nov 22 01:40:22 PM PST 23
Finished Nov 22 01:40:24 PM PST 23
Peak memory 201916 kb
Host smart-bbf9d3a6-3174-44ef-b050-c35bca4b33b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6688982664243066514572826762017544843523727377425515873808673187694343779459 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 11.xbar_smoke.6688982664243066514572826762017544843523727377425515873808673187694343779459
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.84136497838308917137281207636265240388214731244982752726334439497346959470053
Short name T428
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.88 seconds
Started Nov 22 01:40:19 PM PST 23
Finished Nov 22 01:40:34 PM PST 23
Peak memory 201948 kb
Host smart-298fa8db-6ecb-4670-bafc-69a8537f9d61
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=84136497838308917137281207636265240388214731244982752726334439497346959470053 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.84136497838308917137281207636265240388214731244982752726334439497346959470053
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.70827915997976222381478743252923661407856526182147267548725426261584348709988
Short name T144
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.88 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:40:39 PM PST 23
Peak memory 202004 kb
Host smart-c280f13c-be75-4788-b307-2a68688aa233
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=70827915997976222381478743252923661407856526182147267548725426261584348709988 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.70827915997976222381478743252923661407856526182147267548725426261584348709988
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.88309669923599275083509113652437143410337068151520161101913211367250941671784
Short name T777
Test name
Test status
Simulation time 27670935 ps
CPU time 1.2 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:40:28 PM PST 23
Peak memory 201948 kb
Host smart-8271120a-9915-4bec-8dd3-f39a3485208c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88309669923599275083509113652437143410337068151520161101913211367250941671784 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.88309669923599275083509113652437143410337068151520161101913211367250941671784
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.16386078646495010515797531206509263999336427622994920915674096841608857659228
Short name T276
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.25 seconds
Started Nov 22 01:41:12 PM PST 23
Finished Nov 22 01:43:19 PM PST 23
Peak memory 203108 kb
Host smart-2fefde92-8294-4739-8fff-f09508c9f89d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16386078646495010515797531206509263999336427622994920915674096841608857659228 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 11.xbar_stress_all.16386078646495010515797531206509263999336427622994920915674096841608857659228
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.10552700539710236065177864610701047779441921963849801327232547396074476803743
Short name T808
Test name
Test status
Simulation time 13716459184 ps
CPU time 163.4 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:43:20 PM PST 23
Peak memory 205180 kb
Host smart-a86da266-2bc0-4cdd-bb2a-33fb306ebfd2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10552700539710236065177864610701047779441921963849801327232547396074476803743 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.10552700539710236065177864610701047779441921963849801327232547396074476803743
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.96161500037619792718581962073435473356909970342443267027682110141636459351441
Short name T397
Test name
Test status
Simulation time 13716459184 ps
CPU time 138.15 seconds
Started Nov 22 01:40:27 PM PST 23
Finished Nov 22 01:42:47 PM PST 23
Peak memory 206244 kb
Host smart-84f4a2af-e241-40e5-8b2d-976e80127b4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96161500037619792718581962073435473356909970342443267027682110141636459351441 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.96161500037619792718581962073435473356909970342443267027682110141636459351441
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.112045950797386915082592500495783189344719570343366133302421257218361308077137
Short name T228
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.47 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:40:49 PM PST 23
Peak memory 202008 kb
Host smart-7a3a5e92-52f5-45ff-a117-355895b87ed7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112045950797386915082592500495783189344719570343366133302421257218361308077137 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 11.xbar_unmapped_addr.112045950797386915082592500495783189344719570343366133302421257218361308077137
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.49607096831515802818712212302739745825216509936333838640753183807981175017906
Short name T606
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.07 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:41:44 PM PST 23
Peak memory 201968 kb
Host smart-0a079e52-2268-4b01-9068-4056ad9cf9a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49607096831515802818712212302739745825216509936333838640753183807981175017906 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.49607096831515802818712212302739745825216509936333838640753183807981175017906
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.82503234110145365596688688284653339328704579926111229029433161798355646865879
Short name T253
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.68 seconds
Started Nov 22 01:41:31 PM PST 23
Finished Nov 22 01:41:43 PM PST 23
Peak memory 201968 kb
Host smart-0e88c4d4-6220-4b2c-934a-26af2d98d8eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=82503234110145365596688688284653339328704579926111229029433161798355646865879 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.82503234110145365596688688284653339328704579926111229029433161798355646865879
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.2443508142869158768852082703156375307072586320319195297585659863698405135303
Short name T344
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.11 seconds
Started Nov 22 01:41:50 PM PST 23
Finished Nov 22 01:42:06 PM PST 23
Peak memory 201840 kb
Host smart-6cf8dbf2-7186-424e-86b3-36b9427f57d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2443508142869158768852082703156375307072586320319195297585659863698405135303 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 12.xbar_error_random.2443508142869158768852082703156375307072586320319195297585659863698405135303
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.36899783440188964536389293683183160324085361147967325070569764592814554954680
Short name T871
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.24 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:41:31 PM PST 23
Peak memory 202004 kb
Host smart-54b5ae71-eeee-459f-a8b7-c38b23652d4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36899783440188964536389293683183160324085361147967325070569764592814554954680 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 12.xbar_random.36899783440188964536389293683183160324085361147967325070569764592814554954680
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.49241175155859510467109927652560032942783293105618296577734323129968210769112
Short name T411
Test name
Test status
Simulation time 237556670935 ps
CPU time 188.8 seconds
Started Nov 22 01:41:12 PM PST 23
Finished Nov 22 01:44:22 PM PST 23
Peak memory 201968 kb
Host smart-c0993853-428f-438d-a4b0-3432a019cac1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=49241175155859510467109927652560032942783293105618296577734323129968210769112 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 12.xbar_random_large_delays.49241175155859510467109927652560032942783293105618296577734323129968210769112
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.79146392990413667843325134532962026842308602963329753454610894395631358282761
Short name T60
Test name
Test status
Simulation time 160909483435 ps
CPU time 192.9 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:44:31 PM PST 23
Peak memory 201860 kb
Host smart-eaefddd8-4dd4-4053-82d0-8efb72f7403e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=79146392990413667843325134532962026842308602963329753454610894395631358282761 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.79146392990413667843325134532962026842308602963329753454610894395631358282761
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.88044915778348300247733040305997059719334883782884318672666952492425206619676
Short name T583
Test name
Test status
Simulation time 360920935 ps
CPU time 7.67 seconds
Started Nov 22 01:40:40 PM PST 23
Finished Nov 22 01:40:49 PM PST 23
Peak memory 201940 kb
Host smart-314285e0-4e65-451a-a609-0b9c21a42822
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88044915778348300247733040305997059719334883782884318672666952492425206619676 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.88044915778348300247733040305997059719334883782884318672666952492425206619676
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.28300268251648259668044192281657155117218477599941712500252505384815662813515
Short name T686
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.52 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:41:32 PM PST 23
Peak memory 201852 kb
Host smart-a738b651-ddf4-4de7-a11d-9d91c72db546
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28300268251648259668044192281657155117218477599941712500252505384815662813515 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 12.xbar_same_source.28300268251648259668044192281657155117218477599941712500252505384815662813515
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.25825102036953203822990340667239261408643620270371829704438115499521144378817
Short name T701
Test name
Test status
Simulation time 331233435 ps
CPU time 1.55 seconds
Started Nov 22 01:40:37 PM PST 23
Finished Nov 22 01:40:40 PM PST 23
Peak memory 201868 kb
Host smart-f2b69c8e-e089-454d-b5e2-0e22ea0b30ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25825102036953203822990340667239261408643620270371829704438115499521144378817 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 12.xbar_smoke.25825102036953203822990340667239261408643620270371829704438115499521144378817
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.107487957453710473501818735631720156420118528339079568966327082140671854955797
Short name T303
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.81 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:31 PM PST 23
Peak memory 201940 kb
Host smart-f82bf228-9ba3-4f7f-a68d-b948029ef2c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=107487957453710473501818735631720156420118528339079568966327082140671854955797 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.107487957453710473501818735631720156420118528339079568966327082140671854955797
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.60018655323522084130095041783258860220212974170517576516806905386456720942285
Short name T674
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.82 seconds
Started Nov 22 01:40:41 PM PST 23
Finished Nov 22 01:40:55 PM PST 23
Peak memory 201996 kb
Host smart-319d0cd8-51d4-4ac4-b6e4-a4369229f8a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=60018655323522084130095041783258860220212974170517576516806905386456720942285 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.60018655323522084130095041783258860220212974170517576516806905386456720942285
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.94618003609688425669810687183002359555186800116969372890844612022500698221855
Short name T723
Test name
Test status
Simulation time 27670935 ps
CPU time 1.16 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:20 PM PST 23
Peak memory 201880 kb
Host smart-61384a60-2c46-43a5-9ef6-c734ae516cb5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94618003609688425669810687183002359555186800116969372890844612022500698221855 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.94618003609688425669810687183002359555186800116969372890844612022500698221855
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.34769622184402536385165248885121033517867241723366603327689353900183770578564
Short name T275
Test name
Test status
Simulation time 46147859184 ps
CPU time 124.61 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:43:32 PM PST 23
Peak memory 203212 kb
Host smart-74f5e44b-c6be-4aa4-876e-e6dc2f944c38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34769622184402536385165248885121033517867241723366603327689353900183770578564 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 12.xbar_stress_all.34769622184402536385165248885121033517867241723366603327689353900183770578564
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.55220332641384434563389919694802669514512262802968321601154720260191979282928
Short name T317
Test name
Test status
Simulation time 46147859184 ps
CPU time 110.71 seconds
Started Nov 22 01:41:23 PM PST 23
Finished Nov 22 01:43:14 PM PST 23
Peak memory 204852 kb
Host smart-43cfbcb8-390e-4d3e-ae33-47086a47197a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55220332641384434563389919694802669514512262802968321601154720260191979282928 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 12.xbar_stress_all_with_error.55220332641384434563389919694802669514512262802968321601154720260191979282928
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.96232402231229146016887463472962992545660509771564832090200188657566263187811
Short name T704
Test name
Test status
Simulation time 13716459184 ps
CPU time 162.52 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:44:10 PM PST 23
Peak memory 205064 kb
Host smart-749a8d88-6e30-4607-bfb9-d66a1caf99dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96232402231229146016887463472962992545660509771564832090200188657566263187811 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.96232402231229146016887463472962992545660509771564832090200188657566263187811
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.67756699350785920363287360968210237926238029462157818759731445882183480460573
Short name T495
Test name
Test status
Simulation time 13716459184 ps
CPU time 140.36 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:44:05 PM PST 23
Peak memory 206300 kb
Host smart-dca3570a-4fd6-4d54-bf4c-28f6cd6d588c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=67756699350785920363287360968210237926238029462157818759731445882183480460573 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.67756699350785920363287360968210237926238029462157818759731445882183480460573
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.23630374199279427421801539055516619220966146470344195828143406550756949036706
Short name T835
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.97 seconds
Started Nov 22 01:41:50 PM PST 23
Finished Nov 22 01:42:03 PM PST 23
Peak memory 201856 kb
Host smart-cdb8856a-bc1b-48ef-a11b-75950dfc0251
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23630374199279427421801539055516619220966146470344195828143406550756949036706 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 12.xbar_unmapped_addr.23630374199279427421801539055516619220966146470344195828143406550756949036706
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.109355456233508728948762894086013034803026967760691268444527584267063496683413
Short name T898
Test name
Test status
Simulation time 4712795935 ps
CPU time 19.03 seconds
Started Nov 22 01:40:13 PM PST 23
Finished Nov 22 01:40:33 PM PST 23
Peak memory 202004 kb
Host smart-95aef8ab-9b8e-4450-b745-e2d2ead9f1f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=109355456233508728948762894086013034803026967760691268444527584267063496683413 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.109355456233508728948762894086013034803026967760691268444527584267063496683413
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.55860524552580708218144400959129375107844227343048660335289204237321738978409
Short name T243
Test name
Test status
Simulation time 260306045935 ps
CPU time 329.74 seconds
Started Nov 22 01:40:22 PM PST 23
Finished Nov 22 01:45:53 PM PST 23
Peak memory 203008 kb
Host smart-09962586-a93f-405c-8d46-be4e81f89ef4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=55860524552580708218144400959129375107844227343048660335289204237321738978409 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.55860524552580708218144400959129375107844227343048660335289204237321738978409
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.46246991327693722152177041135729994944798071001048478923666632142028041752692
Short name T476
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.43 seconds
Started Nov 22 01:40:14 PM PST 23
Finished Nov 22 01:40:25 PM PST 23
Peak memory 201864 kb
Host smart-176ec26f-4d38-42be-b8d1-b94911df0674
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46246991327693722152177041135729994944798071001048478923666632142028041752692 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.46246991327693722152177041135729994944798071001048478923666632142028041752692
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.14599087089143812339145801580128194659481905999008855736018306528701734586312
Short name T11
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.38 seconds
Started Nov 22 01:40:24 PM PST 23
Finished Nov 22 01:40:38 PM PST 23
Peak memory 201992 kb
Host smart-f8ce81aa-b3dd-4f50-80a4-c1f50f810db4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14599087089143812339145801580128194659481905999008855736018306528701734586312 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 13.xbar_error_random.14599087089143812339145801580128194659481905999008855736018306528701734586312
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.26001902213218947622549618912897347356486064869396732654350877929223767615612
Short name T416
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.81 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:40:24 PM PST 23
Peak memory 202004 kb
Host smart-d9884361-213d-4fc1-a4ca-b95fe30bba8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=26001902213218947622549618912897347356486064869396732654350877929223767615612 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 13.xbar_random.26001902213218947622549618912897347356486064869396732654350877929223767615612
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.35833810171400063324447714513828157890444841255887677207683398327696038390072
Short name T271
Test name
Test status
Simulation time 237556670935 ps
CPU time 186.46 seconds
Started Nov 22 01:40:24 PM PST 23
Finished Nov 22 01:43:32 PM PST 23
Peak memory 202012 kb
Host smart-b15af2e5-18ca-46a2-84d0-141deeb8d447
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=35833810171400063324447714513828157890444841255887677207683398327696038390072 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 13.xbar_random_large_delays.35833810171400063324447714513828157890444841255887677207683398327696038390072
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.10861191812105235282725620370749755463350017172478210155478855335502295267273
Short name T643
Test name
Test status
Simulation time 160909483435 ps
CPU time 194.93 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:43:26 PM PST 23
Peak memory 201988 kb
Host smart-b66745dd-5cc1-4718-be32-b7cf505fb520
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=10861191812105235282725620370749755463350017172478210155478855335502295267273 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.10861191812105235282725620370749755463350017172478210155478855335502295267273
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.7285961797636963962780477514476168435545821346077325695885301891204664752039
Short name T85
Test name
Test status
Simulation time 360920935 ps
CPU time 7.83 seconds
Started Nov 22 01:40:20 PM PST 23
Finished Nov 22 01:40:29 PM PST 23
Peak memory 201840 kb
Host smart-39987a47-53f8-4b58-ad65-6e0159fa0bbd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7285961797636963962780477514476168435545821346077325695885301891204664752039 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.7285961797636963962780477514476168435545821346077325695885301891204664752039
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.95740741837332108903785470174964312301877263891424489530990368649215676973823
Short name T188
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.79 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:40:22 PM PST 23
Peak memory 201992 kb
Host smart-0832fbae-3ea1-426f-a51e-ffa37824ba48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95740741837332108903785470174964312301877263891424489530990368649215676973823 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 13.xbar_same_source.95740741837332108903785470174964312301877263891424489530990368649215676973823
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.92105387571784457514642826472766598794141176573619610327229874310467654065958
Short name T322
Test name
Test status
Simulation time 331233435 ps
CPU time 1.57 seconds
Started Nov 22 01:41:24 PM PST 23
Finished Nov 22 01:41:26 PM PST 23
Peak memory 201960 kb
Host smart-489c7d33-e7fa-4c41-b790-ca161b419a94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92105387571784457514642826472766598794141176573619610327229874310467654065958 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 13.xbar_smoke.92105387571784457514642826472766598794141176573619610327229874310467654065958
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.104361419873020512772778611919390112341928344234674723839394622802429492674839
Short name T347
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.7 seconds
Started Nov 22 01:41:28 PM PST 23
Finished Nov 22 01:41:42 PM PST 23
Peak memory 201968 kb
Host smart-6ccf465b-08ed-4d9c-a266-d7ad3feb345e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=104361419873020512772778611919390112341928344234674723839394622802429492674839 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.104361419873020512772778611919390112341928344234674723839394622802429492674839
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.13973516903982460025003949982552239523271743160003107268360520529278485656874
Short name T97
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.87 seconds
Started Nov 22 01:40:10 PM PST 23
Finished Nov 22 01:40:24 PM PST 23
Peak memory 201976 kb
Host smart-675ad3cd-c80f-4198-b8da-6e4cf312c1b4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=13973516903982460025003949982552239523271743160003107268360520529278485656874 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.13973516903982460025003949982552239523271743160003107268360520529278485656874
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.90267006311589249051515229109323597158496851338404944265305604792699437727879
Short name T678
Test name
Test status
Simulation time 27670935 ps
CPU time 1.21 seconds
Started Nov 22 01:41:35 PM PST 23
Finished Nov 22 01:41:39 PM PST 23
Peak memory 201912 kb
Host smart-869006cb-486d-4505-a6e0-cbe088676a83
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90267006311589249051515229109323597158496851338404944265305604792699437727879 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.90267006311589249051515229109323597158496851338404944265305604792699437727879
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.111822343925453387781317577841137575607318095226859997948454036842698534672700
Short name T595
Test name
Test status
Simulation time 46147859184 ps
CPU time 128.61 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:42:22 PM PST 23
Peak memory 203224 kb
Host smart-5ef57cf3-ae37-4e89-853b-24292e6b2740
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111822343925453387781317577841137575607318095226859997948454036842698534672700 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 13.xbar_stress_all.111822343925453387781317577841137575607318095226859997948454036842698534672700
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.72314042194021027433973237243289256541808506315632573012854721759767877426467
Short name T185
Test name
Test status
Simulation time 46147859184 ps
CPU time 122.71 seconds
Started Nov 22 01:40:29 PM PST 23
Finished Nov 22 01:42:34 PM PST 23
Peak memory 204724 kb
Host smart-3351ec74-17cd-4649-ad6a-2908e7be4179
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72314042194021027433973237243289256541808506315632573012854721759767877426467 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 13.xbar_stress_all_with_error.72314042194021027433973237243289256541808506315632573012854721759767877426467
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.47039995440995522668798782941469253186905551672655070243015176063848150864676
Short name T308
Test name
Test status
Simulation time 13716459184 ps
CPU time 164.7 seconds
Started Nov 22 01:40:29 PM PST 23
Finished Nov 22 01:43:16 PM PST 23
Peak memory 204400 kb
Host smart-ebaca00c-f5f3-4e08-97cc-543bb2f7ce53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47039995440995522668798782941469253186905551672655070243015176063848150864676 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.47039995440995522668798782941469253186905551672655070243015176063848150864676
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1404373387220480235235738889898598464877474052879841783655495109819190827058
Short name T118
Test name
Test status
Simulation time 13716459184 ps
CPU time 137.92 seconds
Started Nov 22 01:40:30 PM PST 23
Finished Nov 22 01:42:50 PM PST 23
Peak memory 206204 kb
Host smart-1bae7515-1b98-4454-97ee-24e262d559eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1404373387220480235235738889898598464877474052879841783655495109819190827058 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.1404373387220480235235738889898598464877474052879841783655495109819190827058
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.72405782059876532099759983738534167004263245407805596971986760847518111679826
Short name T25
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.69 seconds
Started Nov 22 01:40:28 PM PST 23
Finished Nov 22 01:40:40 PM PST 23
Peak memory 201996 kb
Host smart-f15cdb56-bf23-476f-b54a-d00ed00e9056
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72405782059876532099759983738534167004263245407805596971986760847518111679826 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 13.xbar_unmapped_addr.72405782059876532099759983738534167004263245407805596971986760847518111679826
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.29695983725670811380812764443845817908052661425411337040328489105096404901595
Short name T374
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.1 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:40:31 PM PST 23
Peak memory 202036 kb
Host smart-134aeb77-1339-4f19-9213-87d75dfdf14b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29695983725670811380812764443845817908052661425411337040328489105096404901595 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.29695983725670811380812764443845817908052661425411337040328489105096404901595
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.35563871701856040791731340028070762769850368905373501783475365004163764994224
Short name T454
Test name
Test status
Simulation time 260306045935 ps
CPU time 341.71 seconds
Started Nov 22 01:40:28 PM PST 23
Finished Nov 22 01:46:11 PM PST 23
Peak memory 202928 kb
Host smart-0242630a-a0b7-434a-8fc2-260548eda5bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=35563871701856040791731340028070762769850368905373501783475365004163764994224 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.35563871701856040791731340028070762769850368905373501783475365004163764994224
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.47344801858938971925196305527346312346057479045820093049314898394160637244097
Short name T528
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.02 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:40:47 PM PST 23
Peak memory 201924 kb
Host smart-23d74b00-c24c-499b-a0c8-3478b11fc691
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47344801858938971925196305527346312346057479045820093049314898394160637244097 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.47344801858938971925196305527346312346057479045820093049314898394160637244097
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.62954906399465484459285703926563547325342768301061982319769136159867083297370
Short name T812
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.28 seconds
Started Nov 22 01:40:56 PM PST 23
Finished Nov 22 01:41:10 PM PST 23
Peak memory 201944 kb
Host smart-2f400235-591d-4e35-8d5b-84ab6a8fc2a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62954906399465484459285703926563547325342768301061982319769136159867083297370 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 14.xbar_error_random.62954906399465484459285703926563547325342768301061982319769136159867083297370
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.16078297654880914078788898673811090955067452649553618701517919494187075128820
Short name T40
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.98 seconds
Started Nov 22 01:40:04 PM PST 23
Finished Nov 22 01:40:20 PM PST 23
Peak memory 201952 kb
Host smart-8d1545d6-d856-46f2-ab14-276f3577931b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16078297654880914078788898673811090955067452649553618701517919494187075128820 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 14.xbar_random.16078297654880914078788898673811090955067452649553618701517919494187075128820
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.46494264601349360268476812155414865269303646958394695282187287506685477267366
Short name T70
Test name
Test status
Simulation time 237556670935 ps
CPU time 190.4 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:43:24 PM PST 23
Peak memory 202008 kb
Host smart-bca83ff9-b157-4230-930d-08cf294a2480
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=46494264601349360268476812155414865269303646958394695282187287506685477267366 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 14.xbar_random_large_delays.46494264601349360268476812155414865269303646958394695282187287506685477267366
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.66710433382832470941096614133904821238535697372260562488859636094365709541966
Short name T587
Test name
Test status
Simulation time 160909483435 ps
CPU time 190.26 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:43:24 PM PST 23
Peak memory 201816 kb
Host smart-b632067b-1882-4f18-9a98-a286880406bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=66710433382832470941096614133904821238535697372260562488859636094365709541966 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.66710433382832470941096614133904821238535697372260562488859636094365709541966
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.94321734279133328317638863664721789581560659940349428548179733835381637529758
Short name T759
Test name
Test status
Simulation time 360920935 ps
CPU time 8.04 seconds
Started Nov 22 01:40:44 PM PST 23
Finished Nov 22 01:40:52 PM PST 23
Peak memory 201868 kb
Host smart-d53d9535-6884-4a0f-ab5d-a3517c0a16b7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94321734279133328317638863664721789581560659940349428548179733835381637529758 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.94321734279133328317638863664721789581560659940349428548179733835381637529758
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.102411879456253769095645548961316841492706840562904676923016892284369341441017
Short name T433
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.06 seconds
Started Nov 22 01:40:19 PM PST 23
Finished Nov 22 01:40:33 PM PST 23
Peak memory 202016 kb
Host smart-1505afac-a72f-42d6-9651-c14d3db81a4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102411879456253769095645548961316841492706840562904676923016892284369341441017 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 14.xbar_same_source.102411879456253769095645548961316841492706840562904676923016892284369341441017
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.15912297552849863076027151465069273338274380939104646392007618232632722341471
Short name T498
Test name
Test status
Simulation time 331233435 ps
CPU time 1.59 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:40:28 PM PST 23
Peak memory 201940 kb
Host smart-ee547e5a-f1fa-4190-89c0-9b8f839fc0ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15912297552849863076027151465069273338274380939104646392007618232632722341471 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 14.xbar_smoke.15912297552849863076027151465069273338274380939104646392007618232632722341471
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.52805657523828559866855547979798857206021697607531727614312979199935462693720
Short name T500
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.8 seconds
Started Nov 22 01:41:10 PM PST 23
Finished Nov 22 01:41:24 PM PST 23
Peak memory 201888 kb
Host smart-2d3e75bb-bb68-478b-9cb4-2d5dd2bd47f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=52805657523828559866855547979798857206021697607531727614312979199935462693720 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.52805657523828559866855547979798857206021697607531727614312979199935462693720
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.97988784066056485271258932296977415384269017831641310951300289424636014459056
Short name T429
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.96 seconds
Started Nov 22 01:41:01 PM PST 23
Finished Nov 22 01:41:15 PM PST 23
Peak memory 201888 kb
Host smart-219e6f4c-d511-469b-bcad-9a8130c7fef0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=97988784066056485271258932296977415384269017831641310951300289424636014459056 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.97988784066056485271258932296977415384269017831641310951300289424636014459056
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.112984379635111359407541737313704029696583379148788134327007681104687517458852
Short name T142
Test name
Test status
Simulation time 27670935 ps
CPU time 1.14 seconds
Started Nov 22 01:40:24 PM PST 23
Finished Nov 22 01:40:26 PM PST 23
Peak memory 201904 kb
Host smart-d91a902e-102f-48c9-acc4-e2677aeff264
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112984379635111359407541737313704029696583379148788134327007681104687517458852 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.112984379635111359407541737313704029696583379148788134327007681104687517458852
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.112431587345484293241704605246158341306363797377200727743025284082186050519551
Short name T407
Test name
Test status
Simulation time 46147859184 ps
CPU time 121.17 seconds
Started Nov 22 01:40:46 PM PST 23
Finished Nov 22 01:42:48 PM PST 23
Peak memory 203124 kb
Host smart-72492295-0b03-45ad-8fcc-968712952fca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112431587345484293241704605246158341306363797377200727743025284082186050519551 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 14.xbar_stress_all.112431587345484293241704605246158341306363797377200727743025284082186050519551
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.59838057998320450459112637159985109180233668867736795071187078002182845553542
Short name T764
Test name
Test status
Simulation time 46147859184 ps
CPU time 123.78 seconds
Started Nov 22 01:40:10 PM PST 23
Finished Nov 22 01:42:15 PM PST 23
Peak memory 204912 kb
Host smart-f01c4def-46a9-4ab8-8545-d8aa5f8c4530
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59838057998320450459112637159985109180233668867736795071187078002182845553542 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 14.xbar_stress_all_with_error.59838057998320450459112637159985109180233668867736795071187078002182845553542
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.13066965204849011060893585677800974131243031793322445066222413968679936510584
Short name T413
Test name
Test status
Simulation time 13716459184 ps
CPU time 153.37 seconds
Started Nov 22 01:40:46 PM PST 23
Finished Nov 22 01:43:20 PM PST 23
Peak memory 205076 kb
Host smart-fbfdc8fd-2feb-49ed-a82b-b407392ea3cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13066965204849011060893585677800974131243031793322445066222413968679936510584 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.13066965204849011060893585677800974131243031793322445066222413968679936510584
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.103955915761898054791981482270404392533736328453366230339800863433110218140820
Short name T376
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.48 seconds
Started Nov 22 01:40:18 PM PST 23
Finished Nov 22 01:40:31 PM PST 23
Peak memory 201988 kb
Host smart-40cd56e8-04c8-46bb-b1a4-a179481358a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103955915761898054791981482270404392533736328453366230339800863433110218140820 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 14.xbar_unmapped_addr.103955915761898054791981482270404392533736328453366230339800863433110218140820
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.78924139743415114955720981401717187134128440937844184498555991132343034978086
Short name T673
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.21 seconds
Started Nov 22 01:40:20 PM PST 23
Finished Nov 22 01:40:39 PM PST 23
Peak memory 201908 kb
Host smart-20921466-ea78-4ad7-8911-71dd5cde60f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78924139743415114955720981401717187134128440937844184498555991132343034978086 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.78924139743415114955720981401717187134128440937844184498555991132343034978086
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.69719137193778731047769830310149874691973145350353451857316999876606462072429
Short name T81
Test name
Test status
Simulation time 260306045935 ps
CPU time 340.26 seconds
Started Nov 22 01:40:23 PM PST 23
Finished Nov 22 01:46:04 PM PST 23
Peak memory 202784 kb
Host smart-2896bbcb-0c8a-4f23-b79e-0aa099e601c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=69719137193778731047769830310149874691973145350353451857316999876606462072429 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.69719137193778731047769830310149874691973145350353451857316999876606462072429
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.20548672373934577548958368651066473247708109839145252332224636443149111765532
Short name T703
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.01 seconds
Started Nov 22 01:40:31 PM PST 23
Finished Nov 22 01:40:43 PM PST 23
Peak memory 201916 kb
Host smart-ee529ca4-da07-4f37-a6f8-8c747dd88f13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20548672373934577548958368651066473247708109839145252332224636443149111765532 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.20548672373934577548958368651066473247708109839145252332224636443149111765532
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.98978394058272144812956574009896996567524594159518887959315599969103233062274
Short name T387
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.31 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:40:40 PM PST 23
Peak memory 202080 kb
Host smart-87b4614e-7373-488e-a577-e4b4d899a3d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98978394058272144812956574009896996567524594159518887959315599969103233062274 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 15.xbar_error_random.98978394058272144812956574009896996567524594159518887959315599969103233062274
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.1279643976004752513509143996143318306027908370235112791065839553140878380864
Short name T230
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.89 seconds
Started Nov 22 01:40:23 PM PST 23
Finished Nov 22 01:40:38 PM PST 23
Peak memory 201716 kb
Host smart-9301a2bb-6130-4a20-8f95-c2cc7ef79185
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1279643976004752513509143996143318306027908370235112791065839553140878380864 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 15.xbar_random.1279643976004752513509143996143318306027908370235112791065839553140878380864
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.98736386375106213461893824460976161381213385945709014525412999942881563956901
Short name T661
Test name
Test status
Simulation time 237556670935 ps
CPU time 190.17 seconds
Started Nov 22 01:40:37 PM PST 23
Finished Nov 22 01:43:49 PM PST 23
Peak memory 201944 kb
Host smart-019763d1-dfa3-4e0d-be9c-87d8e4897834
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=98736386375106213461893824460976161381213385945709014525412999942881563956901 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 15.xbar_random_large_delays.98736386375106213461893824460976161381213385945709014525412999942881563956901
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.100598126385810488449857972044167783103181376824936659196367792095864277666092
Short name T605
Test name
Test status
Simulation time 160909483435 ps
CPU time 195.1 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:44:36 PM PST 23
Peak memory 201996 kb
Host smart-e6e583f0-0a3c-4559-baa3-ccda5c2b6bcc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=100598126385810488449857972044167783103181376824936659196367792095864277666092 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.100598126385810488449857972044167783103181376824936659196367792095864277666092
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.36995515171550360038819787947490680893893303701651132895009225978971708168655
Short name T101
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.11 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:41:29 PM PST 23
Peak memory 201924 kb
Host smart-d9e0c13c-d3c8-4a60-85b3-d45199e9cc3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36995515171550360038819787947490680893893303701651132895009225978971708168655 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 15.xbar_same_source.36995515171550360038819787947490680893893303701651132895009225978971708168655
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.18448166097243504343114195835630615320716318632054533851682644709424917762520
Short name T138
Test name
Test status
Simulation time 331233435 ps
CPU time 1.56 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:41:17 PM PST 23
Peak memory 201868 kb
Host smart-794791aa-94c2-438b-a1be-c6f1e8444a50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18448166097243504343114195835630615320716318632054533851682644709424917762520 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 15.xbar_smoke.18448166097243504343114195835630615320716318632054533851682644709424917762520
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.322680328005396047712576187355416242824340371227183716902868425918017024191
Short name T406
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.82 seconds
Started Nov 22 01:40:09 PM PST 23
Finished Nov 22 01:40:23 PM PST 23
Peak memory 202004 kb
Host smart-097a54d1-94cc-4256-bd37-720a94bbb908
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=322680328005396047712576187355416242824340371227183716902868425918017024191 -assert nopostproc +UVM_TE
STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.322680328005396047712576187355416242824340371227183716902868425918017024191
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.34863019862715191170044145788904687047767627592628138724368348358430714946832
Short name T832
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.62 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:32 PM PST 23
Peak memory 201940 kb
Host smart-ddb583a9-34d5-4b38-a06d-5f42375c795c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=34863019862715191170044145788904687047767627592628138724368348358430714946832 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.34863019862715191170044145788904687047767627592628138724368348358430714946832
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.19190954098308824078040711138232632404656139002953113013928713368166517339917
Short name T283
Test name
Test status
Simulation time 27670935 ps
CPU time 1.19 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:40:38 PM PST 23
Peak memory 201908 kb
Host smart-ce0a72b7-3795-4eef-bd9d-78c2c3efba78
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19190954098308824078040711138232632404656139002953113013928713368166517339917 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.19190954098308824078040711138232632404656139002953113013928713368166517339917
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.97537703897528483530983356364123600308733004368303631076918171077281292237240
Short name T670
Test name
Test status
Simulation time 46147859184 ps
CPU time 125.15 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:43:21 PM PST 23
Peak memory 203152 kb
Host smart-d3afdacb-a0b7-4883-9fd5-db1a9af09962
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=97537703897528483530983356364123600308733004368303631076918171077281292237240 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 15.xbar_stress_all.97537703897528483530983356364123600308733004368303631076918171077281292237240
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.29112792291488392975204115316676029657757887281876613206216819658798552836646
Short name T504
Test name
Test status
Simulation time 46147859184 ps
CPU time 111.79 seconds
Started Nov 22 01:40:26 PM PST 23
Finished Nov 22 01:42:19 PM PST 23
Peak memory 204948 kb
Host smart-6bceb372-2c6d-4d95-9fdb-80398da2eaf2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29112792291488392975204115316676029657757887281876613206216819658798552836646 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 15.xbar_stress_all_with_error.29112792291488392975204115316676029657757887281876613206216819658798552836646
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.69954496646927716966226110723608872028228443173284385998845507004037532406218
Short name T557
Test name
Test status
Simulation time 13716459184 ps
CPU time 157.8 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:43:04 PM PST 23
Peak memory 205172 kb
Host smart-d19fa08a-06ec-4fd7-addf-5d90b08dc32c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69954496646927716966226110723608872028228443173284385998845507004037532406218 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.69954496646927716966226110723608872028228443173284385998845507004037532406218
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.98256270339749547245401695607705755607617013067464292509793169575827535109818
Short name T388
Test name
Test status
Simulation time 13716459184 ps
CPU time 133.06 seconds
Started Nov 22 01:41:13 PM PST 23
Finished Nov 22 01:43:28 PM PST 23
Peak memory 206272 kb
Host smart-80f74e01-a501-40f3-b7fd-c96a18fba726
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98256270339749547245401695607705755607617013067464292509793169575827535109818 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.98256270339749547245401695607705755607617013067464292509793169575827535109818
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.89882181496560619751377737472370114536700151710374247899131891086322168130301
Short name T837
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.46 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:40:24 PM PST 23
Peak memory 202040 kb
Host smart-72b707c2-ca0e-4aa6-a8f1-e0342707ee84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=89882181496560619751377737472370114536700151710374247899131891086322168130301 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 15.xbar_unmapped_addr.89882181496560619751377737472370114536700151710374247899131891086322168130301
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.797527115376593184275519747599551673689888213126203130362343207011782203767
Short name T52
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.17 seconds
Started Nov 22 01:41:23 PM PST 23
Finished Nov 22 01:41:41 PM PST 23
Peak memory 202000 kb
Host smart-640de375-e708-4fab-bf59-cb3ab6dbc8f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=797527115376593184275519747599551673689888213126203130362343207011782203767 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 16.xbar_access_same_device.797527115376593184275519747599551673689888213126203130362343207011782203767
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.53164565448460309134078174638919587706233975752292807767997386076165906424987
Short name T269
Test name
Test status
Simulation time 260306045935 ps
CPU time 329.64 seconds
Started Nov 22 01:41:28 PM PST 23
Finished Nov 22 01:46:59 PM PST 23
Peak memory 202956 kb
Host smart-775a5fff-ef1a-4367-9eda-adb0d7977ace
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=53164565448460309134078174638919587706233975752292807767997386076165906424987 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.53164565448460309134078174638919587706233975752292807767997386076165906424987
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.50368889589708880621183934821758490510838997555870115974020010779521634086151
Short name T236
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.07 seconds
Started Nov 22 01:41:28 PM PST 23
Finished Nov 22 01:41:40 PM PST 23
Peak memory 201952 kb
Host smart-0a7867a8-32fb-4874-840f-bbc259403468
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=50368889589708880621183934821758490510838997555870115974020010779521634086151 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.50368889589708880621183934821758490510838997555870115974020010779521634086151
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.98240491102927764925336864852137096168565706243538046499211262249909538514228
Short name T657
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.35 seconds
Started Nov 22 01:40:34 PM PST 23
Finished Nov 22 01:40:48 PM PST 23
Peak memory 201960 kb
Host smart-fdcd00f0-5dc0-4c41-bbb9-412972c8d89a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98240491102927764925336864852137096168565706243538046499211262249909538514228 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 16.xbar_error_random.98240491102927764925336864852137096168565706243538046499211262249909538514228
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.50726315971927920555127551550730898507401890038105073198634123748293597562259
Short name T291
Test name
Test status
Simulation time 4923670935 ps
CPU time 15.09 seconds
Started Nov 22 01:41:28 PM PST 23
Finished Nov 22 01:41:44 PM PST 23
Peak memory 201988 kb
Host smart-f3d30f54-88d7-40dc-a4ee-a45f2cdacc10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=50726315971927920555127551550730898507401890038105073198634123748293597562259 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 16.xbar_random.50726315971927920555127551550730898507401890038105073198634123748293597562259
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.86305157700833003154842703976497813463013413121187154305853306253054212166223
Short name T338
Test name
Test status
Simulation time 237556670935 ps
CPU time 189.34 seconds
Started Nov 22 01:40:28 PM PST 23
Finished Nov 22 01:43:39 PM PST 23
Peak memory 201912 kb
Host smart-4f0c529d-e2fb-43aa-99b4-e8a76d4abc50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=86305157700833003154842703976497813463013413121187154305853306253054212166223 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 16.xbar_random_large_delays.86305157700833003154842703976497813463013413121187154305853306253054212166223
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.114109544315428624736129764682567710622834110798498153136609468053606875764429
Short name T384
Test name
Test status
Simulation time 160909483435 ps
CPU time 195.4 seconds
Started Nov 22 01:40:34 PM PST 23
Finished Nov 22 01:43:50 PM PST 23
Peak memory 201988 kb
Host smart-838c9cf9-d02a-494f-9dd9-357ee1f83019
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=114109544315428624736129764682567710622834110798498153136609468053606875764429 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.114109544315428624736129764682567710622834110798498153136609468053606875764429
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.42258675596670632568148093230779475979108452164767212730057013428407131838957
Short name T492
Test name
Test status
Simulation time 360920935 ps
CPU time 7.69 seconds
Started Nov 22 01:40:24 PM PST 23
Finished Nov 22 01:40:33 PM PST 23
Peak memory 201940 kb
Host smart-ec4c1756-dafb-4a60-af83-4e20d5421d60
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42258675596670632568148093230779475979108452164767212730057013428407131838957 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.42258675596670632568148093230779475979108452164767212730057013428407131838957
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.44912270061634985277743728900174046436024962428117827477677984365670078059796
Short name T854
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.42 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:41:45 PM PST 23
Peak memory 201984 kb
Host smart-80a19ed7-00a2-4283-8533-5ce2aa858592
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44912270061634985277743728900174046436024962428117827477677984365670078059796 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 16.xbar_same_source.44912270061634985277743728900174046436024962428117827477677984365670078059796
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.75434272687885408500027377337899410768214378153229946964450558465106779152923
Short name T487
Test name
Test status
Simulation time 331233435 ps
CPU time 1.53 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:21 PM PST 23
Peak memory 201872 kb
Host smart-51e4a592-ed4e-4b31-8056-3ba4478d4437
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=75434272687885408500027377337899410768214378153229946964450558465106779152923 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 16.xbar_smoke.75434272687885408500027377337899410768214378153229946964450558465106779152923
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.89058021393531435703423484873977858886529580384733355498203296370171842094125
Short name T199
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.75 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:41:35 PM PST 23
Peak memory 201916 kb
Host smart-ce31d3ad-b89b-44b5-b9b3-bc3c6f8a02c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=89058021393531435703423484873977858886529580384733355498203296370171842094125 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.89058021393531435703423484873977858886529580384733355498203296370171842094125
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.96534199409633760298223346614526996449997694446829693556107540210525024218729
Short name T552
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.91 seconds
Started Nov 22 01:40:39 PM PST 23
Finished Nov 22 01:40:53 PM PST 23
Peak memory 201804 kb
Host smart-30221185-95b0-47cd-a6cb-c0b905c18faf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=96534199409633760298223346614526996449997694446829693556107540210525024218729 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.96534199409633760298223346614526996449997694446829693556107540210525024218729
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.51118666390762409927712094318919608363549607099935849339421065050241310646223
Short name T467
Test name
Test status
Simulation time 27670935 ps
CPU time 1.17 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:20 PM PST 23
Peak memory 201912 kb
Host smart-6233fa57-6073-4461-994b-2d29c117b31f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51118666390762409927712094318919608363549607099935849339421065050241310646223 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.51118666390762409927712094318919608363549607099935849339421065050241310646223
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.26026481748666360846175748311609391011117452547229446231550218879675168776217
Short name T624
Test name
Test status
Simulation time 46147859184 ps
CPU time 127.21 seconds
Started Nov 22 01:40:45 PM PST 23
Finished Nov 22 01:42:53 PM PST 23
Peak memory 203212 kb
Host smart-c5c7318c-61df-434d-b4ed-c6cdc2ffc382
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=26026481748666360846175748311609391011117452547229446231550218879675168776217 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 16.xbar_stress_all.26026481748666360846175748311609391011117452547229446231550218879675168776217
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.85291913213333819688635164273353170650460024711630664206730863600538681296201
Short name T203
Test name
Test status
Simulation time 46147859184 ps
CPU time 115.36 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:43:17 PM PST 23
Peak memory 204844 kb
Host smart-e220617d-c259-4df3-9880-d7b50ed16e4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85291913213333819688635164273353170650460024711630664206730863600538681296201 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 16.xbar_stress_all_with_error.85291913213333819688635164273353170650460024711630664206730863600538681296201
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.112249098060549909824410301032866082836566149401293530206112667644857177163850
Short name T866
Test name
Test status
Simulation time 13716459184 ps
CPU time 161.79 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:44:19 PM PST 23
Peak memory 205148 kb
Host smart-46ed390f-1564-43f9-a277-e8a5bc6d2e77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112249098060549909824410301032866082836566149401293530206112667644857177163850 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.112249098060549909824410301032866082836566149401293530206112667644857177163850
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.98780842499860107860445562697163900793303113885717196377502513422432833686113
Short name T843
Test name
Test status
Simulation time 13716459184 ps
CPU time 139.66 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:42:47 PM PST 23
Peak memory 206128 kb
Host smart-f91afcc8-e40b-46b7-b73e-de43c3b79f09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98780842499860107860445562697163900793303113885717196377502513422432833686113 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.98780842499860107860445562697163900793303113885717196377502513422432833686113
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.86055041986128577187912548903534604771678457939955791034185520502346290970537
Short name T489
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.94 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:41:32 PM PST 23
Peak memory 201996 kb
Host smart-8a628d1d-e7fa-4f7c-9921-222e491826ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86055041986128577187912548903534604771678457939955791034185520502346290970537 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 16.xbar_unmapped_addr.86055041986128577187912548903534604771678457939955791034185520502346290970537
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.98454110787026282842623986101708446220596551436535988734924432739795736317197
Short name T695
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.44 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:35 PM PST 23
Peak memory 202004 kb
Host smart-581879ef-5ecd-4df4-be4b-6fa49099921b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98454110787026282842623986101708446220596551436535988734924432739795736317197 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.98454110787026282842623986101708446220596551436535988734924432739795736317197
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.64348571565344084745673317677414864151172512332157364248076653486482862504909
Short name T690
Test name
Test status
Simulation time 260306045935 ps
CPU time 336.55 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:46:54 PM PST 23
Peak memory 203020 kb
Host smart-15b99018-d996-4b69-869d-f1fa580ac593
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=64348571565344084745673317677414864151172512332157364248076653486482862504909 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.64348571565344084745673317677414864151172512332157364248076653486482862504909
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.89829452553407990718419433012473704574620710294240013987768613891326540240392
Short name T591
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.33 seconds
Started Nov 22 01:41:13 PM PST 23
Finished Nov 22 01:41:25 PM PST 23
Peak memory 201968 kb
Host smart-facfcafc-6bd0-4181-83ea-073c218904ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=89829452553407990718419433012473704574620710294240013987768613891326540240392 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.89829452553407990718419433012473704574620710294240013987768613891326540240392
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.53216061874299789063454787151468610184785557715621744829564690746209703983505
Short name T827
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.17 seconds
Started Nov 22 01:40:37 PM PST 23
Finished Nov 22 01:40:52 PM PST 23
Peak memory 201928 kb
Host smart-c61038b6-8088-4bcb-9285-90fe96b1d858
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53216061874299789063454787151468610184785557715621744829564690746209703983505 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 17.xbar_error_random.53216061874299789063454787151468610184785557715621744829564690746209703983505
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.23388787844235190786888993967575781461790174278587540973608246675579288188857
Short name T738
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.91 seconds
Started Nov 22 01:41:08 PM PST 23
Finished Nov 22 01:41:23 PM PST 23
Peak memory 201972 kb
Host smart-6b2ca83c-d16c-4966-8a7a-15f36abf5e6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23388787844235190786888993967575781461790174278587540973608246675579288188857 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 17.xbar_random.23388787844235190786888993967575781461790174278587540973608246675579288188857
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.6365520975563261711125055010945233258461880281893811750653272850308626178031
Short name T45
Test name
Test status
Simulation time 237556670935 ps
CPU time 189.38 seconds
Started Nov 22 01:40:58 PM PST 23
Finished Nov 22 01:44:08 PM PST 23
Peak memory 202020 kb
Host smart-9058d561-de82-475e-a938-24f7d4ae4312
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=6365520975563261711125055010945233258461880281893811750653272850308626178031 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 17.xbar_random_large_delays.6365520975563261711125055010945233258461880281893811750653272850308626178031
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.17432792846442286535511725712723076515708084529357346063902169951801042096817
Short name T158
Test name
Test status
Simulation time 160909483435 ps
CPU time 189.71 seconds
Started Nov 22 01:40:59 PM PST 23
Finished Nov 22 01:44:10 PM PST 23
Peak memory 201816 kb
Host smart-1eaedaf1-50a9-4b57-ab33-f84d1e5494d9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=17432792846442286535511725712723076515708084529357346063902169951801042096817 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.17432792846442286535511725712723076515708084529357346063902169951801042096817
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.76667256570309867716323760312489125700021112514946682165739357838404779539230
Short name T17
Test name
Test status
Simulation time 360920935 ps
CPU time 7.58 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:40:45 PM PST 23
Peak memory 201852 kb
Host smart-79c6cb41-7afd-4af2-a49b-16740f67787e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76667256570309867716323760312489125700021112514946682165739357838404779539230 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.76667256570309867716323760312489125700021112514946682165739357838404779539230
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.106413437747726093404931560154810218292362913072004435568173178213759756404550
Short name T400
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.04 seconds
Started Nov 22 01:40:30 PM PST 23
Finished Nov 22 01:40:44 PM PST 23
Peak memory 201908 kb
Host smart-33d56342-81b2-42be-861d-025fc9108558
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=106413437747726093404931560154810218292362913072004435568173178213759756404550 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 17.xbar_same_source.106413437747726093404931560154810218292362913072004435568173178213759756404550
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.16581954451214200634484923361883187436459628727063283478746137042314012794627
Short name T720
Test name
Test status
Simulation time 331233435 ps
CPU time 1.68 seconds
Started Nov 22 01:41:50 PM PST 23
Finished Nov 22 01:41:54 PM PST 23
Peak memory 201904 kb
Host smart-d3e11226-6d3b-4d18-8bfd-7b0c1fdaf612
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16581954451214200634484923361883187436459628727063283478746137042314012794627 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 17.xbar_smoke.16581954451214200634484923361883187436459628727063283478746137042314012794627
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.36724092868702302328580441812553937710954909760563722592755184194115580461946
Short name T162
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.84 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:42:01 PM PST 23
Peak memory 201872 kb
Host smart-37e519bf-3b62-41ed-ba0f-80c89cbd7af6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=36724092868702302328580441812553937710954909760563722592755184194115580461946 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.36724092868702302328580441812553937710954909760563722592755184194115580461946
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.67642171406259820108931726892887097346044871560947790151516978867695263097831
Short name T198
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.6 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:31 PM PST 23
Peak memory 202012 kb
Host smart-0c8d4b83-754e-46a5-9a42-6523259dbfab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=67642171406259820108931726892887097346044871560947790151516978867695263097831 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.67642171406259820108931726892887097346044871560947790151516978867695263097831
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.86316443347192444629811164385022172379683231160305190560163036816825030855623
Short name T27
Test name
Test status
Simulation time 27670935 ps
CPU time 1.16 seconds
Started Nov 22 01:40:37 PM PST 23
Finished Nov 22 01:40:40 PM PST 23
Peak memory 201908 kb
Host smart-5b0aee3c-4fec-499e-b609-2e2232969544
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86316443347192444629811164385022172379683231160305190560163036816825030855623 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.86316443347192444629811164385022172379683231160305190560163036816825030855623
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.87320682650005088467677342331291763715454234264555249837461386485864140512096
Short name T579
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.87 seconds
Started Nov 22 01:41:12 PM PST 23
Finished Nov 22 01:43:20 PM PST 23
Peak memory 203212 kb
Host smart-531055cb-69b6-4ec7-afad-89343058c7c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87320682650005088467677342331291763715454234264555249837461386485864140512096 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 17.xbar_stress_all.87320682650005088467677342331291763715454234264555249837461386485864140512096
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.27150201478677421698873441444462055509415368452889280386543497882430816802474
Short name T293
Test name
Test status
Simulation time 46147859184 ps
CPU time 116.06 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:43:17 PM PST 23
Peak memory 204880 kb
Host smart-688cd278-7d40-4eb1-a536-266d0dc5d66d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27150201478677421698873441444462055509415368452889280386543497882430816802474 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 17.xbar_stress_all_with_error.27150201478677421698873441444462055509415368452889280386543497882430816802474
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.57685097336944005538520489516028010791161429125922095081245741799923227226857
Short name T499
Test name
Test status
Simulation time 13716459184 ps
CPU time 161.69 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:44:02 PM PST 23
Peak memory 205156 kb
Host smart-ff964132-0e7f-4208-ad12-ab6c6c3e495f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57685097336944005538520489516028010791161429125922095081245741799923227226857 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.57685097336944005538520489516028010791161429125922095081245741799923227226857
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.100118972760195321559444038277815554653646573667026664806811550498845078686665
Short name T597
Test name
Test status
Simulation time 13716459184 ps
CPU time 135.91 seconds
Started Nov 22 01:41:23 PM PST 23
Finished Nov 22 01:43:40 PM PST 23
Peak memory 206212 kb
Host smart-24098c8d-8287-4b57-abc3-37db8444eb26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100118972760195321559444038277815554653646573667026664806811550498845078686665 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.100118972760195321559444038277815554653646573667026664806811550498845078686665
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.7860702086385161961141154238477914749848790475668718943937468856407213724922
Short name T840
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.45 seconds
Started Nov 22 01:41:13 PM PST 23
Finished Nov 22 01:41:26 PM PST 23
Peak memory 201992 kb
Host smart-33bd40f5-ee3f-4ccb-ab2e-e92553242150
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=7860702086385161961141154238477914749848790475668718943937468856407213724922 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 17.xbar_unmapped_addr.7860702086385161961141154238477914749848790475668718943937468856407213724922
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.28646625338928949571161213063490958412620940763548378053921519882660221279902
Short name T266
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.28 seconds
Started Nov 22 01:41:24 PM PST 23
Finished Nov 22 01:41:46 PM PST 23
Peak memory 201988 kb
Host smart-3b964234-80f3-45dc-9abd-c00e4631d5dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28646625338928949571161213063490958412620940763548378053921519882660221279902 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.28646625338928949571161213063490958412620940763548378053921519882660221279902
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.30017220081945814347260456541243454037811011415076261481959465355950117456110
Short name T469
Test name
Test status
Simulation time 260306045935 ps
CPU time 334.78 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:47:24 PM PST 23
Peak memory 202904 kb
Host smart-4b2bb3ff-92a3-42dc-9de4-61625addd34a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=30017220081945814347260456541243454037811011415076261481959465355950117456110 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.30017220081945814347260456541243454037811011415076261481959465355950117456110
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.50425967257551915738954714083714676858718495792911769539847109329854408369054
Short name T44
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.72 seconds
Started Nov 22 01:40:19 PM PST 23
Finished Nov 22 01:40:30 PM PST 23
Peak memory 201952 kb
Host smart-1c584542-914d-4abd-ac59-60d890855a30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=50425967257551915738954714083714676858718495792911769539847109329854408369054 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.50425967257551915738954714083714676858718495792911769539847109329854408369054
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.30174288691539035559833497754767855356351198270497592936858481583545766454926
Short name T216
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.36 seconds
Started Nov 22 01:41:29 PM PST 23
Finished Nov 22 01:41:44 PM PST 23
Peak memory 201904 kb
Host smart-f63c3b89-62f8-4bdf-ae53-e902cf54c5f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30174288691539035559833497754767855356351198270497592936858481583545766454926 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 18.xbar_error_random.30174288691539035559833497754767855356351198270497592936858481583545766454926
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.39731342582212038196120409119890809304870216875912149743494593803969471305572
Short name T439
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.91 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:41:59 PM PST 23
Peak memory 201988 kb
Host smart-790bb8bb-7c91-4482-b5af-89ffc12a6673
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=39731342582212038196120409119890809304870216875912149743494593803969471305572 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 18.xbar_random.39731342582212038196120409119890809304870216875912149743494593803969471305572
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.36274895626068152916969805110939261183809156418095857160761398284987416650887
Short name T268
Test name
Test status
Simulation time 237556670935 ps
CPU time 187.94 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:44:57 PM PST 23
Peak memory 201920 kb
Host smart-8c68d576-622f-41f7-91f1-70f31d1af679
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=36274895626068152916969805110939261183809156418095857160761398284987416650887 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 18.xbar_random_large_delays.36274895626068152916969805110939261183809156418095857160761398284987416650887
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.43767193581387539391750652258874924358213580423956630250837071396482145063109
Short name T683
Test name
Test status
Simulation time 160909483435 ps
CPU time 189.27 seconds
Started Nov 22 01:41:27 PM PST 23
Finished Nov 22 01:44:37 PM PST 23
Peak memory 201972 kb
Host smart-735e782b-2ac0-4549-8cac-45b41e981501
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=43767193581387539391750652258874924358213580423956630250837071396482145063109 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.43767193581387539391750652258874924358213580423956630250837071396482145063109
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.110045060274357529058583363624529524920402231030087621219869906591750038020251
Short name T34
Test name
Test status
Simulation time 360920935 ps
CPU time 7.51 seconds
Started Nov 22 01:41:28 PM PST 23
Finished Nov 22 01:41:37 PM PST 23
Peak memory 201936 kb
Host smart-449c9401-7ab5-4e93-91e1-1f2d5dc5cf07
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110045060274357529058583363624529524920402231030087621219869906591750038020251 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.110045060274357529058583363624529524920402231030087621219869906591750038020251
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.10229218324532876409773715399270076050851975954794263337045677078561970383694
Short name T880
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.54 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:42:04 PM PST 23
Peak memory 201856 kb
Host smart-084492fe-8664-402c-af46-57837f9020be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10229218324532876409773715399270076050851975954794263337045677078561970383694 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 18.xbar_same_source.10229218324532876409773715399270076050851975954794263337045677078561970383694
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.57622747069896338939132978094794900045639656696366318701858217524156445710722
Short name T680
Test name
Test status
Simulation time 331233435 ps
CPU time 1.6 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:20 PM PST 23
Peak memory 201824 kb
Host smart-72c6447e-05d0-4051-bc02-b59117cbbf05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57622747069896338939132978094794900045639656696366318701858217524156445710722 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 18.xbar_smoke.57622747069896338939132978094794900045639656696366318701858217524156445710722
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.82290615028039022867899304953459931097323311388871170514077071318757457036559
Short name T634
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.96 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:41:35 PM PST 23
Peak memory 201840 kb
Host smart-860f1d83-ccf1-4387-b239-ed9b332db223
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=82290615028039022867899304953459931097323311388871170514077071318757457036559 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.82290615028039022867899304953459931097323311388871170514077071318757457036559
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.47070761758164797365098781770129744981044421017922533428181582232807137055264
Short name T192
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.76 seconds
Started Nov 22 01:41:24 PM PST 23
Finished Nov 22 01:41:38 PM PST 23
Peak memory 202040 kb
Host smart-2ff5d66b-19ba-42c7-a0a5-57534bb3e9e1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=47070761758164797365098781770129744981044421017922533428181582232807137055264 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.47070761758164797365098781770129744981044421017922533428181582232807137055264
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.46889660336724101424813565297208275987071567289883763478002885204118892358811
Short name T438
Test name
Test status
Simulation time 27670935 ps
CPU time 1.17 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:41:24 PM PST 23
Peak memory 201796 kb
Host smart-4b1fa1a4-582b-492a-a751-fb1df459b2e7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46889660336724101424813565297208275987071567289883763478002885204118892358811 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.46889660336724101424813565297208275987071567289883763478002885204118892358811
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.53455846233744491036459255363304086884946758274940601554059101368876672986904
Short name T547
Test name
Test status
Simulation time 46147859184 ps
CPU time 131.02 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:42:24 PM PST 23
Peak memory 203180 kb
Host smart-8b311a03-741a-43d7-9dbc-3bb08aac76d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53455846233744491036459255363304086884946758274940601554059101368876672986904 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 18.xbar_stress_all.53455846233744491036459255363304086884946758274940601554059101368876672986904
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.16809540583304563189996619108526978057625296341319982748903635569725657183734
Short name T147
Test name
Test status
Simulation time 46147859184 ps
CPU time 114.99 seconds
Started Nov 22 01:40:09 PM PST 23
Finished Nov 22 01:42:05 PM PST 23
Peak memory 204908 kb
Host smart-96541380-9c87-47bc-bc4b-6509e932892a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16809540583304563189996619108526978057625296341319982748903635569725657183734 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 18.xbar_stress_all_with_error.16809540583304563189996619108526978057625296341319982748903635569725657183734
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.77939451347583330076428598578728987027233476253168935433474014570504495476767
Short name T530
Test name
Test status
Simulation time 13716459184 ps
CPU time 160.03 seconds
Started Nov 22 01:40:17 PM PST 23
Finished Nov 22 01:42:59 PM PST 23
Peak memory 205092 kb
Host smart-7bce886b-b299-41a2-a0f7-41c6ddfcc67d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=77939451347583330076428598578728987027233476253168935433474014570504495476767 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.77939451347583330076428598578728987027233476253168935433474014570504495476767
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2975828989146053428136383669464292981234642038823760148219554056270161917463
Short name T810
Test name
Test status
Simulation time 13716459184 ps
CPU time 140.95 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:42:32 PM PST 23
Peak memory 206252 kb
Host smart-0d9e39b3-dd12-4d0a-960e-a898bace5f58
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2975828989146053428136383669464292981234642038823760148219554056270161917463 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.2975828989146053428136383669464292981234642038823760148219554056270161917463
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.86027408353604374612332496000712399804211177658068039472765911407484436623492
Short name T450
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.18 seconds
Started Nov 22 01:41:31 PM PST 23
Finished Nov 22 01:41:44 PM PST 23
Peak memory 202012 kb
Host smart-93285c92-255e-40f9-9637-cd0bdaa6e00f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86027408353604374612332496000712399804211177658068039472765911407484436623492 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 18.xbar_unmapped_addr.86027408353604374612332496000712399804211177658068039472765911407484436623492
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.60864795697172243937889888990901965524660282736539828042850878332251937659190
Short name T426
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.09 seconds
Started Nov 22 01:40:13 PM PST 23
Finished Nov 22 01:40:33 PM PST 23
Peak memory 201608 kb
Host smart-824a6131-d095-481a-8cdb-d92ba16454f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=60864795697172243937889888990901965524660282736539828042850878332251937659190 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.60864795697172243937889888990901965524660282736539828042850878332251937659190
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.18569597338249792876454049567851819484465876553547601013587996262994613528653
Short name T2
Test name
Test status
Simulation time 260306045935 ps
CPU time 332 seconds
Started Nov 22 01:40:03 PM PST 23
Finished Nov 22 01:45:38 PM PST 23
Peak memory 203044 kb
Host smart-6e2f72f1-5b2b-4683-b5b4-90c6e1a82d8d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=18569597338249792876454049567851819484465876553547601013587996262994613528653 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.18569597338249792876454049567851819484465876553547601013587996262994613528653
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.37334935681184509087444487060940964416832548340495515309875845010301779361140
Short name T379
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.72 seconds
Started Nov 22 01:40:29 PM PST 23
Finished Nov 22 01:40:42 PM PST 23
Peak memory 201288 kb
Host smart-75526646-6f51-4130-96ef-88d51fa8a2ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=37334935681184509087444487060940964416832548340495515309875845010301779361140 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.37334935681184509087444487060940964416832548340495515309875845010301779361140
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.87506408430366179684838859898095204233162139753297926398082140587054092437562
Short name T12
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.17 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:40:40 PM PST 23
Peak memory 201988 kb
Host smart-7196f22e-427f-4dd6-aecd-a96787aee9c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87506408430366179684838859898095204233162139753297926398082140587054092437562 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 19.xbar_error_random.87506408430366179684838859898095204233162139753297926398082140587054092437562
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.32190264029424589462858039460503407299834356528703882356272274685349855987226
Short name T577
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.33 seconds
Started Nov 22 01:40:21 PM PST 23
Finished Nov 22 01:40:36 PM PST 23
Peak memory 201984 kb
Host smart-cb4554b5-caf3-4eaa-a8bd-5406c4a5b92a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32190264029424589462858039460503407299834356528703882356272274685349855987226 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 19.xbar_random.32190264029424589462858039460503407299834356528703882356272274685349855987226
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.89746144013133493716701221440333469402440275542522741567841962610070080244324
Short name T289
Test name
Test status
Simulation time 237556670935 ps
CPU time 187.91 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:43:18 PM PST 23
Peak memory 201920 kb
Host smart-f158c5da-5b2e-43b7-b126-91ce9b72bde9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=89746144013133493716701221440333469402440275542522741567841962610070080244324 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 19.xbar_random_large_delays.89746144013133493716701221440333469402440275542522741567841962610070080244324
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.112953383525082033645181475747582765338400624730877292036369780800865314333269
Short name T655
Test name
Test status
Simulation time 160909483435 ps
CPU time 194.1 seconds
Started Nov 22 01:40:09 PM PST 23
Finished Nov 22 01:43:25 PM PST 23
Peak memory 201980 kb
Host smart-f704101b-a638-4c08-a7ab-5d7f54297dd8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=112953383525082033645181475747582765338400624730877292036369780800865314333269 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.112953383525082033645181475747582765338400624730877292036369780800865314333269
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.27315828313758600508147846546358065644317933354336578349193891637338497555450
Short name T622
Test name
Test status
Simulation time 360920935 ps
CPU time 7.4 seconds
Started Nov 22 01:40:01 PM PST 23
Finished Nov 22 01:40:11 PM PST 23
Peak memory 201832 kb
Host smart-de19d0d3-c682-4eea-94d1-6cd7a0bfdf44
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315828313758600508147846546358065644317933354336578349193891637338497555450 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.27315828313758600508147846546358065644317933354336578349193891637338497555450
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.48030556664138874633984223546613166934417797085930989585646656787890258315963
Short name T780
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.02 seconds
Started Nov 22 01:40:03 PM PST 23
Finished Nov 22 01:40:17 PM PST 23
Peak memory 201908 kb
Host smart-5b5c7996-2dc3-4641-aa26-1e5c7613e8be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=48030556664138874633984223546613166934417797085930989585646656787890258315963 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 19.xbar_same_source.48030556664138874633984223546613166934417797085930989585646656787890258315963
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.23594077100992234124402429187647093958117309028711874927694884118420652717328
Short name T739
Test name
Test status
Simulation time 331233435 ps
CPU time 1.66 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:40:28 PM PST 23
Peak memory 201980 kb
Host smart-f30ee6e1-a83a-4eef-89ec-8bed9974e4fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23594077100992234124402429187647093958117309028711874927694884118420652717328 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 19.xbar_smoke.23594077100992234124402429187647093958117309028711874927694884118420652717328
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.109744588481200559079432867263239175849778902034380457852967595216501482517714
Short name T219
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.95 seconds
Started Nov 22 01:40:26 PM PST 23
Finished Nov 22 01:40:40 PM PST 23
Peak memory 201852 kb
Host smart-0c416723-7ba5-423b-9496-86a021a536ec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=109744588481200559079432867263239175849778902034380457852967595216501482517714 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.109744588481200559079432867263239175849778902034380457852967595216501482517714
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.6723012985306139314537177464302407372705322062487902399896703343953965361380
Short name T787
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.85 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:40:27 PM PST 23
Peak memory 202020 kb
Host smart-58c98772-7b2b-4a08-b4b9-2e72d12a2174
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=6723012985306139314537177464302407372705322062487902399896703343953965361380 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.6723012985306139314537177464302407372705322062487902399896703343953965361380
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.34120404525929163620885152270286016623311261014752885361877213425697752682629
Short name T84
Test name
Test status
Simulation time 27670935 ps
CPU time 1.12 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:40:10 PM PST 23
Peak memory 201844 kb
Host smart-49bc9266-a1e9-494f-8046-379ac934e0da
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34120404525929163620885152270286016623311261014752885361877213425697752682629 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.34120404525929163620885152270286016623311261014752885361877213425697752682629
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.66653451269522642931262264269785584398758626190525833109650892054711868117347
Short name T490
Test name
Test status
Simulation time 46147859184 ps
CPU time 129.28 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:42:21 PM PST 23
Peak memory 203244 kb
Host smart-e9946c78-8b65-4676-81fb-dc8e50dc0663
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=66653451269522642931262264269785584398758626190525833109650892054711868117347 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 19.xbar_stress_all.66653451269522642931262264269785584398758626190525833109650892054711868117347
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.71985542008862177244534417318813498425182885991769443641820957250966919948385
Short name T578
Test name
Test status
Simulation time 46147859184 ps
CPU time 110.96 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:42:04 PM PST 23
Peak memory 204772 kb
Host smart-07af39cc-025d-4c1f-9578-300a85211ca6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=71985542008862177244534417318813498425182885991769443641820957250966919948385 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 19.xbar_stress_all_with_error.71985542008862177244534417318813498425182885991769443641820957250966919948385
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.103786943349300767416774661321645838389303171836541876446872063899760734487788
Short name T839
Test name
Test status
Simulation time 13716459184 ps
CPU time 164.94 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:43:12 PM PST 23
Peak memory 205172 kb
Host smart-f679e574-0848-4f3c-ac70-6af3625b9b50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103786943349300767416774661321645838389303171836541876446872063899760734487788 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.103786943349300767416774661321645838389303171836541876446872063899760734487788
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.41543973025539378603804650895762916764603067165460990333510739701681415684816
Short name T654
Test name
Test status
Simulation time 13716459184 ps
CPU time 137.58 seconds
Started Nov 22 01:40:07 PM PST 23
Finished Nov 22 01:42:27 PM PST 23
Peak memory 206264 kb
Host smart-96062ac9-44f4-4806-9abb-e37b27459370
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=41543973025539378603804650895762916764603067165460990333510739701681415684816 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.41543973025539378603804650895762916764603067165460990333510739701681415684816
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.87591196219569552364474588329554975413650756107830562676064065991644474337920
Short name T771
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.75 seconds
Started Nov 22 01:40:30 PM PST 23
Finished Nov 22 01:40:43 PM PST 23
Peak memory 201220 kb
Host smart-c5f3374e-842b-425a-b4fb-b54442609dfd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87591196219569552364474588329554975413650756107830562676064065991644474337920 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 19.xbar_unmapped_addr.87591196219569552364474588329554975413650756107830562676064065991644474337920
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.28422379520486040318594906546483948387807946877928698258834306094358076802359
Short name T455
Test name
Test status
Simulation time 4712795935 ps
CPU time 16.78 seconds
Started Nov 22 01:40:15 PM PST 23
Finished Nov 22 01:40:33 PM PST 23
Peak memory 201860 kb
Host smart-ed62a3ae-b686-4e8f-bb07-f39150018b9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28422379520486040318594906546483948387807946877928698258834306094358076802359 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.28422379520486040318594906546483948387807946877928698258834306094358076802359
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.59427127143275540991538975315510258099357822582721460252377050941953491207683
Short name T232
Test name
Test status
Simulation time 260306045935 ps
CPU time 334.09 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:45:39 PM PST 23
Peak memory 202984 kb
Host smart-8044da2b-b648-4c87-b1ae-17402a37bde2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=59427127143275540991538975315510258099357822582721460252377050941953491207683 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.59427127143275540991538975315510258099357822582721460252377050941953491207683
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.33514133645274114297849258955937381776986955959999609064865948305141026250936
Short name T615
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.71 seconds
Started Nov 22 01:40:04 PM PST 23
Finished Nov 22 01:40:17 PM PST 23
Peak memory 201960 kb
Host smart-f4a1b1fc-d4e7-4953-bd77-8a598f929344
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33514133645274114297849258955937381776986955959999609064865948305141026250936 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.33514133645274114297849258955937381776986955959999609064865948305141026250936
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.32360733970414643819114056216694525945691505229184163671859101818684879869450
Short name T751
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.81 seconds
Started Nov 22 01:40:04 PM PST 23
Finished Nov 22 01:40:19 PM PST 23
Peak memory 201968 kb
Host smart-f6b2b03b-27b2-41da-97a0-3585763fcf62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32360733970414643819114056216694525945691505229184163671859101818684879869450 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 2.xbar_error_random.32360733970414643819114056216694525945691505229184163671859101818684879869450
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.10166730624372003982692459344047909282383710681995530051406550129957184034646
Short name T838
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.43 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:40:19 PM PST 23
Peak memory 201976 kb
Host smart-71cc2b5b-f268-4a5c-9faa-d17acf03a6d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10166730624372003982692459344047909282383710681995530051406550129957184034646 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 2.xbar_random.10166730624372003982692459344047909282383710681995530051406550129957184034646
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.101224471034093306806132574743305071561551685964702506317361978636123915461174
Short name T817
Test name
Test status
Simulation time 237556670935 ps
CPU time 185.09 seconds
Started Nov 22 01:40:20 PM PST 23
Finished Nov 22 01:43:26 PM PST 23
Peak memory 202004 kb
Host smart-fd1fcae7-a5bc-4b09-b103-d13360682736
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=101224471034093306806132574743305071561551685964702506317361978636123915461174 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.101224471034093306806132574743305071561551685964702506317361978636123915461174
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.56232865318233799631925524067411565538796597622686276217683774965375013188436
Short name T464
Test name
Test status
Simulation time 160909483435 ps
CPU time 192.8 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:43:17 PM PST 23
Peak memory 201992 kb
Host smart-571b7377-9fab-4130-8b4b-79bde9ad7001
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=56232865318233799631925524067411565538796597622686276217683774965375013188436 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.56232865318233799631925524067411565538796597622686276217683774965375013188436
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.52425248923167924436652191566339336994170126791480149374119352046001185752841
Short name T494
Test name
Test status
Simulation time 360920935 ps
CPU time 7.39 seconds
Started Nov 22 01:39:51 PM PST 23
Finished Nov 22 01:39:59 PM PST 23
Peak memory 201828 kb
Host smart-e2febc5f-21d3-4898-b6dc-3e5dff2eec54
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52425248923167924436652191566339336994170126791480149374119352046001185752841 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.52425248923167924436652191566339336994170126791480149374119352046001185752841
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.56920307750279213381719373121834439253834125928617173593800163103135470385288
Short name T136
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.27 seconds
Started Nov 22 01:40:01 PM PST 23
Finished Nov 22 01:40:15 PM PST 23
Peak memory 201988 kb
Host smart-f15a2276-7863-4854-a5c8-9987a85d3c64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56920307750279213381719373121834439253834125928617173593800163103135470385288 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 2.xbar_same_source.56920307750279213381719373121834439253834125928617173593800163103135470385288
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.50974979091380843502621183675463988802492621376665199714664759497601827589759
Short name T692
Test name
Test status
Simulation time 331233435 ps
CPU time 1.67 seconds
Started Nov 22 01:40:20 PM PST 23
Finished Nov 22 01:40:23 PM PST 23
Peak memory 201964 kb
Host smart-2e7a2dcf-98fb-4f09-9d46-8ae134f4a601
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=50974979091380843502621183675463988802492621376665199714664759497601827589759 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 2.xbar_smoke.50974979091380843502621183675463988802492621376665199714664759497601827589759
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.85060484441116568488841081333778138779226115291969437754967755771429574740082
Short name T167
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.73 seconds
Started Nov 22 01:40:23 PM PST 23
Finished Nov 22 01:40:36 PM PST 23
Peak memory 201976 kb
Host smart-c3cba762-948c-4ba0-8701-d0944504283c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=85060484441116568488841081333778138779226115291969437754967755771429574740082 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.85060484441116568488841081333778138779226115291969437754967755771429574740082
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.22549482463779313214168725919381727303142428258252135434371101728219947140336
Short name T3
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.31 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:14 PM PST 23
Peak memory 201908 kb
Host smart-8eaa136e-533d-437d-9d89-b694ef37922f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=22549482463779313214168725919381727303142428258252135434371101728219947140336 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.22549482463779313214168725919381727303142428258252135434371101728219947140336
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.40930578615744138288337878026640809368679913483204269431442245638139568090543
Short name T507
Test name
Test status
Simulation time 27670935 ps
CPU time 1.2 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:40:06 PM PST 23
Peak memory 201928 kb
Host smart-a70467ea-86cb-4ac9-84ba-d573a45b69a6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40930578615744138288337878026640809368679913483204269431442245638139568090543 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.40930578615744138288337878026640809368679913483204269431442245638139568090543
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.105788203028406154588042733975766127805926479136747446623282259752870154814128
Short name T742
Test name
Test status
Simulation time 46147859184 ps
CPU time 134.42 seconds
Started Nov 22 01:39:59 PM PST 23
Finished Nov 22 01:42:15 PM PST 23
Peak memory 203176 kb
Host smart-10086a59-b39d-4e9a-9cbe-f34973f01d2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105788203028406154588042733975766127805926479136747446623282259752870154814128 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 2.xbar_stress_all.105788203028406154588042733975766127805926479136747446623282259752870154814128
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.103342688915219972932909598052539160992574005036696112838492394603801029182993
Short name T770
Test name
Test status
Simulation time 46147859184 ps
CPU time 120.06 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:42:09 PM PST 23
Peak memory 202984 kb
Host smart-eb8390f7-4ff3-40de-ae06-d61fc3fa2a43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103342688915219972932909598052539160992574005036696112838492394603801029182993 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.103342688915219972932909598052539160992574005036696112838492394603801029182993
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.49075813689765475966030830277317546080196127083358389692391048712999503940869
Short name T369
Test name
Test status
Simulation time 13716459184 ps
CPU time 165.84 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:42:48 PM PST 23
Peak memory 205120 kb
Host smart-59651538-6a31-4349-ab28-c92b47126074
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49075813689765475966030830277317546080196127083358389692391048712999503940869 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.49075813689765475966030830277317546080196127083358389692391048712999503940869
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.8189491264615283199516726726004519290003975103420344783046017620622095957610
Short name T23
Test name
Test status
Simulation time 13716459184 ps
CPU time 136.01 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:42:20 PM PST 23
Peak memory 206256 kb
Host smart-58f119b1-6019-4951-b923-12b8a2003150
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=8189491264615283199516726726004519290003975103420344783046017620622095957610 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.8189491264615283199516726726004519290003975103420344783046017620622095957610
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.57135542153394084274795483464665466908066811657605535473863775772632292241302
Short name T512
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.96 seconds
Started Nov 22 01:40:19 PM PST 23
Finished Nov 22 01:40:31 PM PST 23
Peak memory 201932 kb
Host smart-97542e98-d22e-4be8-b712-287567df79bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57135542153394084274795483464665466908066811657605535473863775772632292241302 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 2.xbar_unmapped_addr.57135542153394084274795483464665466908066811657605535473863775772632292241302
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.80117795980737076289315187522870710460573114595795581914222585956856721361371
Short name T651
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.41 seconds
Started Nov 22 01:41:11 PM PST 23
Finished Nov 22 01:41:30 PM PST 23
Peak memory 201992 kb
Host smart-94ade568-51dd-49ee-a9b8-ccd0549874cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=80117795980737076289315187522870710460573114595795581914222585956856721361371 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.80117795980737076289315187522870710460573114595795581914222585956856721361371
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.112642491226415325405234336346751810899872413310359063074105992093519225593384
Short name T22
Test name
Test status
Simulation time 260306045935 ps
CPU time 342.26 seconds
Started Nov 22 01:40:30 PM PST 23
Finished Nov 22 01:46:15 PM PST 23
Peak memory 203024 kb
Host smart-162bbfc3-ed3d-4006-b971-342c19fb18e4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=112642491226415325405234336346751810899872413310359063074105992093519225593384 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.112642491226415325405234336346751810899872413310359063074105992093519225593384
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.54880225473442455904070226034855107978935667322554042856574130748898715950582
Short name T445
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.28 seconds
Started Nov 22 01:40:37 PM PST 23
Finished Nov 22 01:40:49 PM PST 23
Peak memory 201848 kb
Host smart-51f3302b-5de0-41b4-8f06-f938ccff416f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54880225473442455904070226034855107978935667322554042856574130748898715950582 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.54880225473442455904070226034855107978935667322554042856574130748898715950582
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.59608756314793080272238285735000759381880138360409621029571453098414360599242
Short name T648
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.41 seconds
Started Nov 22 01:40:27 PM PST 23
Finished Nov 22 01:40:40 PM PST 23
Peak memory 201832 kb
Host smart-6522efc2-9fb9-4fbf-9021-1fcd04cc2594
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59608756314793080272238285735000759381880138360409621029571453098414360599242 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 20.xbar_error_random.59608756314793080272238285735000759381880138360409621029571453098414360599242
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.100384658261511767549656337121487204884289534809675745160181955130876512518789
Short name T381
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.42 seconds
Started Nov 22 01:40:27 PM PST 23
Finished Nov 22 01:40:43 PM PST 23
Peak memory 201948 kb
Host smart-9f5dd95c-6ea6-4456-886e-8e6fb4dd6b9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100384658261511767549656337121487204884289534809675745160181955130876512518789 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 20.xbar_random.100384658261511767549656337121487204884289534809675745160181955130876512518789
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.59831919600361316145434197049518301108384455531434939885301326910473211401473
Short name T788
Test name
Test status
Simulation time 237556670935 ps
CPU time 188.4 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:43:46 PM PST 23
Peak memory 201604 kb
Host smart-48045faa-e162-46fc-b1fa-00e5c4870631
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=59831919600361316145434197049518301108384455531434939885301326910473211401473 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 20.xbar_random_large_delays.59831919600361316145434197049518301108384455531434939885301326910473211401473
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.42125068111408684714894340236732648304225627759939655634534008687706041356937
Short name T248
Test name
Test status
Simulation time 160909483435 ps
CPU time 191.16 seconds
Started Nov 22 01:40:39 PM PST 23
Finished Nov 22 01:43:52 PM PST 23
Peak memory 201804 kb
Host smart-8e1d4d3f-7a61-4d78-9b91-3a51e5da6785
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=42125068111408684714894340236732648304225627759939655634534008687706041356937 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.42125068111408684714894340236732648304225627759939655634534008687706041356937
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.14216317758242716535296011804736337801889001175013143460521235794166368028159
Short name T217
Test name
Test status
Simulation time 360920935 ps
CPU time 7.77 seconds
Started Nov 22 01:40:55 PM PST 23
Finished Nov 22 01:41:04 PM PST 23
Peak memory 201896 kb
Host smart-1776050c-8e24-41d0-8155-9f40887c6540
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14216317758242716535296011804736337801889001175013143460521235794166368028159 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.14216317758242716535296011804736337801889001175013143460521235794166368028159
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.2168187240244567957489721676289538776943371257215149080575605566934999012882
Short name T19
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.44 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:40:50 PM PST 23
Peak memory 201964 kb
Host smart-dc0f1aae-b3c0-4a91-8899-222af6c916ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2168187240244567957489721676289538776943371257215149080575605566934999012882 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 20.xbar_same_source.2168187240244567957489721676289538776943371257215149080575605566934999012882
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.4035874672557703644711597968126466091896927367736743655613750222731280643995
Short name T515
Test name
Test status
Simulation time 331233435 ps
CPU time 1.58 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:40:28 PM PST 23
Peak memory 201852 kb
Host smart-75da7f2a-37c0-44aa-ba37-9e4099a40e9a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4035874672557703644711597968126466091896927367736743655613750222731280643995 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 20.xbar_smoke.4035874672557703644711597968126466091896927367736743655613750222731280643995
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.84936519119324271097320102431523635857729028198835758007492985816780887516027
Short name T550
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.72 seconds
Started Nov 22 01:40:06 PM PST 23
Finished Nov 22 01:40:20 PM PST 23
Peak memory 201964 kb
Host smart-69b3ba14-2a08-4f31-9df9-ba75b4e5407e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=84936519119324271097320102431523635857729028198835758007492985816780887516027 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.84936519119324271097320102431523635857729028198835758007492985816780887516027
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.80487879878029050814910727767908914175449417836115758731265539167570063638934
Short name T288
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.8 seconds
Started Nov 22 01:40:39 PM PST 23
Finished Nov 22 01:40:53 PM PST 23
Peak memory 201804 kb
Host smart-850f7275-2a6c-4aa8-8e9f-bacf2cf7a22d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=80487879878029050814910727767908914175449417836115758731265539167570063638934 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.80487879878029050814910727767908914175449417836115758731265539167570063638934
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.59211470330023352814748578679380082142698983354652270830136984252070661067338
Short name T712
Test name
Test status
Simulation time 27670935 ps
CPU time 1.19 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:40:14 PM PST 23
Peak memory 201748 kb
Host smart-baefe2f6-2e52-443e-b653-34644092b49f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59211470330023352814748578679380082142698983354652270830136984252070661067338 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.59211470330023352814748578679380082142698983354652270830136984252070661067338
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.75537127574492324573723367590480667360575969179407650725288813240941396432922
Short name T664
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.25 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:42:44 PM PST 23
Peak memory 203228 kb
Host smart-1e793de8-8cfd-4ecd-a3ef-c095339b02df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=75537127574492324573723367590480667360575969179407650725288813240941396432922 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 20.xbar_stress_all.75537127574492324573723367590480667360575969179407650725288813240941396432922
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.32794643258511775658679724813978877197927538967384834148000292171245323306581
Short name T567
Test name
Test status
Simulation time 46147859184 ps
CPU time 117.41 seconds
Started Nov 22 01:40:56 PM PST 23
Finished Nov 22 01:42:54 PM PST 23
Peak memory 204920 kb
Host smart-38522156-938c-4a7b-8721-f15f422a1ce6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32794643258511775658679724813978877197927538967384834148000292171245323306581 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 20.xbar_stress_all_with_error.32794643258511775658679724813978877197927538967384834148000292171245323306581
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.20285007514294174226669873118927759645979985442169743899431112169826248580828
Short name T234
Test name
Test status
Simulation time 13716459184 ps
CPU time 164.92 seconds
Started Nov 22 01:40:32 PM PST 23
Finished Nov 22 01:43:19 PM PST 23
Peak memory 205132 kb
Host smart-0b4f6f6f-2bb2-4494-a092-a0c951f8a461
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20285007514294174226669873118927759645979985442169743899431112169826248580828 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.20285007514294174226669873118927759645979985442169743899431112169826248580828
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.28080761348955020042773570048807511228499992330642005711855175765124173966093
Short name T125
Test name
Test status
Simulation time 13716459184 ps
CPU time 138.19 seconds
Started Nov 22 01:40:24 PM PST 23
Finished Nov 22 01:42:44 PM PST 23
Peak memory 206284 kb
Host smart-69c9fb23-c82e-4cae-9f75-0d8ba245ce54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28080761348955020042773570048807511228499992330642005711855175765124173966093 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.28080761348955020042773570048807511228499992330642005711855175765124173966093
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.11402606168540662429758687908637682381668623190557836303578769510627891074969
Short name T434
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.89 seconds
Started Nov 22 01:40:57 PM PST 23
Finished Nov 22 01:41:10 PM PST 23
Peak memory 201992 kb
Host smart-8ab24e8f-81b5-42bb-b90b-01f91294e161
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=11402606168540662429758687908637682381668623190557836303578769510627891074969 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 20.xbar_unmapped_addr.11402606168540662429758687908637682381668623190557836303578769510627891074969
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.53369305269405913900391907873977059863958408940400687959140906975413295524700
Short name T30
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.8 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:41:36 PM PST 23
Peak memory 201976 kb
Host smart-5a8f6f09-c18b-492e-aeee-1f602ac9926c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53369305269405913900391907873977059863958408940400687959140906975413295524700 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.53369305269405913900391907873977059863958408940400687959140906975413295524700
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.4360685321761155751205359913762943625417913249485133211033418913630215052014
Short name T424
Test name
Test status
Simulation time 260306045935 ps
CPU time 339.47 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:46:06 PM PST 23
Peak memory 203000 kb
Host smart-404890f3-7068-417f-9a20-29718b9a8a8a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4360685321761155751205359913762943625417913249485133211033418913630215052014 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build
_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.4360685321761155751205359913762943625417913249485133211033418913630215052014
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.53777230775689215770366896320290482500772172379669709670164558957054681900243
Short name T506
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.96 seconds
Started Nov 22 01:40:36 PM PST 23
Finished Nov 22 01:40:48 PM PST 23
Peak memory 201852 kb
Host smart-62b5a11a-29fe-41d2-bec4-fb64733cd139
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53777230775689215770366896320290482500772172379669709670164558957054681900243 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.53777230775689215770366896320290482500772172379669709670164558957054681900243
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.87250864993104397342914988650045112513955895584585999988910906066197449126520
Short name T719
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.66 seconds
Started Nov 22 01:40:40 PM PST 23
Finished Nov 22 01:40:56 PM PST 23
Peak memory 201956 kb
Host smart-d60062ad-e161-499c-a50a-06fcba9cb21c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87250864993104397342914988650045112513955895584585999988910906066197449126520 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 21.xbar_error_random.87250864993104397342914988650045112513955895584585999988910906066197449126520
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.2278079980275887091808361210841033216263540366630864940339148159260186901229
Short name T569
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.1 seconds
Started Nov 22 01:41:09 PM PST 23
Finished Nov 22 01:41:25 PM PST 23
Peak memory 201992 kb
Host smart-721eaa73-27de-48a5-ad62-efacbdb87b1e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2278079980275887091808361210841033216263540366630864940339148159260186901229 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 21.xbar_random.2278079980275887091808361210841033216263540366630864940339148159260186901229
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.66505117915433459543484899652419111358720015297233412452912313570985403553664
Short name T811
Test name
Test status
Simulation time 237556670935 ps
CPU time 190.75 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:43:48 PM PST 23
Peak memory 201364 kb
Host smart-94d0db61-8221-456a-b526-1e0f5c8ae132
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=66505117915433459543484899652419111358720015297233412452912313570985403553664 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 21.xbar_random_large_delays.66505117915433459543484899652419111358720015297233412452912313570985403553664
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.111559307457073933189685700292639679474103891403245079862897441311946427202441
Short name T122
Test name
Test status
Simulation time 160909483435 ps
CPU time 194.64 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:43:52 PM PST 23
Peak memory 201988 kb
Host smart-847dce62-df4f-4afb-9f61-3fc44bdcb41f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=111559307457073933189685700292639679474103891403245079862897441311946427202441 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.111559307457073933189685700292639679474103891403245079862897441311946427202441
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.23402988653982575363556870923493210102776569817934414134272662673748408262535
Short name T395
Test name
Test status
Simulation time 360920935 ps
CPU time 7.38 seconds
Started Nov 22 01:40:39 PM PST 23
Finished Nov 22 01:40:48 PM PST 23
Peak memory 201740 kb
Host smart-32799e28-d47f-40da-b749-6f50814b1dd4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23402988653982575363556870923493210102776569817934414134272662673748408262535 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.23402988653982575363556870923493210102776569817934414134272662673748408262535
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.87460095140434190758720274316274517708332005095650438890076381301092512121317
Short name T278
Test name
Test status
Simulation time 5235733435 ps
CPU time 13.25 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:40:51 PM PST 23
Peak memory 201504 kb
Host smart-bc273b0c-b62d-44ad-a7d3-f44c73008d93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87460095140434190758720274316274517708332005095650438890076381301092512121317 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 21.xbar_same_source.87460095140434190758720274316274517708332005095650438890076381301092512121317
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.6439831782629140943903226519533974076190560534452139136230999692054464243311
Short name T532
Test name
Test status
Simulation time 331233435 ps
CPU time 1.57 seconds
Started Nov 22 01:40:34 PM PST 23
Finished Nov 22 01:40:36 PM PST 23
Peak memory 201940 kb
Host smart-52c01cff-2bc3-4977-952a-3e8d014b344b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6439831782629140943903226519533974076190560534452139136230999692054464243311 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 21.xbar_smoke.6439831782629140943903226519533974076190560534452139136230999692054464243311
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.42275945920212142716739311116504270606029534890445870537484679072318493717865
Short name T734
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.88 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:40:49 PM PST 23
Peak memory 202016 kb
Host smart-ec91fa40-b917-4a50-a608-f44f659be8aa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=42275945920212142716739311116504270606029534890445870537484679072318493717865 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.42275945920212142716739311116504270606029534890445870537484679072318493717865
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.16436387495190558680098459541458998344888682272019980627240683353751430348084
Short name T224
Test name
Test status
Simulation time 10098608435 ps
CPU time 13.27 seconds
Started Nov 22 01:40:33 PM PST 23
Finished Nov 22 01:40:47 PM PST 23
Peak memory 201964 kb
Host smart-7e7ea919-3737-4d0e-83fa-e37f2935d865
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=16436387495190558680098459541458998344888682272019980627240683353751430348084 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.16436387495190558680098459541458998344888682272019980627240683353751430348084
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.87362958177460978388495361691071525517017765484432475854782944869351993529088
Short name T436
Test name
Test status
Simulation time 27670935 ps
CPU time 1.2 seconds
Started Nov 22 01:41:10 PM PST 23
Finished Nov 22 01:41:13 PM PST 23
Peak memory 201920 kb
Host smart-6e77922c-0c20-4d0f-996b-f3d8c705bbf2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87362958177460978388495361691071525517017765484432475854782944869351993529088 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.87362958177460978388495361691071525517017765484432475854782944869351993529088
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.60313816939603379629881283551848498293060481264829131620040574045045251850574
Short name T480
Test name
Test status
Simulation time 46147859184 ps
CPU time 131.2 seconds
Started Nov 22 01:40:44 PM PST 23
Finished Nov 22 01:42:57 PM PST 23
Peak memory 203200 kb
Host smart-e94c4142-1253-4e81-9340-761bab9e8299
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=60313816939603379629881283551848498293060481264829131620040574045045251850574 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 21.xbar_stress_all.60313816939603379629881283551848498293060481264829131620040574045045251850574
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.6293426999086563586579956496044446637078727478849639851135014056003236305053
Short name T794
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.76 seconds
Started Nov 22 01:41:11 PM PST 23
Finished Nov 22 01:43:19 PM PST 23
Peak memory 204928 kb
Host smart-53d59fc3-e8a7-4b74-8124-860828044128
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6293426999086563586579956496044446637078727478849639851135014056003236305053 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 21.xbar_stress_all_with_error.6293426999086563586579956496044446637078727478849639851135014056003236305053
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.78860495982113881841157217362535374249448515043725148353351312542249406173252
Short name T757
Test name
Test status
Simulation time 13716459184 ps
CPU time 163.43 seconds
Started Nov 22 01:40:27 PM PST 23
Finished Nov 22 01:43:11 PM PST 23
Peak memory 205132 kb
Host smart-9e31a272-e73b-4910-91cc-3e985b94b5c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78860495982113881841157217362535374249448515043725148353351312542249406173252 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.78860495982113881841157217362535374249448515043725148353351312542249406173252
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.74323261451262814249991868864425096762957048721331332777409111084666994392324
Short name T368
Test name
Test status
Simulation time 13716459184 ps
CPU time 132.16 seconds
Started Nov 22 01:40:39 PM PST 23
Finished Nov 22 01:42:53 PM PST 23
Peak memory 206064 kb
Host smart-093ce393-0616-4d71-b032-49e769485a20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=74323261451262814249991868864425096762957048721331332777409111084666994392324 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.74323261451262814249991868864425096762957048721331332777409111084666994392324
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2605451618900447005351845544386920016872109229128480354001158840624862717216
Short name T516
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.79 seconds
Started Nov 22 01:40:37 PM PST 23
Finished Nov 22 01:40:51 PM PST 23
Peak memory 202004 kb
Host smart-ec77b178-c33d-4c69-9cc1-9743bbefa102
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2605451618900447005351845544386920016872109229128480354001158840624862717216 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2605451618900447005351845544386920016872109229128480354001158840624862717216
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3095996600404041186179752652655359154552306555656205575625016880874649341818
Short name T510
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.28 seconds
Started Nov 22 01:40:46 PM PST 23
Finished Nov 22 01:41:04 PM PST 23
Peak memory 201912 kb
Host smart-411ba38f-4235-454b-88a6-aa9d69e98c73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3095996600404041186179752652655359154552306555656205575625016880874649341818 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3095996600404041186179752652655359154552306555656205575625016880874649341818
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.108347886157977389290666034711760360299433077506963637005448135143316692741802
Short name T621
Test name
Test status
Simulation time 260306045935 ps
CPU time 335.55 seconds
Started Nov 22 01:40:27 PM PST 23
Finished Nov 22 01:46:03 PM PST 23
Peak memory 203024 kb
Host smart-602764f8-816a-4442-a77a-c59ce2643ccb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=108347886157977389290666034711760360299433077506963637005448135143316692741802 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.108347886157977389290666034711760360299433077506963637005448135143316692741802
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.73326142499489125969781634318354820603716948330599486160673020078847825522959
Short name T155
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.15 seconds
Started Nov 22 01:40:45 PM PST 23
Finished Nov 22 01:40:56 PM PST 23
Peak memory 201896 kb
Host smart-5d3f61fc-b36e-49c1-a69c-f3a2a4c365d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73326142499489125969781634318354820603716948330599486160673020078847825522959 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.73326142499489125969781634318354820603716948330599486160673020078847825522959
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.85763336064800177139147673057658648303555217886920664887441768112907076864614
Short name T468
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.05 seconds
Started Nov 22 01:41:08 PM PST 23
Finished Nov 22 01:41:24 PM PST 23
Peak memory 201880 kb
Host smart-0e58db9e-8040-4dd1-9d7c-8b6c6095e983
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85763336064800177139147673057658648303555217886920664887441768112907076864614 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 22.xbar_error_random.85763336064800177139147673057658648303555217886920664887441768112907076864614
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.25706941656984553335800399262014397119727004994116841172634606028819017517711
Short name T863
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.05 seconds
Started Nov 22 01:40:46 PM PST 23
Finished Nov 22 01:41:01 PM PST 23
Peak memory 201900 kb
Host smart-ef6be56b-c55b-48c5-923e-9c965669cfba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25706941656984553335800399262014397119727004994116841172634606028819017517711 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 22.xbar_random.25706941656984553335800399262014397119727004994116841172634606028819017517711
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.91702571853366613771660782183110098339082822276632540334657927452324303761575
Short name T73
Test name
Test status
Simulation time 237556670935 ps
CPU time 189.6 seconds
Started Nov 22 01:40:37 PM PST 23
Finished Nov 22 01:43:48 PM PST 23
Peak memory 201888 kb
Host smart-42603a6c-4ce5-45eb-b77d-d1bfba725ab5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=91702571853366613771660782183110098339082822276632540334657927452324303761575 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 22.xbar_random_large_delays.91702571853366613771660782183110098339082822276632540334657927452324303761575
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.111171618176301317530510081796704122096492158968179598707842038582785186328972
Short name T358
Test name
Test status
Simulation time 160909483435 ps
CPU time 191.85 seconds
Started Nov 22 01:40:36 PM PST 23
Finished Nov 22 01:43:50 PM PST 23
Peak memory 201832 kb
Host smart-5f97020f-4301-4bbb-96fb-59e5a049df42
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=111171618176301317530510081796704122096492158968179598707842038582785186328972 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.111171618176301317530510081796704122096492158968179598707842038582785186328972
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.78245056095095595034598567866019020242978380283738220574365348995896697792769
Short name T396
Test name
Test status
Simulation time 360920935 ps
CPU time 7.83 seconds
Started Nov 22 01:40:44 PM PST 23
Finished Nov 22 01:40:53 PM PST 23
Peak memory 201984 kb
Host smart-cb56e6ff-f075-4997-8f8e-61d0d1160d59
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78245056095095595034598567866019020242978380283738220574365348995896697792769 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.78245056095095595034598567866019020242978380283738220574365348995896697792769
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.49351688817743201407221798661502706763904445013287981170194745018275006496297
Short name T414
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.99 seconds
Started Nov 22 01:40:46 PM PST 23
Finished Nov 22 01:40:58 PM PST 23
Peak memory 201900 kb
Host smart-b1de299f-0d48-4c1a-a48a-7bde1f4541cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49351688817743201407221798661502706763904445013287981170194745018275006496297 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 22.xbar_same_source.49351688817743201407221798661502706763904445013287981170194745018275006496297
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.111737283882513898190354557951280256957072017236380342195800433518205228608321
Short name T617
Test name
Test status
Simulation time 331233435 ps
CPU time 1.61 seconds
Started Nov 22 01:40:28 PM PST 23
Finished Nov 22 01:40:30 PM PST 23
Peak memory 201936 kb
Host smart-a847d31b-cd70-4e5d-a50e-456c372311d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111737283882513898190354557951280256957072017236380342195800433518205228608321 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 22.xbar_smoke.111737283882513898190354557951280256957072017236380342195800433518205228608321
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.62540613715775154270731625463589295030697714371308898066488874733063190161032
Short name T740
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.92 seconds
Started Nov 22 01:40:33 PM PST 23
Finished Nov 22 01:40:47 PM PST 23
Peak memory 201968 kb
Host smart-267f3a3d-c2de-4779-8b35-6d95061aedff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=62540613715775154270731625463589295030697714371308898066488874733063190161032 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.62540613715775154270731625463589295030697714371308898066488874733063190161032
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.65610007207790949216355549110350252752945949137170437201220621327865530979491
Short name T756
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.66 seconds
Started Nov 22 01:40:28 PM PST 23
Finished Nov 22 01:40:42 PM PST 23
Peak memory 201856 kb
Host smart-df001181-b805-4f31-ab6f-2d88fd308c02
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=65610007207790949216355549110350252752945949137170437201220621327865530979491 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.65610007207790949216355549110350252752945949137170437201220621327865530979491
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.109403399306738956852166352861123742300948882517723911681021246098214783558401
Short name T589
Test name
Test status
Simulation time 27670935 ps
CPU time 1.21 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:40:39 PM PST 23
Peak memory 201876 kb
Host smart-65583621-e520-48bb-87d4-db7262c76db9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109403399306738956852166352861123742300948882517723911681021246098214783558401 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.109403399306738956852166352861123742300948882517723911681021246098214783558401
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.81862892170291050448622057573002741225339711163934876979027152342295791748874
Short name T633
Test name
Test status
Simulation time 46147859184 ps
CPU time 122.24 seconds
Started Nov 22 01:41:12 PM PST 23
Finished Nov 22 01:43:16 PM PST 23
Peak memory 203212 kb
Host smart-bff5e25c-9ca0-4453-855f-916aad9ca9fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81862892170291050448622057573002741225339711163934876979027152342295791748874 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 22.xbar_stress_all.81862892170291050448622057573002741225339711163934876979027152342295791748874
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.59345077975164477466587185386188612850544140314637859337766888998103541099793
Short name T215
Test name
Test status
Simulation time 46147859184 ps
CPU time 108.5 seconds
Started Nov 22 01:40:39 PM PST 23
Finished Nov 22 01:42:29 PM PST 23
Peak memory 204740 kb
Host smart-51056aac-becf-4cb6-88ea-a0a3f3d5cadb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59345077975164477466587185386188612850544140314637859337766888998103541099793 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 22.xbar_stress_all_with_error.59345077975164477466587185386188612850544140314637859337766888998103541099793
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.33578902244959787859811829833137784831975109205789885577201840396229018546591
Short name T310
Test name
Test status
Simulation time 13716459184 ps
CPU time 158.2 seconds
Started Nov 22 01:40:36 PM PST 23
Finished Nov 22 01:43:16 PM PST 23
Peak memory 205004 kb
Host smart-5a564678-a526-48a1-bd6a-7ad52f557b7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33578902244959787859811829833137784831975109205789885577201840396229018546591 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.33578902244959787859811829833137784831975109205789885577201840396229018546591
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.22238281457399369745429963132606853065240582401004767613372945193636311948869
Short name T13
Test name
Test status
Simulation time 13716459184 ps
CPU time 136.16 seconds
Started Nov 22 01:40:33 PM PST 23
Finished Nov 22 01:42:51 PM PST 23
Peak memory 206216 kb
Host smart-15dde846-97da-49d6-a4f2-7a50c422273f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22238281457399369745429963132606853065240582401004767613372945193636311948869 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.22238281457399369745429963132606853065240582401004767613372945193636311948869
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.102797065246806107904744836870606272894594559716399561720064338867542718970597
Short name T645
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.06 seconds
Started Nov 22 01:40:57 PM PST 23
Finished Nov 22 01:41:09 PM PST 23
Peak memory 202052 kb
Host smart-c5c583e9-60af-4dda-912a-48f4abf02fef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102797065246806107904744836870606272894594559716399561720064338867542718970597 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 22.xbar_unmapped_addr.102797065246806107904744836870606272894594559716399561720064338867542718970597
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.31439361403929945940874740767245091393652517916112094810414965598557407824866
Short name T752
Test name
Test status
Simulation time 4712795935 ps
CPU time 16.17 seconds
Started Nov 22 01:40:27 PM PST 23
Finished Nov 22 01:40:45 PM PST 23
Peak memory 201844 kb
Host smart-878c3321-f36c-4c67-a72b-d47feb7f7b9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31439361403929945940874740767245091393652517916112094810414965598557407824866 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.31439361403929945940874740767245091393652517916112094810414965598557407824866
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.44437289728655410756371363671456613463927973759340023687258992613863928826591
Short name T55
Test name
Test status
Simulation time 260306045935 ps
CPU time 329.94 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:46:52 PM PST 23
Peak memory 203044 kb
Host smart-7f2153bb-8a8a-4381-8c4e-1dfc8b657b97
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=44437289728655410756371363671456613463927973759340023687258992613863928826591 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.44437289728655410756371363671456613463927973759340023687258992613863928826591
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.50348967959699996346578098328865899214576561423111295507700269464819258641615
Short name T121
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.58 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:29 PM PST 23
Peak memory 201936 kb
Host smart-e19925a5-38a0-41fb-bf76-4708df1a1850
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=50348967959699996346578098328865899214576561423111295507700269464819258641615 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.50348967959699996346578098328865899214576561423111295507700269464819258641615
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.77636253526057783084893880335650696076653638189897671538541742252725668510339
Short name T765
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.45 seconds
Started Nov 22 01:40:43 PM PST 23
Finished Nov 22 01:40:58 PM PST 23
Peak memory 201924 kb
Host smart-c6f875e3-1507-4316-88b7-d0f4db5eb831
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=77636253526057783084893880335650696076653638189897671538541742252725668510339 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 23.xbar_error_random.77636253526057783084893880335650696076653638189897671538541742252725668510339
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.52708720337995129700622369956773384497099684076701887059779369757770483268760
Short name T66
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.21 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:40:51 PM PST 23
Peak memory 201444 kb
Host smart-21514761-daa2-4152-9f45-94451fba6e46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=52708720337995129700622369956773384497099684076701887059779369757770483268760 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 23.xbar_random.52708720337995129700622369956773384497099684076701887059779369757770483268760
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.107827629015279006096798042171520599520369209037002838373784217122716256640365
Short name T588
Test name
Test status
Simulation time 237556670935 ps
CPU time 186.52 seconds
Started Nov 22 01:40:39 PM PST 23
Finished Nov 22 01:43:47 PM PST 23
Peak memory 201852 kb
Host smart-33ad7a96-ecf1-4a4e-b24d-b4b9696447cd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=107827629015279006096798042171520599520369209037002838373784217122716256640365 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.107827629015279006096798042171520599520369209037002838373784217122716256640365
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.28654715395406377651666929196121329703322404730827275085913371030659960087030
Short name T195
Test name
Test status
Simulation time 160909483435 ps
CPU time 191.36 seconds
Started Nov 22 01:40:41 PM PST 23
Finished Nov 22 01:43:53 PM PST 23
Peak memory 201976 kb
Host smart-52ccce8c-e8bc-466b-908a-7f9b010f3658
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=28654715395406377651666929196121329703322404730827275085913371030659960087030 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.28654715395406377651666929196121329703322404730827275085913371030659960087030
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.17196608620318389173115421660515858384599064124443738562306400497512016752309
Short name T862
Test name
Test status
Simulation time 360920935 ps
CPU time 7.96 seconds
Started Nov 22 01:40:41 PM PST 23
Finished Nov 22 01:40:50 PM PST 23
Peak memory 201940 kb
Host smart-a94d1f9e-4eb4-4b54-b1ea-60b8e53d51f7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17196608620318389173115421660515858384599064124443738562306400497512016752309 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.17196608620318389173115421660515858384599064124443738562306400497512016752309
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.46738213404152384298705246403861315447340028817573535309827023036349759401517
Short name T319
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.9 seconds
Started Nov 22 01:40:31 PM PST 23
Finished Nov 22 01:40:44 PM PST 23
Peak memory 201852 kb
Host smart-c44c45d9-c2b9-4891-b897-59e9c07861ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46738213404152384298705246403861315447340028817573535309827023036349759401517 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 23.xbar_same_source.46738213404152384298705246403861315447340028817573535309827023036349759401517
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.3617590276020453944017990064508753491894437089192937541954584472071395718117
Short name T182
Test name
Test status
Simulation time 331233435 ps
CPU time 1.73 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:41:24 PM PST 23
Peak memory 201748 kb
Host smart-18312642-e843-4c5c-9b27-21bd8e14d1b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3617590276020453944017990064508753491894437089192937541954584472071395718117 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 23.xbar_smoke.3617590276020453944017990064508753491894437089192937541954584472071395718117
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.98188621466692872359846258269510664506917667782327325202225215992253981898624
Short name T554
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.74 seconds
Started Nov 22 01:40:27 PM PST 23
Finished Nov 22 01:40:40 PM PST 23
Peak memory 202020 kb
Host smart-92448c21-f36b-4516-8e19-d01923038587
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=98188621466692872359846258269510664506917667782327325202225215992253981898624 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.98188621466692872359846258269510664506917667782327325202225215992253981898624
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.95612768371634519710589161505105558276918110588890393485743044953518270665782
Short name T635
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.88 seconds
Started Nov 22 01:40:39 PM PST 23
Finished Nov 22 01:40:53 PM PST 23
Peak memory 201968 kb
Host smart-fb9436bb-d1e4-4c1c-b1fc-90514342ecde
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=95612768371634519710589161505105558276918110588890393485743044953518270665782 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.95612768371634519710589161505105558276918110588890393485743044953518270665782
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.50162141171684068912611681284308833942102380131266568114376787531693861470445
Short name T186
Test name
Test status
Simulation time 27670935 ps
CPU time 1.16 seconds
Started Nov 22 01:40:58 PM PST 23
Finished Nov 22 01:41:01 PM PST 23
Peak memory 201916 kb
Host smart-f41322d7-7889-4ab0-bb44-e0f8fa5028c1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50162141171684068912611681284308833942102380131266568114376787531693861470445 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.50162141171684068912611681284308833942102380131266568114376787531693861470445
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.51433585999994007338564563658201531541594833006841435122506996635931381896425
Short name T76
Test name
Test status
Simulation time 46147859184 ps
CPU time 132.19 seconds
Started Nov 22 01:40:57 PM PST 23
Finished Nov 22 01:43:11 PM PST 23
Peak memory 203220 kb
Host smart-5f9bb156-a1e5-4e04-b37e-dda944697dd0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=51433585999994007338564563658201531541594833006841435122506996635931381896425 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 23.xbar_stress_all.51433585999994007338564563658201531541594833006841435122506996635931381896425
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.24567276492996179066438602074610949239174395135568918918722874920068081455143
Short name T398
Test name
Test status
Simulation time 46147859184 ps
CPU time 122.15 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:43:19 PM PST 23
Peak memory 204904 kb
Host smart-c0dc55af-390b-4370-b9af-abd8989b6974
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24567276492996179066438602074610949239174395135568918918722874920068081455143 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 23.xbar_stress_all_with_error.24567276492996179066438602074610949239174395135568918918722874920068081455143
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.115497849124201801755337668347798682752971174212861080706422726191637471715283
Short name T772
Test name
Test status
Simulation time 13716459184 ps
CPU time 164.24 seconds
Started Nov 22 01:40:42 PM PST 23
Finished Nov 22 01:43:27 PM PST 23
Peak memory 205160 kb
Host smart-a873b7fe-6001-4103-9d3e-1f4afcc36a44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115497849124201801755337668347798682752971174212861080706422726191637471715283 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.115497849124201801755337668347798682752971174212861080706422726191637471715283
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.14907180419225758263482284307883277166503028216457637930617178165753963460019
Short name T858
Test name
Test status
Simulation time 13716459184 ps
CPU time 138.67 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:43:35 PM PST 23
Peak memory 206228 kb
Host smart-662b8b45-57a5-41b9-9f4d-d90784067ccd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14907180419225758263482284307883277166503028216457637930617178165753963460019 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.14907180419225758263482284307883277166503028216457637930617178165753963460019
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.96636591856456283105024801048188102744905356607937372113812271641618526223961
Short name T630
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.59 seconds
Started Nov 22 01:41:10 PM PST 23
Finished Nov 22 01:41:22 PM PST 23
Peak memory 201804 kb
Host smart-bc5bca48-a7a6-49a2-8445-1e3e63c5ab4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96636591856456283105024801048188102744905356607937372113812271641618526223961 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 23.xbar_unmapped_addr.96636591856456283105024801048188102744905356607937372113812271641618526223961
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.110423629242982226667042794457783951990418469617052806770892424609681016048984
Short name T549
Test name
Test status
Simulation time 4712795935 ps
CPU time 16.5 seconds
Started Nov 22 01:40:43 PM PST 23
Finished Nov 22 01:41:00 PM PST 23
Peak memory 201876 kb
Host smart-b440575c-c797-4b39-9ef9-01f044567518
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110423629242982226667042794457783951990418469617052806770892424609681016048984 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.110423629242982226667042794457783951990418469617052806770892424609681016048984
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.112060050833275982987209810293051881245530607018795373550096467665347444249293
Short name T418
Test name
Test status
Simulation time 260306045935 ps
CPU time 340.86 seconds
Started Nov 22 01:41:12 PM PST 23
Finished Nov 22 01:46:55 PM PST 23
Peak memory 202924 kb
Host smart-df5eecbd-6efc-4ba8-8acb-ab400981cbeb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=112060050833275982987209810293051881245530607018795373550096467665347444249293 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.112060050833275982987209810293051881245530607018795373550096467665347444249293
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.16771002475387766227866700995496617845226832748073429731580651719697828405284
Short name T755
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.16 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:41:31 PM PST 23
Peak memory 201940 kb
Host smart-cf161e73-a8b4-49f0-922f-7a0598a958f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16771002475387766227866700995496617845226832748073429731580651719697828405284 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.16771002475387766227866700995496617845226832748073429731580651719697828405284
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.55183053338591295782409139679439130236465030024159486508333961876230258668633
Short name T423
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.13 seconds
Started Nov 22 01:40:46 PM PST 23
Finished Nov 22 01:41:00 PM PST 23
Peak memory 201896 kb
Host smart-bfc3ed45-130a-40b8-a078-5db1a552278a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55183053338591295782409139679439130236465030024159486508333961876230258668633 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 24.xbar_error_random.55183053338591295782409139679439130236465030024159486508333961876230258668633
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.95530861876356983158505139471843852367508554194422073597741216538003457448069
Short name T697
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.51 seconds
Started Nov 22 01:40:57 PM PST 23
Finished Nov 22 01:41:13 PM PST 23
Peak memory 201912 kb
Host smart-954593c6-a849-4c68-8ad6-8cbf74bdc8e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95530861876356983158505139471843852367508554194422073597741216538003457448069 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 24.xbar_random.95530861876356983158505139471843852367508554194422073597741216538003457448069
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.36922264345438966267533149366041307574462424967311977556197208397979535266711
Short name T735
Test name
Test status
Simulation time 160909483435 ps
CPU time 193.59 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:44:31 PM PST 23
Peak memory 202008 kb
Host smart-8e90f93c-e405-4e72-af05-a9a02af51116
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=36922264345438966267533149366041307574462424967311977556197208397979535266711 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.36922264345438966267533149366041307574462424967311977556197208397979535266711
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.26497328064719185808317076954053188779664712321183341799433318129695955140547
Short name T36
Test name
Test status
Simulation time 360920935 ps
CPU time 8.12 seconds
Started Nov 22 01:40:55 PM PST 23
Finished Nov 22 01:41:04 PM PST 23
Peak memory 201836 kb
Host smart-6cf3fc8a-8277-476d-bfea-eeef0e728441
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26497328064719185808317076954053188779664712321183341799433318129695955140547 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.26497328064719185808317076954053188779664712321183341799433318129695955140547
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.57852696509093277268177266834122843747395995242016812870349711917942785835864
Short name T327
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.51 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:41:32 PM PST 23
Peak memory 201988 kb
Host smart-7c9e07d3-e3fa-490f-be0f-4a12c4af3f0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57852696509093277268177266834122843747395995242016812870349711917942785835864 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 24.xbar_same_source.57852696509093277268177266834122843747395995242016812870349711917942785835864
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.99263048452112162039504948840532386369185897765106407669083822379784801249799
Short name T459
Test name
Test status
Simulation time 331233435 ps
CPU time 1.62 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:22 PM PST 23
Peak memory 201928 kb
Host smart-2618731b-3974-44a6-b6d6-b58745f15e8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99263048452112162039504948840532386369185897765106407669083822379784801249799 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 24.xbar_smoke.99263048452112162039504948840532386369185897765106407669083822379784801249799
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.27400717550529099057133111949951051804681418218651490235149889161442254602128
Short name T585
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.78 seconds
Started Nov 22 01:41:12 PM PST 23
Finished Nov 22 01:41:27 PM PST 23
Peak memory 202004 kb
Host smart-075877e3-3432-4557-ab2a-9c9c37c46405
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=27400717550529099057133111949951051804681418218651490235149889161442254602128 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.27400717550529099057133111949951051804681418218651490235149889161442254602128
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.100375074134478190900764224759707518440912783499532960362867392191592632229214
Short name T179
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.98 seconds
Started Nov 22 01:40:40 PM PST 23
Finished Nov 22 01:40:54 PM PST 23
Peak memory 201968 kb
Host smart-08b52ead-b0ad-45b8-b4ef-20c8da16355b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=100375074134478190900764224759707518440912783499532960362867392191592632229214 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.100375074134478190900764224759707518440912783499532960362867392191592632229214
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.103269139454036260197925862846177745272318495596373070436983321206212475289838
Short name T631
Test name
Test status
Simulation time 27670935 ps
CPU time 1.2 seconds
Started Nov 22 01:40:48 PM PST 23
Finished Nov 22 01:40:51 PM PST 23
Peak memory 201936 kb
Host smart-cb48b189-16da-4769-8fc9-fa27a432f9c4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103269139454036260197925862846177745272318495596373070436983321206212475289838 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.103269139454036260197925862846177745272318495596373070436983321206212475289838
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.76131764461937522303443718197489810466721930198879327385781478215424215283282
Short name T733
Test name
Test status
Simulation time 46147859184 ps
CPU time 129.61 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:43:26 PM PST 23
Peak memory 203224 kb
Host smart-3ea085ec-c864-4adc-bc46-84b005dc67f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76131764461937522303443718197489810466721930198879327385781478215424215283282 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 24.xbar_stress_all.76131764461937522303443718197489810466721930198879327385781478215424215283282
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.41593071024531308639628895073573476275898934734132638074359238482788256751676
Short name T456
Test name
Test status
Simulation time 46147859184 ps
CPU time 117.58 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:43:14 PM PST 23
Peak memory 204884 kb
Host smart-7700745a-3de4-463a-9520-6a1a2c669077
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=41593071024531308639628895073573476275898934734132638074359238482788256751676 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 24.xbar_stress_all_with_error.41593071024531308639628895073573476275898934734132638074359238482788256751676
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.107446354861184923659804317265699857978737823881215009345517060261054905937507
Short name T714
Test name
Test status
Simulation time 13716459184 ps
CPU time 163.34 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:44:03 PM PST 23
Peak memory 205168 kb
Host smart-998936b0-aa71-4900-96f7-c4ceebfa29ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=107446354861184923659804317265699857978737823881215009345517060261054905937507 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.107446354861184923659804317265699857978737823881215009345517060261054905937507
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.4304253032330681980691279909951137766324605830762789766845376090876713019813
Short name T175
Test name
Test status
Simulation time 13716459184 ps
CPU time 136.09 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:43:36 PM PST 23
Peak memory 206260 kb
Host smart-1f709f98-20e8-4dbc-837d-042c31d4eb50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4304253032330681980691279909951137766324605830762789766845376090876713019813 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.4304253032330681980691279909951137766324605830762789766845376090876713019813
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.39082779040392937878109358005990307570656551554858094006566593084766255693907
Short name T442
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.17 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:41:28 PM PST 23
Peak memory 202008 kb
Host smart-4a99be7f-5c65-4c87-bcd8-a0985e2f045c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=39082779040392937878109358005990307570656551554858094006566593084766255693907 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 24.xbar_unmapped_addr.39082779040392937878109358005990307570656551554858094006566593084766255693907
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.77783057072940031357194764113127122734793098803551514607938049170412803685974
Short name T885
Test name
Test status
Simulation time 4712795935 ps
CPU time 16.84 seconds
Started Nov 22 01:40:40 PM PST 23
Finished Nov 22 01:40:58 PM PST 23
Peak memory 201924 kb
Host smart-fd9dde4b-8fc8-4f44-922c-c32f0a9ec662
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=77783057072940031357194764113127122734793098803551514607938049170412803685974 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.77783057072940031357194764113127122734793098803551514607938049170412803685974
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.27882306844198648483841598821001629872284568671047468740379779106902770189411
Short name T353
Test name
Test status
Simulation time 260306045935 ps
CPU time 337.42 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:46:56 PM PST 23
Peak memory 202492 kb
Host smart-211b83f7-ed95-4e11-85e8-1f5ae06c080a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=27882306844198648483841598821001629872284568671047468740379779106902770189411 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.27882306844198648483841598821001629872284568671047468740379779106902770189411
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.12972100692164680575880168929210422550588207790591266482599165180490437752132
Short name T336
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.92 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:41:26 PM PST 23
Peak memory 201928 kb
Host smart-020dd16c-3e99-43f0-9a17-a61a7be6381e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12972100692164680575880168929210422550588207790591266482599165180490437752132 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.12972100692164680575880168929210422550588207790591266482599165180490437752132
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.74769255656986077551487078983269811522100015673098334040563681792199011384111
Short name T24
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.76 seconds
Started Nov 22 01:40:58 PM PST 23
Finished Nov 22 01:41:14 PM PST 23
Peak memory 201988 kb
Host smart-ee5813d1-e243-42c2-ba65-16980c857ddd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=74769255656986077551487078983269811522100015673098334040563681792199011384111 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 25.xbar_error_random.74769255656986077551487078983269811522100015673098334040563681792199011384111
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.88585795771569409769290897322937233849059013967372524870136532395227417779314
Short name T65
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.89 seconds
Started Nov 22 01:40:42 PM PST 23
Finished Nov 22 01:40:57 PM PST 23
Peak memory 201912 kb
Host smart-a20a3221-2f2b-44e4-9324-6f3b679b0606
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=88585795771569409769290897322937233849059013967372524870136532395227417779314 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 25.xbar_random.88585795771569409769290897322937233849059013967372524870136532395227417779314
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.31322098125935472893548291394037041694436717253633528894037749806607655081467
Short name T545
Test name
Test status
Simulation time 237556670935 ps
CPU time 189.39 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:44:25 PM PST 23
Peak memory 201980 kb
Host smart-ea2e5666-86a3-4997-ae3a-621461319e81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=31322098125935472893548291394037041694436717253633528894037749806607655081467 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 25.xbar_random_large_delays.31322098125935472893548291394037041694436717253633528894037749806607655081467
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.66390103909326897101201240702283781849508747889122955079033723894604724926912
Short name T667
Test name
Test status
Simulation time 160909483435 ps
CPU time 193.38 seconds
Started Nov 22 01:40:51 PM PST 23
Finished Nov 22 01:44:05 PM PST 23
Peak memory 201944 kb
Host smart-915a3a3a-e945-46be-8505-35c1cd04172a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=66390103909326897101201240702283781849508747889122955079033723894604724926912 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.66390103909326897101201240702283781849508747889122955079033723894604724926912
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.5836343756258265724647405604694305402417505987686337941255010424887106584390
Short name T706
Test name
Test status
Simulation time 360920935 ps
CPU time 7.84 seconds
Started Nov 22 01:41:09 PM PST 23
Finished Nov 22 01:41:19 PM PST 23
Peak memory 201908 kb
Host smart-9d504e64-1b7e-4e1a-a086-71e0c14bcdf9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5836343756258265724647405604694305402417505987686337941255010424887106584390 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.5836343756258265724647405604694305402417505987686337941255010424887106584390
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.31823169326198851489402426367090255928400263846301307517122022486949755836695
Short name T171
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.33 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:31 PM PST 23
Peak memory 201980 kb
Host smart-dac5d181-1dc4-48fa-bc49-40aaf954fdad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31823169326198851489402426367090255928400263846301307517122022486949755836695 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 25.xbar_same_source.31823169326198851489402426367090255928400263846301307517122022486949755836695
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.34186779488690048256693632048551292171698488802709564041120603097686200446408
Short name T41
Test name
Test status
Simulation time 331233435 ps
CPU time 1.62 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:20 PM PST 23
Peak memory 201788 kb
Host smart-6522157e-e0d3-4684-935b-1ff907d80ec0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34186779488690048256693632048551292171698488802709564041120603097686200446408 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 25.xbar_smoke.34186779488690048256693632048551292171698488802709564041120603097686200446408
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.60214557195055953912763444075634865584773921075066096701566067312326822193260
Short name T864
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.76 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:32 PM PST 23
Peak memory 201964 kb
Host smart-b7f609fb-f348-483a-bfa3-928514495f3a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=60214557195055953912763444075634865584773921075066096701566067312326822193260 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.60214557195055953912763444075634865584773921075066096701566067312326822193260
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.40362545561647533628823761609194670897750732765863712499498836914432265239536
Short name T114
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.84 seconds
Started Nov 22 01:40:41 PM PST 23
Finished Nov 22 01:40:54 PM PST 23
Peak memory 201916 kb
Host smart-0e2a4c45-155a-4208-90e9-dfe7bce4e257
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=40362545561647533628823761609194670897750732765863712499498836914432265239536 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.40362545561647533628823761609194670897750732765863712499498836914432265239536
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.57163959858394886105068184294647365691600393992929548903697067129262779990005
Short name T200
Test name
Test status
Simulation time 27670935 ps
CPU time 1.21 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:41:17 PM PST 23
Peak memory 201876 kb
Host smart-bc1d561e-ba13-4bb0-be8d-0d63e042b02d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57163959858394886105068184294647365691600393992929548903697067129262779990005 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.57163959858394886105068184294647365691600393992929548903697067129262779990005
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.55561865484329161895723817169074480284243403364064956361524579965705541932457
Short name T611
Test name
Test status
Simulation time 46147859184 ps
CPU time 127.17 seconds
Started Nov 22 01:40:41 PM PST 23
Finished Nov 22 01:42:49 PM PST 23
Peak memory 203184 kb
Host smart-8800bd8f-af8e-4a31-947f-4d91c49a8b27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55561865484329161895723817169074480284243403364064956361524579965705541932457 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 25.xbar_stress_all.55561865484329161895723817169074480284243403364064956361524579965705541932457
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.105406456673535135376371762717771202409233647726292486244211612615685627787860
Short name T620
Test name
Test status
Simulation time 46147859184 ps
CPU time 118.73 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:43:17 PM PST 23
Peak memory 203024 kb
Host smart-21ffcefd-a89f-413c-b523-4cf1230aca5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105406456673535135376371762717771202409233647726292486244211612615685627787860 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.105406456673535135376371762717771202409233647726292486244211612615685627787860
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.51224436004343555047211554587953554208214352137584225270005810688479591115520
Short name T115
Test name
Test status
Simulation time 13716459184 ps
CPU time 158.16 seconds
Started Nov 22 01:41:19 PM PST 23
Finished Nov 22 01:43:59 PM PST 23
Peak memory 205140 kb
Host smart-16b37eae-180b-4cd2-8c2f-eabda2098973
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=51224436004343555047211554587953554208214352137584225270005810688479591115520 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.51224436004343555047211554587953554208214352137584225270005810688479591115520
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.98400900629469478524122009506777111048613719785534218108169372447315020863087
Short name T363
Test name
Test status
Simulation time 13716459184 ps
CPU time 137.14 seconds
Started Nov 22 01:41:13 PM PST 23
Finished Nov 22 01:43:32 PM PST 23
Peak memory 206272 kb
Host smart-a89a4087-f692-4276-97c4-9179ea3af2fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98400900629469478524122009506777111048613719785534218108169372447315020863087 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.98400900629469478524122009506777111048613719785534218108169372447315020863087
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.13013206608342839248850741207337063272778592997732512620603715746641694312829
Short name T707
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.46 seconds
Started Nov 22 01:41:29 PM PST 23
Finished Nov 22 01:41:42 PM PST 23
Peak memory 201968 kb
Host smart-ce67cbc2-e9f0-4f6f-90d1-21e03e701320
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13013206608342839248850741207337063272778592997732512620603715746641694312829 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 25.xbar_unmapped_addr.13013206608342839248850741207337063272778592997732512620603715746641694312829
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.328784259515916267458357796813516822632263046023838735826688339135615691430
Short name T769
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.01 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:41:34 PM PST 23
Peak memory 201648 kb
Host smart-0cec4118-2767-4684-ab08-578cef6cc322
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=328784259515916267458357796813516822632263046023838735826688339135615691430 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 26.xbar_access_same_device.328784259515916267458357796813516822632263046023838735826688339135615691430
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.36856400059581047647807494234053129692320162605363456242147428661720316201469
Short name T725
Test name
Test status
Simulation time 260306045935 ps
CPU time 331.89 seconds
Started Nov 22 01:41:23 PM PST 23
Finished Nov 22 01:46:56 PM PST 23
Peak memory 203032 kb
Host smart-1c3fe2c5-a54b-4598-8f73-cf77998416a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=36856400059581047647807494234053129692320162605363456242147428661720316201469 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.36856400059581047647807494234053129692320162605363456242147428661720316201469
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.62760816550099936919749082875023464916868289479456453712607247763189093405921
Short name T614
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.12 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:41:47 PM PST 23
Peak memory 201816 kb
Host smart-3288cd01-1b5f-48d4-af1e-6068dea71e24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62760816550099936919749082875023464916868289479456453712607247763189093405921 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.62760816550099936919749082875023464916868289479456453712607247763189093405921
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.11623887759382694934008173125853593925173519146267885523154767863922281350469
Short name T305
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.47 seconds
Started Nov 22 01:40:41 PM PST 23
Finished Nov 22 01:40:55 PM PST 23
Peak memory 201968 kb
Host smart-0f706ad6-debc-4ce2-9ac8-082e288b58bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=11623887759382694934008173125853593925173519146267885523154767863922281350469 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 26.xbar_error_random.11623887759382694934008173125853593925173519146267885523154767863922281350469
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.60558579102858343086900638679854960875225053417539713598458208854244323935785
Short name T222
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.29 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:41:34 PM PST 23
Peak memory 201988 kb
Host smart-788a65ed-e8bf-4405-9410-31ecdd3cc3f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=60558579102858343086900638679854960875225053417539713598458208854244323935785 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 26.xbar_random.60558579102858343086900638679854960875225053417539713598458208854244323935785
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.23533256514274966223003381250786590968527687375123293129327440993649875056130
Short name T382
Test name
Test status
Simulation time 237556670935 ps
CPU time 187.3 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:44:27 PM PST 23
Peak memory 201940 kb
Host smart-1f2b35b8-0a04-4c24-97c4-1afd9214b504
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=23533256514274966223003381250786590968527687375123293129327440993649875056130 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 26.xbar_random_large_delays.23533256514274966223003381250786590968527687375123293129327440993649875056130
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.81903114181215882903222018568470620427477875493423033783918695903014376387725
Short name T39
Test name
Test status
Simulation time 160909483435 ps
CPU time 193.55 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:44:36 PM PST 23
Peak memory 201944 kb
Host smart-73e7df64-1029-422b-896a-610f65264ad1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=81903114181215882903222018568470620427477875493423033783918695903014376387725 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.81903114181215882903222018568470620427477875493423033783918695903014376387725
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.25662479133014181376668018094780566363509753577318667801552086789578213555333
Short name T328
Test name
Test status
Simulation time 360920935 ps
CPU time 8.49 seconds
Started Nov 22 01:40:50 PM PST 23
Finished Nov 22 01:41:00 PM PST 23
Peak memory 202032 kb
Host smart-7039a74f-4150-4e74-b223-744bbb91d724
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25662479133014181376668018094780566363509753577318667801552086789578213555333 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.25662479133014181376668018094780566363509753577318667801552086789578213555333
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.58413718143313302735272627894493321749961086131585087235341976589124831646157
Short name T295
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.35 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:30 PM PST 23
Peak memory 201924 kb
Host smart-6c4491bc-b0c8-46a8-a3f9-32ccad59c9aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=58413718143313302735272627894493321749961086131585087235341976589124831646157 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 26.xbar_same_source.58413718143313302735272627894493321749961086131585087235341976589124831646157
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.110548936159286821857859715510918801049618464485040093449532215136275052232905
Short name T105
Test name
Test status
Simulation time 331233435 ps
CPU time 1.54 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:41:23 PM PST 23
Peak memory 201888 kb
Host smart-2461d76d-9f8c-4db6-89fd-11a2fb969633
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110548936159286821857859715510918801049618464485040093449532215136275052232905 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 26.xbar_smoke.110548936159286821857859715510918801049618464485040093449532215136275052232905
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2030425716881051661249407126294807187123148428799630270971724336371926830918
Short name T562
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.74 seconds
Started Nov 22 01:41:10 PM PST 23
Finished Nov 22 01:41:24 PM PST 23
Peak memory 201964 kb
Host smart-3cbcfb0d-ac72-4cd9-bdac-bedabd95aa35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030425716881051661249407126294807187123148428799630270971724336371926830918 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2030425716881051661249407126294807187123148428799630270971724336371926830918
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.10256649084910844371076629037774492984652586700169996051370065916752653519575
Short name T572
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.46 seconds
Started Nov 22 01:41:31 PM PST 23
Finished Nov 22 01:41:45 PM PST 23
Peak memory 201972 kb
Host smart-32d43fb0-ad3b-479b-a3a6-7d88a1e1cce4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=10256649084910844371076629037774492984652586700169996051370065916752653519575 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.10256649084910844371076629037774492984652586700169996051370065916752653519575
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.62471820074544991026396331236512707769651928023946070487721726349238010385032
Short name T612
Test name
Test status
Simulation time 27670935 ps
CPU time 1.17 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:19 PM PST 23
Peak memory 201928 kb
Host smart-23a4ca63-21fc-49a6-99f1-41614bc4f0f5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62471820074544991026396331236512707769651928023946070487721726349238010385032 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.62471820074544991026396331236512707769651928023946070487721726349238010385032
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.13188274485644493625641146432656691045781428004471531208331587713187915634778
Short name T255
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.32 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:43:29 PM PST 23
Peak memory 203064 kb
Host smart-d07d58ab-07b3-4dfb-a640-7ae846dd0d23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13188274485644493625641146432656691045781428004471531208331587713187915634778 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 26.xbar_stress_all.13188274485644493625641146432656691045781428004471531208331587713187915634778
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.107621140156595351426365797775692049568482805395584248420760563418562612181187
Short name T221
Test name
Test status
Simulation time 46147859184 ps
CPU time 116.33 seconds
Started Nov 22 01:41:10 PM PST 23
Finished Nov 22 01:43:08 PM PST 23
Peak memory 203004 kb
Host smart-d857f664-1ed8-4bb4-98e1-9756c7c582f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=107621140156595351426365797775692049568482805395584248420760563418562612181187 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.107621140156595351426365797775692049568482805395584248420760563418562612181187
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.103845593977268720093430818998869960472034510653782362954472733658044066011769
Short name T684
Test name
Test status
Simulation time 13716459184 ps
CPU time 158.94 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:43:59 PM PST 23
Peak memory 205128 kb
Host smart-4dea048f-bc8d-4cab-905c-5fdf12aefd47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103845593977268720093430818998869960472034510653782362954472733658044066011769 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.103845593977268720093430818998869960472034510653782362954472733658044066011769
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.35100735815857065522087425341710872468972746114860330194238122017861329392216
Short name T126
Test name
Test status
Simulation time 13716459184 ps
CPU time 136.39 seconds
Started Nov 22 01:40:59 PM PST 23
Finished Nov 22 01:43:16 PM PST 23
Peak memory 206360 kb
Host smart-627c042c-c3cb-4a8e-837a-2b5cb60fb0d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35100735815857065522087425341710872468972746114860330194238122017861329392216 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.35100735815857065522087425341710872468972746114860330194238122017861329392216
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.68609363254008983195708269245340239239660675490851206206762820775873422624238
Short name T152
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.46 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:41:27 PM PST 23
Peak memory 201972 kb
Host smart-8362aed0-4939-4427-b1ae-004a0ecd908d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=68609363254008983195708269245340239239660675490851206206762820775873422624238 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 26.xbar_unmapped_addr.68609363254008983195708269245340239239660675490851206206762820775873422624238
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.46398531805023376595107231783297725916572253050379652004801560954990795697525
Short name T881
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.43 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:41:38 PM PST 23
Peak memory 201952 kb
Host smart-eb8a4903-5e04-436d-aa21-571eab2c51e8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46398531805023376595107231783297725916572253050379652004801560954990795697525 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.46398531805023376595107231783297725916572253050379652004801560954990795697525
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.24370602679997895049820786616513522848129016802101889830128131969533610778197
Short name T82
Test name
Test status
Simulation time 260306045935 ps
CPU time 337.3 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:46:56 PM PST 23
Peak memory 202468 kb
Host smart-3f0414fd-3039-4358-bc9e-c4875475b576
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=24370602679997895049820786616513522848129016802101889830128131969533610778197 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.24370602679997895049820786616513522848129016802101889830128131969533610778197
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.101479465599384372331282893135189861927571775130261150344079878599719798582283
Short name T496
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.1 seconds
Started Nov 22 01:40:56 PM PST 23
Finished Nov 22 01:41:07 PM PST 23
Peak memory 201872 kb
Host smart-81259b3f-f884-43c7-bf4d-e3678a4d234c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=101479465599384372331282893135189861927571775130261150344079878599719798582283 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.101479465599384372331282893135189861927571775130261150344079878599719798582283
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.92483306130065984727288121396032980184397773467974308221035987479335556397735
Short name T534
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.15 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:32 PM PST 23
Peak memory 201984 kb
Host smart-d30c7d22-d712-4179-9596-43da11e894ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92483306130065984727288121396032980184397773467974308221035987479335556397735 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 27.xbar_error_random.92483306130065984727288121396032980184397773467974308221035987479335556397735
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.51401817953417806537058041945980944783146432851079087418636302648373325469514
Short name T389
Test name
Test status
Simulation time 4923670935 ps
CPU time 15.04 seconds
Started Nov 22 01:40:41 PM PST 23
Finished Nov 22 01:40:57 PM PST 23
Peak memory 202004 kb
Host smart-59cc5a32-b4c1-434b-a034-e734c066394a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=51401817953417806537058041945980944783146432851079087418636302648373325469514 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 27.xbar_random.51401817953417806537058041945980944783146432851079087418636302648373325469514
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.94497955083672572340508059413231579471434898093297141118402358648684532616526
Short name T542
Test name
Test status
Simulation time 237556670935 ps
CPU time 191.22 seconds
Started Nov 22 01:40:47 PM PST 23
Finished Nov 22 01:43:59 PM PST 23
Peak memory 201980 kb
Host smart-15539687-e14e-4a4b-ad14-831b265e01d1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=94497955083672572340508059413231579471434898093297141118402358648684532616526 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 27.xbar_random_large_delays.94497955083672572340508059413231579471434898093297141118402358648684532616526
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.22098693681637348173116278981718541162013429287657353147578007941068117044459
Short name T847
Test name
Test status
Simulation time 160909483435 ps
CPU time 195.26 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:44:32 PM PST 23
Peak memory 201988 kb
Host smart-6847e8d1-f17e-464a-9786-0ad447bddf13
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=22098693681637348173116278981718541162013429287657353147578007941068117044459 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.22098693681637348173116278981718541162013429287657353147578007941068117044459
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.26996899833651654122875799857607767313256615667920410048830219924702284724392
Short name T829
Test name
Test status
Simulation time 360920935 ps
CPU time 7.87 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:28 PM PST 23
Peak memory 201784 kb
Host smart-f25c3093-3d67-40bb-8d09-5b0bce05a509
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26996899833651654122875799857607767313256615667920410048830219924702284724392 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.26996899833651654122875799857607767313256615667920410048830219924702284724392
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.1678737150847873297637741507282872540460582173114425880110635007084868725268
Short name T879
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.49 seconds
Started Nov 22 01:40:58 PM PST 23
Finished Nov 22 01:41:12 PM PST 23
Peak memory 201992 kb
Host smart-7bc3bcd0-72b4-4f9f-b579-d3abe3341a56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1678737150847873297637741507282872540460582173114425880110635007084868725268 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 27.xbar_same_source.1678737150847873297637741507282872540460582173114425880110635007084868725268
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.111165693847273261677550401315151765234137768443217877847811859173961568381468
Short name T119
Test name
Test status
Simulation time 331233435 ps
CPU time 1.62 seconds
Started Nov 22 01:41:08 PM PST 23
Finished Nov 22 01:41:10 PM PST 23
Peak memory 201904 kb
Host smart-151a933e-748a-482c-a67f-326678d296ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111165693847273261677550401315151765234137768443217877847811859173961568381468 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 27.xbar_smoke.111165693847273261677550401315151765234137768443217877847811859173961568381468
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.27199557351497118817490595333333653693439282942298961555497610514579983071543
Short name T750
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.89 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:32 PM PST 23
Peak memory 201964 kb
Host smart-ff5755a7-270f-431b-877c-b11d7f842fbf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=27199557351497118817490595333333653693439282942298961555497610514579983071543 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.27199557351497118817490595333333653693439282942298961555497610514579983071543
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.95368302836202629814368077589305395026640270260610887520030313909192743658942
Short name T315
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.73 seconds
Started Nov 22 01:41:11 PM PST 23
Finished Nov 22 01:41:24 PM PST 23
Peak memory 201908 kb
Host smart-1bcf28f4-c854-4bf6-a6c6-95da19319cc6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=95368302836202629814368077589305395026640270260610887520030313909192743658942 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.95368302836202629814368077589305395026640270260610887520030313909192743658942
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.5754518569404624159055613211354629625609507060152561072664308792662025062879
Short name T178
Test name
Test status
Simulation time 27670935 ps
CPU time 1.14 seconds
Started Nov 22 01:41:13 PM PST 23
Finished Nov 22 01:41:16 PM PST 23
Peak memory 201936 kb
Host smart-0111a2f8-1e80-406b-954f-1aabfc41b958
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5754518569404624159055613211354629625609507060152561072664308792662025062879 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.5754518569404624159055613211354629625609507060152561072664308792662025062879
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.55768020844567177287956055533822933844049587326285155538213797472953501536060
Short name T486
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.24 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:43:25 PM PST 23
Peak memory 203208 kb
Host smart-dbe08b30-5638-446f-a13c-94580a2d1e52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55768020844567177287956055533822933844049587326285155538213797472953501536060 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 27.xbar_stress_all.55768020844567177287956055533822933844049587326285155538213797472953501536060
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.69729744746760926195739478491256697585527517992846007214942131845057330166710
Short name T180
Test name
Test status
Simulation time 46147859184 ps
CPU time 117.61 seconds
Started Nov 22 01:41:32 PM PST 23
Finished Nov 22 01:43:31 PM PST 23
Peak memory 204880 kb
Host smart-54fc692e-847e-4075-a4aa-33cdde1b5107
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69729744746760926195739478491256697585527517992846007214942131845057330166710 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 27.xbar_stress_all_with_error.69729744746760926195739478491256697585527517992846007214942131845057330166710
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.99350769299908341836070486879165508511345328416960039252309576201751529401481
Short name T860
Test name
Test status
Simulation time 13716459184 ps
CPU time 162.3 seconds
Started Nov 22 01:41:01 PM PST 23
Finished Nov 22 01:43:44 PM PST 23
Peak memory 205160 kb
Host smart-69dd0d88-b995-4367-a18d-5dd74b21d4ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99350769299908341836070486879165508511345328416960039252309576201751529401481 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.99350769299908341836070486879165508511345328416960039252309576201751529401481
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.56419309026282965327084959231244595170855655836881252435221827427410247403846
Short name T247
Test name
Test status
Simulation time 13716459184 ps
CPU time 137.8 seconds
Started Nov 22 01:40:54 PM PST 23
Finished Nov 22 01:43:13 PM PST 23
Peak memory 206208 kb
Host smart-16893f61-a248-4b48-9d27-5aa696a86e3f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56419309026282965327084959231244595170855655836881252435221827427410247403846 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.56419309026282965327084959231244595170855655836881252435221827427410247403846
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.19259514608429111392878472580801779814058846699191731505416361368900264539452
Short name T422
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.68 seconds
Started Nov 22 01:41:08 PM PST 23
Finished Nov 22 01:41:20 PM PST 23
Peak memory 201904 kb
Host smart-da92d721-835b-49e4-853c-a0e15694ea6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=19259514608429111392878472580801779814058846699191731505416361368900264539452 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 27.xbar_unmapped_addr.19259514608429111392878472580801779814058846699191731505416361368900264539452
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.31183493042357877981309065740814210236645820826793440053803687058369465795162
Short name T109
Test name
Test status
Simulation time 4712795935 ps
CPU time 16.79 seconds
Started Nov 22 01:41:24 PM PST 23
Finished Nov 22 01:41:42 PM PST 23
Peak memory 201916 kb
Host smart-b50fb287-9fcc-425e-895d-135a17ec3887
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31183493042357877981309065740814210236645820826793440053803687058369465795162 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.31183493042357877981309065740814210236645820826793440053803687058369465795162
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.20599884094670704768318131578638087094628139153494688441106709808768402761063
Short name T834
Test name
Test status
Simulation time 260306045935 ps
CPU time 330.81 seconds
Started Nov 22 01:41:24 PM PST 23
Finished Nov 22 01:46:55 PM PST 23
Peak memory 203028 kb
Host smart-be1a70f9-62cc-4545-99a8-7d601bbf9874
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=20599884094670704768318131578638087094628139153494688441106709808768402761063 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.20599884094670704768318131578638087094628139153494688441106709808768402761063
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.104124096354718058155254998602072639493555479523917508901541605779263306625759
Short name T790
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.74 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:41:54 PM PST 23
Peak memory 201808 kb
Host smart-26366195-ce7e-4bc6-861f-472413e152d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104124096354718058155254998602072639493555479523917508901541605779263306625759 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.104124096354718058155254998602072639493555479523917508901541605779263306625759
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.35744343228531695197346905670834199329864417958213984945311533982521299575500
Short name T172
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.96 seconds
Started Nov 22 01:41:27 PM PST 23
Finished Nov 22 01:41:41 PM PST 23
Peak memory 201844 kb
Host smart-e9f754b2-a5a2-4e57-bb78-90c711a69d2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35744343228531695197346905670834199329864417958213984945311533982521299575500 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 28.xbar_error_random.35744343228531695197346905670834199329864417958213984945311533982521299575500
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.17553522986059541417922503324554160449893379517475515689785454400512293670439
Short name T814
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.01 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:41:36 PM PST 23
Peak memory 201928 kb
Host smart-f7e61d39-615c-4a84-9235-97b0af2323f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=17553522986059541417922503324554160449893379517475515689785454400512293670439 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 28.xbar_random.17553522986059541417922503324554160449893379517475515689785454400512293670439
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.80768244901016121254817534399474314965479429759019066145483461601679278828091
Short name T71
Test name
Test status
Simulation time 237556670935 ps
CPU time 186.75 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:44:25 PM PST 23
Peak memory 201904 kb
Host smart-5a4c251d-d646-40b4-a441-d4ce543d2a27
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=80768244901016121254817534399474314965479429759019066145483461601679278828091 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 28.xbar_random_large_delays.80768244901016121254817534399474314965479429759019066145483461601679278828091
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.68202600123592429556930403555397530831344496928990098719557265285550118563709
Short name T743
Test name
Test status
Simulation time 160909483435 ps
CPU time 191.45 seconds
Started Nov 22 01:41:23 PM PST 23
Finished Nov 22 01:44:36 PM PST 23
Peak memory 201928 kb
Host smart-ba3ac24b-6d0d-407d-8b16-ec2ab34a7dbf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=68202600123592429556930403555397530831344496928990098719557265285550118563709 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.68202600123592429556930403555397530831344496928990098719557265285550118563709
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.15456013835504260588385243766289027226803167048747381736725079542340981443187
Short name T883
Test name
Test status
Simulation time 360920935 ps
CPU time 7.42 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:41:45 PM PST 23
Peak memory 201844 kb
Host smart-af30d955-be99-41b1-ab39-8be80d8a79b8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15456013835504260588385243766289027226803167048747381736725079542340981443187 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.15456013835504260588385243766289027226803167048747381736725079542340981443187
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.29651814430158750319643907048806858277741449559490791632313129171851871867246
Short name T61
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.39 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:41:50 PM PST 23
Peak memory 201880 kb
Host smart-df98b7e4-4928-44c0-8450-3a1aa34614a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29651814430158750319643907048806858277741449559490791632313129171851871867246 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 28.xbar_same_source.29651814430158750319643907048806858277741449559490791632313129171851871867246
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.61671152904890154235088259970714057014666360983491228864094655407135775594538
Short name T715
Test name
Test status
Simulation time 331233435 ps
CPU time 1.57 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:41:24 PM PST 23
Peak memory 201756 kb
Host smart-b5b2b4bb-ce44-4900-be9f-1ffefca28a9a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=61671152904890154235088259970714057014666360983491228864094655407135775594538 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 28.xbar_smoke.61671152904890154235088259970714057014666360983491228864094655407135775594538
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.112172556495141530655297503109269098674900612058688375673811302678506903901380
Short name T471
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.81 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:41:40 PM PST 23
Peak memory 201956 kb
Host smart-b4fdc9a4-d377-4d23-a4ff-25fafb09ccfe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=112172556495141530655297503109269098674900612058688375673811302678506903901380 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.112172556495141530655297503109269098674900612058688375673811302678506903901380
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.31313957692224770982524525712794956954182367487654777984688287278889902967629
Short name T457
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.81 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:41:34 PM PST 23
Peak memory 201992 kb
Host smart-ce34232d-65a6-41ba-b868-3b459438fedb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=31313957692224770982524525712794956954182367487654777984688287278889902967629 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.31313957692224770982524525712794956954182367487654777984688287278889902967629
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.65396785277284220748204407894069592019704456446853455000392752109261816163519
Short name T629
Test name
Test status
Simulation time 27670935 ps
CPU time 1.25 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:41:18 PM PST 23
Peak memory 201932 kb
Host smart-98e1e89c-1ab9-4d13-aca8-6f35ad214ee9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65396785277284220748204407894069592019704456446853455000392752109261816163519 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.65396785277284220748204407894069592019704456446853455000392752109261816163519
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.109285334567922531420574763313858391178944316470973332440306903118423258781746
Short name T165
Test name
Test status
Simulation time 46147859184 ps
CPU time 123.75 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:43:43 PM PST 23
Peak memory 203192 kb
Host smart-e2e606e0-cd9a-442b-a227-650cfe0acda7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=109285334567922531420574763313858391178944316470973332440306903118423258781746 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 28.xbar_stress_all.109285334567922531420574763313858391178944316470973332440306903118423258781746
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.21976588274266245831922190263899338915448493446500543304759848146402131233969
Short name T582
Test name
Test status
Simulation time 46147859184 ps
CPU time 111.97 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:43:31 PM PST 23
Peak memory 204900 kb
Host smart-c6396a94-b4d5-4d8d-91c3-7a058802eb14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=21976588274266245831922190263899338915448493446500543304759848146402131233969 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 28.xbar_stress_all_with_error.21976588274266245831922190263899338915448493446500543304759848146402131233969
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.112645986660883783769203780027039454426297976994404325304301414791037655667917
Short name T553
Test name
Test status
Simulation time 13716459184 ps
CPU time 160.06 seconds
Started Nov 22 01:41:32 PM PST 23
Finished Nov 22 01:44:14 PM PST 23
Peak memory 205180 kb
Host smart-563269f6-bdcb-4f7a-b87c-bde21ae15ed1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112645986660883783769203780027039454426297976994404325304301414791037655667917 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.112645986660883783769203780027039454426297976994404325304301414791037655667917
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.49974168648462369655133139070981727682869304018329651830671579005903970390507
Short name T813
Test name
Test status
Simulation time 13716459184 ps
CPU time 135.45 seconds
Started Nov 22 01:42:03 PM PST 23
Finished Nov 22 01:44:26 PM PST 23
Peak memory 206196 kb
Host smart-8aa19555-9b3b-4112-b42a-96107e984bfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49974168648462369655133139070981727682869304018329651830671579005903970390507 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.49974168648462369655133139070981727682869304018329651830671579005903970390507
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.99084443013730974760771840446641939564158036969339258701242631634053256593962
Short name T49
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.76 seconds
Started Nov 22 01:41:32 PM PST 23
Finished Nov 22 01:41:45 PM PST 23
Peak memory 202012 kb
Host smart-9857e494-71ad-4cb9-b063-275459fd97c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99084443013730974760771840446641939564158036969339258701242631634053256593962 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 28.xbar_unmapped_addr.99084443013730974760771840446641939564158036969339258701242631634053256593962
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.15557918559592918526030870380074977797044591065066064924974101311614125452243
Short name T897
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.51 seconds
Started Nov 22 01:41:36 PM PST 23
Finished Nov 22 01:41:56 PM PST 23
Peak memory 202092 kb
Host smart-67bb1172-956e-486e-9705-84310a28b5a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15557918559592918526030870380074977797044591065066064924974101311614125452243 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.15557918559592918526030870380074977797044591065066064924974101311614125452243
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.52708088033977090942020980633617784276627787999450183591540758056218030006913
Short name T886
Test name
Test status
Simulation time 260306045935 ps
CPU time 331.53 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:47:22 PM PST 23
Peak memory 203020 kb
Host smart-eb420c41-7ce7-4d2e-8e39-a548daf25643
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=52708088033977090942020980633617784276627787999450183591540758056218030006913 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.52708088033977090942020980633617784276627787999450183591540758056218030006913
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1661554864372148424299856469467204401535692210872087536957456502727289763462
Short name T89
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.2 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:41:57 PM PST 23
Peak memory 201964 kb
Host smart-afb791c7-f16c-4483-bdc1-fc81391eee8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1661554864372148424299856469467204401535692210872087536957456502727289763462 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1661554864372148424299856469467204401535692210872087536957456502727289763462
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.55816065774783123287159832011973156957891135946763881360234413182638304661163
Short name T831
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.94 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:42:02 PM PST 23
Peak memory 201904 kb
Host smart-85dc8c7e-55df-4678-8fa2-16005c638251
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55816065774783123287159832011973156957891135946763881360234413182638304661163 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 29.xbar_error_random.55816065774783123287159832011973156957891135946763881360234413182638304661163
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.7091073563412830927980189572819242147941874367387633755789110976060082188144
Short name T540
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.71 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:42:02 PM PST 23
Peak memory 201892 kb
Host smart-a284a49b-636e-47fc-af14-9cc7c841d273
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=7091073563412830927980189572819242147941874367387633755789110976060082188144 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 29.xbar_random.7091073563412830927980189572819242147941874367387633755789110976060082188144
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.92056484498234022819765752187969068800623492050544685933347685856662553478280
Short name T346
Test name
Test status
Simulation time 237556670935 ps
CPU time 188.5 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:45:00 PM PST 23
Peak memory 201908 kb
Host smart-6d0aa68e-2dd5-4113-9827-69c54bd8195e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=92056484498234022819765752187969068800623492050544685933347685856662553478280 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 29.xbar_random_large_delays.92056484498234022819765752187969068800623492050544685933347685856662553478280
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.36328422710851543528958856408617490489102025730628844109750393626519639505411
Short name T58
Test name
Test status
Simulation time 160909483435 ps
CPU time 191.3 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:45:01 PM PST 23
Peak memory 202032 kb
Host smart-aad29e73-5be5-4bf9-ad2b-ea4ff191df2a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=36328422710851543528958856408617490489102025730628844109750393626519639505411 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.36328422710851543528958856408617490489102025730628844109750393626519639505411
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.91926607555944637975185502835620821767593093212868832403231494871695896533472
Short name T662
Test name
Test status
Simulation time 360920935 ps
CPU time 7.67 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:41:47 PM PST 23
Peak memory 201956 kb
Host smart-3cb48c37-5e2c-4818-9fd3-c3df0f3555f8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91926607555944637975185502835620821767593093212868832403231494871695896533472 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.91926607555944637975185502835620821767593093212868832403231494871695896533472
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.86918383594170668716343647426607148491246754538678153390899283335554019930746
Short name T517
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.87 seconds
Started Nov 22 01:41:47 PM PST 23
Finished Nov 22 01:42:01 PM PST 23
Peak memory 201992 kb
Host smart-18f47dcd-5c12-4efb-acaf-dc2839b10389
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86918383594170668716343647426607148491246754538678153390899283335554019930746 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 29.xbar_same_source.86918383594170668716343647426607148491246754538678153390899283335554019930746
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.112005392545917885511471550983544470103032969474088126069878015465711441754012
Short name T149
Test name
Test status
Simulation time 331233435 ps
CPU time 1.62 seconds
Started Nov 22 01:41:31 PM PST 23
Finished Nov 22 01:41:35 PM PST 23
Peak memory 201924 kb
Host smart-84745c85-652a-4f4d-abb1-e6ee100472f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112005392545917885511471550983544470103032969474088126069878015465711441754012 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 29.xbar_smoke.112005392545917885511471550983544470103032969474088126069878015465711441754012
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.112655904353318638241435797159800891968647250627964560198180149569565798927997
Short name T652
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.96 seconds
Started Nov 22 01:41:00 PM PST 23
Finished Nov 22 01:41:14 PM PST 23
Peak memory 201992 kb
Host smart-5eb73357-f73d-4f41-b7e2-668289aa713b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=112655904353318638241435797159800891968647250627964560198180149569565798927997 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.112655904353318638241435797159800891968647250627964560198180149569565798927997
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.54440699537725874947329168604786972499400229488707561192552330668827265794416
Short name T746
Test name
Test status
Simulation time 10098608435 ps
CPU time 13.08 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:41:57 PM PST 23
Peak memory 201920 kb
Host smart-d4678742-061a-416f-ba23-9ca3d1fdace9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=54440699537725874947329168604786972499400229488707561192552330668827265794416 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.54440699537725874947329168604786972499400229488707561192552330668827265794416
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.22475054661138883450468843545975330413224347599744303412621983498376547191575
Short name T857
Test name
Test status
Simulation time 27670935 ps
CPU time 1.15 seconds
Started Nov 22 01:41:27 PM PST 23
Finished Nov 22 01:41:29 PM PST 23
Peak memory 201820 kb
Host smart-36d6c750-917d-4069-99dd-6d6d1946da80
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22475054661138883450468843545975330413224347599744303412621983498376547191575 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.22475054661138883450468843545975330413224347599744303412621983498376547191575
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.6517687550186036915500199862183733128439889452703461489727640219066750601923
Short name T453
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.34 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:43:52 PM PST 23
Peak memory 203184 kb
Host smart-5f45fb1e-096a-4166-a171-23c1008c595f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6517687550186036915500199862183733128439889452703461489727640219066750601923 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_
log /dev/null -cm_name 29.xbar_stress_all.6517687550186036915500199862183733128439889452703461489727640219066750601923
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.105123982710980612608324156330945369988710496016123531301515065029701089956399
Short name T570
Test name
Test status
Simulation time 46147859184 ps
CPU time 113.65 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:43:46 PM PST 23
Peak memory 202924 kb
Host smart-1d664faf-f541-44d6-ae98-2c3a4779bc59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105123982710980612608324156330945369988710496016123531301515065029701089956399 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.105123982710980612608324156330945369988710496016123531301515065029701089956399
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.103834433293509283037605886332909608621181506848322156561553413475985457250676
Short name T207
Test name
Test status
Simulation time 13716459184 ps
CPU time 157.42 seconds
Started Nov 22 01:41:51 PM PST 23
Finished Nov 22 01:44:30 PM PST 23
Peak memory 204988 kb
Host smart-cc5c62d9-7d14-45d9-ad42-789e0a8d79aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103834433293509283037605886332909608621181506848322156561553413475985457250676 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.103834433293509283037605886332909608621181506848322156561553413475985457250676
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.38583879045782893735746185341887669939700255798885805696402738916086577356312
Short name T402
Test name
Test status
Simulation time 13716459184 ps
CPU time 131.44 seconds
Started Nov 22 01:41:57 PM PST 23
Finished Nov 22 01:44:12 PM PST 23
Peak memory 206072 kb
Host smart-7807a863-ca47-4d18-899f-b57e567b7be9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=38583879045782893735746185341887669939700255798885805696402738916086577356312 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.38583879045782893735746185341887669939700255798885805696402738916086577356312
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.75100427081288527198919743670194470946972148584433167362728302413856731844588
Short name T458
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.36 seconds
Started Nov 22 01:41:10 PM PST 23
Finished Nov 22 01:41:23 PM PST 23
Peak memory 201972 kb
Host smart-765a9602-2c05-4f4d-badb-64265cbe1c3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=75100427081288527198919743670194470946972148584433167362728302413856731844588 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 29.xbar_unmapped_addr.75100427081288527198919743670194470946972148584433167362728302413856731844588
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.80830224073083705011487044822019805629215550141223083826185408566543636472340
Short name T258
Test name
Test status
Simulation time 4712795935 ps
CPU time 20.09 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:40:31 PM PST 23
Peak memory 201976 kb
Host smart-451b0d4f-ac54-4155-ae47-c52338ac66e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=80830224073083705011487044822019805629215550141223083826185408566543636472340 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.80830224073083705011487044822019805629215550141223083826185408566543636472340
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.49020523182220595100080183955174217346411965184654795789944949240719173297687
Short name T83
Test name
Test status
Simulation time 260306045935 ps
CPU time 337.06 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:45:38 PM PST 23
Peak memory 202908 kb
Host smart-bebc21b8-7ba0-4af3-ac94-54c0b74f1b12
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=49020523182220595100080183955174217346411965184654795789944949240719173297687 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.49020523182220595100080183955174217346411965184654795789944949240719173297687
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.102105894279340491781986528371191415884459614407717059967859886783292730592862
Short name T190
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.3 seconds
Started Nov 22 01:40:16 PM PST 23
Finished Nov 22 01:40:27 PM PST 23
Peak memory 201964 kb
Host smart-9378efa0-a737-4c21-bfc4-036efef7e79f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102105894279340491781986528371191415884459614407717059967859886783292730592862 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.102105894279340491781986528371191415884459614407717059967859886783292730592862
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.67143002293871025050291990194160817334867888962710974722366222033818994412336
Short name T378
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.99 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:16 PM PST 23
Peak memory 201880 kb
Host smart-da168cc3-49aa-4323-b0e7-1cddc1227d6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=67143002293871025050291990194160817334867888962710974722366222033818994412336 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 3.xbar_error_random.67143002293871025050291990194160817334867888962710974722366222033818994412336
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.72380792808830778691649866678996500139790532253089577083199052350890475666862
Short name T62
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.66 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:40:19 PM PST 23
Peak memory 201860 kb
Host smart-c3aa9a7e-790a-4407-a704-24a21a8457dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72380792808830778691649866678996500139790532253089577083199052350890475666862 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 3.xbar_random.72380792808830778691649866678996500139790532253089577083199052350890475666862
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.106186695354698788947926212517902565559082129120957664955999629167178324582816
Short name T440
Test name
Test status
Simulation time 237556670935 ps
CPU time 188.6 seconds
Started Nov 22 01:40:03 PM PST 23
Finished Nov 22 01:43:14 PM PST 23
Peak memory 201952 kb
Host smart-ff06a4c3-732b-4d7a-acb5-a5182f51a656
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=106186695354698788947926212517902565559082129120957664955999629167178324582816 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.106186695354698788947926212517902565559082129120957664955999629167178324582816
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.51477874313387681582385402575156780725420634811223291783088796690012693358339
Short name T146
Test name
Test status
Simulation time 160909483435 ps
CPU time 192.02 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:43:13 PM PST 23
Peak memory 202016 kb
Host smart-9baf40fb-b77c-466f-b680-7568a9565f04
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=51477874313387681582385402575156780725420634811223291783088796690012693358339 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.51477874313387681582385402575156780725420634811223291783088796690012693358339
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.56267258589506316189436380424715275195475163999455615804361891560060937805047
Short name T38
Test name
Test status
Simulation time 360920935 ps
CPU time 7.76 seconds
Started Nov 22 01:40:17 PM PST 23
Finished Nov 22 01:40:26 PM PST 23
Peak memory 201940 kb
Host smart-d62473b6-bfce-418b-9bf7-350597f92ae9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56267258589506316189436380424715275195475163999455615804361891560060937805047 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.56267258589506316189436380424715275195475163999455615804361891560060937805047
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.74386435382378902213452418002136159605845208990511921883043184648631992806107
Short name T844
Test name
Test status
Simulation time 5235733435 ps
CPU time 13.25 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:40:18 PM PST 23
Peak memory 201988 kb
Host smart-3983e555-55a1-41b8-9f8f-24ab63e19bda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=74386435382378902213452418002136159605845208990511921883043184648631992806107 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 3.xbar_same_source.74386435382378902213452418002136159605845208990511921883043184648631992806107
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.47733103432926789201945249585729106151536385838382082597343973562544432531772
Short name T797
Test name
Test status
Simulation time 331233435 ps
CPU time 1.7 seconds
Started Nov 22 01:39:54 PM PST 23
Finished Nov 22 01:39:56 PM PST 23
Peak memory 201888 kb
Host smart-53d50f7a-f3d7-4314-841d-b55e72c00dd7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47733103432926789201945249585729106151536385838382082597343973562544432531772 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 3.xbar_smoke.47733103432926789201945249585729106151536385838382082597343973562544432531772
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1009357913345182244245523452091913817277351368135565170194254784219322785565
Short name T870
Test name
Test status
Simulation time 15405233435 ps
CPU time 13.04 seconds
Started Nov 22 01:40:18 PM PST 23
Finished Nov 22 01:40:33 PM PST 23
Peak memory 201972 kb
Host smart-99457fad-5a3b-48b1-8d80-e22c0911cb9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009357913345182244245523452091913817277351368135565170194254784219322785565 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1009357913345182244245523452091913817277351368135565170194254784219322785565
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.49595100481597488149188813225928774935331253413895146407689679277750888259752
Short name T603
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.86 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:40:22 PM PST 23
Peak memory 201864 kb
Host smart-fb4ef478-507c-4a29-8c90-dc43abe8859e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=49595100481597488149188813225928774935331253413895146407689679277750888259752 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.49595100481597488149188813225928774935331253413895146407689679277750888259752
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2622876166313027114197965578158879966030160610047179805268785821249939465776
Short name T124
Test name
Test status
Simulation time 27670935 ps
CPU time 1.14 seconds
Started Nov 22 01:39:53 PM PST 23
Finished Nov 22 01:39:55 PM PST 23
Peak memory 201888 kb
Host smart-efc574dc-d29b-4632-8ec5-f44d58b651ce
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622876166313027114197965578158879966030160610047179805268785821249939465776 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2622876166313027114197965578158879966030160610047179805268785821249939465776
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.20157286606813016235693011523349630383582444920001830055061747231937871323647
Short name T157
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.61 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:42:11 PM PST 23
Peak memory 203108 kb
Host smart-127b38e6-a20f-420b-a651-35ef04cd0fa6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20157286606813016235693011523349630383582444920001830055061747231937871323647 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 3.xbar_stress_all.20157286606813016235693011523349630383582444920001830055061747231937871323647
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.112579511442414724845908694503559654359917178988797301999392380117602657139128
Short name T127
Test name
Test status
Simulation time 46147859184 ps
CPU time 113.82 seconds
Started Nov 22 01:40:06 PM PST 23
Finished Nov 22 01:42:02 PM PST 23
Peak memory 202972 kb
Host smart-cd1bd9aa-1fbc-4cee-b043-fe5cd03a0707
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112579511442414724845908694503559654359917178988797301999392380117602657139128 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.112579511442414724845908694503559654359917178988797301999392380117602657139128
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.103093715247035538037623820340069638645939849114385987490310086841950369068797
Short name T421
Test name
Test status
Simulation time 13716459184 ps
CPU time 161.75 seconds
Started Nov 22 01:40:28 PM PST 23
Finished Nov 22 01:43:11 PM PST 23
Peak memory 205088 kb
Host smart-b9eb270a-bc92-4e93-b846-46a620c31429
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103093715247035538037623820340069638645939849114385987490310086841950369068797 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.103093715247035538037623820340069638645939849114385987490310086841950369068797
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.22729645290504910808445004900556214433098336148167049067291913862852529039747
Short name T316
Test name
Test status
Simulation time 13716459184 ps
CPU time 137.37 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:42:27 PM PST 23
Peak memory 206276 kb
Host smart-0449d655-e700-43f2-9fb4-733c1babfc99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22729645290504910808445004900556214433098336148167049067291913862852529039747 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.22729645290504910808445004900556214433098336148167049067291913862852529039747
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.39817744011609543051232556278799186582422763103762065941849615613419236178944
Short name T249
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.76 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:11 PM PST 23
Peak memory 202008 kb
Host smart-bef1bddf-310c-4aae-8795-211c3f13ec29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=39817744011609543051232556278799186582422763103762065941849615613419236178944 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 3.xbar_unmapped_addr.39817744011609543051232556278799186582422763103762065941849615613419236178944
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.69167915952967140856123173077807783052390748970864473978172342450971319281776
Short name T581
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.32 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:36 PM PST 23
Peak memory 202008 kb
Host smart-6ab3dc2c-df7f-43f0-963e-1c81146c0d3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69167915952967140856123173077807783052390748970864473978172342450971319281776 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.69167915952967140856123173077807783052390748970864473978172342450971319281776
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.19756918244318244250122302925311254168570742084078531259118263796125925357642
Short name T804
Test name
Test status
Simulation time 260306045935 ps
CPU time 341.33 seconds
Started Nov 22 01:40:58 PM PST 23
Finished Nov 22 01:46:41 PM PST 23
Peak memory 203124 kb
Host smart-fec53d80-0eb6-4959-88c0-a139a6512bc1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=19756918244318244250122302925311254168570742084078531259118263796125925357642 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.19756918244318244250122302925311254168570742084078531259118263796125925357642
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.12618424832146777291246289751858933937247925782311475738020547368768075269883
Short name T638
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.16 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:29 PM PST 23
Peak memory 201988 kb
Host smart-a43d9582-5686-4062-8454-e1adb16912d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12618424832146777291246289751858933937247925782311475738020547368768075269883 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.12618424832146777291246289751858933937247925782311475738020547368768075269883
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.94512458231148474177017772500137139131760163454699760547593639309893598868462
Short name T668
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.92 seconds
Started Nov 22 01:41:27 PM PST 23
Finished Nov 22 01:41:42 PM PST 23
Peak memory 201960 kb
Host smart-ee047a7c-8730-44b5-accd-6b456676b537
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94512458231148474177017772500137139131760163454699760547593639309893598868462 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 30.xbar_error_random.94512458231148474177017772500137139131760163454699760547593639309893598868462
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.35088325271988910893097492866754383139781190925368284229122728230441497239179
Short name T393
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.29 seconds
Started Nov 22 01:42:06 PM PST 23
Finished Nov 22 01:42:25 PM PST 23
Peak memory 201984 kb
Host smart-044d0ed9-618a-4e71-84df-c5a0f350cb81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35088325271988910893097492866754383139781190925368284229122728230441497239179 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 30.xbar_random.35088325271988910893097492866754383139781190925368284229122728230441497239179
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.55306491161807967088035783292756580596429764663214193416992357937918716551261
Short name T357
Test name
Test status
Simulation time 237556670935 ps
CPU time 190.67 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:44:30 PM PST 23
Peak memory 201992 kb
Host smart-2d8692a9-dda9-49c3-ba54-79c1f530e2b1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=55306491161807967088035783292756580596429764663214193416992357937918716551261 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 30.xbar_random_large_delays.55306491161807967088035783292756580596429764663214193416992357937918716551261
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.10503792653893116235025865074226884722442504519027417458679211326145181106542
Short name T727
Test name
Test status
Simulation time 160909483435 ps
CPU time 193.44 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:44:32 PM PST 23
Peak memory 202000 kb
Host smart-50abcc57-9104-4adf-add8-7b5d75554107
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=10503792653893116235025865074226884722442504519027417458679211326145181106542 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.10503792653893116235025865074226884722442504519027417458679211326145181106542
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.103151038477482053450526169028179038278357676390553847935704115931252298157302
Short name T556
Test name
Test status
Simulation time 360920935 ps
CPU time 7.65 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:41:28 PM PST 23
Peak memory 201912 kb
Host smart-e1796a74-5979-465f-a59b-3d2c735ed1da
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103151038477482053450526169028179038278357676390553847935704115931252298157302 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.103151038477482053450526169028179038278357676390553847935704115931252298157302
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.24902081870723354657636653796964479373907042889266497580652660932503152072440
Short name T335
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.85 seconds
Started Nov 22 01:40:43 PM PST 23
Finished Nov 22 01:40:57 PM PST 23
Peak memory 201992 kb
Host smart-6f278e20-40b2-4390-9564-57b9fc86d437
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24902081870723354657636653796964479373907042889266497580652660932503152072440 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 30.xbar_same_source.24902081870723354657636653796964479373907042889266497580652660932503152072440
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.85260673420890124544389106373687813561185953789393070047313685676302119921347
Short name T141
Test name
Test status
Simulation time 331233435 ps
CPU time 1.64 seconds
Started Nov 22 01:41:31 PM PST 23
Finished Nov 22 01:41:34 PM PST 23
Peak memory 201844 kb
Host smart-9bd5c474-eb61-4f87-baf7-8368d5497c36
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85260673420890124544389106373687813561185953789393070047313685676302119921347 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 30.xbar_smoke.85260673420890124544389106373687813561185953789393070047313685676302119921347
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.64801316862098933732710269500513296952856156594802121687432689352174940183718
Short name T700
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.89 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:41:57 PM PST 23
Peak memory 201848 kb
Host smart-339f9b1f-ebf4-454c-b8ed-00f9c30a4b4c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=64801316862098933732710269500513296952856156594802121687432689352174940183718 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.64801316862098933732710269500513296952856156594802121687432689352174940183718
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.61060211914677998740321090500211689091594047992720014751347560706693484350877
Short name T93
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.79 seconds
Started Nov 22 01:41:25 PM PST 23
Finished Nov 22 01:41:38 PM PST 23
Peak memory 201952 kb
Host smart-b792dbef-2820-43d8-9dfe-d1157fe828b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=61060211914677998740321090500211689091594047992720014751347560706693484350877 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.61060211914677998740321090500211689091594047992720014751347560706693484350877
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.9887436610268011263104365528344894214664243815792577133130633183389345457591
Short name T452
Test name
Test status
Simulation time 27670935 ps
CPU time 1.16 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:41:53 PM PST 23
Peak memory 201860 kb
Host smart-74b16c4e-9498-4462-9545-ca5b12183005
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9887436610268011263104365528344894214664243815792577133130633183389345457591 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.9887436610268011263104365528344894214664243815792577133130633183389345457591
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.101215176747067358730605299327520689971271960626165060426582402005298384004323
Short name T449
Test name
Test status
Simulation time 46147859184 ps
CPU time 128.36 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:43:29 PM PST 23
Peak memory 203308 kb
Host smart-25dedda6-78b0-4262-9eb7-bc50d81406e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=101215176747067358730605299327520689971271960626165060426582402005298384004323 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 30.xbar_stress_all.101215176747067358730605299327520689971271960626165060426582402005298384004323
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.928599454189710867998797164261235264402536565546450870042732091791264260668
Short name T721
Test name
Test status
Simulation time 46147859184 ps
CPU time 125.66 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:43:27 PM PST 23
Peak memory 204880 kb
Host smart-6df795ee-3e80-41f4-bdce-a2533190761f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=928599454189710867998797164261235264402536565546450870042732091791264260668 -assert nopostproc +UVM_TESTNAME=xba
r_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_
log /dev/null -cm_name 30.xbar_stress_all_with_error.928599454189710867998797164261235264402536565546450870042732091791264260668
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.90559862654529584351735375737412898573307893145815130423922175229243410489380
Short name T783
Test name
Test status
Simulation time 13716459184 ps
CPU time 159.06 seconds
Started Nov 22 01:41:13 PM PST 23
Finished Nov 22 01:43:54 PM PST 23
Peak memory 205168 kb
Host smart-d3ab1989-c8bc-419d-82b0-26e9d566614a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=90559862654529584351735375737412898573307893145815130423922175229243410489380 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.90559862654529584351735375737412898573307893145815130423922175229243410489380
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.36164514306464732039460588188235442737319428494463719457981485046540089100933
Short name T636
Test name
Test status
Simulation time 13716459184 ps
CPU time 134.97 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:43:37 PM PST 23
Peak memory 206224 kb
Host smart-e1dd0b5f-ef8f-47db-bf31-153be154be61
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36164514306464732039460588188235442737319428494463719457981485046540089100933 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.36164514306464732039460588188235442737319428494463719457981485046540089100933
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.22174667400494787732071619670593322773176905964658128674487146969465825807937
Short name T539
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.94 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:30 PM PST 23
Peak memory 202008 kb
Host smart-8e892f44-1914-498a-a9d2-195412d6e5ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22174667400494787732071619670593322773176905964658128674487146969465825807937 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 30.xbar_unmapped_addr.22174667400494787732071619670593322773176905964658128674487146969465825807937
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.85891157917891013387125336860614425852208679537775882774641009273135428565551
Short name T610
Test name
Test status
Simulation time 4712795935 ps
CPU time 16.76 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:41:34 PM PST 23
Peak memory 201836 kb
Host smart-5839e31d-8a65-473d-be9e-0e109247d8b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85891157917891013387125336860614425852208679537775882774641009273135428565551 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.85891157917891013387125336860614425852208679537775882774641009273135428565551
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.11795497401294683190469594921661213470356131450109965951216911835050893330343
Short name T383
Test name
Test status
Simulation time 260306045935 ps
CPU time 327.13 seconds
Started Nov 22 01:41:32 PM PST 23
Finished Nov 22 01:47:01 PM PST 23
Peak memory 202960 kb
Host smart-3a95003f-8a67-4934-8c48-b021f91e2b32
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=11795497401294683190469594921661213470356131450109965951216911835050893330343 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.11795497401294683190469594921661213470356131450109965951216911835050893330343
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.32635127410029779639269793489437436261214727819565544198854972183322944446868
Short name T86
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.06 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:41:54 PM PST 23
Peak memory 202004 kb
Host smart-89a5635e-6077-44e1-8cb7-69f1b319bdea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32635127410029779639269793489437436261214727819565544198854972183322944446868 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.32635127410029779639269793489437436261214727819565544198854972183322944446868
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.33668545282114217603731087120022963123317412490844383164147883209926288956358
Short name T417
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.32 seconds
Started Nov 22 01:41:51 PM PST 23
Finished Nov 22 01:42:06 PM PST 23
Peak memory 201960 kb
Host smart-351c8a6f-7f56-462a-aa6c-09f8e684136f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33668545282114217603731087120022963123317412490844383164147883209926288956358 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 31.xbar_error_random.33668545282114217603731087120022963123317412490844383164147883209926288956358
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.30717732944793978890210577508732305404139112243088670080531858161748834508189
Short name T874
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.02 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:41:36 PM PST 23
Peak memory 201920 kb
Host smart-6b079e05-2ba1-4a31-84d0-c810adabf60c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30717732944793978890210577508732305404139112243088670080531858161748834508189 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 31.xbar_random.30717732944793978890210577508732305404139112243088670080531858161748834508189
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.36132011640277134689241875646576424063118803918187244813493862102266612948941
Short name T575
Test name
Test status
Simulation time 237556670935 ps
CPU time 186.86 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:44:30 PM PST 23
Peak memory 201932 kb
Host smart-fe502607-bfe3-4254-ba58-57a55bac2c4f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=36132011640277134689241875646576424063118803918187244813493862102266612948941 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 31.xbar_random_large_delays.36132011640277134689241875646576424063118803918187244813493862102266612948941
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.91315673651568393836813960569309376366141586320211727893109091792911358943440
Short name T250
Test name
Test status
Simulation time 160909483435 ps
CPU time 192.33 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:44:34 PM PST 23
Peak memory 202028 kb
Host smart-64dadd05-a395-4c3a-b621-afefb46d3250
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=91315673651568393836813960569309376366141586320211727893109091792911358943440 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.91315673651568393836813960569309376366141586320211727893109091792911358943440
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.27728155300353530023592205050903335171520406091045845664259103961347425946880
Short name T35
Test name
Test status
Simulation time 360920935 ps
CPU time 7.88 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:41:29 PM PST 23
Peak memory 201924 kb
Host smart-c68958ca-712c-4144-a8ad-d29654c99136
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27728155300353530023592205050903335171520406091045845664259103961347425946880 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.27728155300353530023592205050903335171520406091045845664259103961347425946880
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.72365810489591636151869593713816453916391201245836749769038864653248578687821
Short name T792
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.13 seconds
Started Nov 22 01:41:25 PM PST 23
Finished Nov 22 01:41:38 PM PST 23
Peak memory 201912 kb
Host smart-e62a4de7-bf2b-4658-94d8-2e1e48dd5440
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72365810489591636151869593713816453916391201245836749769038864653248578687821 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 31.xbar_same_source.72365810489591636151869593713816453916391201245836749769038864653248578687821
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.23666982806983042303553643441019373056364180005431575253213895006139268081120
Short name T137
Test name
Test status
Simulation time 331233435 ps
CPU time 1.65 seconds
Started Nov 22 01:41:36 PM PST 23
Finished Nov 22 01:41:40 PM PST 23
Peak memory 201916 kb
Host smart-e81ff631-1158-43aa-ad33-d84b98fea1a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23666982806983042303553643441019373056364180005431575253213895006139268081120 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 31.xbar_smoke.23666982806983042303553643441019373056364180005431575253213895006139268081120
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.69899442562475745458940316709156002053154880702783052440221342452566038136393
Short name T169
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.77 seconds
Started Nov 22 01:41:12 PM PST 23
Finished Nov 22 01:41:27 PM PST 23
Peak memory 201980 kb
Host smart-2145e84e-a95b-4989-95b9-a796504ea12a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=69899442562475745458940316709156002053154880702783052440221342452566038136393 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.69899442562475745458940316709156002053154880702783052440221342452566038136393
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.25747879663689018142930688870090903621392394380323605488268649865115996046250
Short name T824
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.91 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:41:29 PM PST 23
Peak memory 201968 kb
Host smart-fe88c648-81f8-4c70-8b65-8a91ff33da9d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=25747879663689018142930688870090903621392394380323605488268649865115996046250 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.25747879663689018142930688870090903621392394380323605488268649865115996046250
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.14638254618838369133439506281791913011899272077206828720887183872584382101882
Short name T628
Test name
Test status
Simulation time 27670935 ps
CPU time 1.15 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:20 PM PST 23
Peak memory 201792 kb
Host smart-73171097-31ca-4f9b-a623-45a911660624
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14638254618838369133439506281791913011899272077206828720887183872584382101882 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.14638254618838369133439506281791913011899272077206828720887183872584382101882
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.65129878503477627279431316309894802756161267990626698905300777470384341778351
Short name T563
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.73 seconds
Started Nov 22 01:41:51 PM PST 23
Finished Nov 22 01:44:00 PM PST 23
Peak memory 203188 kb
Host smart-0ab01adf-d6c4-45cb-a9d0-68a34ef96d8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65129878503477627279431316309894802756161267990626698905300777470384341778351 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 31.xbar_stress_all.65129878503477627279431316309894802756161267990626698905300777470384341778351
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.73591631446996670620246906913797145029710064806024121215576751738223223853846
Short name T386
Test name
Test status
Simulation time 46147859184 ps
CPU time 119.19 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:43:32 PM PST 23
Peak memory 204872 kb
Host smart-8497642f-cc5c-48cf-8cd0-fd43fbe9b3ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73591631446996670620246906913797145029710064806024121215576751738223223853846 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 31.xbar_stress_all_with_error.73591631446996670620246906913797145029710064806024121215576751738223223853846
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.55284775758333161606071567497369405643204986812568884739160049908797247564681
Short name T443
Test name
Test status
Simulation time 13716459184 ps
CPU time 159.2 seconds
Started Nov 22 01:41:33 PM PST 23
Finished Nov 22 01:44:14 PM PST 23
Peak memory 205112 kb
Host smart-9684d82a-b19b-4060-86aa-a12ee6502cbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55284775758333161606071567497369405643204986812568884739160049908797247564681 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.55284775758333161606071567497369405643204986812568884739160049908797247564681
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.10802477876104057825234476715095033593532612470455157683818841101725761488429
Short name T43
Test name
Test status
Simulation time 13716459184 ps
CPU time 133.84 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:44:00 PM PST 23
Peak memory 206088 kb
Host smart-ce04b8e6-d6a3-458a-8bfd-d9e504bdb28d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10802477876104057825234476715095033593532612470455157683818841101725761488429 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.10802477876104057825234476715095033593532612470455157683818841101725761488429
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.21397291761799400090373942716822596072463000296903564230288295716406005564459
Short name T544
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.79 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:41:28 PM PST 23
Peak memory 202008 kb
Host smart-9ea022e2-5822-4afb-a7a7-74fb4fb24106
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=21397291761799400090373942716822596072463000296903564230288295716406005564459 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 31.xbar_unmapped_addr.21397291761799400090373942716822596072463000296903564230288295716406005564459
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.99838978333101952525961623865130942977740383805627398965453920618713591775073
Short name T462
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.39 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:41:45 PM PST 23
Peak memory 201940 kb
Host smart-4239d1e5-2370-479f-9177-27f6d37e0e3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99838978333101952525961623865130942977740383805627398965453920618713591775073 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.99838978333101952525961623865130942977740383805627398965453920618713591775073
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.45048453739671407525962775081084408296492788226195078825209767878599695775558
Short name T702
Test name
Test status
Simulation time 260306045935 ps
CPU time 335.69 seconds
Started Nov 22 01:42:04 PM PST 23
Finished Nov 22 01:47:46 PM PST 23
Peak memory 202936 kb
Host smart-27c15e90-dde2-4115-906e-e97c05a8d382
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=45048453739671407525962775081084408296492788226195078825209767878599695775558 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.45048453739671407525962775081084408296492788226195078825209767878599695775558
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.517272775865006262720554768752269756028633355056185581227218539635709100927
Short name T320
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.11 seconds
Started Nov 22 01:41:38 PM PST 23
Finished Nov 22 01:41:50 PM PST 23
Peak memory 201908 kb
Host smart-7f00b875-1267-4db0-aa81-b8269bdf3e80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=517272775865006262720554768752269756028633355056185581227218539635709100927 -assert nopostproc +UVM_TESTNAME=xba
r_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.517272775865006262720554768752269756028633355056185581227218539635709100927
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.92705125097088341406366517642654552599475305157058231774998292266689909901943
Short name T596
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.8 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:41:49 PM PST 23
Peak memory 201952 kb
Host smart-ed7d7914-fe6f-452d-a48f-d86804b83f85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92705125097088341406366517642654552599475305157058231774998292266689909901943 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 32.xbar_error_random.92705125097088341406366517642654552599475305157058231774998292266689909901943
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.59297172141419642625716595479476875937750255749529035063780862617552587116071
Short name T518
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.58 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:42:01 PM PST 23
Peak memory 201996 kb
Host smart-79d5656b-66b0-462a-8d31-2d8aed09c434
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59297172141419642625716595479476875937750255749529035063780862617552587116071 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 32.xbar_random.59297172141419642625716595479476875937750255749529035063780862617552587116071
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.31099266447878032779619912047197224307570323775371384276273640167598795319875
Short name T892
Test name
Test status
Simulation time 237556670935 ps
CPU time 187.27 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:44:34 PM PST 23
Peak memory 201996 kb
Host smart-2696af0c-ed28-44b3-9885-6a70200138f6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=31099266447878032779619912047197224307570323775371384276273640167598795319875 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 32.xbar_random_large_delays.31099266447878032779619912047197224307570323775371384276273640167598795319875
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.4952780414476823447973935850136970093695235217926099450315475719845852543792
Short name T748
Test name
Test status
Simulation time 160909483435 ps
CPU time 197.19 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:45:09 PM PST 23
Peak memory 201956 kb
Host smart-24b3c26c-7f4d-4a0f-b82e-6ac32395715e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4952780414476823447973935850136970093695235217926099450315475719845852543792 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 32.xbar_random_slow_rsp.4952780414476823447973935850136970093695235217926099450315475719845852543792
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.93475423873781252300929585763014264062599822548068430799721443170612670957392
Short name T681
Test name
Test status
Simulation time 360920935 ps
CPU time 8.17 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:42:00 PM PST 23
Peak memory 201904 kb
Host smart-0a05804a-5b0d-422e-9bcd-6e16d0d41c99
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93475423873781252300929585763014264062599822548068430799721443170612670957392 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.93475423873781252300929585763014264062599822548068430799721443170612670957392
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.54740534343512082522780630709677874636698948356179213082860940666315932548806
Short name T164
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.01 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:41:52 PM PST 23
Peak memory 201996 kb
Host smart-91560773-de0e-45a8-897c-16cffdd67ba6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54740534343512082522780630709677874636698948356179213082860940666315932548806 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 32.xbar_same_source.54740534343512082522780630709677874636698948356179213082860940666315932548806
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.71950704637697151671520665235212285401134321150839314005700452744601588903501
Short name T650
Test name
Test status
Simulation time 331233435 ps
CPU time 1.57 seconds
Started Nov 22 01:41:33 PM PST 23
Finished Nov 22 01:41:37 PM PST 23
Peak memory 201832 kb
Host smart-032e70a3-6d8c-4054-a1d7-994962f25ca4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=71950704637697151671520665235212285401134321150839314005700452744601588903501 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 32.xbar_smoke.71950704637697151671520665235212285401134321150839314005700452744601588903501
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.104647477850493351427142356517785028347907579656864747273034781406624923045140
Short name T405
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.82 seconds
Started Nov 22 01:41:47 PM PST 23
Finished Nov 22 01:42:02 PM PST 23
Peak memory 201916 kb
Host smart-bd65054b-4561-4813-85c3-71ea9f056081
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=104647477850493351427142356517785028347907579656864747273034781406624923045140 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.104647477850493351427142356517785028347907579656864747273034781406624923045140
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.63945430235406309260753851836457087253378717875461320449712926044944996354993
Short name T658
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.67 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:42:04 PM PST 23
Peak memory 202016 kb
Host smart-ae1161de-e35f-4884-b5c7-1500974258bc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=63945430235406309260753851836457087253378717875461320449712926044944996354993 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.63945430235406309260753851836457087253378717875461320449712926044944996354993
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.98496914778085246852862682951595440730480570883070231392367453152941177594120
Short name T212
Test name
Test status
Simulation time 27670935 ps
CPU time 1.15 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:41:51 PM PST 23
Peak memory 201844 kb
Host smart-283413b6-0299-4090-9263-4154812dc070
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98496914778085246852862682951595440730480570883070231392367453152941177594120 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.98496914778085246852862682951595440730480570883070231392367453152941177594120
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.25579460058638063508346938279464107697966587339204515663342004587031916076393
Short name T803
Test name
Test status
Simulation time 46147859184 ps
CPU time 128.12 seconds
Started Nov 22 01:41:29 PM PST 23
Finished Nov 22 01:43:39 PM PST 23
Peak memory 203200 kb
Host smart-0f79aa8d-1a5f-436f-b3a0-01268b7c5ada
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25579460058638063508346938279464107697966587339204515663342004587031916076393 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 32.xbar_stress_all.25579460058638063508346938279464107697966587339204515663342004587031916076393
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.47179663470723163649549645051006978388172107570227829218081569392423730781467
Short name T682
Test name
Test status
Simulation time 46147859184 ps
CPU time 114.64 seconds
Started Nov 22 01:41:41 PM PST 23
Finished Nov 22 01:43:37 PM PST 23
Peak memory 204752 kb
Host smart-d51946a0-9e38-4caa-be8f-35aae77cd25b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47179663470723163649549645051006978388172107570227829218081569392423730781467 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 32.xbar_stress_all_with_error.47179663470723163649549645051006978388172107570227829218081569392423730781467
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.6845319616401188512171786051154048433360507867692578558539150855126167788361
Short name T274
Test name
Test status
Simulation time 13716459184 ps
CPU time 160.48 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:44:18 PM PST 23
Peak memory 205168 kb
Host smart-3dbbfc11-364e-4e27-adc9-6c05456698b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6845319616401188512171786051154048433360507867692578558539150855126167788361 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.6845319616401188512171786051154048433360507867692578558539150855126167788361
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.31955859239936384486480238731013309990589328291702063823082605957843225707160
Short name T805
Test name
Test status
Simulation time 13716459184 ps
CPU time 136.1 seconds
Started Nov 22 01:41:35 PM PST 23
Finished Nov 22 01:43:54 PM PST 23
Peak memory 206132 kb
Host smart-3cfb719b-8044-4f18-8a76-2acd7c0bdc4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31955859239936384486480238731013309990589328291702063823082605957843225707160 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.31955859239936384486480238731013309990589328291702063823082605957843225707160
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.44108933043139422052237255531977037907351228401772483223083160025121606496887
Short name T211
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.63 seconds
Started Nov 22 01:41:39 PM PST 23
Finished Nov 22 01:41:52 PM PST 23
Peak memory 201964 kb
Host smart-96cbd134-7d46-4268-b8fa-92a53a7a06d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44108933043139422052237255531977037907351228401772483223083160025121606496887 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 32.xbar_unmapped_addr.44108933043139422052237255531977037907351228401772483223083160025121606496887
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.56801101575858391307875317034782445883183027470979564580173122047362471128538
Short name T132
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.74 seconds
Started Nov 22 01:42:00 PM PST 23
Finished Nov 22 01:42:26 PM PST 23
Peak memory 201936 kb
Host smart-2a6a7a4b-e6ba-48fc-9f67-29c415ff7357
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56801101575858391307875317034782445883183027470979564580173122047362471128538 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.56801101575858391307875317034782445883183027470979564580173122047362471128538
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.444192746146048333090880485279052369662674796952823589602090945314132725462
Short name T526
Test name
Test status
Simulation time 260306045935 ps
CPU time 335.69 seconds
Started Nov 22 01:41:11 PM PST 23
Finished Nov 22 01:46:48 PM PST 23
Peak memory 203028 kb
Host smart-bbe74a56-6532-4cac-80b9-14ab71fd6b27
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=444192746146048333090880485279052369662674796952823589602090945314132725462 -assert nopostproc +UVM_TESTNA
ME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.444192746146048333090880485279052369662674796952823589602090945314132725462
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.85124147933730856460365787461096322402937848672256183592475853870340247468706
Short name T815
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.91 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:41:31 PM PST 23
Peak memory 201884 kb
Host smart-7a17ce01-6cc1-42dd-82d9-8d9148d9eac0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85124147933730856460365787461096322402937848672256183592475853870340247468706 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.85124147933730856460365787461096322402937848672256183592475853870340247468706
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.46811389799043306632218278760639458606991628793935344997654655608279850929022
Short name T718
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.6 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:41:34 PM PST 23
Peak memory 201912 kb
Host smart-5b73fe5e-ec3c-41b8-8554-2419874434e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46811389799043306632218278760639458606991628793935344997654655608279850929022 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 33.xbar_error_random.46811389799043306632218278760639458606991628793935344997654655608279850929022
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.29756045318925142368945242430499843754174556171431164200704711554789117575960
Short name T241
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.26 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:41:51 PM PST 23
Peak memory 201936 kb
Host smart-39940c62-315d-47a1-9b3c-1b6d5eaf66b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29756045318925142368945242430499843754174556171431164200704711554789117575960 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 33.xbar_random.29756045318925142368945242430499843754174556171431164200704711554789117575960
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.22456537140464181028717047010016484862411330615866656635822906929892922584678
Short name T590
Test name
Test status
Simulation time 237556670935 ps
CPU time 186.87 seconds
Started Nov 22 01:41:52 PM PST 23
Finished Nov 22 01:45:01 PM PST 23
Peak memory 201988 kb
Host smart-17a84d17-95e4-4023-9638-5ac4d35bd80d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=22456537140464181028717047010016484862411330615866656635822906929892922584678 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 33.xbar_random_large_delays.22456537140464181028717047010016484862411330615866656635822906929892922584678
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.69329629760092723222818271008381512285136633564486259847822095443251475804442
Short name T385
Test name
Test status
Simulation time 160909483435 ps
CPU time 193.31 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:45:00 PM PST 23
Peak memory 201896 kb
Host smart-9a692aa8-ada6-4fc7-8f77-4ba477555779
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=69329629760092723222818271008381512285136633564486259847822095443251475804442 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.69329629760092723222818271008381512285136633564486259847822095443251475804442
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.77261620547584133006657791557882707639130138455249204014343604090557897968715
Short name T446
Test name
Test status
Simulation time 360920935 ps
CPU time 7.27 seconds
Started Nov 22 01:42:07 PM PST 23
Finished Nov 22 01:42:19 PM PST 23
Peak memory 201916 kb
Host smart-4b209ca6-0323-42de-a53d-7a0b99cac646
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77261620547584133006657791557882707639130138455249204014343604090557897968715 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.77261620547584133006657791557882707639130138455249204014343604090557897968715
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.77006601701032645962689371066820299761448717871351014967923527139640329186144
Short name T297
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.9 seconds
Started Nov 22 01:42:02 PM PST 23
Finished Nov 22 01:42:23 PM PST 23
Peak memory 201912 kb
Host smart-3511b791-0c8d-4c63-a322-43ab429f250e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=77006601701032645962689371066820299761448717871351014967923527139640329186144 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 33.xbar_same_source.77006601701032645962689371066820299761448717871351014967923527139640329186144
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.6528388643419422694672803683533595461395790062881129816119894334224267031954
Short name T470
Test name
Test status
Simulation time 331233435 ps
CPU time 1.57 seconds
Started Nov 22 01:41:54 PM PST 23
Finished Nov 22 01:41:58 PM PST 23
Peak memory 201752 kb
Host smart-ec8cc31c-83dc-43bb-bb2b-94b720842b57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6528388643419422694672803683533595461395790062881129816119894334224267031954 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 33.xbar_smoke.6528388643419422694672803683533595461395790062881129816119894334224267031954
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.99380218454312627173054916040819170689563336617076687648130772815179255842641
Short name T849
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.87 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:42:05 PM PST 23
Peak memory 201928 kb
Host smart-14930b5e-46e8-4c22-a340-41a96780ffb6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=99380218454312627173054916040819170689563336617076687648130772815179255842641 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.99380218454312627173054916040819170689563336617076687648130772815179255842641
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.102735977114132377176915595434246552198171477097544964643055138204145146046456
Short name T410
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.71 seconds
Started Nov 22 01:41:36 PM PST 23
Finished Nov 22 01:41:51 PM PST 23
Peak memory 201896 kb
Host smart-4562e81d-79b0-41f3-8fbf-2fbef8e4868d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=102735977114132377176915595434246552198171477097544964643055138204145146046456 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.102735977114132377176915595434246552198171477097544964643055138204145146046456
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.59614071443628175461962945498901185215296271031561055123348433277520232158417
Short name T705
Test name
Test status
Simulation time 27670935 ps
CPU time 1.14 seconds
Started Nov 22 01:41:58 PM PST 23
Finished Nov 22 01:42:06 PM PST 23
Peak memory 201776 kb
Host smart-5009431c-9732-473b-a302-ca2ecabaac14
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59614071443628175461962945498901185215296271031561055123348433277520232158417 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.59614071443628175461962945498901185215296271031561055123348433277520232158417
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.62896798407836204042268153253305892126232972572963250731705847792103511142792
Short name T663
Test name
Test status
Simulation time 46147859184 ps
CPU time 122.54 seconds
Started Nov 22 01:41:25 PM PST 23
Finished Nov 22 01:43:29 PM PST 23
Peak memory 203184 kb
Host smart-dfdd34c6-feb1-4002-9c06-ef4234604b45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62896798407836204042268153253305892126232972572963250731705847792103511142792 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 33.xbar_stress_all.62896798407836204042268153253305892126232972572963250731705847792103511142792
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.114574811308378220161505559884371352368537571384859294864420347072308142711551
Short name T227
Test name
Test status
Simulation time 46147859184 ps
CPU time 115.74 seconds
Started Nov 22 01:41:19 PM PST 23
Finished Nov 22 01:43:16 PM PST 23
Peak memory 202976 kb
Host smart-c08a78f6-25c0-42bf-903e-a7b36b0a6c1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=114574811308378220161505559884371352368537571384859294864420347072308142711551 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.114574811308378220161505559884371352368537571384859294864420347072308142711551
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.105268421954341363236644602963099184989734185450357097466962086957451359122338
Short name T110
Test name
Test status
Simulation time 13716459184 ps
CPU time 161.78 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:43:58 PM PST 23
Peak memory 205164 kb
Host smart-12d98552-0be2-43c3-875c-02c92746baed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105268421954341363236644602963099184989734185450357097466962086957451359122338 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.105268421954341363236644602963099184989734185450357097466962086957451359122338
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.99317663601158462529552837689525370860323786455055318447483196971670582273968
Short name T343
Test name
Test status
Simulation time 13716459184 ps
CPU time 135.84 seconds
Started Nov 22 01:40:58 PM PST 23
Finished Nov 22 01:43:16 PM PST 23
Peak memory 206176 kb
Host smart-8e446c63-9eb5-4c16-8c9f-f83105525ba3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99317663601158462529552837689525370860323786455055318447483196971670582273968 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.99317663601158462529552837689525370860323786455055318447483196971670582273968
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.21301395940447748864215080144319112089311532223551868810137262045882156646498
Short name T333
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.94 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:41:29 PM PST 23
Peak memory 201932 kb
Host smart-29112279-58ab-4a29-aea6-7e256f2b5f89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=21301395940447748864215080144319112089311532223551868810137262045882156646498 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 33.xbar_unmapped_addr.21301395940447748864215080144319112089311532223551868810137262045882156646498
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.107275534286645164104781884690240377015040982301204571387414197297639901572100
Short name T859
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.47 seconds
Started Nov 22 01:41:33 PM PST 23
Finished Nov 22 01:41:52 PM PST 23
Peak memory 201968 kb
Host smart-c34e5c3f-9984-4d25-9a8c-f70fbf8a5310
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=107275534286645164104781884690240377015040982301204571387414197297639901572100 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.107275534286645164104781884690240377015040982301204571387414197297639901572100
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.65574651308963587279718289780497415607097547352818325833356412091342353311063
Short name T285
Test name
Test status
Simulation time 260306045935 ps
CPU time 325.26 seconds
Started Nov 22 01:41:27 PM PST 23
Finished Nov 22 01:46:54 PM PST 23
Peak memory 202912 kb
Host smart-d3cf36e5-4ffd-45df-a4dc-76405daac6fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=65574651308963587279718289780497415607097547352818325833356412091342353311063 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.65574651308963587279718289780497415607097547352818325833356412091342353311063
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.82170375356176753358897972128515749876673385591650795499253995174127692734754
Short name T431
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.35 seconds
Started Nov 22 01:41:23 PM PST 23
Finished Nov 22 01:41:34 PM PST 23
Peak memory 201984 kb
Host smart-fd26b123-50b9-49d9-a817-1993c6406c7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=82170375356176753358897972128515749876673385591650795499253995174127692734754 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.82170375356176753358897972128515749876673385591650795499253995174127692734754
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.105992241644933935604680045689131684279598235618284135281296432046545839903977
Short name T836
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.6 seconds
Started Nov 22 01:41:27 PM PST 23
Finished Nov 22 01:41:41 PM PST 23
Peak memory 201932 kb
Host smart-db3704dc-056c-43f2-9c42-d21960c13bbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105992241644933935604680045689131684279598235618284135281296432046545839903977 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_l
og /dev/null -cm_name 34.xbar_error_random.105992241644933935604680045689131684279598235618284135281296432046545839903977
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.80936163803981747010978434743554613294570524435745250235288944108205326414335
Short name T67
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.98 seconds
Started Nov 22 01:41:50 PM PST 23
Finished Nov 22 01:42:07 PM PST 23
Peak memory 201852 kb
Host smart-41bfae66-c939-4fbd-be05-e7ae1222f450
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=80936163803981747010978434743554613294570524435745250235288944108205326414335 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 34.xbar_random.80936163803981747010978434743554613294570524435745250235288944108205326414335
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.70078367228553351377605786616905397840564204620935876120205476158342379601602
Short name T726
Test name
Test status
Simulation time 237556670935 ps
CPU time 186.5 seconds
Started Nov 22 01:41:40 PM PST 23
Finished Nov 22 01:44:49 PM PST 23
Peak memory 202040 kb
Host smart-79558b1f-41a1-41ab-91c5-08b66ede5894
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=70078367228553351377605786616905397840564204620935876120205476158342379601602 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 34.xbar_random_large_delays.70078367228553351377605786616905397840564204620935876120205476158342379601602
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.11726035403571772062035130076989992119251169606275005354243356123388641824100
Short name T869
Test name
Test status
Simulation time 160909483435 ps
CPU time 191.48 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:45:03 PM PST 23
Peak memory 201868 kb
Host smart-3caba912-805c-4883-9a49-2692b264d076
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=11726035403571772062035130076989992119251169606275005354243356123388641824100 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.11726035403571772062035130076989992119251169606275005354243356123388641824100
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.39617869328305376409736573023743328109529623348515048310225656752653896380328
Short name T466
Test name
Test status
Simulation time 360920935 ps
CPU time 7.75 seconds
Started Nov 22 01:41:33 PM PST 23
Finished Nov 22 01:41:42 PM PST 23
Peak memory 201956 kb
Host smart-e9efad0d-1d1d-47cd-aee0-49d410f2d422
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39617869328305376409736573023743328109529623348515048310225656752653896380328 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.39617869328305376409736573023743328109529623348515048310225656752653896380328
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.28019300940679991520186749619796792252752869672370113010218580356664494240300
Short name T888
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.97 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:41:55 PM PST 23
Peak memory 201808 kb
Host smart-82151994-b093-4da3-be8f-a0a2027d7422
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28019300940679991520186749619796792252752869672370113010218580356664494240300 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 34.xbar_same_source.28019300940679991520186749619796792252752869672370113010218580356664494240300
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.13816161124634495281826477174572867304215896366542335344633235127325320666581
Short name T660
Test name
Test status
Simulation time 331233435 ps
CPU time 1.6 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:41:29 PM PST 23
Peak memory 201908 kb
Host smart-f18d1fe3-ad4e-4a0f-ac0e-a02f5ff4b7b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13816161124634495281826477174572867304215896366542335344633235127325320666581 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 34.xbar_smoke.13816161124634495281826477174572867304215896366542335344633235127325320666581
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.40135207563443933923188476877838532458260154536848234225743940947883449467509
Short name T460
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.82 seconds
Started Nov 22 01:41:23 PM PST 23
Finished Nov 22 01:41:37 PM PST 23
Peak memory 201968 kb
Host smart-22048234-e3c4-446b-aec2-bca3c94b8ada
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=40135207563443933923188476877838532458260154536848234225743940947883449467509 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.40135207563443933923188476877838532458260154536848234225743940947883449467509
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.103850768388636306671822537962605014647368240349657443361588952998081856723750
Short name T156
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.91 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:41:51 PM PST 23
Peak memory 201968 kb
Host smart-d68b0442-e566-48ff-9d70-cfa1da26d55a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=103850768388636306671822537962605014647368240349657443361588952998081856723750 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.103850768388636306671822537962605014647368240349657443361588952998081856723750
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.37221827674167691431437021963131881659844684591574954169476146785201787114891
Short name T256
Test name
Test status
Simulation time 27670935 ps
CPU time 1.2 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:41:52 PM PST 23
Peak memory 201908 kb
Host smart-f2306aa5-7b64-41d3-bcf1-280ae6b4b6a7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37221827674167691431437021963131881659844684591574954169476146785201787114891 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.37221827674167691431437021963131881659844684591574954169476146785201787114891
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.70114690089762571733170886166287188281176910784703622013100391879135590867832
Short name T598
Test name
Test status
Simulation time 46147859184 ps
CPU time 130.01 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:43:26 PM PST 23
Peak memory 202868 kb
Host smart-a5239149-439e-4c79-a94b-be0625d5a96c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70114690089762571733170886166287188281176910784703622013100391879135590867832 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 34.xbar_stress_all.70114690089762571733170886166287188281176910784703622013100391879135590867832
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.30085235223775150783621055994625538438654025344549628357423820606557987537582
Short name T776
Test name
Test status
Simulation time 46147859184 ps
CPU time 114.78 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:43:22 PM PST 23
Peak memory 204904 kb
Host smart-b201a458-b0a7-49a3-bbb5-24542bec40a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30085235223775150783621055994625538438654025344549628357423820606557987537582 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 34.xbar_stress_all_with_error.30085235223775150783621055994625538438654025344549628357423820606557987537582
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.48893146022309730311365523983247384549875147363184235304783426770194426938201
Short name T693
Test name
Test status
Simulation time 13716459184 ps
CPU time 158 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:43:59 PM PST 23
Peak memory 205092 kb
Host smart-ad5e592f-9eda-4aa6-92e5-54a41189943c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=48893146022309730311365523983247384549875147363184235304783426770194426938201 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.48893146022309730311365523983247384549875147363184235304783426770194426938201
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.74510661605546569266781916689892983155071332628276368081299695508860068392210
Short name T1
Test name
Test status
Simulation time 13716459184 ps
CPU time 138.93 seconds
Started Nov 22 01:41:10 PM PST 23
Finished Nov 22 01:43:30 PM PST 23
Peak memory 206360 kb
Host smart-95a564d1-74b0-44b3-b862-dea4844c1882
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=74510661605546569266781916689892983155071332628276368081299695508860068392210 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.74510661605546569266781916689892983155071332628276368081299695508860068392210
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.46780893120776414443294149630913348005478445937175173274557241846978229140758
Short name T139
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.76 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:41:59 PM PST 23
Peak memory 201812 kb
Host smart-896d81e9-61a3-4f6b-8f7a-2b1aeaa92d64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46780893120776414443294149630913348005478445937175173274557241846978229140758 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 34.xbar_unmapped_addr.46780893120776414443294149630913348005478445937175173274557241846978229140758
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.44848976784181855923073179943819167883817940639339940717461707909522119101440
Short name T111
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.75 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:36 PM PST 23
Peak memory 201976 kb
Host smart-e5f03e6e-6599-46ac-a344-6440110ca784
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44848976784181855923073179943819167883817940639339940717461707909522119101440 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.44848976784181855923073179943819167883817940639339940717461707909522119101440
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.89287449015209529556703869197695797130656047504537809037455217198952424933305
Short name T254
Test name
Test status
Simulation time 260306045935 ps
CPU time 337.75 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:46:57 PM PST 23
Peak memory 202892 kb
Host smart-e381d007-9e8d-4cbe-b972-5af66476b993
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=89287449015209529556703869197695797130656047504537809037455217198952424933305 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.89287449015209529556703869197695797130656047504537809037455217198952424933305
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.56737337518298031304796740800622762027595378288388518514865083850459331273436
Short name T820
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.99 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:41:32 PM PST 23
Peak memory 201916 kb
Host smart-e5747f26-5513-4afd-b6cb-a763beac6ad7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56737337518298031304796740800622762027595378288388518514865083850459331273436 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.56737337518298031304796740800622762027595378288388518514865083850459331273436
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.33770338879792903604302267487226460261202101015565407755657028960753553959507
Short name T522
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.86 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:41:36 PM PST 23
Peak memory 201808 kb
Host smart-befe2905-0ad9-4a03-ae48-e96097de175a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33770338879792903604302267487226460261202101015565407755657028960753553959507 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 35.xbar_error_random.33770338879792903604302267487226460261202101015565407755657028960753553959507
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.91463229739359254096514386125145296534405511812350194207404775442570790497992
Short name T63
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.5 seconds
Started Nov 22 01:41:25 PM PST 23
Finished Nov 22 01:41:40 PM PST 23
Peak memory 201976 kb
Host smart-d4a900e7-8417-4288-94ab-90a7286384cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91463229739359254096514386125145296534405511812350194207404775442570790497992 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 35.xbar_random.91463229739359254096514386125145296534405511812350194207404775442570790497992
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.100798470796792729054246227416274630316590127406535302814011694715825844291896
Short name T345
Test name
Test status
Simulation time 237556670935 ps
CPU time 189.34 seconds
Started Nov 22 01:41:19 PM PST 23
Finished Nov 22 01:44:29 PM PST 23
Peak memory 201964 kb
Host smart-b6962402-95a2-44b9-b1b0-9ef6aa20ea40
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=100798470796792729054246227416274630316590127406535302814011694715825844291896 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.100798470796792729054246227416274630316590127406535302814011694715825844291896
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.32327111230381088029890560179650090312719950978026572475356267375879212476548
Short name T785
Test name
Test status
Simulation time 160909483435 ps
CPU time 190.01 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:44:27 PM PST 23
Peak memory 201836 kb
Host smart-fe2415d5-2f00-46fe-af15-7f4c476b270f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=32327111230381088029890560179650090312719950978026572475356267375879212476548 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.32327111230381088029890560179650090312719950978026572475356267375879212476548
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.48668087194792131229928713026735720699093532860530551586478754689462228255188
Short name T781
Test name
Test status
Simulation time 360920935 ps
CPU time 7.6 seconds
Started Nov 22 01:41:24 PM PST 23
Finished Nov 22 01:41:33 PM PST 23
Peak memory 201936 kb
Host smart-6c6442b7-e6de-4a30-9b2e-52306630aea1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48668087194792131229928713026735720699093532860530551586478754689462228255188 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.48668087194792131229928713026735720699093532860530551586478754689462228255188
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.76611715665441702037554935337954233237569220050458058659186092474246887581576
Short name T314
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.61 seconds
Started Nov 22 01:41:24 PM PST 23
Finished Nov 22 01:41:37 PM PST 23
Peak memory 201980 kb
Host smart-4af263cb-0e6b-464b-a7e8-ab134a1889a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76611715665441702037554935337954233237569220050458058659186092474246887581576 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 35.xbar_same_source.76611715665441702037554935337954233237569220050458058659186092474246887581576
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.35288148723992875128404583506909387537684085929240272753518541161163437941195
Short name T404
Test name
Test status
Simulation time 331233435 ps
CPU time 1.65 seconds
Started Nov 22 01:41:29 PM PST 23
Finished Nov 22 01:41:33 PM PST 23
Peak memory 201868 kb
Host smart-31022944-fb37-401a-b102-c1788bfa1b23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35288148723992875128404583506909387537684085929240272753518541161163437941195 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 35.xbar_smoke.35288148723992875128404583506909387537684085929240272753518541161163437941195
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.71446115047145300366427806423017973533962842616756144397545646740969652788026
Short name T448
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.81 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:41:35 PM PST 23
Peak memory 201820 kb
Host smart-880b7f83-c971-4664-8fe5-83fed28fbbf5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=71446115047145300366427806423017973533962842616756144397545646740969652788026 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.71446115047145300366427806423017973533962842616756144397545646740969652788026
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.63712624403844815319020616322411675652961750058760380967534808555732242149413
Short name T370
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.59 seconds
Started Nov 22 01:41:12 PM PST 23
Finished Nov 22 01:41:26 PM PST 23
Peak memory 201980 kb
Host smart-c69059aa-2c22-4db5-9309-7cf4cbbf6d34
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=63712624403844815319020616322411675652961750058760380967534808555732242149413 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.63712624403844815319020616322411675652961750058760380967534808555732242149413
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.65824523055080339112102978428562897514596629547085044768961876650526460914309
Short name T444
Test name
Test status
Simulation time 27670935 ps
CPU time 1.21 seconds
Started Nov 22 01:41:11 PM PST 23
Finished Nov 22 01:41:14 PM PST 23
Peak memory 201884 kb
Host smart-ecedd4fc-5939-4302-a8f9-2d8e1398e43b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65824523055080339112102978428562897514596629547085044768961876650526460914309 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.65824523055080339112102978428562897514596629547085044768961876650526460914309
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.72462466109708632260055840032549785451991155406353000743429942253053252228643
Short name T270
Test name
Test status
Simulation time 46147859184 ps
CPU time 122.05 seconds
Started Nov 22 01:41:24 PM PST 23
Finished Nov 22 01:43:27 PM PST 23
Peak memory 203140 kb
Host smart-0ae1c159-e64e-42da-8ad1-160d610812e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72462466109708632260055840032549785451991155406353000743429942253053252228643 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 35.xbar_stress_all.72462466109708632260055840032549785451991155406353000743429942253053252228643
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.6967308395734791499833599461765593124511543154940813401280366129341986006601
Short name T265
Test name
Test status
Simulation time 46147859184 ps
CPU time 115.74 seconds
Started Nov 22 01:41:13 PM PST 23
Finished Nov 22 01:43:10 PM PST 23
Peak memory 204896 kb
Host smart-6fe065af-7899-494a-84d6-092a4146a55e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6967308395734791499833599461765593124511543154940813401280366129341986006601 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 35.xbar_stress_all_with_error.6967308395734791499833599461765593124511543154940813401280366129341986006601
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.92624853990145917039866020833113176835373874404263348740981015259899474623405
Short name T223
Test name
Test status
Simulation time 13716459184 ps
CPU time 162.17 seconds
Started Nov 22 01:41:09 PM PST 23
Finished Nov 22 01:43:53 PM PST 23
Peak memory 205168 kb
Host smart-fe62a448-aedd-4cdd-8d0f-5ed2ea718af3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92624853990145917039866020833113176835373874404263348740981015259899474623405 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.92624853990145917039866020833113176835373874404263348740981015259899474623405
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.105271457272204301285408262626427678186981115976358879288478244526165472499428
Short name T801
Test name
Test status
Simulation time 13716459184 ps
CPU time 135.06 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:43:36 PM PST 23
Peak memory 206232 kb
Host smart-cf353f8b-2bd1-44c2-a95f-ee351ee4b309
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105271457272204301285408262626427678186981115976358879288478244526165472499428 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.105271457272204301285408262626427678186981115976358879288478244526165472499428
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.27012017663590799994003212237767759586577425173812743718306969250665934369988
Short name T535
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.53 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:41:44 PM PST 23
Peak memory 201992 kb
Host smart-c4cc6474-f60a-4b1f-a7ad-fa0a750d7ca3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27012017663590799994003212237767759586577425173812743718306969250665934369988 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 35.xbar_unmapped_addr.27012017663590799994003212237767759586577425173812743718306969250665934369988
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.29021269484526450533101509804564259178327409796758613035853462071391118773389
Short name T479
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.42 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:41:40 PM PST 23
Peak memory 201600 kb
Host smart-37947278-6728-4411-b748-8f3c1a95816b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29021269484526450533101509804564259178327409796758613035853462071391118773389 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.29021269484526450533101509804564259178327409796758613035853462071391118773389
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.35802712683295137572010032919670009803130443718144639254087344563509371901603
Short name T580
Test name
Test status
Simulation time 260306045935 ps
CPU time 330.79 seconds
Started Nov 22 01:41:13 PM PST 23
Finished Nov 22 01:46:46 PM PST 23
Peak memory 202868 kb
Host smart-310d7635-9a82-4288-a9af-0fe49efe6c96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=35802712683295137572010032919670009803130443718144639254087344563509371901603 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.35802712683295137572010032919670009803130443718144639254087344563509371901603
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.39247719872790209848066005684974740771007617637298187468184215102171461374571
Short name T653
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.15 seconds
Started Nov 22 01:41:23 PM PST 23
Finished Nov 22 01:41:35 PM PST 23
Peak memory 201952 kb
Host smart-9befcab9-699e-46b4-af1f-716ebdd48f0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=39247719872790209848066005684974740771007617637298187468184215102171461374571 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.39247719872790209848066005684974740771007617637298187468184215102171461374571
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.39047727783957535107451925532869299549227421976399632375579617058824343594791
Short name T647
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.62 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:41:29 PM PST 23
Peak memory 201988 kb
Host smart-61d04502-ac26-4aaa-be60-541d6e295736
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=39047727783957535107451925532869299549227421976399632375579617058824343594791 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 36.xbar_error_random.39047727783957535107451925532869299549227421976399632375579617058824343594791
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.52568532230170716925978354642664858781316002960381394107939489153165193326390
Short name T350
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.84 seconds
Started Nov 22 01:41:28 PM PST 23
Finished Nov 22 01:41:44 PM PST 23
Peak memory 201964 kb
Host smart-3689f2e4-6d88-4359-b386-400bcbc0df9f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=52568532230170716925978354642664858781316002960381394107939489153165193326390 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 36.xbar_random.52568532230170716925978354642664858781316002960381394107939489153165193326390
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.78126631698294988722448678554706959139610967592629318759235152812811295684539
Short name T724
Test name
Test status
Simulation time 237556670935 ps
CPU time 185.46 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:44:26 PM PST 23
Peak memory 201972 kb
Host smart-b9d34d5d-dd40-431e-a25c-64906156b12c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=78126631698294988722448678554706959139610967592629318759235152812811295684539 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 36.xbar_random_large_delays.78126631698294988722448678554706959139610967592629318759235152812811295684539
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.16626726592020439184719280030559380858771702842403270079839550683723737173847
Short name T604
Test name
Test status
Simulation time 160909483435 ps
CPU time 191.98 seconds
Started Nov 22 01:41:19 PM PST 23
Finished Nov 22 01:44:33 PM PST 23
Peak memory 201356 kb
Host smart-3659b54a-acff-4405-88ef-97bf587cde30
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=16626726592020439184719280030559380858771702842403270079839550683723737173847 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.16626726592020439184719280030559380858771702842403270079839550683723737173847
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.115198247425057155315568990074467863134284134111377316138924264486538585555415
Short name T37
Test name
Test status
Simulation time 360920935 ps
CPU time 7.66 seconds
Started Nov 22 01:41:27 PM PST 23
Finished Nov 22 01:41:37 PM PST 23
Peak memory 201848 kb
Host smart-1e5539bf-b938-4efe-a616-0bea9ab21aee
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115198247425057155315568990074467863134284134111377316138924264486538585555415 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.115198247425057155315568990074467863134284134111377316138924264486538585555415
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.57707018589274052513302326178153863888993394324540125008361801158646780843893
Short name T819
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.54 seconds
Started Nov 22 01:41:11 PM PST 23
Finished Nov 22 01:41:24 PM PST 23
Peak memory 201968 kb
Host smart-de6b6ab3-f307-4da7-aa93-08f35d626af7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57707018589274052513302326178153863888993394324540125008361801158646780843893 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 36.xbar_same_source.57707018589274052513302326178153863888993394324540125008361801158646780843893
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.36408659745200705756395608449957638740136388592437560431070886602129342702550
Short name T151
Test name
Test status
Simulation time 331233435 ps
CPU time 1.6 seconds
Started Nov 22 01:41:25 PM PST 23
Finished Nov 22 01:41:28 PM PST 23
Peak memory 201924 kb
Host smart-1e9ca359-16f7-40ea-9d5f-b152ec4bb213
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36408659745200705756395608449957638740136388592437560431070886602129342702550 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 36.xbar_smoke.36408659745200705756395608449957638740136388592437560431070886602129342702550
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.93152541899923194981543833677589881798279151515626107827164015379055987195891
Short name T88
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.8 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:41:34 PM PST 23
Peak memory 201956 kb
Host smart-0bf2afad-b430-4bfa-8d80-544e2c0af7e1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=93152541899923194981543833677589881798279151515626107827164015379055987195891 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.93152541899923194981543833677589881798279151515626107827164015379055987195891
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.17543354943152819340204601633080663865386417737651485005974149010826844424884
Short name T607
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.8 seconds
Started Nov 22 01:41:33 PM PST 23
Finished Nov 22 01:41:47 PM PST 23
Peak memory 201968 kb
Host smart-2c5aec3e-ec4e-4e10-8e62-7312c7795d2a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=17543354943152819340204601633080663865386417737651485005974149010826844424884 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.17543354943152819340204601633080663865386417737651485005974149010826844424884
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.88203300452360344881501876468806568022558881028789455650131057026456215660321
Short name T419
Test name
Test status
Simulation time 27670935 ps
CPU time 1.27 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:41:24 PM PST 23
Peak memory 201568 kb
Host smart-351764c6-a582-4904-b66a-7256c03aed50
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88203300452360344881501876468806568022558881028789455650131057026456215660321 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.88203300452360344881501876468806568022558881028789455650131057026456215660321
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.18630924274569442494040389382998338601841078174956462387673289992718993941223
Short name T576
Test name
Test status
Simulation time 46147859184 ps
CPU time 134.51 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:43:42 PM PST 23
Peak memory 203176 kb
Host smart-04b5e1a8-c871-445a-a745-c5d281e09a2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18630924274569442494040389382998338601841078174956462387673289992718993941223 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 36.xbar_stress_all.18630924274569442494040389382998338601841078174956462387673289992718993941223
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.39730547550703170727454082622028864431077593875175643862912617652457484043546
Short name T527
Test name
Test status
Simulation time 46147859184 ps
CPU time 117.28 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:43:41 PM PST 23
Peak memory 204924 kb
Host smart-dabfbdb2-76dd-45ba-8b17-b336805f9214
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=39730547550703170727454082622028864431077593875175643862912617652457484043546 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 36.xbar_stress_all_with_error.39730547550703170727454082622028864431077593875175643862912617652457484043546
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.66623527938709779750885245731072796751850071642552987366863833992605861689025
Short name T302
Test name
Test status
Simulation time 13716459184 ps
CPU time 167.13 seconds
Started Nov 22 01:41:23 PM PST 23
Finished Nov 22 01:44:17 PM PST 23
Peak memory 205204 kb
Host smart-7133a6c1-6665-4eaa-80c0-a3b3eff50206
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=66623527938709779750885245731072796751850071642552987366863833992605861689025 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.66623527938709779750885245731072796751850071642552987366863833992605861689025
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.4934094609838060834170453850529879456929112894223605420336153033867861321806
Short name T823
Test name
Test status
Simulation time 13716459184 ps
CPU time 132.4 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:43:31 PM PST 23
Peak memory 206212 kb
Host smart-2033465d-1b0d-4d7d-b809-61ccaf0beb28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4934094609838060834170453850529879456929112894223605420336153033867861321806 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.4934094609838060834170453850529879456929112894223605420336153033867861321806
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.52222863948743289171278864819135643010931207517790557803571339922708219835730
Short name T300
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.18 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:41:38 PM PST 23
Peak memory 201944 kb
Host smart-77bf31d4-7c24-43a1-ba57-c7482a67f7e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=52222863948743289171278864819135643010931207517790557803571339922708219835730 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 36.xbar_unmapped_addr.52222863948743289171278864819135643010931207517790557803571339922708219835730
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.62679239036064099149042257875607411902912066629474873857886929169740419552292
Short name T758
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.08 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:41:49 PM PST 23
Peak memory 201964 kb
Host smart-82ba613b-5272-4ae3-926f-f531a7f632cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62679239036064099149042257875607411902912066629474873857886929169740419552292 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.62679239036064099149042257875607411902912066629474873857886929169740419552292
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.48430534620195426974119245275287940066112605598365452517483610557174822892922
Short name T79
Test name
Test status
Simulation time 260306045935 ps
CPU time 335.91 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:46:59 PM PST 23
Peak memory 202928 kb
Host smart-bbf901bb-6805-4594-8d22-1bce0ebbcc96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=48430534620195426974119245275287940066112605598365452517483610557174822892922 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.48430534620195426974119245275287940066112605598365452517483610557174822892922
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.103808223449176610667759412921193504316879192304376516393946806707050066821441
Short name T380
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.95 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:41:33 PM PST 23
Peak memory 201960 kb
Host smart-42720768-5b58-46ac-8fa6-5d1c3fcf81bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103808223449176610667759412921193504316879192304376516393946806707050066821441 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.103808223449176610667759412921193504316879192304376516393946806707050066821441
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.72963427793440561342451380511203212749666604123585565616585065346143447730241
Short name T472
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.94 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:32 PM PST 23
Peak memory 202000 kb
Host smart-eafa2990-fc4d-4cdd-8837-2cd0e5aa7ebd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72963427793440561342451380511203212749666604123585565616585065346143447730241 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 37.xbar_error_random.72963427793440561342451380511203212749666604123585565616585065346143447730241
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.42787392207845449157670300446333035572525535611165274134780627476664121082489
Short name T538
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.98 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:41:36 PM PST 23
Peak memory 201968 kb
Host smart-db6cac2f-9cee-4c51-ab58-c24be5667a2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=42787392207845449157670300446333035572525535611165274134780627476664121082489 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 37.xbar_random.42787392207845449157670300446333035572525535611165274134780627476664121082489
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.7427761063959587280177982733843057246910244929941760001188033942343190705036
Short name T856
Test name
Test status
Simulation time 237556670935 ps
CPU time 187.27 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:44:25 PM PST 23
Peak memory 201944 kb
Host smart-e2581592-d83f-4be1-a91c-e7910db76c0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=7427761063959587280177982733843057246910244929941760001188033942343190705036 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 37.xbar_random_large_delays.7427761063959587280177982733843057246910244929941760001188033942343190705036
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.91720008885506492262650432871386118247148401784704404574753665774364447560247
Short name T233
Test name
Test status
Simulation time 160909483435 ps
CPU time 192.86 seconds
Started Nov 22 01:41:19 PM PST 23
Finished Nov 22 01:44:34 PM PST 23
Peak memory 202028 kb
Host smart-7cdb784a-4e0a-4bcc-a0eb-013f42c5cfdd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=91720008885506492262650432871386118247148401784704404574753665774364447560247 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.91720008885506492262650432871386118247148401784704404574753665774364447560247
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.60712690800010526179146783668554338026453314179957638013645075464646665966252
Short name T14
Test name
Test status
Simulation time 360920935 ps
CPU time 7.63 seconds
Started Nov 22 01:41:19 PM PST 23
Finished Nov 22 01:41:28 PM PST 23
Peak memory 201400 kb
Host smart-af07cc37-9e1c-46d7-bc48-62eb55ad590b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60712690800010526179146783668554338026453314179957638013645075464646665966252 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.60712690800010526179146783668554338026453314179957638013645075464646665966252
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.21497236692510904343699301649954605916872496347500642323247857746588970507709
Short name T427
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.55 seconds
Started Nov 22 01:41:23 PM PST 23
Finished Nov 22 01:41:36 PM PST 23
Peak memory 201900 kb
Host smart-f103d14b-cd02-472e-945c-a6bc54a52923
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=21497236692510904343699301649954605916872496347500642323247857746588970507709 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 37.xbar_same_source.21497236692510904343699301649954605916872496347500642323247857746588970507709
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.37735029682996284646372096096213138879448051473006563371656180175982245673801
Short name T359
Test name
Test status
Simulation time 331233435 ps
CPU time 1.69 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:41:18 PM PST 23
Peak memory 201932 kb
Host smart-238b9428-7e08-4b0e-9c1e-86ff68af309c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=37735029682996284646372096096213138879448051473006563371656180175982245673801 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 37.xbar_smoke.37735029682996284646372096096213138879448051473006563371656180175982245673801
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.44585793166081053894771458154612738363220365485047025945703797279534362259704
Short name T9
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.74 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:31 PM PST 23
Peak memory 201864 kb
Host smart-30617047-144e-48ba-a80a-6d47072601f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=44585793166081053894771458154612738363220365485047025945703797279534362259704 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.44585793166081053894771458154612738363220365485047025945703797279534362259704
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.88540567859423167076976537396576900420141762443197116999823134990643819897631
Short name T326
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.68 seconds
Started Nov 22 01:41:13 PM PST 23
Finished Nov 22 01:41:28 PM PST 23
Peak memory 202004 kb
Host smart-cab48c01-25b0-49ae-834e-ada51718c988
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=88540567859423167076976537396576900420141762443197116999823134990643819897631 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.88540567859423167076976537396576900420141762443197116999823134990643819897631
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.97336597377869765595875140521062244106671799786337558334442668049509221714012
Short name T181
Test name
Test status
Simulation time 27670935 ps
CPU time 1.17 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:41:25 PM PST 23
Peak memory 201884 kb
Host smart-d5d2297b-d07e-45ac-8688-edfa620e8ff2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97336597377869765595875140521062244106671799786337558334442668049509221714012 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.97336597377869765595875140521062244106671799786337558334442668049509221714012
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.73422937686354043910834629597942041106977096811511395382070870785701773766092
Short name T29
Test name
Test status
Simulation time 46147859184 ps
CPU time 122.07 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:43:39 PM PST 23
Peak memory 203040 kb
Host smart-ff8fce35-abb4-4ac1-8b08-6aa4307332c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73422937686354043910834629597942041106977096811511395382070870785701773766092 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 37.xbar_stress_all.73422937686354043910834629597942041106977096811511395382070870785701773766092
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.106463632252761999358105821575733945456079876737582068392192073636304186025958
Short name T183
Test name
Test status
Simulation time 46147859184 ps
CPU time 119.82 seconds
Started Nov 22 01:41:51 PM PST 23
Finished Nov 22 01:43:53 PM PST 23
Peak memory 203004 kb
Host smart-8fe4ccdb-0141-47e1-9ca9-210ed5f40f8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=106463632252761999358105821575733945456079876737582068392192073636304186025958 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.106463632252761999358105821575733945456079876737582068392192073636304186025958
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.65784077544201011670035841964076510685552107891897772401201623569863858336250
Short name T251
Test name
Test status
Simulation time 13716459184 ps
CPU time 161.63 seconds
Started Nov 22 01:41:35 PM PST 23
Finished Nov 22 01:44:20 PM PST 23
Peak memory 205160 kb
Host smart-128cf107-ed8c-402f-8a68-a71ec949e96b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65784077544201011670035841964076510685552107891897772401201623569863858336250 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.65784077544201011670035841964076510685552107891897772401201623569863858336250
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2712239375529175863431579909817308196078593967919841240637717192599835666615
Short name T312
Test name
Test status
Simulation time 13716459184 ps
CPU time 131.11 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:43:34 PM PST 23
Peak memory 206200 kb
Host smart-c08f7949-bb7a-47d9-857d-2113c9ff55fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2712239375529175863431579909817308196078593967919841240637717192599835666615 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.2712239375529175863431579909817308196078593967919841240637717192599835666615
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.75636417338363987569717132963398789073387035403755818933132161390899680633596
Short name T134
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.11 seconds
Started Nov 22 01:41:14 PM PST 23
Finished Nov 22 01:41:27 PM PST 23
Peak memory 201976 kb
Host smart-9e967adb-724d-4849-a4f2-b0a22dc112e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=75636417338363987569717132963398789073387035403755818933132161390899680633596 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 37.xbar_unmapped_addr.75636417338363987569717132963398789073387035403755818933132161390899680633596
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.36969606907165566749140175043809124474422333805390129780127617968311388861848
Short name T342
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.05 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:41:38 PM PST 23
Peak memory 201948 kb
Host smart-933e773f-e59a-483c-9479-59653fae42c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36969606907165566749140175043809124474422333805390129780127617968311388861848 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.36969606907165566749140175043809124474422333805390129780127617968311388861848
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.41199229305002287317518572272698260657972516713366563796535200867869712573078
Short name T782
Test name
Test status
Simulation time 260306045935 ps
CPU time 336.29 seconds
Started Nov 22 01:41:28 PM PST 23
Finished Nov 22 01:47:06 PM PST 23
Peak memory 203032 kb
Host smart-1094a619-a861-481c-92d0-83e96dc54d9d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=41199229305002287317518572272698260657972516713366563796535200867869712573078 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.41199229305002287317518572272698260657972516713366563796535200867869712573078
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.37825860101082343161997504403587546893845319117839134959788613648939474251761
Short name T737
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.99 seconds
Started Nov 22 01:41:38 PM PST 23
Finished Nov 22 01:41:50 PM PST 23
Peak memory 202004 kb
Host smart-35548023-597b-4bb4-b507-0564230281b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=37825860101082343161997504403587546893845319117839134959788613648939474251761 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.37825860101082343161997504403587546893845319117839134959788613648939474251761
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.66230815961415717011876272767389101810252630497443166345208216313569700934637
Short name T601
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.35 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:42:02 PM PST 23
Peak memory 201924 kb
Host smart-57674a17-8d65-4965-8b1a-80c2b92a5a9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=66230815961415717011876272767389101810252630497443166345208216313569700934637 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 38.xbar_error_random.66230815961415717011876272767389101810252630497443166345208216313569700934637
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.102768210631333133056052907205789385811100361120953544115668070664807343835270
Short name T286
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.95 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:33 PM PST 23
Peak memory 202004 kb
Host smart-e17f5702-d684-420e-90aa-22a53e0973bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102768210631333133056052907205789385811100361120953544115668070664807343835270 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 38.xbar_random.102768210631333133056052907205789385811100361120953544115668070664807343835270
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.55627973369961506684791840611967747841172216423541491983840302627391410935198
Short name T656
Test name
Test status
Simulation time 237556670935 ps
CPU time 187.88 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:44:57 PM PST 23
Peak memory 201920 kb
Host smart-22638aae-6b57-4ccb-8d9e-3b2101c0433d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=55627973369961506684791840611967747841172216423541491983840302627391410935198 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 38.xbar_random_large_delays.55627973369961506684791840611967747841172216423541491983840302627391410935198
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.24684501643026560017597311130141830581755529100614567891254851546127058717573
Short name T133
Test name
Test status
Simulation time 160909483435 ps
CPU time 193.2 seconds
Started Nov 22 01:41:33 PM PST 23
Finished Nov 22 01:44:49 PM PST 23
Peak memory 202008 kb
Host smart-c68e3460-95ea-49e4-bff7-acfda8f3c426
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=24684501643026560017597311130141830581755529100614567891254851546127058717573 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.24684501643026560017597311130141830581755529100614567891254851546127058717573
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.53361398184016701710020804396881700447869305598081913614449361396729184070954
Short name T691
Test name
Test status
Simulation time 360920935 ps
CPU time 7.58 seconds
Started Nov 22 01:42:04 PM PST 23
Finished Nov 22 01:42:18 PM PST 23
Peak memory 201848 kb
Host smart-45f5f235-175e-4440-b1a6-1fce77f1cd60
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53361398184016701710020804396881700447869305598081913614449361396729184070954 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.53361398184016701710020804396881700447869305598081913614449361396729184070954
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.41616410730906869404648172688432872636369131288549466392365012150888905204175
Short name T242
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.66 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:41:35 PM PST 23
Peak memory 202004 kb
Host smart-d3ce08b8-879a-4271-a7e1-c7f106ba0507
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=41616410730906869404648172688432872636369131288549466392365012150888905204175 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 38.xbar_same_source.41616410730906869404648172688432872636369131288549466392365012150888905204175
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.76376097051777960797685906669285033341998354687189701998234434069429887211136
Short name T877
Test name
Test status
Simulation time 331233435 ps
CPU time 1.54 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:41:39 PM PST 23
Peak memory 201904 kb
Host smart-99846cf4-4730-4712-a24d-7efcb8af407f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76376097051777960797685906669285033341998354687189701998234434069429887211136 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 38.xbar_smoke.76376097051777960797685906669285033341998354687189701998234434069429887211136
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.110198068429359208044380406180413223062980385195780379938052643595255033294250
Short name T505
Test name
Test status
Simulation time 15405233435 ps
CPU time 13.84 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:41:51 PM PST 23
Peak memory 202036 kb
Host smart-7ae1dcc9-e17f-487f-9855-977dfe4722b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=110198068429359208044380406180413223062980385195780379938052643595255033294250 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.110198068429359208044380406180413223062980385195780379938052643595255033294250
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.21070039982751274233004753486229997898188997691536589677570960240322587935506
Short name T104
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.72 seconds
Started Nov 22 01:41:33 PM PST 23
Finished Nov 22 01:41:47 PM PST 23
Peak memory 202020 kb
Host smart-e51c47f2-b396-4c1b-8273-166b7e5ca59d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=21070039982751274233004753486229997898188997691536589677570960240322587935506 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.21070039982751274233004753486229997898188997691536589677570960240322587935506
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.55658594490338899488623886154174571521908764653262223834645363174489345691888
Short name T277
Test name
Test status
Simulation time 27670935 ps
CPU time 1.18 seconds
Started Nov 22 01:41:36 PM PST 23
Finished Nov 22 01:41:40 PM PST 23
Peak memory 201896 kb
Host smart-3d4aeb5a-ac09-4420-a48e-d679c46bf081
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55658594490338899488623886154174571521908764653262223834645363174489345691888 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.55658594490338899488623886154174571521908764653262223834645363174489345691888
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.3417937217040331828198415679861781466977081938207641406253345370206413764734
Short name T639
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.7 seconds
Started Nov 22 01:42:09 PM PST 23
Finished Nov 22 01:44:24 PM PST 23
Peak memory 203220 kb
Host smart-0734e0a1-8c94-4640-8028-193f39708c9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3417937217040331828198415679861781466977081938207641406253345370206413764734 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_
log /dev/null -cm_name 38.xbar_stress_all.3417937217040331828198415679861781466977081938207641406253345370206413764734
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.70237645677312566372129295114097883454011254313700285448122584905339890870679
Short name T95
Test name
Test status
Simulation time 46147859184 ps
CPU time 114.78 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:43:41 PM PST 23
Peak memory 204952 kb
Host smart-578bfc28-d6fd-410b-9634-78674003f0ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70237645677312566372129295114097883454011254313700285448122584905339890870679 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 38.xbar_stress_all_with_error.70237645677312566372129295114097883454011254313700285448122584905339890870679
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.103657716859709544730325097221820479274820329096123341727212676965263465111568
Short name T355
Test name
Test status
Simulation time 13716459184 ps
CPU time 164.02 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:44:36 PM PST 23
Peak memory 205136 kb
Host smart-cde5e49e-12a4-4486-9318-cc0b031b3a84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103657716859709544730325097221820479274820329096123341727212676965263465111568 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.103657716859709544730325097221820479274820329096123341727212676965263465111568
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.102431732702477562667781135956425703785450605255425149859633983376183782691040
Short name T806
Test name
Test status
Simulation time 13716459184 ps
CPU time 134.44 seconds
Started Nov 22 01:41:29 PM PST 23
Finished Nov 22 01:43:45 PM PST 23
Peak memory 206172 kb
Host smart-1ab54f07-cc96-44a4-87c8-b34b2cfcec74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102431732702477562667781135956425703785450605255425149859633983376183782691040 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.102431732702477562667781135956425703785450605255425149859633983376183782691040
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.76112608146612342670268158570235040908720442664895771851653374948592054712878
Short name T845
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.21 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:41:58 PM PST 23
Peak memory 202000 kb
Host smart-d7e310b6-7e39-4ca2-979d-4716401c442f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76112608146612342670268158570235040908720442664895771851653374948592054712878 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 38.xbar_unmapped_addr.76112608146612342670268158570235040908720442664895771851653374948592054712878
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.11834529447612854124249385218296382087300334602915352302520602611285537688660
Short name T261
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.31 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:42:08 PM PST 23
Peak memory 201980 kb
Host smart-ee80efe0-3380-482d-b412-ab4aef766073
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=11834529447612854124249385218296382087300334602915352302520602611285537688660 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.11834529447612854124249385218296382087300334602915352302520602611285537688660
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.75947094697543748106796766063598828510971959619975399316899331070429472327449
Short name T533
Test name
Test status
Simulation time 260306045935 ps
CPU time 331.52 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:47:09 PM PST 23
Peak memory 202896 kb
Host smart-86db69ae-7aa9-4874-9840-70c4d5da60c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=75947094697543748106796766063598828510971959619975399316899331070429472327449 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.75947094697543748106796766063598828510971959619975399316899331070429472327449
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.27332928520861125130490064720970502031006391472769671842592477771209155876131
Short name T334
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.13 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:41:53 PM PST 23
Peak memory 201856 kb
Host smart-7860f746-f351-40c6-b846-ee94828aede0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27332928520861125130490064720970502031006391472769671842592477771209155876131 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.27332928520861125130490064720970502031006391472769671842592477771209155876131
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.91908093437234988396266254119463811169743763756216845813628755155877652358895
Short name T481
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.17 seconds
Started Nov 22 01:41:34 PM PST 23
Finished Nov 22 01:41:51 PM PST 23
Peak memory 201980 kb
Host smart-3cf9021d-ee7f-480f-a593-9fbd33da30bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91908093437234988396266254119463811169743763756216845813628755155877652358895 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 39.xbar_error_random.91908093437234988396266254119463811169743763756216845813628755155877652358895
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.31255474310314363378607570948562465095410703882237735300167260432976946721714
Short name T69
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.38 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:41:46 PM PST 23
Peak memory 201988 kb
Host smart-2ed56bb0-b01e-4dff-9ba3-f9ecfb865470
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31255474310314363378607570948562465095410703882237735300167260432976946721714 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 39.xbar_random.31255474310314363378607570948562465095410703882237735300167260432976946721714
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.83289070601254267413602423233015763217221771145605824799533634610242853760224
Short name T821
Test name
Test status
Simulation time 237556670935 ps
CPU time 187.94 seconds
Started Nov 22 01:41:24 PM PST 23
Finished Nov 22 01:44:38 PM PST 23
Peak memory 201992 kb
Host smart-e575ff73-72c8-4751-8bf7-90742f4e436b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=83289070601254267413602423233015763217221771145605824799533634610242853760224 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 39.xbar_random_large_delays.83289070601254267413602423233015763217221771145605824799533634610242853760224
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.42018280791208179527395915136063503834866206019194476987719973958233532657600
Short name T129
Test name
Test status
Simulation time 160909483435 ps
CPU time 193.16 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:44:40 PM PST 23
Peak memory 201860 kb
Host smart-cda64010-dbae-44fc-b362-adb1560d4f36
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=42018280791208179527395915136063503834866206019194476987719973958233532657600 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.42018280791208179527395915136063503834866206019194476987719973958233532657600
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.108945808909434448436637657307334664864807450665867986490032999928555113119143
Short name T235
Test name
Test status
Simulation time 360920935 ps
CPU time 7.46 seconds
Started Nov 22 01:41:19 PM PST 23
Finished Nov 22 01:41:27 PM PST 23
Peak memory 201936 kb
Host smart-1be8ddc3-a88b-451b-ad4e-7ec0d34d485b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108945808909434448436637657307334664864807450665867986490032999928555113119143 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.108945808909434448436637657307334664864807450665867986490032999928555113119143
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.63153290303595746357979435882899827825802507185456453151639853736803785674887
Short name T627
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.11 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:41:32 PM PST 23
Peak memory 201900 kb
Host smart-b6831fb0-f17f-4520-a884-f155b1fa622f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=63153290303595746357979435882899827825802507185456453151639853736803785674887 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 39.xbar_same_source.63153290303595746357979435882899827825802507185456453151639853736803785674887
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.66884828277935411102394303694711939334840554988084757002681271972523519274271
Short name T711
Test name
Test status
Simulation time 331233435 ps
CPU time 1.55 seconds
Started Nov 22 01:42:10 PM PST 23
Finished Nov 22 01:42:17 PM PST 23
Peak memory 201936 kb
Host smart-a40a2a16-29c0-4a14-81e7-aa3829ab6e01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=66884828277935411102394303694711939334840554988084757002681271972523519274271 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 39.xbar_smoke.66884828277935411102394303694711939334840554988084757002681271972523519274271
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.18801542196659211666978637127698423058004601360475351342580391107625636587589
Short name T676
Test name
Test status
Simulation time 15405233435 ps
CPU time 13.11 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:41:31 PM PST 23
Peak memory 201980 kb
Host smart-d33cf10c-97cf-475a-a8f8-b21658fab3e1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=18801542196659211666978637127698423058004601360475351342580391107625636587589 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.18801542196659211666978637127698423058004601360475351342580391107625636587589
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.24989033357382402374114282275032676103859259307738134380448176634679397130629
Short name T560
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.81 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:41:44 PM PST 23
Peak memory 201984 kb
Host smart-fc76b241-8ded-4381-b6e2-c7fdc7443ca8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=24989033357382402374114282275032676103859259307738134380448176634679397130629 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.24989033357382402374114282275032676103859259307738134380448176634679397130629
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.86410623672689731319977579262794834858512667416368597729438004645783889886127
Short name T290
Test name
Test status
Simulation time 27670935 ps
CPU time 1.14 seconds
Started Nov 22 01:41:38 PM PST 23
Finished Nov 22 01:41:41 PM PST 23
Peak memory 201940 kb
Host smart-4b188a15-e0ab-4d24-a4f4-03a5c2d35261
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86410623672689731319977579262794834858512667416368597729438004645783889886127 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.86410623672689731319977579262794834858512667416368597729438004645783889886127
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.10877107304652614710393501097990443764426017694384089307596728178319531057534
Short name T332
Test name
Test status
Simulation time 46147859184 ps
CPU time 127.96 seconds
Started Nov 22 01:41:51 PM PST 23
Finished Nov 22 01:44:01 PM PST 23
Peak memory 203188 kb
Host smart-3cafc815-c381-419a-8284-6791d2547c56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10877107304652614710393501097990443764426017694384089307596728178319531057534 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 39.xbar_stress_all.10877107304652614710393501097990443764426017694384089307596728178319531057534
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.28591364773685116189055302209081792069720812169877120373346289672261444144976
Short name T102
Test name
Test status
Simulation time 46147859184 ps
CPU time 117.5 seconds
Started Nov 22 01:41:28 PM PST 23
Finished Nov 22 01:43:27 PM PST 23
Peak memory 204880 kb
Host smart-20b795e7-2521-450c-ae81-c55a52ea8a1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28591364773685116189055302209081792069720812169877120373346289672261444144976 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 39.xbar_stress_all_with_error.28591364773685116189055302209081792069720812169877120373346289672261444144976
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.93395193716920539994830650753350554073988135085507018856735832595473110547215
Short name T524
Test name
Test status
Simulation time 13716459184 ps
CPU time 160.67 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:44:26 PM PST 23
Peak memory 205184 kb
Host smart-ad534f72-3750-4388-914b-6afbd4ccc0f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93395193716920539994830650753350554073988135085507018856735832595473110547215 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.93395193716920539994830650753350554073988135085507018856735832595473110547215
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.27608823136854460722872054353496149006555281231750567984650625457329639787082
Short name T477
Test name
Test status
Simulation time 13716459184 ps
CPU time 135.87 seconds
Started Nov 22 01:41:35 PM PST 23
Finished Nov 22 01:43:54 PM PST 23
Peak memory 206232 kb
Host smart-f3d2904a-cb9c-419a-9ff6-49f567859feb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27608823136854460722872054353496149006555281231750567984650625457329639787082 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.27608823136854460722872054353496149006555281231750567984650625457329639787082
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.57181940426142319042885216317096746401595394992990912967498365067401500694692
Short name T26
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.05 seconds
Started Nov 22 01:41:39 PM PST 23
Finished Nov 22 01:41:52 PM PST 23
Peak memory 201864 kb
Host smart-3a7f55fd-9c1c-4550-91a0-7a9340e7f251
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57181940426142319042885216317096746401595394992990912967498365067401500694692 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 39.xbar_unmapped_addr.57181940426142319042885216317096746401595394992990912967498365067401500694692
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.27869986539225929675914854231693555529386281618238335127931595081466314251189
Short name T187
Test name
Test status
Simulation time 4712795935 ps
CPU time 16.69 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:40:43 PM PST 23
Peak memory 201972 kb
Host smart-178c0d62-675a-4054-885e-b98f99292894
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27869986539225929675914854231693555529386281618238335127931595081466314251189 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.27869986539225929675914854231693555529386281618238335127931595081466314251189
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.103793770466276717525748969048653141114278076841832412116733620666237682851482
Short name T80
Test name
Test status
Simulation time 260306045935 ps
CPU time 338.83 seconds
Started Nov 22 01:40:29 PM PST 23
Finished Nov 22 01:46:10 PM PST 23
Peak memory 203004 kb
Host smart-f86b39d6-0f6e-48cf-a34c-c943bc5ee487
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=103793770466276717525748969048653141114278076841832412116733620666237682851482 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.103793770466276717525748969048653141114278076841832412116733620666237682851482
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2556479268769733556411262502383865215208673711935978892350803637271612917256
Short name T197
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.13 seconds
Started Nov 22 01:40:32 PM PST 23
Finished Nov 22 01:40:44 PM PST 23
Peak memory 201960 kb
Host smart-1565cca9-ec78-4fbc-96b4-cdf7f56c31ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2556479268769733556411262502383865215208673711935978892350803637271612917256 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2556479268769733556411262502383865215208673711935978892350803637271612917256
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.96864104877069187730325405916701656641132004503135199216243196207872640970023
Short name T846
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.92 seconds
Started Nov 22 01:40:36 PM PST 23
Finished Nov 22 01:40:51 PM PST 23
Peak memory 201828 kb
Host smart-2a2180cb-ad4e-46e0-aa1c-418c4467d8d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96864104877069187730325405916701656641132004503135199216243196207872640970023 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 4.xbar_error_random.96864104877069187730325405916701656641132004503135199216243196207872640970023
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.70635581901140182868162016515978992245208572737925224088873374179407913345370
Short name T574
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.59 seconds
Started Nov 22 01:40:13 PM PST 23
Finished Nov 22 01:40:29 PM PST 23
Peak memory 201892 kb
Host smart-2692f380-cf35-40d6-a54e-1d26203776cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70635581901140182868162016515978992245208572737925224088873374179407913345370 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 4.xbar_random.70635581901140182868162016515978992245208572737925224088873374179407913345370
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.106392221808040410770725296595294063899657470732862768485731085981584225842547
Short name T257
Test name
Test status
Simulation time 237556670935 ps
CPU time 190.84 seconds
Started Nov 22 01:40:26 PM PST 23
Finished Nov 22 01:43:38 PM PST 23
Peak memory 201424 kb
Host smart-0c7e2dee-4b1e-496c-8eda-9fde1647b34e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=106392221808040410770725296595294063899657470732862768485731085981584225842547 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.106392221808040410770725296595294063899657470732862768485731085981584225842547
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.93584243079788250094923945732702653535905185279065677844444538406306123763805
Short name T279
Test name
Test status
Simulation time 160909483435 ps
CPU time 191.3 seconds
Started Nov 22 01:40:24 PM PST 23
Finished Nov 22 01:43:37 PM PST 23
Peak memory 201972 kb
Host smart-dafe1d08-c14f-469d-8507-46e83214415d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=93584243079788250094923945732702653535905185279065677844444538406306123763805 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.93584243079788250094923945732702653535905185279065677844444538406306123763805
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.61353748986194663622952793609835893121921722453442835925094400163468139951649
Short name T484
Test name
Test status
Simulation time 360920935 ps
CPU time 7.61 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:40:20 PM PST 23
Peak memory 201976 kb
Host smart-b8e55ec7-8cfc-415e-8c62-fc7d9bf30cfd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61353748986194663622952793609835893121921722453442835925094400163468139951649 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.61353748986194663622952793609835893121921722453442835925094400163468139951649
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.82752439469603469876220339630241411305612253212097565910191522023933427241783
Short name T747
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.98 seconds
Started Nov 22 01:40:34 PM PST 23
Finished Nov 22 01:40:49 PM PST 23
Peak memory 202004 kb
Host smart-b476f781-a9e1-43aa-b3a5-c4440394f0d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=82752439469603469876220339630241411305612253212097565910191522023933427241783 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 4.xbar_same_source.82752439469603469876220339630241411305612253212097565910191522023933427241783
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.19617190239174837240802036642856850773134528324116031275681217293685421747991
Short name T861
Test name
Test status
Simulation time 331233435 ps
CPU time 1.51 seconds
Started Nov 22 01:40:23 PM PST 23
Finished Nov 22 01:40:26 PM PST 23
Peak memory 201904 kb
Host smart-c5caf16a-e382-421f-a9af-efeae1d8a501
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=19617190239174837240802036642856850773134528324116031275681217293685421747991 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 4.xbar_smoke.19617190239174837240802036642856850773134528324116031275681217293685421747991
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.54281058244229441666338599052742300532595676300006090346749573146109909838041
Short name T773
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.81 seconds
Started Nov 22 01:40:13 PM PST 23
Finished Nov 22 01:40:28 PM PST 23
Peak memory 201744 kb
Host smart-3c832476-f974-4699-b692-7578f5d2bc0a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=54281058244229441666338599052742300532595676300006090346749573146109909838041 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.54281058244229441666338599052742300532595676300006090346749573146109909838041
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.109254338683077563833911709716070555383175765896401868682307093787273155321653
Short name T564
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.58 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:40:22 PM PST 23
Peak memory 201988 kb
Host smart-970e7ccf-0731-4af2-a01c-5acca3e18b2f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=109254338683077563833911709716070555383175765896401868682307093787273155321653 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.109254338683077563833911709716070555383175765896401868682307093787273155321653
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.37124465866473725922328285345581799614095670822896805499781961179990075278980
Short name T352
Test name
Test status
Simulation time 27670935 ps
CPU time 1.14 seconds
Started Nov 22 01:40:24 PM PST 23
Finished Nov 22 01:40:26 PM PST 23
Peak memory 201904 kb
Host smart-3f2cd621-c043-42b2-87a9-0b462af62bdc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37124465866473725922328285345581799614095670822896805499781961179990075278980 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.37124465866473725922328285345581799614095670822896805499781961179990075278980
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.34716789900564663271125870803198613774819574032530336146649207488489756727069
Short name T229
Test name
Test status
Simulation time 46147859184 ps
CPU time 122.86 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:42:15 PM PST 23
Peak memory 203040 kb
Host smart-07bdce05-9f1f-4253-b885-c4f656b0e680
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34716789900564663271125870803198613774819574032530336146649207488489756727069 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 4.xbar_stress_all.34716789900564663271125870803198613774819574032530336146649207488489756727069
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.54251259042882617772488844539700698923506556142979250226767199063161449980338
Short name T775
Test name
Test status
Simulation time 46147859184 ps
CPU time 118.85 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:43:19 PM PST 23
Peak memory 204888 kb
Host smart-dbd86cd9-13f8-41d5-9bc7-6414823ee6b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54251259042882617772488844539700698923506556142979250226767199063161449980338 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 4.xbar_stress_all_with_error.54251259042882617772488844539700698923506556142979250226767199063161449980338
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3812571202699334330363656261200150455116151660044544855595862447328184479257
Short name T558
Test name
Test status
Simulation time 13716459184 ps
CPU time 160 seconds
Started Nov 22 01:40:38 PM PST 23
Finished Nov 22 01:43:19 PM PST 23
Peak memory 205080 kb
Host smart-92c99238-280e-4559-bb2f-116e7a39f3f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3812571202699334330363656261200150455116151660044544855595862447328184479257 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.3812571202699334330363656261200150455116151660044544855595862447328184479257
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.98261283752223027410047757651867954195866209411351492685521772700905698953361
Short name T177
Test name
Test status
Simulation time 13716459184 ps
CPU time 140.03 seconds
Started Nov 22 01:41:00 PM PST 23
Finished Nov 22 01:43:21 PM PST 23
Peak memory 206272 kb
Host smart-d0d69cb5-a3a1-4c86-a202-7ac142f1d788
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98261283752223027410047757651867954195866209411351492685521772700905698953361 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.98261283752223027410047757651867954195866209411351492685521772700905698953361
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.110309177029236027850166559730126853689422998555549567314491270251675377946021
Short name T618
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.93 seconds
Started Nov 22 01:41:13 PM PST 23
Finished Nov 22 01:41:25 PM PST 23
Peak memory 201992 kb
Host smart-6fae2738-e4e8-4f92-aa2d-2211ffa67875
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110309177029236027850166559730126853689422998555549567314491270251675377946021 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 4.xbar_unmapped_addr.110309177029236027850166559730126853689422998555549567314491270251675377946021
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.909997502393626564889651283517729012307813835386433347838205563429917704625
Short name T143
Test name
Test status
Simulation time 4712795935 ps
CPU time 16.79 seconds
Started Nov 22 01:42:03 PM PST 23
Finished Nov 22 01:42:27 PM PST 23
Peak memory 202036 kb
Host smart-83b62111-1fba-43e9-8fac-8705d7ed9b33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=909997502393626564889651283517729012307813835386433347838205563429917704625 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 40.xbar_access_same_device.909997502393626564889651283517729012307813835386433347838205563429917704625
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.23296984210731384393716944303570249734576521904114925805541032043558629545155
Short name T717
Test name
Test status
Simulation time 260306045935 ps
CPU time 329.99 seconds
Started Nov 22 01:41:40 PM PST 23
Finished Nov 22 01:47:12 PM PST 23
Peak memory 203036 kb
Host smart-5d90804b-e024-4e6a-9606-d4b44a63de73
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=23296984210731384393716944303570249734576521904114925805541032043558629545155 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.23296984210731384393716944303570249734576521904114925805541032043558629545155
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.100173522617229998887872140754392039663939915381518394894200238364414963850829
Short name T760
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.93 seconds
Started Nov 22 01:41:56 PM PST 23
Finished Nov 22 01:42:10 PM PST 23
Peak memory 201792 kb
Host smart-a94d434a-25aa-43e7-8db1-5a0c28d1dd3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100173522617229998887872140754392039663939915381518394894200238364414963850829 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.100173522617229998887872140754392039663939915381518394894200238364414963850829
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.36802567728027487189141441177256832367102088556542385299183467024041506624723
Short name T174
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.79 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:41:53 PM PST 23
Peak memory 201992 kb
Host smart-0efdb891-edbf-44f7-8bee-658b557d2b83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36802567728027487189141441177256832367102088556542385299183467024041506624723 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 40.xbar_error_random.36802567728027487189141441177256832367102088556542385299183467024041506624723
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.112651938623464934279770756018216749381077579147286370344569882658341551464597
Short name T768
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.94 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:41:58 PM PST 23
Peak memory 201884 kb
Host smart-86557fb6-c7c2-4fac-b3ec-e76b70d55b21
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112651938623464934279770756018216749381077579147286370344569882658341551464597 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 40.xbar_random.112651938623464934279770756018216749381077579147286370344569882658341551464597
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.63458492908282018975469890631801879457874864852194231838554115992260257341882
Short name T523
Test name
Test status
Simulation time 237556670935 ps
CPU time 188.56 seconds
Started Nov 22 01:41:39 PM PST 23
Finished Nov 22 01:44:50 PM PST 23
Peak memory 202024 kb
Host smart-2f4877a0-2fd9-4cbf-b956-c7b0098afc84
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=63458492908282018975469890631801879457874864852194231838554115992260257341882 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 40.xbar_random_large_delays.63458492908282018975469890631801879457874864852194231838554115992260257341882
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.37546648072686592668085512851535401935579287462871790288824559988024211279276
Short name T59
Test name
Test status
Simulation time 160909483435 ps
CPU time 194.39 seconds
Started Nov 22 01:41:39 PM PST 23
Finished Nov 22 01:44:56 PM PST 23
Peak memory 201884 kb
Host smart-0d7ac0ae-7daa-4a46-abea-a46f7ce41120
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=37546648072686592668085512851535401935579287462871790288824559988024211279276 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.37546648072686592668085512851535401935579287462871790288824559988024211279276
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.71586549265559539342264472757399817538236424094268059299597436106264438763303
Short name T796
Test name
Test status
Simulation time 360920935 ps
CPU time 7.56 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:41:55 PM PST 23
Peak memory 201956 kb
Host smart-57f65a62-f74f-42c0-a142-a068dc8c778c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71586549265559539342264472757399817538236424094268059299597436106264438763303 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.71586549265559539342264472757399817538236424094268059299597436106264438763303
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.2988326436472280242644713931629872966395387061763396846557328655225319862388
Short name T543
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.72 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:42:04 PM PST 23
Peak memory 201956 kb
Host smart-82591778-d06f-4e36-bc2c-16a314374c91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2988326436472280242644713931629872966395387061763396846557328655225319862388 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 40.xbar_same_source.2988326436472280242644713931629872966395387061763396846557328655225319862388
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.84518695110585271091286512066297629289857454232137918534386870123702417613973
Short name T894
Test name
Test status
Simulation time 331233435 ps
CPU time 1.6 seconds
Started Nov 22 01:42:03 PM PST 23
Finished Nov 22 01:42:12 PM PST 23
Peak memory 201852 kb
Host smart-b3f9fb35-f2e6-4547-8341-c322b8c8df09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=84518695110585271091286512066297629289857454232137918534386870123702417613973 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 40.xbar_smoke.84518695110585271091286512066297629289857454232137918534386870123702417613973
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.63166612984592025410305206131433387059067729855935366771121008270843654231102
Short name T586
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.74 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:41:44 PM PST 23
Peak memory 201968 kb
Host smart-46fbbbd1-3cb7-47ec-9fc6-6980e7f88956
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=63166612984592025410305206131433387059067729855935366771121008270843654231102 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.63166612984592025410305206131433387059067729855935366771121008270843654231102
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.62550253926153292718830970974170039849904264346856221686224298516279200216922
Short name T709
Test name
Test status
Simulation time 10098608435 ps
CPU time 13.01 seconds
Started Nov 22 01:41:29 PM PST 23
Finished Nov 22 01:41:44 PM PST 23
Peak memory 201968 kb
Host smart-89253c44-3c2e-42b0-8f99-7d3fb46949c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=62550253926153292718830970974170039849904264346856221686224298516279200216922 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.62550253926153292718830970974170039849904264346856221686224298516279200216922
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.33145121110942331932889716978566461099925087274594971591519657755005174218653
Short name T774
Test name
Test status
Simulation time 27670935 ps
CPU time 1.13 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:41:48 PM PST 23
Peak memory 201744 kb
Host smart-8760d9e5-2159-482e-809b-7306e42e7fd9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33145121110942331932889716978566461099925087274594971591519657755005174218653 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.33145121110942331932889716978566461099925087274594971591519657755005174218653
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.61726335622280078882428537085443609540444610146635178761498104172551749881777
Short name T408
Test name
Test status
Simulation time 46147859184 ps
CPU time 123.37 seconds
Started Nov 22 01:41:39 PM PST 23
Finished Nov 22 01:43:44 PM PST 23
Peak memory 203184 kb
Host smart-7199a418-aefb-4add-8c95-c36dda02e33f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=61726335622280078882428537085443609540444610146635178761498104172551749881777 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 40.xbar_stress_all.61726335622280078882428537085443609540444610146635178761498104172551749881777
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.96892076725587275589086293764718750244763861337884929828898596457103065570376
Short name T287
Test name
Test status
Simulation time 46147859184 ps
CPU time 114.86 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:43:46 PM PST 23
Peak memory 204860 kb
Host smart-cd2e93ec-dfa6-401f-849c-96ff21ddbff0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96892076725587275589086293764718750244763861337884929828898596457103065570376 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 40.xbar_stress_all_with_error.96892076725587275589086293764718750244763861337884929828898596457103065570376
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.56383625373722525937749325792452497366489558861649259810715623328755719229394
Short name T330
Test name
Test status
Simulation time 13716459184 ps
CPU time 159.47 seconds
Started Nov 22 01:41:40 PM PST 23
Finished Nov 22 01:44:22 PM PST 23
Peak memory 205172 kb
Host smart-79eef2ef-5639-4715-aeb5-a3fd3c73dbca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56383625373722525937749325792452497366489558861649259810715623328755719229394 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.56383625373722525937749325792452497366489558861649259810715623328755719229394
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.31632478712012185636237239551174330324341593278284335701071661887341654194366
Short name T884
Test name
Test status
Simulation time 13716459184 ps
CPU time 136.32 seconds
Started Nov 22 01:41:50 PM PST 23
Finished Nov 22 01:44:09 PM PST 23
Peak memory 206192 kb
Host smart-a9d0341a-01c3-4eae-ac4b-1b5edd14f483
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31632478712012185636237239551174330324341593278284335701071661887341654194366 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.31632478712012185636237239551174330324341593278284335701071661887341654194366
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.52192411156404878343243287536765574101166230623023795367773024033001912807130
Short name T573
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.98 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:41:59 PM PST 23
Peak memory 202000 kb
Host smart-c3a63dda-3dd7-46d1-9dd5-85f3afb2e14a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=52192411156404878343243287536765574101166230623023795367773024033001912807130 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 40.xbar_unmapped_addr.52192411156404878343243287536765574101166230623023795367773024033001912807130
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.57142478370201356444408865050980191945490886333979524768086466754889611462043
Short name T56
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.41 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:41:46 PM PST 23
Peak memory 201964 kb
Host smart-83c5c088-f219-400b-94ba-8a36a6839e8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57142478370201356444408865050980191945490886333979524768086466754889611462043 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.57142478370201356444408865050980191945490886333979524768086466754889611462043
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.85149688718960231738987358489360561110642732592129580514689711589390194765877
Short name T329
Test name
Test status
Simulation time 260306045935 ps
CPU time 322.27 seconds
Started Nov 22 01:42:32 PM PST 23
Finished Nov 22 01:47:59 PM PST 23
Peak memory 202420 kb
Host smart-dc0b622b-2881-4564-9a2a-b4a5f8400673
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=85149688718960231738987358489360561110642732592129580514689711589390194765877 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.85149688718960231738987358489360561110642732592129580514689711589390194765877
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.59797215037849498332396925774617747342314605520449852086162932971255033854418
Short name T116
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.77 seconds
Started Nov 22 01:41:50 PM PST 23
Finished Nov 22 01:42:03 PM PST 23
Peak memory 201816 kb
Host smart-3d003d42-4d2f-4b31-9d0e-15de40d80ded
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59797215037849498332396925774617747342314605520449852086162932971255033854418 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.59797215037849498332396925774617747342314605520449852086162932971255033854418
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.74389645320969740339237255978905928842242249130896261592324895063364478943678
Short name T441
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.97 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:32 PM PST 23
Peak memory 201884 kb
Host smart-de2527c7-f19b-4a19-97b1-9c217479cf54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=74389645320969740339237255978905928842242249130896261592324895063364478943678 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 41.xbar_error_random.74389645320969740339237255978905928842242249130896261592324895063364478943678
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.17825178838272150655829478982691035436396657416411568531850039410119462085893
Short name T602
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.77 seconds
Started Nov 22 01:41:50 PM PST 23
Finished Nov 22 01:42:06 PM PST 23
Peak memory 201916 kb
Host smart-97974f4a-bfbc-4915-b19c-861d13b4f2a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=17825178838272150655829478982691035436396657416411568531850039410119462085893 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 41.xbar_random.17825178838272150655829478982691035436396657416411568531850039410119462085893
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.53277461653828069755788319961189121996388935900436309544802058895137603618164
Short name T828
Test name
Test status
Simulation time 237556670935 ps
CPU time 186.5 seconds
Started Nov 22 01:41:40 PM PST 23
Finished Nov 22 01:44:48 PM PST 23
Peak memory 201852 kb
Host smart-ea536443-4c86-4a32-9411-f1767cda33a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=53277461653828069755788319961189121996388935900436309544802058895137603618164 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 41.xbar_random_large_delays.53277461653828069755788319961189121996388935900436309544802058895137603618164
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.98419590177376728105512527699789637146550312070808373465428437583506146319411
Short name T57
Test name
Test status
Simulation time 160909483435 ps
CPU time 190.46 seconds
Started Nov 22 01:41:41 PM PST 23
Finished Nov 22 01:44:53 PM PST 23
Peak memory 201844 kb
Host smart-1081bc53-4dc8-4e74-8cbe-61b8afd3bae9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=98419590177376728105512527699789637146550312070808373465428437583506146319411 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.98419590177376728105512527699789637146550312070808373465428437583506146319411
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.102680262525207495277695335004237203062919509628265807587909443126719919056799
Short name T390
Test name
Test status
Simulation time 360920935 ps
CPU time 7.73 seconds
Started Nov 22 01:42:07 PM PST 23
Finished Nov 22 01:42:19 PM PST 23
Peak memory 201924 kb
Host smart-cc78a8b8-c813-4d5a-a5a1-e7d35d475959
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102680262525207495277695335004237203062919509628265807587909443126719919056799 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.102680262525207495277695335004237203062919509628265807587909443126719919056799
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.24373840764087845529714417615340154589242410486061302984795651085087316309667
Short name T263
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.52 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:41:52 PM PST 23
Peak memory 201940 kb
Host smart-b53e919a-8992-43a2-b9f6-ec4293b70f00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24373840764087845529714417615340154589242410486061302984795651085087316309667 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 41.xbar_same_source.24373840764087845529714417615340154589242410486061302984795651085087316309667
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.65521012664590206256803442300659988605170409885142025468695067474778041769039
Short name T176
Test name
Test status
Simulation time 331233435 ps
CPU time 1.59 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:41:54 PM PST 23
Peak memory 201852 kb
Host smart-e035aea9-2b5c-46d5-a124-3603e8eaf2f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65521012664590206256803442300659988605170409885142025468695067474778041769039 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 41.xbar_smoke.65521012664590206256803442300659988605170409885142025468695067474778041769039
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.39704779501985367922588527191230686281464465163921884893470524114383766393503
Short name T855
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.91 seconds
Started Nov 22 01:41:50 PM PST 23
Finished Nov 22 01:42:06 PM PST 23
Peak memory 201800 kb
Host smart-51b3d70c-5c58-4595-bb2c-efc3f434dc2e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=39704779501985367922588527191230686281464465163921884893470524114383766393503 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.39704779501985367922588527191230686281464465163921884893470524114383766393503
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.75837018333249328382242032291275371902046284802832746037929264210914215747967
Short name T619
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.7 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:41:56 PM PST 23
Peak memory 201988 kb
Host smart-917183e8-189f-496d-bea8-8cf4bce448c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=75837018333249328382242032291275371902046284802832746037929264210914215747967 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.75837018333249328382242032291275371902046284802832746037929264210914215747967
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.41674681400767571160594171555985347413761130759737736770428836307085549048887
Short name T762
Test name
Test status
Simulation time 27670935 ps
CPU time 1.14 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:41:53 PM PST 23
Peak memory 201912 kb
Host smart-09cd3606-f529-4c58-a48b-30698bcf6246
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41674681400767571160594171555985347413761130759737736770428836307085549048887 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.41674681400767571160594171555985347413761130759737736770428836307085549048887
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.6502839862565093454936834646544876545781663127533943050583674857697660156674
Short name T321
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.32 seconds
Started Nov 22 01:41:29 PM PST 23
Finished Nov 22 01:43:37 PM PST 23
Peak memory 203132 kb
Host smart-f96fadf1-d5f1-4757-9380-5c520fc18f4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6502839862565093454936834646544876545781663127533943050583674857697660156674 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_
log /dev/null -cm_name 41.xbar_stress_all.6502839862565093454936834646544876545781663127533943050583674857697660156674
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.31117891161316393694528219614510890898709586503061921146944606250910948735024
Short name T340
Test name
Test status
Simulation time 46147859184 ps
CPU time 113.76 seconds
Started Nov 22 01:41:35 PM PST 23
Finished Nov 22 01:43:32 PM PST 23
Peak memory 204848 kb
Host smart-1c32872e-037f-453a-879a-237abe906ae7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31117891161316393694528219614510890898709586503061921146944606250910948735024 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 41.xbar_stress_all_with_error.31117891161316393694528219614510890898709586503061921146944606250910948735024
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.108254591884972301745638836258239483904197560364565199809976874845388030436882
Short name T15
Test name
Test status
Simulation time 13716459184 ps
CPU time 156.46 seconds
Started Nov 22 01:42:32 PM PST 23
Finished Nov 22 01:45:14 PM PST 23
Peak memory 204640 kb
Host smart-06b06604-18d6-42fe-a0ee-5f405f5b7f2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=108254591884972301745638836258239483904197560364565199809976874845388030436882 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.108254591884972301745638836258239483904197560364565199809976874845388030436882
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.60808759779833623394901951564417084943464216917560920856082497689394016558563
Short name T749
Test name
Test status
Simulation time 13716459184 ps
CPU time 130.22 seconds
Started Nov 22 01:42:31 PM PST 23
Finished Nov 22 01:44:43 PM PST 23
Peak memory 204052 kb
Host smart-6298007e-81c1-499f-aac7-18b532d0fcc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=60808759779833623394901951564417084943464216917560920856082497689394016558563 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.60808759779833623394901951564417084943464216917560920856082497689394016558563
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.35003343355784694150852198610262546740311408617147039150869398144329300158130
Short name T148
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.85 seconds
Started Nov 22 01:42:01 PM PST 23
Finished Nov 22 01:42:21 PM PST 23
Peak memory 201216 kb
Host smart-57fc80de-10bc-4245-93d8-72ce4320b0a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35003343355784694150852198610262546740311408617147039150869398144329300158130 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 41.xbar_unmapped_addr.35003343355784694150852198610262546740311408617147039150869398144329300158130
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.79853452424591926486317414395993382074731071321560909621277790171032901738287
Short name T900
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.63 seconds
Started Nov 22 01:41:28 PM PST 23
Finished Nov 22 01:41:47 PM PST 23
Peak memory 201944 kb
Host smart-0a9fd9b3-05ce-47f8-b3cd-7766ae336ba3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=79853452424591926486317414395993382074731071321560909621277790171032901738287 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.79853452424591926486317414395993382074731071321560909621277790171032901738287
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.49031356174454822635987773415623163762040712298645608590607053991706871715923
Short name T78
Test name
Test status
Simulation time 260306045935 ps
CPU time 330.04 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:47:15 PM PST 23
Peak memory 202836 kb
Host smart-4a114780-a6b7-46b1-a272-e720c7d9badd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=49031356174454822635987773415623163762040712298645608590607053991706871715923 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.49031356174454822635987773415623163762040712298645608590607053991706871715923
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.51645474681870464689823606714612844666809946809724202508649728339340442986662
Short name T561
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.13 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:41:37 PM PST 23
Peak memory 201932 kb
Host smart-faedcbd7-3ebf-4fd7-ad72-023badab5993
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=51645474681870464689823606714612844666809946809724202508649728339340442986662 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.51645474681870464689823606714612844666809946809724202508649728339340442986662
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.4516446975414793146211742541616697960722048793292697893890790333751324165646
Short name T613
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.07 seconds
Started Nov 22 01:41:39 PM PST 23
Finished Nov 22 01:41:54 PM PST 23
Peak memory 201952 kb
Host smart-7f801757-1394-4fff-bca4-e7486b2f5525
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4516446975414793146211742541616697960722048793292697893890790333751324165646 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 42.xbar_error_random.4516446975414793146211742541616697960722048793292697893890790333751324165646
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.45333165255807826559362622303768586943195826234887669971360751665681405690533
Short name T513
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.08 seconds
Started Nov 22 01:41:41 PM PST 23
Finished Nov 22 01:41:57 PM PST 23
Peak memory 201912 kb
Host smart-7d1421e5-61bc-49c0-9216-5ce55584aea6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45333165255807826559362622303768586943195826234887669971360751665681405690533 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 42.xbar_random.45333165255807826559362622303768586943195826234887669971360751665681405690533
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.112063275980785953450994971058750107888139517968296282722344830094937857079792
Short name T425
Test name
Test status
Simulation time 237556670935 ps
CPU time 185.39 seconds
Started Nov 22 01:41:31 PM PST 23
Finished Nov 22 01:44:38 PM PST 23
Peak memory 201984 kb
Host smart-e0cb13a9-2684-4619-8e75-e17af669be87
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=112063275980785953450994971058750107888139517968296282722344830094937857079792 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.112063275980785953450994971058750107888139517968296282722344830094937857079792
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.76505569645356100428635098396960695582275729348188303103579705729256487936209
Short name T600
Test name
Test status
Simulation time 160909483435 ps
CPU time 194.12 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:45:02 PM PST 23
Peak memory 202032 kb
Host smart-5c5c388e-b812-4d52-85d5-06ba04d0a863
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=76505569645356100428635098396960695582275729348188303103579705729256487936209 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.76505569645356100428635098396960695582275729348188303103579705729256487936209
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.99721975339181233771509380535366291765681021206328850124410823163089568057243
Short name T565
Test name
Test status
Simulation time 360920935 ps
CPU time 7.74 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:41:35 PM PST 23
Peak memory 201876 kb
Host smart-375ccedb-96e9-4d82-9128-6cebe60475a1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99721975339181233771509380535366291765681021206328850124410823163089568057243 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.99721975339181233771509380535366291765681021206328850124410823163089568057243
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.99782403090755213670237281085281880032967465990897980365019986001913190668135
Short name T722
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.98 seconds
Started Nov 22 01:42:00 PM PST 23
Finished Nov 22 01:42:20 PM PST 23
Peak memory 201880 kb
Host smart-0e892e87-229f-4fc4-a066-10c174b6fe09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99782403090755213670237281085281880032967465990897980365019986001913190668135 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 42.xbar_same_source.99782403090755213670237281085281880032967465990897980365019986001913190668135
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.105421847828250968709653090602705797324480169289211036346954310190111993844183
Short name T331
Test name
Test status
Simulation time 331233435 ps
CPU time 1.61 seconds
Started Nov 22 01:41:38 PM PST 23
Finished Nov 22 01:41:42 PM PST 23
Peak memory 201976 kb
Host smart-06c2d8d1-805d-4b42-8f87-845a637667ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105421847828250968709653090602705797324480169289211036346954310190111993844183 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 42.xbar_smoke.105421847828250968709653090602705797324480169289211036346954310190111993844183
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.108177404964227103909808525748497552940128112859885060103218645238355009329273
Short name T833
Test name
Test status
Simulation time 15405233435 ps
CPU time 13.01 seconds
Started Nov 22 01:41:19 PM PST 23
Finished Nov 22 01:41:34 PM PST 23
Peak memory 202004 kb
Host smart-ab862343-39bc-4031-88d2-3c7e546eb287
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=108177404964227103909808525748497552940128112859885060103218645238355009329273 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.108177404964227103909808525748497552940128112859885060103218645238355009329273
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.41457503688634958713498797516501841080317596565750309409882293948985712352766
Short name T159
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.67 seconds
Started Nov 22 01:41:29 PM PST 23
Finished Nov 22 01:41:43 PM PST 23
Peak memory 201916 kb
Host smart-58e8f4d9-7879-4b70-bbcb-70a231615795
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=41457503688634958713498797516501841080317596565750309409882293948985712352766 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.41457503688634958713498797516501841080317596565750309409882293948985712352766
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.42228226003037307701112549517178271456615181716055411537051907991045039041012
Short name T371
Test name
Test status
Simulation time 27670935 ps
CPU time 1.19 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:41:29 PM PST 23
Peak memory 201936 kb
Host smart-85d701af-1b02-424a-b276-0e8c59fae629
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42228226003037307701112549517178271456615181716055411537051907991045039041012 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.42228226003037307701112549517178271456615181716055411537051907991045039041012
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.48742807390005170012650385927856965286420861705072177368025176016137144536642
Short name T135
Test name
Test status
Simulation time 46147859184 ps
CPU time 122.39 seconds
Started Nov 22 01:41:20 PM PST 23
Finished Nov 22 01:43:24 PM PST 23
Peak memory 203124 kb
Host smart-5e289a62-3560-428e-97ff-90bfeaf7f1ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=48742807390005170012650385927856965286420861705072177368025176016137144536642 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 42.xbar_stress_all.48742807390005170012650385927856965286420861705072177368025176016137144536642
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.46743360756048490799695080488946155150273973802677210990536379453318333496630
Short name T482
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.18 seconds
Started Nov 22 01:41:32 PM PST 23
Finished Nov 22 01:43:40 PM PST 23
Peak memory 204928 kb
Host smart-dac83c59-758f-4c61-aa9a-e4126edb6867
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46743360756048490799695080488946155150273973802677210990536379453318333496630 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 42.xbar_stress_all_with_error.46743360756048490799695080488946155150273973802677210990536379453318333496630
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.54876888271921041800744016123683886624652495513759439054748588053975833475927
Short name T31
Test name
Test status
Simulation time 13716459184 ps
CPU time 156.85 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:44:28 PM PST 23
Peak memory 205068 kb
Host smart-cb512a93-8f4e-4561-9c0f-39723ab6d5dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54876888271921041800744016123683886624652495513759439054748588053975833475927 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.54876888271921041800744016123683886624652495513759439054748588053975833475927
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.35279344333006852510490409689409744197669571187213537124537354488695524007012
Short name T485
Test name
Test status
Simulation time 13716459184 ps
CPU time 135.43 seconds
Started Nov 22 01:42:04 PM PST 23
Finished Nov 22 01:44:26 PM PST 23
Peak memory 206292 kb
Host smart-5212784a-f10f-47f0-be3e-7b9b1fb720b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35279344333006852510490409689409744197669571187213537124537354488695524007012 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.35279344333006852510490409689409744197669571187213537124537354488695524007012
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2918456953535004273191726702620204197262216184749217437238630604269702532352
Short name T337
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.44 seconds
Started Nov 22 01:41:36 PM PST 23
Finished Nov 22 01:41:50 PM PST 23
Peak memory 201932 kb
Host smart-ddf85ec4-9e1b-4cb4-9b30-a6e431b67945
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2918456953535004273191726702620204197262216184749217437238630604269702532352 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2918456953535004273191726702620204197262216184749217437238630604269702532352
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.71083823344075476307892343188915505053911154569000175301508861880044302235003
Short name T10
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.77 seconds
Started Nov 22 01:41:47 PM PST 23
Finished Nov 22 01:42:07 PM PST 23
Peak memory 201968 kb
Host smart-da0ef1b7-cdba-485e-b659-545c16c00301
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=71083823344075476307892343188915505053911154569000175301508861880044302235003 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.71083823344075476307892343188915505053911154569000175301508861880044302235003
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.74744908274153157489929934238724152479444477332492097250031959719223990812951
Short name T799
Test name
Test status
Simulation time 260306045935 ps
CPU time 337.32 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:47:10 PM PST 23
Peak memory 203032 kb
Host smart-1d714773-1b79-4d08-a7da-7c016338db28
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=74744908274153157489929934238724152479444477332492097250031959719223990812951 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.74744908274153157489929934238724152479444477332492097250031959719223990812951
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.31828700117273222196622855978892989481547837926353819558931985357143911393318
Short name T841
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.77 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:41:54 PM PST 23
Peak memory 201980 kb
Host smart-193138aa-fb6d-4857-965e-53aab119e5ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31828700117273222196622855978892989481547837926353819558931985357143911393318 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.31828700117273222196622855978892989481547837926353819558931985357143911393318
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.62728970909105707261944351246928395476187005868256470600323346703289441954298
Short name T736
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.19 seconds
Started Nov 22 01:41:39 PM PST 23
Finished Nov 22 01:41:55 PM PST 23
Peak memory 201956 kb
Host smart-96cd65e2-7fed-43e5-9b56-208bd76c9191
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62728970909105707261944351246928395476187005868256470600323346703289441954298 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 43.xbar_error_random.62728970909105707261944351246928395476187005868256470600323346703289441954298
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.96026979344589212206203243740256484178317761411258310339242823268068819403193
Short name T891
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.66 seconds
Started Nov 22 01:42:00 PM PST 23
Finished Nov 22 01:42:21 PM PST 23
Peak memory 201920 kb
Host smart-fb07836c-525e-483c-87e7-8717e4cef186
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96026979344589212206203243740256484178317761411258310339242823268068819403193 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 43.xbar_random.96026979344589212206203243740256484178317761411258310339242823268068819403193
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.97547304118848690680331863720330902899967407411134713425240567069626187986425
Short name T252
Test name
Test status
Simulation time 237556670935 ps
CPU time 186.52 seconds
Started Nov 22 01:42:03 PM PST 23
Finished Nov 22 01:45:17 PM PST 23
Peak memory 201880 kb
Host smart-e179dbb6-7ff3-4b32-b78e-0fe2929ec164
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=97547304118848690680331863720330902899967407411134713425240567069626187986425 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 43.xbar_random_large_delays.97547304118848690680331863720330902899967407411134713425240567069626187986425
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.76137385893757746597949265795953042170759866361096016585478270974264914203933
Short name T699
Test name
Test status
Simulation time 160909483435 ps
CPU time 191.13 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:44:50 PM PST 23
Peak memory 201996 kb
Host smart-ced53cf5-8d20-44e3-99f1-05b304d8b30d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=76137385893757746597949265795953042170759866361096016585478270974264914203933 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.76137385893757746597949265795953042170759866361096016585478270974264914203933
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.5626136509423172598310783514822238522808294019072320281484855354855798641034
Short name T744
Test name
Test status
Simulation time 360920935 ps
CPU time 7.4 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:41:52 PM PST 23
Peak memory 201844 kb
Host smart-15524898-f56d-449b-b37e-7b4f8584f297
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5626136509423172598310783514822238522808294019072320281484855354855798641034 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.5626136509423172598310783514822238522808294019072320281484855354855798641034
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.73125332164266269204120402459204369786294296764947039414414071465379134232968
Short name T311
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.91 seconds
Started Nov 22 01:42:03 PM PST 23
Finished Nov 22 01:42:22 PM PST 23
Peak memory 201872 kb
Host smart-ce43d4b0-1a36-4b91-a25d-de837966dec2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73125332164266269204120402459204369786294296764947039414414071465379134232968 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 43.xbar_same_source.73125332164266269204120402459204369786294296764947039414414071465379134232968
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.80465502823956026416225755999514949577665856436996232616435385279905342135237
Short name T94
Test name
Test status
Simulation time 331233435 ps
CPU time 1.64 seconds
Started Nov 22 01:41:47 PM PST 23
Finished Nov 22 01:41:51 PM PST 23
Peak memory 201960 kb
Host smart-407a049c-b4b1-4017-9f2e-525f1b290843
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=80465502823956026416225755999514949577665856436996232616435385279905342135237 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 43.xbar_smoke.80465502823956026416225755999514949577665856436996232616435385279905342135237
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.31532384244103343399309212832309281965097586034022083442901050640119986420130
Short name T91
Test name
Test status
Simulation time 15405233435 ps
CPU time 13.08 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:42:02 PM PST 23
Peak memory 202008 kb
Host smart-e9366d61-9dd2-4008-a1f8-d62f565d1012
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=31532384244103343399309212832309281965097586034022083442901050640119986420130 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.31532384244103343399309212832309281965097586034022083442901050640119986420130
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.43038873567478857894185918686843575596079869126299798706627814563627483344853
Short name T296
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.73 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:41:58 PM PST 23
Peak memory 201996 kb
Host smart-021b7a8b-653e-4d5c-be32-7e8675ba94d3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=43038873567478857894185918686843575596079869126299798706627814563627483344853 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.43038873567478857894185918686843575596079869126299798706627814563627483344853
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.69407628164522143294161769740731643857041408937132808302933731706095892574887
Short name T541
Test name
Test status
Simulation time 27670935 ps
CPU time 1.17 seconds
Started Nov 22 01:41:33 PM PST 23
Finished Nov 22 01:41:37 PM PST 23
Peak memory 201856 kb
Host smart-1f1754b3-55c4-49b2-821d-2936b5119692
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69407628164522143294161769740731643857041408937132808302933731706095892574887 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.69407628164522143294161769740731643857041408937132808302933731706095892574887
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.41507447688919992454363426985869013757131410554052279485453109601484668742606
Short name T644
Test name
Test status
Simulation time 46147859184 ps
CPU time 122.73 seconds
Started Nov 22 01:41:50 PM PST 23
Finished Nov 22 01:43:56 PM PST 23
Peak memory 203144 kb
Host smart-f95da4c7-5c41-4a24-bc03-65c91e94f46b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=41507447688919992454363426985869013757131410554052279485453109601484668742606 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 43.xbar_stress_all.41507447688919992454363426985869013757131410554052279485453109601484668742606
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.85395797482519533068555424980163219121929931084337792125092707833211666302722
Short name T890
Test name
Test status
Simulation time 46147859184 ps
CPU time 112.53 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:43:37 PM PST 23
Peak memory 204920 kb
Host smart-0a07a07f-ead9-47cd-8c3b-3748a6f2ad2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85395797482519533068555424980163219121929931084337792125092707833211666302722 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 43.xbar_stress_all_with_error.85395797482519533068555424980163219121929931084337792125092707833211666302722
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.96671697213447686103441513798045158522574397734050479840572238413519576673687
Short name T669
Test name
Test status
Simulation time 13716459184 ps
CPU time 155.41 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:44:26 PM PST 23
Peak memory 205156 kb
Host smart-0780c1bb-352f-447a-b619-de5664ed1148
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96671697213447686103441513798045158522574397734050479840572238413519576673687 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.96671697213447686103441513798045158522574397734050479840572238413519576673687
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.59687750764752486027080714967186730958758588000020931134954401742084965902488
Short name T675
Test name
Test status
Simulation time 13716459184 ps
CPU time 138.65 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:44:06 PM PST 23
Peak memory 206164 kb
Host smart-dd55c446-e956-43ce-a60c-4982b9a8d8b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59687750764752486027080714967186730958758588000020931134954401742084965902488 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.59687750764752486027080714967186730958758588000020931134954401742084965902488
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.112300161671835988405833801727735998676170354474392318370942949491243901406410
Short name T47
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.53 seconds
Started Nov 22 01:41:50 PM PST 23
Finished Nov 22 01:42:04 PM PST 23
Peak memory 201820 kb
Host smart-9e4bb441-ea5f-4fef-8610-228184dba4ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112300161671835988405833801727735998676170354474392318370942949491243901406410 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 43.xbar_unmapped_addr.112300161671835988405833801727735998676170354474392318370942949491243901406410
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.49752676845725528031367352865517364027627769405988111297849615736043031825855
Short name T231
Test name
Test status
Simulation time 4712795935 ps
CPU time 16.48 seconds
Started Nov 22 01:42:06 PM PST 23
Finished Nov 22 01:42:27 PM PST 23
Peak memory 201816 kb
Host smart-4044daab-018b-4041-96c3-6ac09163fc6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49752676845725528031367352865517364027627769405988111297849615736043031825855 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.49752676845725528031367352865517364027627769405988111297849615736043031825855
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.90648424242603805548507763101835339531081020222450384126365017450047581102573
Short name T878
Test name
Test status
Simulation time 260306045935 ps
CPU time 341.74 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:47:26 PM PST 23
Peak memory 203012 kb
Host smart-5c7c8950-1bc0-4f03-a508-e016e64b0012
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=90648424242603805548507763101835339531081020222450384126365017450047581102573 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.90648424242603805548507763101835339531081020222450384126365017450047581102573
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.86084291854980007059679386162549009977857865653742684021964285605615015038024
Short name T366
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.05 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:41:54 PM PST 23
Peak memory 201880 kb
Host smart-d1881fb8-9d9b-4ee9-b266-880488949df7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86084291854980007059679386162549009977857865653742684021964285605615015038024 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.86084291854980007059679386162549009977857865653742684021964285605615015038024
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.14124219938857384059202969366403818457970007085888149342832237296422052834770
Short name T830
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.49 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:41:53 PM PST 23
Peak memory 201876 kb
Host smart-eda0be11-f5b2-4a06-baaf-4e68d86d4275
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14124219938857384059202969366403818457970007085888149342832237296422052834770 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 44.xbar_error_random.14124219938857384059202969366403818457970007085888149342832237296422052834770
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.25350633207738064922003827787306934600213529395307974963266943117912640023318
Short name T48
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.8 seconds
Started Nov 22 01:42:01 PM PST 23
Finished Nov 22 01:42:22 PM PST 23
Peak memory 201936 kb
Host smart-5891b5be-ee37-48e4-8b4d-657a992d11ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25350633207738064922003827787306934600213529395307974963266943117912640023318 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 44.xbar_random.25350633207738064922003827787306934600213529395307974963266943117912640023318
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.39804665663890739133345835596443792150774477153083291833681115015744758058424
Short name T50
Test name
Test status
Simulation time 237556670935 ps
CPU time 186.21 seconds
Started Nov 22 01:41:59 PM PST 23
Finished Nov 22 01:45:14 PM PST 23
Peak memory 200608 kb
Host smart-f7715189-321f-4261-8da7-cab84cb7cefd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=39804665663890739133345835596443792150774477153083291833681115015744758058424 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 44.xbar_random_large_delays.39804665663890739133345835596443792150774477153083291833681115015744758058424
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.102572735888378329700290938860318323280016310431073548457891616282711948646431
Short name T867
Test name
Test status
Simulation time 160909483435 ps
CPU time 195.23 seconds
Started Nov 22 01:42:01 PM PST 23
Finished Nov 22 01:45:25 PM PST 23
Peak memory 201184 kb
Host smart-237f7505-6f54-4a73-a2a8-6223e0c7cf5e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=102572735888378329700290938860318323280016310431073548457891616282711948646431 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.102572735888378329700290938860318323280016310431073548457891616282711948646431
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.10192145350572481665544601613344508638051391717389469692409653642994771458400
Short name T240
Test name
Test status
Simulation time 360920935 ps
CPU time 7.38 seconds
Started Nov 22 01:41:59 PM PST 23
Finished Nov 22 01:42:13 PM PST 23
Peak memory 201780 kb
Host smart-00c9b5b2-1530-4475-a2d6-775b19734f5f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10192145350572481665544601613344508638051391717389469692409653642994771458400 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.10192145350572481665544601613344508638051391717389469692409653642994771458400
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.82323592712619494542431803552055679319903646205633524097886018414653646429546
Short name T716
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.82 seconds
Started Nov 22 01:42:03 PM PST 23
Finished Nov 22 01:42:22 PM PST 23
Peak memory 201388 kb
Host smart-98f5d769-bff4-43e3-84e4-da1506e2e772
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=82323592712619494542431803552055679319903646205633524097886018414653646429546 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 44.xbar_same_source.82323592712619494542431803552055679319903646205633524097886018414653646429546
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.111058148421544863413980326711062082867703005751356146238693358749937913696109
Short name T626
Test name
Test status
Simulation time 331233435 ps
CPU time 1.54 seconds
Started Nov 22 01:41:41 PM PST 23
Finished Nov 22 01:41:45 PM PST 23
Peak memory 201768 kb
Host smart-a4a6851b-2f8d-4a63-aebc-bccb43772db9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111058148421544863413980326711062082867703005751356146238693358749937913696109 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 44.xbar_smoke.111058148421544863413980326711062082867703005751356146238693358749937913696109
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.75826762105274208919528596214789155420252912186290009718009514205694214776514
Short name T351
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.98 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:41:59 PM PST 23
Peak memory 201848 kb
Host smart-b7d0ca54-cbe0-4ac3-ae62-037d7d1d6eec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=75826762105274208919528596214789155420252912186290009718009514205694214776514 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.75826762105274208919528596214789155420252912186290009718009514205694214776514
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.16260895538385463796618626748544112323399623087544653279631541450893418252490
Short name T324
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.66 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:41:58 PM PST 23
Peak memory 201844 kb
Host smart-44da597f-6f7d-4644-a868-91c01ab8163d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=16260895538385463796618626748544112323399623087544653279631541450893418252490 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.16260895538385463796618626748544112323399623087544653279631541450893418252490
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.111306159387811318391330679294461093078200040660204067120948837234400742333946
Short name T537
Test name
Test status
Simulation time 27670935 ps
CPU time 1.14 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:41:48 PM PST 23
Peak memory 201776 kb
Host smart-03f8a31c-35f0-47dc-8183-faabf0112074
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111306159387811318391330679294461093078200040660204067120948837234400742333946 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.111306159387811318391330679294461093078200040660204067120948837234400742333946
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.53394088781630263785008070770308903462059711029410479534173230324401946975807
Short name T685
Test name
Test status
Simulation time 46147859184 ps
CPU time 129.85 seconds
Started Nov 22 01:41:36 PM PST 23
Finished Nov 22 01:43:49 PM PST 23
Peak memory 203244 kb
Host smart-7c76424d-066b-4f83-b1bc-bffb0da7c1c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53394088781630263785008070770308903462059711029410479534173230324401946975807 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 44.xbar_stress_all.53394088781630263785008070770308903462059711029410479534173230324401946975807
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.21629399639608424837783776924240419961693060391629440354664121107597177546494
Short name T502
Test name
Test status
Simulation time 46147859184 ps
CPU time 117.38 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:43:25 PM PST 23
Peak memory 204976 kb
Host smart-50c1de93-0c68-4aea-acf1-e4255d39743c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=21629399639608424837783776924240419961693060391629440354664121107597177546494 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 44.xbar_stress_all_with_error.21629399639608424837783776924240419961693060391629440354664121107597177546494
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.104424338411352760817002205133536489363805115478731140607869813425698781278531
Short name T18
Test name
Test status
Simulation time 13716459184 ps
CPU time 159.84 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:44:32 PM PST 23
Peak memory 205060 kb
Host smart-c227af23-0295-426c-95b5-ee1aa64f3dbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104424338411352760817002205133536489363805115478731140607869813425698781278531 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.104424338411352760817002205133536489363805115478731140607869813425698781278531
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.102623973359615623509263450413023313887883402478906066381223249167624874411510
Short name T107
Test name
Test status
Simulation time 13716459184 ps
CPU time 130.94 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:43:43 PM PST 23
Peak memory 206196 kb
Host smart-bda321cb-9c3d-40c9-b00d-729a70dc59d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102623973359615623509263450413023313887883402478906066381223249167624874411510 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.102623973359615623509263450413023313887883402478906066381223249167624874411510
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.5436432180042319871855754697282591831550649465713892915756157862308592256340
Short name T531
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.92 seconds
Started Nov 22 01:41:55 PM PST 23
Finished Nov 22 01:42:10 PM PST 23
Peak memory 201816 kb
Host smart-c207dd26-2d11-4530-9983-81cc345afcd1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5436432180042319871855754697282591831550649465713892915756157862308592256340 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 44.xbar_unmapped_addr.5436432180042319871855754697282591831550649465713892915756157862308592256340
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.91238857577296715287491198840562991585699671804152421269607430667162020868329
Short name T98
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.87 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:42:09 PM PST 23
Peak memory 202036 kb
Host smart-ef7f11a7-f0b5-466a-aa7e-7b5d9ddefa93
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91238857577296715287491198840562991585699671804152421269607430667162020868329 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.91238857577296715287491198840562991585699671804152421269607430667162020868329
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.57329333803916367811715903503663601517005248134539544200754967355179228344878
Short name T708
Test name
Test status
Simulation time 260306045935 ps
CPU time 331.09 seconds
Started Nov 22 01:42:00 PM PST 23
Finished Nov 22 01:47:39 PM PST 23
Peak memory 202908 kb
Host smart-7b7e7399-480c-4be0-8db2-cb1f23fa5331
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=57329333803916367811715903503663601517005248134539544200754967355179228344878 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.57329333803916367811715903503663601517005248134539544200754967355179228344878
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.19041866980265610279230072015823953408919948267532744994546639942179902698841
Short name T646
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.59 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:42:02 PM PST 23
Peak memory 201952 kb
Host smart-e61c5bcc-07a9-43f6-badf-248c98cae28c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=19041866980265610279230072015823953408919948267532744994546639942179902698841 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.19041866980265610279230072015823953408919948267532744994546639942179902698841
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.82988569683116094089472286383777870206739028634042177958940532997411617381397
Short name T273
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.61 seconds
Started Nov 22 01:41:52 PM PST 23
Finished Nov 22 01:42:07 PM PST 23
Peak memory 201988 kb
Host smart-9dc98994-f4c6-41f5-9a95-3fd7cc58df61
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=82988569683116094089472286383777870206739028634042177958940532997411617381397 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 45.xbar_error_random.82988569683116094089472286383777870206739028634042177958940532997411617381397
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.69351731592446717667331274890509267033872747295880300835666058328098765157323
Short name T872
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.08 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:41:59 PM PST 23
Peak memory 201916 kb
Host smart-85208783-2e1d-46cf-bfdb-0c4f602ce021
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69351731592446717667331274890509267033872747295880300835666058328098765157323 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 45.xbar_random.69351731592446717667331274890509267033872747295880300835666058328098765157323
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.100976643472992566233580505270203078931332544848154168780330857711902191853398
Short name T798
Test name
Test status
Simulation time 237556670935 ps
CPU time 187.21 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:44:58 PM PST 23
Peak memory 201892 kb
Host smart-8f81a1bb-ca31-424c-a3a3-6ee7e7aa11d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=100976643472992566233580505270203078931332544848154168780330857711902191853398 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.100976643472992566233580505270203078931332544848154168780330857711902191853398
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.99920469457362809380350556970324766301248609478686759626315319127255734541545
Short name T16
Test name
Test status
Simulation time 160909483435 ps
CPU time 194.33 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:45:06 PM PST 23
Peak memory 201900 kb
Host smart-526f1e9d-0a14-4510-a82f-4a14204fce8d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=99920469457362809380350556970324766301248609478686759626315319127255734541545 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.99920469457362809380350556970324766301248609478686759626315319127255734541545
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.28413075615176473695683311909930175291322019370023064815399166620393489688028
Short name T672
Test name
Test status
Simulation time 360920935 ps
CPU time 7.32 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:41:54 PM PST 23
Peak memory 201748 kb
Host smart-9e16c038-2ec0-494c-a713-f9cf5f359f67
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28413075615176473695683311909930175291322019370023064815399166620393489688028 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.28413075615176473695683311909930175291322019370023064815399166620393489688028
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.27886648652722733672531751737262183504011309131706487482580912040617000220931
Short name T280
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.84 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:41:59 PM PST 23
Peak memory 202036 kb
Host smart-1dcbb839-7024-479d-a7a3-5af46318691f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27886648652722733672531751737262183504011309131706487482580912040617000220931 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 45.xbar_same_source.27886648652722733672531751737262183504011309131706487482580912040617000220931
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.25752946414516689325651343870292446335828951290699668041084646476717226345848
Short name T592
Test name
Test status
Simulation time 331233435 ps
CPU time 1.56 seconds
Started Nov 22 01:41:27 PM PST 23
Finished Nov 22 01:41:30 PM PST 23
Peak memory 201852 kb
Host smart-22491ab0-ba44-47b6-bc72-03b217c30535
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25752946414516689325651343870292446335828951290699668041084646476717226345848 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 45.xbar_smoke.25752946414516689325651343870292446335828951290699668041084646476717226345848
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1943795342237895309325522451696253186678664805425837938337736637655494971877
Short name T140
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.72 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:41:45 PM PST 23
Peak memory 201936 kb
Host smart-3a533454-fb7c-4cc9-892c-4354d06843c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943795342237895309325522451696253186678664805425837938337736637655494971877 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1943795342237895309325522451696253186678664805425837938337736637655494971877
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.16722689281135222205049805189523037695581880847546615843740744899113946498560
Short name T551
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.79 seconds
Started Nov 22 01:41:33 PM PST 23
Finished Nov 22 01:41:48 PM PST 23
Peak memory 201888 kb
Host smart-4e1b43c6-8e15-4102-812d-78b364e4a658
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=16722689281135222205049805189523037695581880847546615843740744899113946498560 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.16722689281135222205049805189523037695581880847546615843740744899113946498560
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.115367531788169878720168394295518030545521202229360558378257903753647724436268
Short name T475
Test name
Test status
Simulation time 27670935 ps
CPU time 1.21 seconds
Started Nov 22 01:41:43 PM PST 23
Finished Nov 22 01:41:46 PM PST 23
Peak memory 201812 kb
Host smart-d43a359c-d625-4c1f-8ea7-89443e70145f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115367531788169878720168394295518030545521202229360558378257903753647724436268 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.115367531788169878720168394295518030545521202229360558378257903753647724436268
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.19104393294199739219158061539074004477249546829718815707568236015080989181331
Short name T623
Test name
Test status
Simulation time 46147859184 ps
CPU time 122.54 seconds
Started Nov 22 01:41:47 PM PST 23
Finished Nov 22 01:43:52 PM PST 23
Peak memory 203136 kb
Host smart-d92177b3-f046-41f6-9d4b-05d607557e89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=19104393294199739219158061539074004477249546829718815707568236015080989181331 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 45.xbar_stress_all.19104393294199739219158061539074004477249546829718815707568236015080989181331
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.62012496355856238805450304540959847751284598244008440698502608360367946810001
Short name T90
Test name
Test status
Simulation time 46147859184 ps
CPU time 114.02 seconds
Started Nov 22 01:42:05 PM PST 23
Finished Nov 22 01:44:05 PM PST 23
Peak memory 204868 kb
Host smart-c7344a93-06fd-492d-9ec5-e139e12c388a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62012496355856238805450304540959847751284598244008440698502608360367946810001 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 45.xbar_stress_all_with_error.62012496355856238805450304540959847751284598244008440698502608360367946810001
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.52741094857906627841545837923897291461210314929139166738117773257783094046294
Short name T637
Test name
Test status
Simulation time 13716459184 ps
CPU time 157.65 seconds
Started Nov 22 01:41:58 PM PST 23
Finished Nov 22 01:44:43 PM PST 23
Peak memory 204968 kb
Host smart-8b124b0b-111c-48a8-aad7-27163bef0715
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=52741094857906627841545837923897291461210314929139166738117773257783094046294 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.52741094857906627841545837923897291461210314929139166738117773257783094046294
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.98571494546042930884399101008423530938385630608368163632906229062267834066682
Short name T625
Test name
Test status
Simulation time 13716459184 ps
CPU time 133.92 seconds
Started Nov 22 01:42:06 PM PST 23
Finished Nov 22 01:44:25 PM PST 23
Peak memory 206072 kb
Host smart-cd80d962-8239-447d-939a-c3960b490eda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98571494546042930884399101008423530938385630608368163632906229062267834066682 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.98571494546042930884399101008423530938385630608368163632906229062267834066682
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3355567722294321346016569408345451176782974338774230255568455161894524489901
Short name T377
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.75 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:42:03 PM PST 23
Peak memory 201996 kb
Host smart-39c8afba-1b19-4ff3-89fd-c2e1de071243
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3355567722294321346016569408345451176782974338774230255568455161894524489901 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3355567722294321346016569408345451176782974338774230255568455161894524489901
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.29902295302738025272110763045917351474302550857263294693460075286101074147403
Short name T281
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.99 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:42:02 PM PST 23
Peak memory 202036 kb
Host smart-c24198ce-2cad-428c-9751-4004cf007969
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29902295302738025272110763045917351474302550857263294693460075286101074147403 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.29902295302738025272110763045917351474302550857263294693460075286101074147403
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.41575708875373308238620075928279284460643450957968870338243689573732279049998
Short name T791
Test name
Test status
Simulation time 260306045935 ps
CPU time 339.93 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:47:19 PM PST 23
Peak memory 202996 kb
Host smart-b9862f9a-59e6-470b-95fa-4782de396c4f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=41575708875373308238620075928279284460643450957968870338243689573732279049998 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.41575708875373308238620075928279284460643450957968870338243689573732279049998
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.54817971694909597482633185514949696908231834063433130009268529469818760653691
Short name T503
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.4 seconds
Started Nov 22 01:42:02 PM PST 23
Finished Nov 22 01:42:21 PM PST 23
Peak memory 201884 kb
Host smart-8f14b508-48a3-4216-ad7a-92a19c22c74b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54817971694909597482633185514949696908231834063433130009268529469818760653691 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.54817971694909597482633185514949696908231834063433130009268529469818760653691
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.27462957320967125078214889384205788518698596386522618876619359179346149150891
Short name T204
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.21 seconds
Started Nov 22 01:42:02 PM PST 23
Finished Nov 22 01:42:23 PM PST 23
Peak memory 201944 kb
Host smart-c8f008dc-295e-45f3-b014-10cd07cc8e6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27462957320967125078214889384205788518698596386522618876619359179346149150891 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 46.xbar_error_random.27462957320967125078214889384205788518698596386522618876619359179346149150891
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.45192777143158151971653826335176064086610317259295931690438636281558959575278
Short name T362
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.78 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:42:00 PM PST 23
Peak memory 201984 kb
Host smart-648f0a1c-e09e-49b1-825d-2607853ef716
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45192777143158151971653826335176064086610317259295931690438636281558959575278 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 46.xbar_random.45192777143158151971653826335176064086610317259295931690438636281558959575278
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.33650654079063660399091563524714358580466038553596524940914947088027736597856
Short name T375
Test name
Test status
Simulation time 237556670935 ps
CPU time 187.04 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:44:35 PM PST 23
Peak memory 201944 kb
Host smart-40011441-14d5-486d-8954-7e4e1438da25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=33650654079063660399091563524714358580466038553596524940914947088027736597856 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 46.xbar_random_large_delays.33650654079063660399091563524714358580466038553596524940914947088027736597856
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.72719000275548960531192824038559435798657766078150599797145224585163233852162
Short name T42
Test name
Test status
Simulation time 160909483435 ps
CPU time 192.87 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:44:40 PM PST 23
Peak memory 201996 kb
Host smart-1cbebc67-65c8-4925-8cf8-f82e94124534
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=72719000275548960531192824038559435798657766078150599797145224585163233852162 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.72719000275548960531192824038559435798657766078150599797145224585163233852162
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.16270693645246862668018223348731055874952042545234000589832779392504981192279
Short name T875
Test name
Test status
Simulation time 360920935 ps
CPU time 7.52 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:41:56 PM PST 23
Peak memory 201884 kb
Host smart-4f969bd1-c705-4b46-a852-9d62a8398e58
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16270693645246862668018223348731055874952042545234000589832779392504981192279 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.16270693645246862668018223348731055874952042545234000589832779392504981192279
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.79873151555236870236951305436040625326807456989824332631569152914984331199452
Short name T92
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.51 seconds
Started Nov 22 01:42:02 PM PST 23
Finished Nov 22 01:42:23 PM PST 23
Peak memory 201860 kb
Host smart-954eab16-2fa6-4b67-a2bc-26d7bca29384
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=79873151555236870236951305436040625326807456989824332631569152914984331199452 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 46.xbar_same_source.79873151555236870236951305436040625326807456989824332631569152914984331199452
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.56795540284421476522053806589232769209865796901491612361729213199987690264084
Short name T214
Test name
Test status
Simulation time 331233435 ps
CPU time 1.59 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:41:34 PM PST 23
Peak memory 201824 kb
Host smart-2ce938a1-4d3a-4a71-b490-a9722fc63396
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56795540284421476522053806589232769209865796901491612361729213199987690264084 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 46.xbar_smoke.56795540284421476522053806589232769209865796901491612361729213199987690264084
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.36215753888038566397544311863323051204034548647349557414628044417265485807276
Short name T778
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.86 seconds
Started Nov 22 01:41:50 PM PST 23
Finished Nov 22 01:42:06 PM PST 23
Peak memory 201928 kb
Host smart-cd243e3c-97f7-4fa0-b92c-38bf5050f0b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=36215753888038566397544311863323051204034548647349557414628044417265485807276 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.36215753888038566397544311863323051204034548647349557414628044417265485807276
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.19596955446948896936519600654942032719641384915494184890009924110036793866167
Short name T318
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.56 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:42:00 PM PST 23
Peak memory 201796 kb
Host smart-20a8f8e9-f7f7-42fb-8df8-c4c48fef0199
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=19596955446948896936519600654942032719641384915494184890009924110036793866167 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.19596955446948896936519600654942032719641384915494184890009924110036793866167
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.57713911993060663915574159951207383878927952098319187088760409351197798977640
Short name T184
Test name
Test status
Simulation time 27670935 ps
CPU time 1.18 seconds
Started Nov 22 01:41:38 PM PST 23
Finished Nov 22 01:41:42 PM PST 23
Peak memory 201848 kb
Host smart-950a2a36-7251-4d1f-98f9-5542a4bf2460
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57713911993060663915574159951207383878927952098319187088760409351197798977640 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.57713911993060663915574159951207383878927952098319187088760409351197798977640
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.115368337018724956954339081164671546374321367278722760134472368021613214723662
Short name T826
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.88 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:43:53 PM PST 23
Peak memory 203172 kb
Host smart-43ea3988-3194-4081-bf2d-9961ca4a40cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115368337018724956954339081164671546374321367278722760134472368021613214723662 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 46.xbar_stress_all.115368337018724956954339081164671546374321367278722760134472368021613214723662
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.64961056803397040537862436778078516191240425343364283444042958283743399919480
Short name T729
Test name
Test status
Simulation time 46147859184 ps
CPU time 121.77 seconds
Started Nov 22 01:41:25 PM PST 23
Finished Nov 22 01:43:27 PM PST 23
Peak memory 204948 kb
Host smart-7cd046dd-c864-4a27-8fed-ba567390e701
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64961056803397040537862436778078516191240425343364283444042958283743399919480 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 46.xbar_stress_all_with_error.64961056803397040537862436778078516191240425343364283444042958283743399919480
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.17780219404225754431756042322737317646729350832869301419031222038975876932297
Short name T432
Test name
Test status
Simulation time 13716459184 ps
CPU time 161.69 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:44:32 PM PST 23
Peak memory 205124 kb
Host smart-d1d5cc23-7117-4ab8-8cdf-e0bd8da94055
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=17780219404225754431756042322737317646729350832869301419031222038975876932297 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.17780219404225754431756042322737317646729350832869301419031222038975876932297
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.5514355003087965645370260376572591423615945175685570029481978682487267405115
Short name T213
Test name
Test status
Simulation time 13716459184 ps
CPU time 140.41 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:44:07 PM PST 23
Peak memory 206268 kb
Host smart-67762abb-ef01-46df-8d35-c45bbe316526
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5514355003087965645370260376572591423615945175685570029481978682487267405115 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.5514355003087965645370260376572591423615945175685570029481978682487267405115
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.40729247630261877104362949986316112602307529878077371516278052732785900807847
Short name T399
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.62 seconds
Started Nov 22 01:41:22 PM PST 23
Finished Nov 22 01:41:33 PM PST 23
Peak memory 201900 kb
Host smart-f854d203-48bc-4eb0-8639-be79e42f9da4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40729247630261877104362949986316112602307529878077371516278052732785900807847 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 46.xbar_unmapped_addr.40729247630261877104362949986316112602307529878077371516278052732785900807847
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.81494699423986666378060831419790864409853699680689339752321147163335513310663
Short name T130
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.66 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:42:07 PM PST 23
Peak memory 202012 kb
Host smart-207ec506-884c-4be9-b55a-ed80d2c2d7c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81494699423986666378060831419790864409853699680689339752321147163335513310663 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.81494699423986666378060831419790864409853699680689339752321147163335513310663
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.27455967351648999231954598879940587494139517650368844561237394217101914365967
Short name T301
Test name
Test status
Simulation time 260306045935 ps
CPU time 333.97 seconds
Started Nov 22 01:41:53 PM PST 23
Finished Nov 22 01:47:30 PM PST 23
Peak memory 203056 kb
Host smart-0741fa4e-5945-4b2b-9094-09cd03de892d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=27455967351648999231954598879940587494139517650368844561237394217101914365967 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.27455967351648999231954598879940587494139517650368844561237394217101914365967
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.23467945391346064665022030077099757529937212371526787013478034941295974062756
Short name T202
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.21 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:41:57 PM PST 23
Peak memory 202008 kb
Host smart-75138908-ca6e-49ab-a2cf-dbf783fdcdaf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23467945391346064665022030077099757529937212371526787013478034941295974062756 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.23467945391346064665022030077099757529937212371526787013478034941295974062756
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.106195392505727896329882214761120032511537327120946999491200856617920775649618
Short name T226
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.33 seconds
Started Nov 22 01:41:21 PM PST 23
Finished Nov 22 01:41:35 PM PST 23
Peak memory 201920 kb
Host smart-04bc7cbd-4541-4e4c-a6a6-5c74889d87a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=106195392505727896329882214761120032511537327120946999491200856617920775649618 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_l
og /dev/null -cm_name 47.xbar_error_random.106195392505727896329882214761120032511537327120946999491200856617920775649618
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.67565488647857965441192720679188934030503120257594955484394998902270362510993
Short name T501
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.64 seconds
Started Nov 22 01:42:03 PM PST 23
Finished Nov 22 01:42:25 PM PST 23
Peak memory 201952 kb
Host smart-7d86d35f-96b2-42ba-b630-f614b1ab3f8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=67565488647857965441192720679188934030503120257594955484394998902270362510993 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 47.xbar_random.67565488647857965441192720679188934030503120257594955484394998902270362510993
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.108001898504551765765222166490711406427739782193787495866159879349080828538904
Short name T74
Test name
Test status
Simulation time 237556670935 ps
CPU time 189.08 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:44:55 PM PST 23
Peak memory 202004 kb
Host smart-9b77234a-2c3d-40da-9aff-b0a89f3ff7a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=108001898504551765765222166490711406427739782193787495866159879349080828538904 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.108001898504551765765222166490711406427739782193787495866159879349080828538904
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.37084716252443812430153516050060796318154923217499274696313160219363532960039
Short name T239
Test name
Test status
Simulation time 160909483435 ps
CPU time 196.15 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:45:00 PM PST 23
Peak memory 202020 kb
Host smart-516c4bea-883f-47d9-8c38-64fe2e8be8c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=37084716252443812430153516050060796318154923217499274696313160219363532960039 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.37084716252443812430153516050060796318154923217499274696313160219363532960039
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.95092379604037906895462509769256642814523754659172919025362626024220372286632
Short name T599
Test name
Test status
Simulation time 360920935 ps
CPU time 7.66 seconds
Started Nov 22 01:41:58 PM PST 23
Finished Nov 22 01:42:12 PM PST 23
Peak memory 201820 kb
Host smart-9aaf22a3-e377-4de6-b0df-6a81db508b6a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95092379604037906895462509769256642814523754659172919025362626024220372286632 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.95092379604037906895462509769256642814523754659172919025362626024220372286632
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.114515759461140987909944418033378497140425823295043310542746616033387168777355
Short name T87
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.32 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:41:52 PM PST 23
Peak memory 201928 kb
Host smart-d0b3b23c-bc3e-4b06-8894-b7e72998150b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=114515759461140987909944418033378497140425823295043310542746616033387168777355 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 47.xbar_same_source.114515759461140987909944418033378497140425823295043310542746616033387168777355
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.17650482403558405784920645305253764727918072821903587868901607088191231653428
Short name T536
Test name
Test status
Simulation time 331233435 ps
CPU time 1.55 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:41:48 PM PST 23
Peak memory 201824 kb
Host smart-bd122bf8-721d-49b8-8121-29679c16328e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=17650482403558405784920645305253764727918072821903587868901607088191231653428 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 47.xbar_smoke.17650482403558405784920645305253764727918072821903587868901607088191231653428
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.65446839219583928823654989442422024589465528104655581625423405944920112472996
Short name T196
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.81 seconds
Started Nov 22 01:41:26 PM PST 23
Finished Nov 22 01:41:40 PM PST 23
Peak memory 201976 kb
Host smart-b46898cb-cde0-4287-aff4-212cacf26ee9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=65446839219583928823654989442422024589465528104655581625423405944920112472996 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.65446839219583928823654989442422024589465528104655581625423405944920112472996
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.34215631262177880855851231839503343920432690944795014761791342854435396444163
Short name T170
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.71 seconds
Started Nov 22 01:41:24 PM PST 23
Finished Nov 22 01:41:38 PM PST 23
Peak memory 201816 kb
Host smart-aec80ee5-e839-4bc6-b218-8f90cffb1f08
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=34215631262177880855851231839503343920432690944795014761791342854435396444163 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.34215631262177880855851231839503343920432690944795014761791342854435396444163
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.21715427791153955987914527882790142915678820962892605828075848380914629912317
Short name T822
Test name
Test status
Simulation time 27670935 ps
CPU time 1.15 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:41:49 PM PST 23
Peak memory 201880 kb
Host smart-f585c049-5458-476a-9247-0acd59a97d04
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21715427791153955987914527882790142915678820962892605828075848380914629912317 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.21715427791153955987914527882790142915678820962892605828075848380914629912317
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.28155615971448184591293128759262989659061602585329165967475944282372566021420
Short name T128
Test name
Test status
Simulation time 46147859184 ps
CPU time 133.01 seconds
Started Nov 22 01:41:33 PM PST 23
Finished Nov 22 01:43:47 PM PST 23
Peak memory 203152 kb
Host smart-8520ab72-5cff-4d1e-99ea-1cbce4550fb0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28155615971448184591293128759262989659061602585329165967475944282372566021420 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 47.xbar_stress_all.28155615971448184591293128759262989659061602585329165967475944282372566021420
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.31997920623438583566493632730858799285138312457468455024813823921950591273498
Short name T409
Test name
Test status
Simulation time 46147859184 ps
CPU time 117.79 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:43:47 PM PST 23
Peak memory 204952 kb
Host smart-a94a85a6-e6ef-4df1-b85a-7b9296c757d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31997920623438583566493632730858799285138312457468455024813823921950591273498 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 47.xbar_stress_all_with_error.31997920623438583566493632730858799285138312457468455024813823921950591273498
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.92405144980419779659545148135647390708700784862234232535957961467549554845206
Short name T32
Test name
Test status
Simulation time 13716459184 ps
CPU time 162.59 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:44:27 PM PST 23
Peak memory 205160 kb
Host smart-bf4e3622-d04d-4f95-bace-a854788195e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92405144980419779659545148135647390708700784862234232535957961467549554845206 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.92405144980419779659545148135647390708700784862234232535957961467549554845206
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.45267415818286494838879590895429390656668989355413678898130846825053948926956
Short name T348
Test name
Test status
Simulation time 13716459184 ps
CPU time 134.52 seconds
Started Nov 22 01:41:32 PM PST 23
Finished Nov 22 01:43:48 PM PST 23
Peak memory 206284 kb
Host smart-0a6311fe-6f1b-4b1a-ab8b-156ab453265c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45267415818286494838879590895429390656668989355413678898130846825053948926956 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.45267415818286494838879590895429390656668989355413678898130846825053948926956
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.36595907420246427565278350781811748875788415002499224315850901905510528980790
Short name T800
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.02 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:41:51 PM PST 23
Peak memory 201996 kb
Host smart-b6bde864-739c-4e24-9e73-c64792b2c135
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36595907420246427565278350781811748875788415002499224315850901905510528980790 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 47.xbar_unmapped_addr.36595907420246427565278350781811748875788415002499224315850901905510528980790
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.47125926421928159569916412728413162673804582390595784803994210089192352975049
Short name T325
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.74 seconds
Started Nov 22 01:41:30 PM PST 23
Finished Nov 22 01:41:50 PM PST 23
Peak memory 202004 kb
Host smart-d27cde2e-2b25-4826-86e1-10b6388bb212
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47125926421928159569916412728413162673804582390595784803994210089192352975049 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.47125926421928159569916412728413162673804582390595784803994210089192352975049
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.101933056932638905041194265871517228568187497344545369519938438005088431854872
Short name T868
Test name
Test status
Simulation time 260306045935 ps
CPU time 341 seconds
Started Nov 22 01:41:52 PM PST 23
Finished Nov 22 01:47:35 PM PST 23
Peak memory 202928 kb
Host smart-252d8301-a21b-44b1-ac29-4675b2f897b9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=101933056932638905041194265871517228568187497344545369519938438005088431854872 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.101933056932638905041194265871517228568187497344545369519938438005088431854872
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.91243011619965454251887129774191109296440580389822874076478343719896956142157
Short name T106
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.68 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:41:57 PM PST 23
Peak memory 201860 kb
Host smart-59e56e46-60b5-44c2-8ccf-100363ed5043
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91243011619965454251887129774191109296440580389822874076478343719896956142157 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.91243011619965454251887129774191109296440580389822874076478343719896956142157
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.15863591289322355823368080948315909035908312623737924583798585956255360086051
Short name T741
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.12 seconds
Started Nov 22 01:41:47 PM PST 23
Finished Nov 22 01:42:03 PM PST 23
Peak memory 202032 kb
Host smart-46557359-d1ac-434b-b024-4e29541bf398
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15863591289322355823368080948315909035908312623737924583798585956255360086051 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 48.xbar_error_random.15863591289322355823368080948315909035908312623737924583798585956255360086051
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.73969854933368975660572650161899359247530296382734070895683604951926738626341
Short name T473
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.91 seconds
Started Nov 22 01:41:55 PM PST 23
Finished Nov 22 01:42:13 PM PST 23
Peak memory 202012 kb
Host smart-890c81ed-e4db-45ea-b352-5f917c5037ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73969854933368975660572650161899359247530296382734070895683604951926738626341 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 48.xbar_random.73969854933368975660572650161899359247530296382734070895683604951926738626341
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.24584428076210625022096933105626297209058822509530689355315824485105950553696
Short name T895
Test name
Test status
Simulation time 237556670935 ps
CPU time 187.51 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:44:51 PM PST 23
Peak memory 202000 kb
Host smart-edd3e477-adff-4c1d-9c56-c61e493c48b9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=24584428076210625022096933105626297209058822509530689355315824485105950553696 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 48.xbar_random_large_delays.24584428076210625022096933105626297209058822509530689355315824485105950553696
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.91815319779644196954328467356084617591972524489853825053834043848832596235849
Short name T677
Test name
Test status
Simulation time 160909483435 ps
CPU time 194.52 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:44:34 PM PST 23
Peak memory 201852 kb
Host smart-d33fa8c1-89ff-4fa6-a8c5-f67401fd4d8b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=91815319779644196954328467356084617591972524489853825053834043848832596235849 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.91815319779644196954328467356084617591972524489853825053834043848832596235849
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.81972360852624626178273276699808712352343285551679689946137754840453017727791
Short name T292
Test name
Test status
Simulation time 360920935 ps
CPU time 7.76 seconds
Started Nov 22 01:41:56 PM PST 23
Finished Nov 22 01:42:08 PM PST 23
Peak memory 201944 kb
Host smart-cc7afed0-99ff-45a4-bb94-a0e4bf276927
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81972360852624626178273276699808712352343285551679689946137754840453017727791 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.81972360852624626178273276699808712352343285551679689946137754840453017727791
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.108414143170354334829928638793068059034757102767785580433283858119247033078973
Short name T899
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.69 seconds
Started Nov 22 01:41:48 PM PST 23
Finished Nov 22 01:42:04 PM PST 23
Peak memory 201964 kb
Host smart-b9f74f86-2a47-41bf-8580-1832919c0dab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=108414143170354334829928638793068059034757102767785580433283858119247033078973 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 48.xbar_same_source.108414143170354334829928638793068059034757102767785580433283858119247033078973
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.69543007903411861240595579530166015413041037342675183973108118355662710542711
Short name T698
Test name
Test status
Simulation time 331233435 ps
CPU time 1.6 seconds
Started Nov 22 01:41:46 PM PST 23
Finished Nov 22 01:41:50 PM PST 23
Peak memory 201824 kb
Host smart-a1b24ad6-dfaf-4842-bf1c-1e86e569ac10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69543007903411861240595579530166015413041037342675183973108118355662710542711 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 48.xbar_smoke.69543007903411861240595579530166015413041037342675183973108118355662710542711
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.41204988534809467903427232124511491347006905030067346060139316546015467596685
Short name T525
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.72 seconds
Started Nov 22 01:42:00 PM PST 23
Finished Nov 22 01:42:21 PM PST 23
Peak memory 201888 kb
Host smart-0468b71c-87ba-4f71-91d7-7d035cf8126c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=41204988534809467903427232124511491347006905030067346060139316546015467596685 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.41204988534809467903427232124511491347006905030067346060139316546015467596685
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.111616448938753657035519373865478212529171003599856380179804590428284477693063
Short name T632
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.81 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:42:00 PM PST 23
Peak memory 201996 kb
Host smart-935e042b-397f-4afb-8325-08e1392f69c5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=111616448938753657035519373865478212529171003599856380179804590428284477693063 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.111616448938753657035519373865478212529171003599856380179804590428284477693063
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.76320320449949460045570859347832500866002771466587086018258293335125132219494
Short name T807
Test name
Test status
Simulation time 27670935 ps
CPU time 1.21 seconds
Started Nov 22 01:41:37 PM PST 23
Finished Nov 22 01:41:41 PM PST 23
Peak memory 201952 kb
Host smart-45ce8740-f77a-41b9-b501-d52fb5ae6c0b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76320320449949460045570859347832500866002771466587086018258293335125132219494 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.76320320449949460045570859347832500866002771466587086018258293335125132219494
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.110837466476322329351716687882574355927724946896507413030418817417021130816463
Short name T451
Test name
Test status
Simulation time 46147859184 ps
CPU time 117.07 seconds
Started Nov 22 01:42:01 PM PST 23
Finished Nov 22 01:44:07 PM PST 23
Peak memory 202612 kb
Host smart-fff352b1-25a9-4ef4-814b-11881b3e96cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110837466476322329351716687882574355927724946896507413030418817417021130816463 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 48.xbar_stress_all.110837466476322329351716687882574355927724946896507413030418817417021130816463
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.10680758343791627647496841915330440440137045347578932352489377810226971978698
Short name T372
Test name
Test status
Simulation time 46147859184 ps
CPU time 113.95 seconds
Started Nov 22 01:41:45 PM PST 23
Finished Nov 22 01:43:41 PM PST 23
Peak memory 204952 kb
Host smart-93cc97ea-e079-4de9-a660-c03895fde1ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10680758343791627647496841915330440440137045347578932352489377810226971978698 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 48.xbar_stress_all_with_error.10680758343791627647496841915330440440137045347578932352489377810226971978698
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.45760337097212072679341274512897880577878980352318213950129574243385642779567
Short name T793
Test name
Test status
Simulation time 13716459184 ps
CPU time 160.86 seconds
Started Nov 22 01:41:49 PM PST 23
Finished Nov 22 01:44:33 PM PST 23
Peak memory 205068 kb
Host smart-ed818380-1959-4d7b-94d7-c7a50f7e0d09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45760337097212072679341274512897880577878980352318213950129574243385642779567 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.45760337097212072679341274512897880577878980352318213950129574243385642779567
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.95609880016639449223341769380812677247916986923873808838083645133652268712549
Short name T412
Test name
Test status
Simulation time 13716459184 ps
CPU time 136.91 seconds
Started Nov 22 01:42:01 PM PST 23
Finished Nov 22 01:44:26 PM PST 23
Peak memory 206216 kb
Host smart-152be2a4-3847-4816-8c2e-f499dde5d72b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95609880016639449223341769380812677247916986923873808838083645133652268712549 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.95609880016639449223341769380812677247916986923873808838083645133652268712549
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.5575037780542176096952596157716041372302836701424407384991333723559580620700
Short name T789
Test name
Test status
Simulation time 3423420935 ps
CPU time 11.2 seconds
Started Nov 22 01:41:44 PM PST 23
Finished Nov 22 01:41:58 PM PST 23
Peak memory 202000 kb
Host smart-99b692e5-12db-4ef2-89af-4b89d33881c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5575037780542176096952596157716041372302836701424407384991333723559580620700 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 48.xbar_unmapped_addr.5575037780542176096952596157716041372302836701424407384991333723559580620700
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.101952501821991967101791391701402144394658297082175203062672783292355976244717
Short name T786
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.56 seconds
Started Nov 22 01:42:38 PM PST 23
Finished Nov 22 01:42:57 PM PST 23
Peak memory 201800 kb
Host smart-e16c97ab-ec13-4aa9-86b8-b4be7efeea2c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=101952501821991967101791391701402144394658297082175203062672783292355976244717 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.101952501821991967101791391701402144394658297082175203062672783292355976244717
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.55483923409166274376976091334648452936559260566500903891627924232078246505724
Short name T694
Test name
Test status
Simulation time 260306045935 ps
CPU time 333.17 seconds
Started Nov 22 01:41:53 PM PST 23
Finished Nov 22 01:47:28 PM PST 23
Peak memory 202840 kb
Host smart-88a671de-6213-48fe-9c60-1a6dda524ffe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=55483923409166274376976091334648452936559260566500903891627924232078246505724 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.55483923409166274376976091334648452936559260566500903891627924232078246505724
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.88582402672153641045020036812094728065537676981366954059166971049387491372302
Short name T688
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.23 seconds
Started Nov 22 01:42:00 PM PST 23
Finished Nov 22 01:42:18 PM PST 23
Peak memory 201932 kb
Host smart-2487358b-6ae6-42ca-b3f5-79dd50cf6884
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=88582402672153641045020036812094728065537676981366954059166971049387491372302 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.88582402672153641045020036812094728065537676981366954059166971049387491372302
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.87418481409135785252104734718039864902096449437770225698915454328979958948892
Short name T262
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.56 seconds
Started Nov 22 01:42:31 PM PST 23
Finished Nov 22 01:42:46 PM PST 23
Peak memory 200232 kb
Host smart-fba0eba6-7755-4735-8772-3d4546bcb136
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87418481409135785252104734718039864902096449437770225698915454328979958948892 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 49.xbar_error_random.87418481409135785252104734718039864902096449437770225698915454328979958948892
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.21192599724662962172129806323815429186181899851085621605738065909078116637870
Short name T415
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.81 seconds
Started Nov 22 01:41:32 PM PST 23
Finished Nov 22 01:41:47 PM PST 23
Peak memory 201848 kb
Host smart-fc23e1f3-a5f7-4b1d-a007-5dca73d2ae3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=21192599724662962172129806323815429186181899851085621605738065909078116637870 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 49.xbar_random.21192599724662962172129806323815429186181899851085621605738065909078116637870
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.75864699315105875120186987973122731194563933830250485258166079597767429054733
Short name T571
Test name
Test status
Simulation time 237556670935 ps
CPU time 186.61 seconds
Started Nov 22 01:41:56 PM PST 23
Finished Nov 22 01:45:06 PM PST 23
Peak memory 201940 kb
Host smart-c56d1748-7186-46f3-a2cf-c4610ebfcc87
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=75864699315105875120186987973122731194563933830250485258166079597767429054733 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 49.xbar_random_large_delays.75864699315105875120186987973122731194563933830250485258166079597767429054733
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3469591166601959014747971822223683983914023388541479529984144304735278806830
Short name T514
Test name
Test status
Simulation time 160909483435 ps
CPU time 190.81 seconds
Started Nov 22 01:42:06 PM PST 23
Finished Nov 22 01:45:22 PM PST 23
Peak memory 201820 kb
Host smart-c805559a-d0ae-4c62-989a-de385c17026e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3469591166601959014747971822223683983914023388541479529984144304735278806830 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 49.xbar_random_slow_rsp.3469591166601959014747971822223683983914023388541479529984144304735278806830
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.101486574287590620478488741997319858164768212165931183393182430564558629127019
Short name T488
Test name
Test status
Simulation time 360920935 ps
CPU time 7.55 seconds
Started Nov 22 01:41:36 PM PST 23
Finished Nov 22 01:41:46 PM PST 23
Peak memory 201972 kb
Host smart-aceb93a4-bb31-46cf-811d-556a1f205a93
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101486574287590620478488741997319858164768212165931183393182430564558629127019 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.101486574287590620478488741997319858164768212165931183393182430564558629127019
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.76518053480589095434973652213154926702134002764756581904148389770963874930272
Short name T478
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.92 seconds
Started Nov 22 01:42:01 PM PST 23
Finished Nov 22 01:42:21 PM PST 23
Peak memory 201388 kb
Host smart-43b67d05-fce3-48ef-beba-e82cfe23e5f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76518053480589095434973652213154926702134002764756581904148389770963874930272 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 49.xbar_same_source.76518053480589095434973652213154926702134002764756581904148389770963874930272
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.14528052984043127662780708769625970525365301781158114507964945602861679332603
Short name T659
Test name
Test status
Simulation time 331233435 ps
CPU time 1.58 seconds
Started Nov 22 01:41:42 PM PST 23
Finished Nov 22 01:41:46 PM PST 23
Peak memory 201872 kb
Host smart-5d49ba89-c89b-41d4-9858-14798c23deba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14528052984043127662780708769625970525365301781158114507964945602861679332603 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 49.xbar_smoke.14528052984043127662780708769625970525365301781158114507964945602861679332603
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.7739700248820872594747877102692403888802196901350233184335437916089014352334
Short name T356
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.73 seconds
Started Nov 22 01:42:03 PM PST 23
Finished Nov 22 01:42:23 PM PST 23
Peak memory 201816 kb
Host smart-62b42446-1a80-4f3d-83fc-41591d8e199d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=7739700248820872594747877102692403888802196901350233184335437916089014352334 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.7739700248820872594747877102692403888802196901350233184335437916089014352334
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.54613074690322557598569905463642572332717447097132979947066795857178505054954
Short name T206
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.83 seconds
Started Nov 22 01:42:00 PM PST 23
Finished Nov 22 01:42:21 PM PST 23
Peak memory 201940 kb
Host smart-68295632-94f1-46ef-aec7-62764e17840a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=54613074690322557598569905463642572332717447097132979947066795857178505054954 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.54613074690322557598569905463642572332717447097132979947066795857178505054954
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.53186889099801172419904132406661087979066588350829150186262922315371579854230
Short name T437
Test name
Test status
Simulation time 27670935 ps
CPU time 1.17 seconds
Started Nov 22 01:42:00 PM PST 23
Finished Nov 22 01:42:09 PM PST 23
Peak memory 201864 kb
Host smart-3472e897-6be2-4638-9c36-4513ee5a4e97
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53186889099801172419904132406661087979066588350829150186262922315371579854230 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.53186889099801172419904132406661087979066588350829150186262922315371579854230
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.10788071223562272222007175876855212138331523664891466654967266289207437735985
Short name T754
Test name
Test status
Simulation time 46147859184 ps
CPU time 124.54 seconds
Started Nov 22 01:42:00 PM PST 23
Finished Nov 22 01:44:13 PM PST 23
Peak memory 203156 kb
Host smart-42f20869-2a11-4d98-87eb-12497e82ffc8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10788071223562272222007175876855212138331523664891466654967266289207437735985 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 49.xbar_stress_all.10788071223562272222007175876855212138331523664891466654967266289207437735985
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.18930960234254817843663089340469342334726383600914317232173101687973694644510
Short name T520
Test name
Test status
Simulation time 46147859184 ps
CPU time 109.65 seconds
Started Nov 22 01:42:02 PM PST 23
Finished Nov 22 01:44:00 PM PST 23
Peak memory 204332 kb
Host smart-d80d2039-1e44-4398-b874-40edab40364a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18930960234254817843663089340469342334726383600914317232173101687973694644510 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 49.xbar_stress_all_with_error.18930960234254817843663089340469342334726383600914317232173101687973694644510
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.46173083008897593601437348597188925242572565244209111595247753927954938833356
Short name T168
Test name
Test status
Simulation time 13716459184 ps
CPU time 154.2 seconds
Started Nov 22 01:42:02 PM PST 23
Finished Nov 22 01:44:44 PM PST 23
Peak memory 204564 kb
Host smart-5cca9ec4-6049-48e2-ac60-9210c95160db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46173083008897593601437348597188925242572565244209111595247753927954938833356 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.46173083008897593601437348597188925242572565244209111595247753927954938833356
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.45735668076525045848664712862823093264067157625975662894819310223043771245664
Short name T349
Test name
Test status
Simulation time 13716459184 ps
CPU time 129.22 seconds
Started Nov 22 01:42:31 PM PST 23
Finished Nov 22 01:44:42 PM PST 23
Peak memory 204076 kb
Host smart-f0da11c3-b47c-4541-b89a-72c873532d7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45735668076525045848664712862823093264067157625975662894819310223043771245664 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.45735668076525045848664712862823093264067157625975662894819310223043771245664
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.83701626274921773461853799994273017216695270273073240603115730656609100622942
Short name T593
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.89 seconds
Started Nov 22 01:42:36 PM PST 23
Finished Nov 22 01:42:50 PM PST 23
Peak memory 201640 kb
Host smart-3ad9d2e9-55ae-4b10-b79a-438cdf9315e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83701626274921773461853799994273017216695270273073240603115730656609100622942 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 49.xbar_unmapped_addr.83701626274921773461853799994273017216695270273073240603115730656609100622942
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.84131889444825037067730201171119884309736445723072702977740953012158072300434
Short name T173
Test name
Test status
Simulation time 4712795935 ps
CPU time 18.22 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:41:35 PM PST 23
Peak memory 201968 kb
Host smart-ca2aae63-7f30-41de-8c5e-69e4c3eda78f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=84131889444825037067730201171119884309736445723072702977740953012158072300434 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.84131889444825037067730201171119884309736445723072702977740953012158072300434
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.105477138232409089511793524402475097051325695080704539613049934590728531982450
Short name T745
Test name
Test status
Simulation time 260306045935 ps
CPU time 334.11 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:45:39 PM PST 23
Peak memory 202896 kb
Host smart-42958c9a-97fd-4f03-b71e-493fdd4a72a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=105477138232409089511793524402475097051325695080704539613049934590728531982450 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.105477138232409089511793524402475097051325695080704539613049934590728531982450
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.36007168048717605540843028201705605122042950790230307711191240591066487912709
Short name T238
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.33 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:40:15 PM PST 23
Peak memory 201996 kb
Host smart-6e749ebe-5b63-4bc2-9673-a36db8308343
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36007168048717605540843028201705605122042950790230307711191240591066487912709 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.36007168048717605540843028201705605122042950790230307711191240591066487912709
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.5852786669796934531785153013181720683425662087562785575754940663449551121898
Short name T365
Test name
Test status
Simulation time 4923670935 ps
CPU time 12.64 seconds
Started Nov 22 01:40:19 PM PST 23
Finished Nov 22 01:40:33 PM PST 23
Peak memory 201992 kb
Host smart-c805055f-b2c1-4699-89f9-4479248ae7d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5852786669796934531785153013181720683425662087562785575754940663449551121898 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 5.xbar_error_random.5852786669796934531785153013181720683425662087562785575754940663449551121898
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.54941769313734915578808659927628392666505827245545255703926234372620590348990
Short name T68
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.71 seconds
Started Nov 22 01:40:36 PM PST 23
Finished Nov 22 01:40:51 PM PST 23
Peak memory 201932 kb
Host smart-a69c3b3c-952d-4a30-b819-c9ca22bcfe3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54941769313734915578808659927628392666505827245545255703926234372620590348990 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 5.xbar_random.54941769313734915578808659927628392666505827245545255703926234372620590348990
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.11185928759422569609592275645651118998775153603279344694404491328277409237223
Short name T665
Test name
Test status
Simulation time 237556670935 ps
CPU time 185.79 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:44:26 PM PST 23
Peak memory 201940 kb
Host smart-48531bd9-a52c-46e4-a22f-7e75f79b4948
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=11185928759422569609592275645651118998775153603279344694404491328277409237223 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 5.xbar_random_large_delays.11185928759422569609592275645651118998775153603279344694404491328277409237223
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.94136971760253621558682324799632538248925072569743898261473738646419656257528
Short name T259
Test name
Test status
Simulation time 160909483435 ps
CPU time 193.09 seconds
Started Nov 22 01:40:28 PM PST 23
Finished Nov 22 01:43:43 PM PST 23
Peak memory 201844 kb
Host smart-83162926-30d7-4f1a-a369-1c5a08625189
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=94136971760253621558682324799632538248925072569743898261473738646419656257528 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.94136971760253621558682324799632538248925072569743898261473738646419656257528
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.21596889961403028248219096275373093783370078739554746040512132211348498425662
Short name T730
Test name
Test status
Simulation time 360920935 ps
CPU time 7.89 seconds
Started Nov 22 01:40:44 PM PST 23
Finished Nov 22 01:40:53 PM PST 23
Peak memory 201880 kb
Host smart-42e741f2-be47-4864-a8d5-03864b5ca65f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21596889961403028248219096275373093783370078739554746040512132211348498425662 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.21596889961403028248219096275373093783370078739554746040512132211348498425662
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.41717628163991925221065463334335993148896631484884959825689604745293967711096
Short name T364
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.03 seconds
Started Nov 22 01:40:30 PM PST 23
Finished Nov 22 01:40:44 PM PST 23
Peak memory 201868 kb
Host smart-9901dbf1-4b22-495c-a407-9ae071fa24a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=41717628163991925221065463334335993148896631484884959825689604745293967711096 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 5.xbar_same_source.41717628163991925221065463334335993148896631484884959825689604745293967711096
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.10812589799421940306119491190079252475020511787130184431807513441972737817661
Short name T113
Test name
Test status
Simulation time 331233435 ps
CPU time 1.57 seconds
Started Nov 22 01:40:38 PM PST 23
Finished Nov 22 01:40:41 PM PST 23
Peak memory 201928 kb
Host smart-cd8592a8-2bd5-41ea-acda-a7a00e4d9c8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10812589799421940306119491190079252475020511787130184431807513441972737817661 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 5.xbar_smoke.10812589799421940306119491190079252475020511787130184431807513441972737817661
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.62101416043421280431193393462388172129050214196551206958147000552183297077960
Short name T555
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.85 seconds
Started Nov 22 01:40:45 PM PST 23
Finished Nov 22 01:40:59 PM PST 23
Peak memory 201908 kb
Host smart-e861c541-b947-4841-875c-c7cf20bbfd6c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=62101416043421280431193393462388172129050214196551206958147000552183297077960 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.62101416043421280431193393462388172129050214196551206958147000552183297077960
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.11353419649921198303968270129119153780598481213687136990167181773852032068881
Short name T117
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.82 seconds
Started Nov 22 01:40:34 PM PST 23
Finished Nov 22 01:40:49 PM PST 23
Peak memory 201996 kb
Host smart-938152ef-cd0f-44a5-89fa-a286ddb3c519
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=11353419649921198303968270129119153780598481213687136990167181773852032068881 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.11353419649921198303968270129119153780598481213687136990167181773852032068881
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.40535446147878670410214208085494988823886686209097527251466872563948583150815
Short name T153
Test name
Test status
Simulation time 27670935 ps
CPU time 1.2 seconds
Started Nov 22 01:41:11 PM PST 23
Finished Nov 22 01:41:13 PM PST 23
Peak memory 201912 kb
Host smart-44b892ce-ce5e-4a34-a628-87cc6e2e0e3c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40535446147878670410214208085494988823886686209097527251466872563948583150815 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.40535446147878670410214208085494988823886686209097527251466872563948583150815
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.103911246850716748308915390366266736538929604859108013257225885026189574589875
Short name T851
Test name
Test status
Simulation time 46147859184 ps
CPU time 119.24 seconds
Started Nov 22 01:40:23 PM PST 23
Finished Nov 22 01:42:23 PM PST 23
Peak memory 203192 kb
Host smart-3d537e83-508f-4afb-a7e0-e48fe9813fb2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103911246850716748308915390366266736538929604859108013257225885026189574589875 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 5.xbar_stress_all.103911246850716748308915390366266736538929604859108013257225885026189574589875
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.44650994092167316057005418193009229479968803667804296621619036910805950215327
Short name T491
Test name
Test status
Simulation time 46147859184 ps
CPU time 119.5 seconds
Started Nov 22 01:40:03 PM PST 23
Finished Nov 22 01:42:05 PM PST 23
Peak memory 204928 kb
Host smart-08cee7b4-8543-4ce6-9431-3a7674d84ce5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44650994092167316057005418193009229479968803667804296621619036910805950215327 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 5.xbar_stress_all_with_error.44650994092167316057005418193009229479968803667804296621619036910805950215327
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.58115065241177995267465924949370801150004741856659054665419668580870539626258
Short name T246
Test name
Test status
Simulation time 13716459184 ps
CPU time 162.77 seconds
Started Nov 22 01:40:21 PM PST 23
Finished Nov 22 01:43:05 PM PST 23
Peak memory 205116 kb
Host smart-87708305-d514-44d4-bde7-489e8e5821b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=58115065241177995267465924949370801150004741856659054665419668580870539626258 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.58115065241177995267465924949370801150004741856659054665419668580870539626258
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.14095727280251341092517616652709162496909338793759336987866292244964380677161
Short name T391
Test name
Test status
Simulation time 13716459184 ps
CPU time 135.38 seconds
Started Nov 22 01:40:21 PM PST 23
Finished Nov 22 01:42:37 PM PST 23
Peak memory 206276 kb
Host smart-d083c24b-9042-40a9-899a-80d2c2bfcf5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14095727280251341092517616652709162496909338793759336987866292244964380677161 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.14095727280251341092517616652709162496909338793759336987866292244964380677161
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.91525172014705430263865890807181668772920836894480369227389586099479073086303
Short name T568
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.23 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:12 PM PST 23
Peak memory 201928 kb
Host smart-33f0f782-bf7e-43c2-af97-f90eb2936488
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91525172014705430263865890807181668772920836894480369227389586099479073086303 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 5.xbar_unmapped_addr.91525172014705430263865890807181668772920836894480369227389586099479073086303
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.93060733234695024113284955761155513073978610610306929387196379014219017483444
Short name T497
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.34 seconds
Started Nov 22 01:40:10 PM PST 23
Finished Nov 22 01:40:28 PM PST 23
Peak memory 201972 kb
Host smart-70a5b60d-206f-4d35-8761-4c6004c81d11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93060733234695024113284955761155513073978610610306929387196379014219017483444 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.93060733234695024113284955761155513073978610610306929387196379014219017483444
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.105812831583827619073175774739029807065808902065902693575860003227603380414033
Short name T284
Test name
Test status
Simulation time 260306045935 ps
CPU time 332.99 seconds
Started Nov 22 01:40:07 PM PST 23
Finished Nov 22 01:45:42 PM PST 23
Peak memory 202996 kb
Host smart-12ffd59b-befe-4afa-97f8-50c3088b08d3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=105812831583827619073175774739029807065808902065902693575860003227603380414033 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.105812831583827619073175774739029807065808902065902693575860003227603380414033
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.105528754012896495755762055537208114619322277623358076621510859743038543715602
Short name T112
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.73 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:40:19 PM PST 23
Peak memory 201988 kb
Host smart-83164268-2b0d-48f0-a81c-9b4b5bf86a23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105528754012896495755762055537208114619322277623358076621510859743038543715602 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.105528754012896495755762055537208114619322277623358076621510859743038543715602
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.18482737567627948217896360019215915798570260318202978081225086476915161239011
Short name T209
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.43 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:40:18 PM PST 23
Peak memory 201932 kb
Host smart-83fb1c7c-33a9-4553-a42b-94d38faf4e21
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18482737567627948217896360019215915798570260318202978081225086476915161239011 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 6.xbar_error_random.18482737567627948217896360019215915798570260318202978081225086476915161239011
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.8717257838169355971947024152760446662057559237690851430527635063771011825918
Short name T306
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.88 seconds
Started Nov 22 01:40:23 PM PST 23
Finished Nov 22 01:40:38 PM PST 23
Peak memory 201912 kb
Host smart-65176688-c7b8-402d-a1fe-76db630a6bc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=8717257838169355971947024152760446662057559237690851430527635063771011825918 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 6.xbar_random.8717257838169355971947024152760446662057559237690851430527635063771011825918
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.34718365618209068344379560840948972027415612359380578956368198389127012797913
Short name T493
Test name
Test status
Simulation time 237556670935 ps
CPU time 184.72 seconds
Started Nov 22 01:40:15 PM PST 23
Finished Nov 22 01:43:20 PM PST 23
Peak memory 201860 kb
Host smart-fbd89ee7-6f3a-4e45-9797-ae356b42a119
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=34718365618209068344379560840948972027415612359380578956368198389127012797913 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 6.xbar_random_large_delays.34718365618209068344379560840948972027415612359380578956368198389127012797913
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.29722443683873683493476262841363798028958538098812501594623349269726420840976
Short name T511
Test name
Test status
Simulation time 160909483435 ps
CPU time 191.95 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:43:22 PM PST 23
Peak memory 201924 kb
Host smart-cea58369-6df3-43e9-8f09-bf63e49c549d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=29722443683873683493476262841363798028958538098812501594623349269726420840976 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.29722443683873683493476262841363798028958538098812501594623349269726420840976
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.42902969374190449449252167879689248092503597844553288920177778717504588146080
Short name T403
Test name
Test status
Simulation time 360920935 ps
CPU time 8.52 seconds
Started Nov 22 01:40:03 PM PST 23
Finished Nov 22 01:40:14 PM PST 23
Peak memory 201928 kb
Host smart-6b8e966e-9bf9-41a4-b08e-28f56d3dc32a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42902969374190449449252167879689248092503597844553288920177778717504588146080 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.42902969374190449449252167879689248092503597844553288920177778717504588146080
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.13222075236368051935799329078334632570733668370957690726269042730122035595722
Short name T887
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.86 seconds
Started Nov 22 01:40:21 PM PST 23
Finished Nov 22 01:40:33 PM PST 23
Peak memory 201936 kb
Host smart-9e0bad67-a752-43a1-ae95-5caeee757087
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13222075236368051935799329078334632570733668370957690726269042730122035595722 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 6.xbar_same_source.13222075236368051935799329078334632570733668370957690726269042730122035595722
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.65230284137612222415978229704156179695187270631810008135167797237256618610031
Short name T509
Test name
Test status
Simulation time 331233435 ps
CPU time 1.65 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:40:14 PM PST 23
Peak memory 201988 kb
Host smart-2b17bf15-221c-49eb-808d-4031ad6b6bbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65230284137612222415978229704156179695187270631810008135167797237256618610031 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 6.xbar_smoke.65230284137612222415978229704156179695187270631810008135167797237256618610031
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.83341730982107933647833970610865283513690203978165835067793865202459479412170
Short name T103
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.96 seconds
Started Nov 22 01:40:22 PM PST 23
Finished Nov 22 01:40:36 PM PST 23
Peak memory 201988 kb
Host smart-7b96abc9-cae2-40f8-b3c1-c9d30326dcd2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=83341730982107933647833970610865283513690203978165835067793865202459479412170 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.83341730982107933647833970610865283513690203978165835067793865202459479412170
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.112228353977720920982743837710249070773790489276387905023301837620513545265507
Short name T166
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.7 seconds
Started Nov 22 01:40:30 PM PST 23
Finished Nov 22 01:40:45 PM PST 23
Peak memory 202012 kb
Host smart-38991a33-3724-4fe2-9928-853f411f8b8e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=112228353977720920982743837710249070773790489276387905023301837620513545265507 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.112228353977720920982743837710249070773790489276387905023301837620513545265507
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.89957801260133177540959473646982468118493343891354497404037247489040750744154
Short name T710
Test name
Test status
Simulation time 27670935 ps
CPU time 1.23 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:40:05 PM PST 23
Peak memory 201860 kb
Host smart-0c3acda7-11ba-45fa-975c-5c82863d7e1f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89957801260133177540959473646982468118493343891354497404037247489040750744154 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.89957801260133177540959473646982468118493343891354497404037247489040750744154
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.26668426907239867584446056548868948519825063373747118050282067316124686922604
Short name T205
Test name
Test status
Simulation time 46147859184 ps
CPU time 132.66 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:42:25 PM PST 23
Peak memory 203272 kb
Host smart-eedd8b04-6582-4e5c-b8da-8fdd3391dafd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=26668426907239867584446056548868948519825063373747118050282067316124686922604 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 6.xbar_stress_all.26668426907239867584446056548868948519825063373747118050282067316124686922604
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.4267384540395086852726384615343653235832199230178699881229543321632625702844
Short name T889
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.17 seconds
Started Nov 22 01:40:12 PM PST 23
Finished Nov 22 01:42:19 PM PST 23
Peak memory 204868 kb
Host smart-4e89d1e6-33e0-4327-b68a-7999f00ac4cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4267384540395086852726384615343653235832199230178699881229543321632625702844 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 6.xbar_stress_all_with_error.4267384540395086852726384615343653235832199230178699881229543321632625702844
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.54687135177480559107941839396449662198060388892174530473899871667101639121723
Short name T354
Test name
Test status
Simulation time 13716459184 ps
CPU time 161.31 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:42:51 PM PST 23
Peak memory 205172 kb
Host smart-b84fd9e5-3ce7-4b5a-b13e-2bad62a4f18b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54687135177480559107941839396449662198060388892174530473899871667101639121723 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.54687135177480559107941839396449662198060388892174530473899871667101639121723
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.33095992667242274775877871365882319047168442212237818107388595866430974120296
Short name T865
Test name
Test status
Simulation time 13716459184 ps
CPU time 139 seconds
Started Nov 22 01:40:19 PM PST 23
Finished Nov 22 01:42:39 PM PST 23
Peak memory 206280 kb
Host smart-5fb300c9-e4c1-4ea8-b6fd-d4976e1d265a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33095992667242274775877871365882319047168442212237818107388595866430974120296 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.33095992667242274775877871365882319047168442212237818107388595866430974120296
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.25514615625563319235021720459509978133981460601167470555315737491852689198430
Short name T225
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.9 seconds
Started Nov 22 01:40:23 PM PST 23
Finished Nov 22 01:40:36 PM PST 23
Peak memory 201996 kb
Host smart-a9da7202-5f95-42bf-92f8-360cbcee6ca2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25514615625563319235021720459509978133981460601167470555315737491852689198430 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 6.xbar_unmapped_addr.25514615625563319235021720459509978133981460601167470555315737491852689198430
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.40638830060427009815650533615069078601918622336933581739325940649007706579521
Short name T53
Test name
Test status
Simulation time 4712795935 ps
CPU time 16.94 seconds
Started Nov 22 01:40:19 PM PST 23
Finished Nov 22 01:40:37 PM PST 23
Peak memory 202008 kb
Host smart-d73ffed1-df76-4194-af88-5f10c69d45f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40638830060427009815650533615069078601918622336933581739325940649007706579521 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.40638830060427009815650533615069078601918622336933581739325940649007706579521
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.22830466804757355087876012952214915281063680400740896302927462841866640447794
Short name T766
Test name
Test status
Simulation time 260306045935 ps
CPU time 339.51 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:45:41 PM PST 23
Peak memory 202992 kb
Host smart-04d5c6a9-95bd-4221-9422-f37c0be80a29
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=22830466804757355087876012952214915281063680400740896302927462841866640447794 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.22830466804757355087876012952214915281063680400740896302927462841866640447794
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.92101432034169195909618033054947927675873202241178119044388985651455552671287
Short name T546
Test name
Test status
Simulation time 3423420935 ps
CPU time 9.61 seconds
Started Nov 22 01:40:06 PM PST 23
Finished Nov 22 01:40:17 PM PST 23
Peak memory 201948 kb
Host smart-232ef2c8-09d0-4e8b-b97d-f9c2e3f6d4dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92101432034169195909618033054947927675873202241178119044388985651455552671287 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.92101432034169195909618033054947927675873202241178119044388985651455552671287
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.69645858989199077448674084234868703461093979116729611608415550464102173448107
Short name T145
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.15 seconds
Started Nov 22 01:40:20 PM PST 23
Finished Nov 22 01:40:35 PM PST 23
Peak memory 201952 kb
Host smart-52c96efa-edea-45cd-81d0-39410a26fb12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69645858989199077448674084234868703461093979116729611608415550464102173448107 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 7.xbar_error_random.69645858989199077448674084234868703461093979116729611608415550464102173448107
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.86228556853928486059465360961200830571892212351292463653182631929345333991904
Short name T218
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.19 seconds
Started Nov 22 01:40:06 PM PST 23
Finished Nov 22 01:40:22 PM PST 23
Peak memory 201976 kb
Host smart-cfa96491-9e96-41e6-bffa-aa5856a42f27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86228556853928486059465360961200830571892212351292463653182631929345333991904 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 7.xbar_random.86228556853928486059465360961200830571892212351292463653182631929345333991904
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.8789062537517222792295539583325360666755780238114146685425446600660766171464
Short name T75
Test name
Test status
Simulation time 237556670935 ps
CPU time 189.51 seconds
Started Nov 22 01:40:26 PM PST 23
Finished Nov 22 01:43:37 PM PST 23
Peak memory 200944 kb
Host smart-9e11935e-7087-4067-af1c-80783f86e37a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=8789062537517222792295539583325360666755780238114146685425446600660766171464 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 7.xbar_random_large_delays.8789062537517222792295539583325360666755780238114146685425446600660766171464
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.86196987294197902162850693625067364036451629770655719147709620909093112637002
Short name T304
Test name
Test status
Simulation time 160909483435 ps
CPU time 196.18 seconds
Started Nov 22 01:40:23 PM PST 23
Finished Nov 22 01:43:40 PM PST 23
Peak memory 201988 kb
Host smart-8fd587c7-e1b2-4025-9dd5-2187a4c08b14
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=86196987294197902162850693625067364036451629770655719147709620909093112637002 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.86196987294197902162850693625067364036451629770655719147709620909093112637002
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.58241005905756686840244790220747689369143218884886013569775968622396565386596
Short name T763
Test name
Test status
Simulation time 360920935 ps
CPU time 7.94 seconds
Started Nov 22 01:40:14 PM PST 23
Finished Nov 22 01:40:23 PM PST 23
Peak memory 201812 kb
Host smart-c9284ec8-502e-42d6-9514-5a88089ae39a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58241005905756686840244790220747689369143218884886013569775968622396565386596 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.58241005905756686840244790220747689369143218884886013569775968622396565386596
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.99208598865357358392202400552941158587197440199408945775846390897356237332474
Short name T521
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.39 seconds
Started Nov 22 01:40:20 PM PST 23
Finished Nov 22 01:40:33 PM PST 23
Peak memory 201940 kb
Host smart-f1a57dee-7bb7-4469-a30d-0cc6fcb2dc4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99208598865357358392202400552941158587197440199408945775846390897356237332474 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 7.xbar_same_source.99208598865357358392202400552941158587197440199408945775846390897356237332474
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.52182666190716220167846193027942620354632040385437689565607710377971006985300
Short name T150
Test name
Test status
Simulation time 331233435 ps
CPU time 1.61 seconds
Started Nov 22 01:40:06 PM PST 23
Finished Nov 22 01:40:09 PM PST 23
Peak memory 201904 kb
Host smart-1d92da6b-092f-405f-857b-417375eb5774
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=52182666190716220167846193027942620354632040385437689565607710377971006985300 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 7.xbar_smoke.52182666190716220167846193027942620354632040385437689565607710377971006985300
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.111915420998532444371752500970637576524330065668564053494819547953496689492977
Short name T123
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.67 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:14 PM PST 23
Peak memory 201972 kb
Host smart-fdff103c-04d5-47d8-b9e9-1c15959edace
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=111915420998532444371752500970637576524330065668564053494819547953496689492977 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.111915420998532444371752500970637576524330065668564053494819547953496689492977
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.6645742482350188623411534962177525750942728529914146504362513447108322576817
Short name T313
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.78 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:40:25 PM PST 23
Peak memory 202028 kb
Host smart-ace0215e-ae61-4d5a-8df5-d817c4a51b6a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=6645742482350188623411534962177525750942728529914146504362513447108322576817 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.6645742482350188623411534962177525750942728529914146504362513447108322576817
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.30228640095815581118263652762872879113734393844064154495001720622022367402434
Short name T237
Test name
Test status
Simulation time 27670935 ps
CPU time 1.24 seconds
Started Nov 22 01:40:26 PM PST 23
Finished Nov 22 01:40:29 PM PST 23
Peak memory 201136 kb
Host smart-baf8c558-03d5-40c0-ae51-f08458ada42e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30228640095815581118263652762872879113734393844064154495001720622022367402434 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.30228640095815581118263652762872879113734393844064154495001720622022367402434
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.40850983072180794349733589180818670976517669254627638866654818920663088517444
Short name T260
Test name
Test status
Simulation time 46147859184 ps
CPU time 121.25 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:42:06 PM PST 23
Peak memory 203072 kb
Host smart-bcd1a953-e609-44e5-a1e0-7a26da26fc8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40850983072180794349733589180818670976517669254627638866654818920663088517444 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 7.xbar_stress_all.40850983072180794349733589180818670976517669254627638866654818920663088517444
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.81296415709489000756241106954092747722506298019905293556907917862341533433093
Short name T244
Test name
Test status
Simulation time 46147859184 ps
CPU time 109.94 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:41:59 PM PST 23
Peak memory 204852 kb
Host smart-3f0981b5-d5fb-4b14-86ae-1583c6ffbed1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81296415709489000756241106954092747722506298019905293556907917862341533433093 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 7.xbar_stress_all_with_error.81296415709489000756241106954092747722506298019905293556907917862341533433093
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.93927699096749534291352046999234995414113029335457445832633357007501005129551
Short name T220
Test name
Test status
Simulation time 13716459184 ps
CPU time 159.71 seconds
Started Nov 22 01:40:21 PM PST 23
Finished Nov 22 01:43:02 PM PST 23
Peak memory 205184 kb
Host smart-e596fb66-7add-4157-8434-c366914b4d2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93927699096749534291352046999234995414113029335457445832633357007501005129551 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.93927699096749534291352046999234995414113029335457445832633357007501005129551
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.94635808925817124013467365795048161312060632680889432295016625203801741339649
Short name T99
Test name
Test status
Simulation time 13716459184 ps
CPU time 140.55 seconds
Started Nov 22 01:40:29 PM PST 23
Finished Nov 22 01:42:52 PM PST 23
Peak memory 206120 kb
Host smart-73a16f6a-ea89-4655-801f-ad73cd9e4956
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94635808925817124013467365795048161312060632680889432295016625203801741339649 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.94635808925817124013467365795048161312060632680889432295016625203801741339649
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.46797661944494279248348574961494709072572431958683186769174490704408054863925
Short name T825
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.66 seconds
Started Nov 22 01:40:07 PM PST 23
Finished Nov 22 01:40:19 PM PST 23
Peak memory 201952 kb
Host smart-ae158338-ac38-4a27-b85b-c01feca2787f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46797661944494279248348574961494709072572431958683186769174490704408054863925 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 7.xbar_unmapped_addr.46797661944494279248348574961494709072572431958683186769174490704408054863925
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.68673154095578146570863319952957186998491151272210259853974943128940658691236
Short name T882
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.76 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:40:29 PM PST 23
Peak memory 202036 kb
Host smart-d6f8410a-40bc-4a3f-a3da-a85103dba417
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=68673154095578146570863319952957186998491151272210259853974943128940658691236 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.68673154095578146570863319952957186998491151272210259853974943128940658691236
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.72728818499150729008598078477816954501214242692111234923124794373695486965986
Short name T848
Test name
Test status
Simulation time 260306045935 ps
CPU time 330.4 seconds
Started Nov 22 01:40:03 PM PST 23
Finished Nov 22 01:45:36 PM PST 23
Peak memory 202936 kb
Host smart-1a0c726a-95bc-488a-b031-96aacbed2e80
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=72728818499150729008598078477816954501214242692111234923124794373695486965986 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.72728818499150729008598078477816954501214242692111234923124794373695486965986
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.93674587651655579602452133262688400131967574822671830814254526197712279523646
Short name T100
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.26 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:40:37 PM PST 23
Peak memory 201996 kb
Host smart-95b589d9-d256-4c9c-9913-dba6c22ec575
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93674587651655579602452133262688400131967574822671830814254526197712279523646 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.93674587651655579602452133262688400131967574822671830814254526197712279523646
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.53509707693304001349096780775814450482259539853170035679291223241067449597078
Short name T131
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.61 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:40:51 PM PST 23
Peak memory 201996 kb
Host smart-676683a4-1d5d-41cd-9deb-f5e72a4cc7c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53509707693304001349096780775814450482259539853170035679291223241067449597078 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 8.xbar_error_random.53509707693304001349096780775814450482259539853170035679291223241067449597078
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.112427149606137703120167127711714532361807647864699348549078280695600245077400
Short name T640
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.84 seconds
Started Nov 22 01:40:23 PM PST 23
Finished Nov 22 01:40:38 PM PST 23
Peak memory 201920 kb
Host smart-24098afe-bc1b-4446-bbe6-462fee6ecafc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112427149606137703120167127711714532361807647864699348549078280695600245077400 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 8.xbar_random.112427149606137703120167127711714532361807647864699348549078280695600245077400
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.84496646041439189285168487161620822779154211877366558705188358418085450980179
Short name T642
Test name
Test status
Simulation time 237556670935 ps
CPU time 189.86 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:43:36 PM PST 23
Peak memory 202008 kb
Host smart-f4b04859-c81a-4552-b025-bae472410789
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=84496646041439189285168487161620822779154211877366558705188358418085450980179 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 8.xbar_random_large_delays.84496646041439189285168487161620822779154211877366558705188358418085450980179
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.76522815060612350116339218870617884840815930193383546759826321501056971242815
Short name T54
Test name
Test status
Simulation time 160909483435 ps
CPU time 195.22 seconds
Started Nov 22 01:40:06 PM PST 23
Finished Nov 22 01:43:23 PM PST 23
Peak memory 201972 kb
Host smart-70228c0a-21bd-41ff-91df-b4698affd3e4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=76522815060612350116339218870617884840815930193383546759826321501056971242815 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.76522815060612350116339218870617884840815930193383546759826321501056971242815
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.4002722389861819167123028390692698874100504568123863550865781737290200083356
Short name T853
Test name
Test status
Simulation time 360920935 ps
CPU time 7.85 seconds
Started Nov 22 01:40:14 PM PST 23
Finished Nov 22 01:40:23 PM PST 23
Peak memory 201812 kb
Host smart-2240c801-f30a-48d8-9c74-d422a764099b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002722389861819167123028390692698874100504568123863550865781737290200083356 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.4002722389861819167123028390692698874100504568123863550865781737290200083356
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.76301503241293827901697439369453304446687195414124788311987746302689558291505
Short name T779
Test name
Test status
Simulation time 5235733435 ps
CPU time 12.03 seconds
Started Nov 22 01:40:26 PM PST 23
Finished Nov 22 01:40:39 PM PST 23
Peak memory 202004 kb
Host smart-f88bb85f-7557-4b9c-8293-dffe1b8d93f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76301503241293827901697439369453304446687195414124788311987746302689558291505 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 8.xbar_same_source.76301503241293827901697439369453304446687195414124788311987746302689558291505
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.5819808926470250128379074931954309804692218058971761192685249262722007674435
Short name T594
Test name
Test status
Simulation time 331233435 ps
CPU time 1.6 seconds
Started Nov 22 01:40:13 PM PST 23
Finished Nov 22 01:40:16 PM PST 23
Peak memory 201940 kb
Host smart-d200810c-9972-4f4b-9860-9465a1faa1b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5819808926470250128379074931954309804692218058971761192685249262722007674435 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 8.xbar_smoke.5819808926470250128379074931954309804692218058971761192685249262722007674435
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.32139607460768781829896572529725215797830628849346593097509457645120381232114
Short name T360
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.95 seconds
Started Nov 22 01:40:09 PM PST 23
Finished Nov 22 01:40:24 PM PST 23
Peak memory 201980 kb
Host smart-ddbaeb5c-e27b-4aba-9031-2d3553d874f4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=32139607460768781829896572529725215797830628849346593097509457645120381232114 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.32139607460768781829896572529725215797830628849346593097509457645120381232114
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.88131412552554704397962446832596092059031713738359319168753980648984802933397
Short name T447
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.9 seconds
Started Nov 22 01:40:29 PM PST 23
Finished Nov 22 01:40:44 PM PST 23
Peak memory 201960 kb
Host smart-d7f8dbb8-6b0d-45a5-a07c-25ca67cfc6ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=88131412552554704397962446832596092059031713738359319168753980648984802933397 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.88131412552554704397962446832596092059031713738359319168753980648984802933397
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.36747477435539548553986109969879279369230056384701023074410735121349674833552
Short name T435
Test name
Test status
Simulation time 27670935 ps
CPU time 1.19 seconds
Started Nov 22 01:40:30 PM PST 23
Finished Nov 22 01:40:34 PM PST 23
Peak memory 201328 kb
Host smart-ccf94adb-3bfb-44cc-ba0f-3b74c42958d5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36747477435539548553986109969879279369230056384701023074410735121349674833552 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.36747477435539548553986109969879279369230056384701023074410735121349674833552
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.110883132197976910540614887854436153943390348589275805116135558305278545143568
Short name T609
Test name
Test status
Simulation time 46147859184 ps
CPU time 126.08 seconds
Started Nov 22 01:41:12 PM PST 23
Finished Nov 22 01:43:19 PM PST 23
Peak memory 203120 kb
Host smart-5efe890f-f002-41a9-92b2-bf8c7278729d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110883132197976910540614887854436153943390348589275805116135558305278545143568 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 8.xbar_stress_all.110883132197976910540614887854436153943390348589275805116135558305278545143568
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.72448933821704507678660751145681212801204101665411695590916346626886726418631
Short name T508
Test name
Test status
Simulation time 46147859184 ps
CPU time 113.83 seconds
Started Nov 22 01:41:13 PM PST 23
Finished Nov 22 01:43:08 PM PST 23
Peak memory 204944 kb
Host smart-8d0dcca2-9242-4217-9b4b-6e92e908fa80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72448933821704507678660751145681212801204101665411695590916346626886726418631 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 8.xbar_stress_all_with_error.72448933821704507678660751145681212801204101665411695590916346626886726418631
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.76033061871386770376022031987261530746304619026854427714883686809636715080161
Short name T893
Test name
Test status
Simulation time 13716459184 ps
CPU time 158.36 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:43:16 PM PST 23
Peak memory 205140 kb
Host smart-e1e057b1-477a-4946-9187-b41da20a9bce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76033061871386770376022031987261530746304619026854427714883686809636715080161 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.76033061871386770376022031987261530746304619026854427714883686809636715080161
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.83484969856807378147786760421081560929321467645270096657290085768264427360531
Short name T713
Test name
Test status
Simulation time 13716459184 ps
CPU time 134.4 seconds
Started Nov 22 01:40:35 PM PST 23
Finished Nov 22 01:42:51 PM PST 23
Peak memory 206248 kb
Host smart-55e31e0e-9ade-482e-872d-d5a6b7f1d4a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83484969856807378147786760421081560929321467645270096657290085768264427360531 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.83484969856807378147786760421081560929321467645270096657290085768264427360531
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.22737415864825604999689059125812299228021273304975051852937424493154425901998
Short name T687
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.68 seconds
Started Nov 22 01:40:11 PM PST 23
Finished Nov 22 01:40:23 PM PST 23
Peak memory 201816 kb
Host smart-f8b3e308-d7aa-40f5-8fc3-4ecc4f01bf61
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22737415864825604999689059125812299228021273304975051852937424493154425901998 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 8.xbar_unmapped_addr.22737415864825604999689059125812299228021273304975051852937424493154425901998
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.29972754204792193794653879698016365655923319501890893522891124097986955151226
Short name T28
Test name
Test status
Simulation time 4712795935 ps
CPU time 17.94 seconds
Started Nov 22 01:40:34 PM PST 23
Finished Nov 22 01:40:54 PM PST 23
Peak memory 201960 kb
Host smart-812772ef-0502-435f-823b-85d06b42ed11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29972754204792193794653879698016365655923319501890893522891124097986955151226 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.29972754204792193794653879698016365655923319501890893522891124097986955151226
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.96496197603277961134431223217566307971541397167915019427694107326577651687368
Short name T608
Test name
Test status
Simulation time 260306045935 ps
CPU time 336.85 seconds
Started Nov 22 01:40:29 PM PST 23
Finished Nov 22 01:46:07 PM PST 23
Peak memory 202964 kb
Host smart-7fed6825-0dd9-4f74-a9b8-7f76d49cb62f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=96496197603277961134431223217566307971541397167915019427694107326577651687368 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.96496197603277961134431223217566307971541397167915019427694107326577651687368
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.62677032983812965718245794612565846962737848700140707049098130067041767977368
Short name T341
Test name
Test status
Simulation time 3423420935 ps
CPU time 10.41 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:41:29 PM PST 23
Peak memory 201848 kb
Host smart-c2b9f784-2df7-427d-8a48-4d343f4d0d0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62677032983812965718245794612565846962737848700140707049098130067041767977368 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.62677032983812965718245794612565846962737848700140707049098130067041767977368
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.45150413606418823082868632444960753342833376077820237935564146697611834181693
Short name T809
Test name
Test status
Simulation time 4923670935 ps
CPU time 13.23 seconds
Started Nov 22 01:41:15 PM PST 23
Finished Nov 22 01:41:30 PM PST 23
Peak memory 201996 kb
Host smart-bb344b57-1d56-4288-a761-a38ebadc88ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45150413606418823082868632444960753342833376077820237935564146697611834181693 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 9.xbar_error_random.45150413606418823082868632444960753342833376077820237935564146697611834181693
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.87319248612766031143888982739205344978466466140504853623980887832189530037174
Short name T298
Test name
Test status
Simulation time 4923670935 ps
CPU time 14.18 seconds
Started Nov 22 01:40:31 PM PST 23
Finished Nov 22 01:40:47 PM PST 23
Peak memory 202000 kb
Host smart-7e6072e5-3832-4fc1-8e35-2e59e92a888e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87319248612766031143888982739205344978466466140504853623980887832189530037174 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 9.xbar_random.87319248612766031143888982739205344978466466140504853623980887832189530037174
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.20134141663513099524576581480761386545934063449144036687053199929971374341304
Short name T696
Test name
Test status
Simulation time 237556670935 ps
CPU time 188.86 seconds
Started Nov 22 01:40:38 PM PST 23
Finished Nov 22 01:43:48 PM PST 23
Peak memory 201948 kb
Host smart-17c5d413-604e-4397-b831-8a2e5f77454a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=20134141663513099524576581480761386545934063449144036687053199929971374341304 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 9.xbar_random_large_delays.20134141663513099524576581480761386545934063449144036687053199929971374341304
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.13722342847677623779045321994726141706537725949951664241144700522332743090723
Short name T802
Test name
Test status
Simulation time 160909483435 ps
CPU time 194.59 seconds
Started Nov 22 01:41:16 PM PST 23
Finished Nov 22 01:44:32 PM PST 23
Peak memory 201948 kb
Host smart-51fb51f0-8f1a-49fe-bb69-efc8a35b9d75
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=13722342847677623779045321994726141706537725949951664241144700522332743090723 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.13722342847677623779045321994726141706537725949951664241144700522332743090723
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.97825595801671886760929454633780910653240483252958932168732890720664628629751
Short name T420
Test name
Test status
Simulation time 360920935 ps
CPU time 8.36 seconds
Started Nov 22 01:40:44 PM PST 23
Finished Nov 22 01:40:53 PM PST 23
Peak memory 201932 kb
Host smart-18301fa2-f2fe-4641-a6b0-feb84bb47045
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97825595801671886760929454633780910653240483252958932168732890720664628629751 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.97825595801671886760929454633780910653240483252958932168732890720664628629751
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.85344232006268270997405282896677415584722156610889992631691729677631843713556
Short name T483
Test name
Test status
Simulation time 5235733435 ps
CPU time 11.85 seconds
Started Nov 22 01:41:11 PM PST 23
Finished Nov 22 01:41:25 PM PST 23
Peak memory 201896 kb
Host smart-153b4610-0fb5-4ebc-91a5-3fcc94c660d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85344232006268270997405282896677415584722156610889992631691729677631843713556 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 9.xbar_same_source.85344232006268270997405282896677415584722156610889992631691729677631843713556
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.94958950344828896701247094172059925162669285402967491554886759244215327106569
Short name T294
Test name
Test status
Simulation time 331233435 ps
CPU time 1.57 seconds
Started Nov 22 01:40:33 PM PST 23
Finished Nov 22 01:40:36 PM PST 23
Peak memory 201868 kb
Host smart-56674538-9702-4e9b-be23-dca012ee5fcf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94958950344828896701247094172059925162669285402967491554886759244215327106569 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 9.xbar_smoke.94958950344828896701247094172059925162669285402967491554886759244215327106569
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.42141557646550843044243404483503955337601355693534498339803836925801893642826
Short name T272
Test name
Test status
Simulation time 15405233435 ps
CPU time 12.84 seconds
Started Nov 22 01:40:25 PM PST 23
Finished Nov 22 01:40:39 PM PST 23
Peak memory 201936 kb
Host smart-744b29fd-15d5-4579-a49c-8593aba9b6b0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=42141557646550843044243404483503955337601355693534498339803836925801893642826 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.42141557646550843044243404483503955337601355693534498339803836925801893642826
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.59904705518106816326529862817437786554113680219309691463602134099266533222260
Short name T373
Test name
Test status
Simulation time 10098608435 ps
CPU time 12.97 seconds
Started Nov 22 01:40:55 PM PST 23
Finished Nov 22 01:41:09 PM PST 23
Peak memory 201880 kb
Host smart-7c3e9f8e-49fd-45ee-978d-cdfe32e45cf8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=59904705518106816326529862817437786554113680219309691463602134099266533222260 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.59904705518106816326529862817437786554113680219309691463602134099266533222260
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.18390994973714930759722032638353223911235199453240350633817124590301643246372
Short name T649
Test name
Test status
Simulation time 27670935 ps
CPU time 1.18 seconds
Started Nov 22 01:40:34 PM PST 23
Finished Nov 22 01:40:37 PM PST 23
Peak memory 201904 kb
Host smart-b679c620-2e79-45a8-9e3f-b4050f687992
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18390994973714930759722032638353223911235199453240350633817124590301643246372 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.18390994973714930759722032638353223911235199453240350633817124590301643246372
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.34599627704879668380399047027777465261843393084369843480221870927712977021898
Short name T20
Test name
Test status
Simulation time 46147859184 ps
CPU time 125.92 seconds
Started Nov 22 01:40:41 PM PST 23
Finished Nov 22 01:42:48 PM PST 23
Peak memory 203136 kb
Host smart-4d4111fe-f9ee-478d-bf63-7943f9599fe9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34599627704879668380399047027777465261843393084369843480221870927712977021898 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 9.xbar_stress_all.34599627704879668380399047027777465261843393084369843480221870927712977021898
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.79613348220316639953802615693711700542852228271275178278903093562851931442272
Short name T307
Test name
Test status
Simulation time 46147859184 ps
CPU time 119.12 seconds
Started Nov 22 01:41:18 PM PST 23
Finished Nov 22 01:43:18 PM PST 23
Peak memory 204928 kb
Host smart-3434389e-1cf4-4e32-94dc-9ba222a890ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=79613348220316639953802615693711700542852228271275178278903093562851931442272 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 9.xbar_stress_all_with_error.79613348220316639953802615693711700542852228271275178278903093562851931442272
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.47859943598089443693383778513961621296241810133333935110619991202198613049481
Short name T161
Test name
Test status
Simulation time 13716459184 ps
CPU time 160.42 seconds
Started Nov 22 01:41:17 PM PST 23
Finished Nov 22 01:43:59 PM PST 23
Peak memory 205164 kb
Host smart-1acb99dd-424d-4dc5-ad0e-c6b46aef47b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47859943598089443693383778513961621296241810133333935110619991202198613049481 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.47859943598089443693383778513961621296241810133333935110619991202198613049481
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.4122566323174162321596471184473544102265564462395066062412758142237115692623
Short name T210
Test name
Test status
Simulation time 13716459184 ps
CPU time 135.38 seconds
Started Nov 22 01:41:29 PM PST 23
Finished Nov 22 01:43:46 PM PST 23
Peak memory 206272 kb
Host smart-c734bfd9-dfc8-4d72-9caf-17ad4f12d335
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4122566323174162321596471184473544102265564462395066062412758142237115692623 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.4122566323174162321596471184473544102265564462395066062412758142237115692623
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.12520353049639201517671545372693270677734355034500515837652018584396124861424
Short name T323
Test name
Test status
Simulation time 3423420935 ps
CPU time 12.14 seconds
Started Nov 22 01:41:00 PM PST 23
Finished Nov 22 01:41:13 PM PST 23
Peak memory 202000 kb
Host smart-cd139637-41d7-456d-85e9-fee9d47d27eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12520353049639201517671545372693270677734355034500515837652018584396124861424 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 9.xbar_unmapped_addr.12520353049639201517671545372693270677734355034500515837652018584396124861424
Directory /workspace/9.xbar_unmapped_addr/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%