| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.25 | 100.00 | 95.52 | 100.00 | 100.00 | 99.99 | 100.00 |
| T768 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1748474761 | Dec 24 01:13:55 PM PST 23 | Dec 24 01:14:44 PM PST 23 | 343987527 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2266788130 | Dec 24 01:14:13 PM PST 23 | Dec 24 01:14:34 PM PST 23 | 873216926 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.4283574725 | Dec 24 01:13:06 PM PST 23 | Dec 24 01:14:50 PM PST 23 | 74903957936 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.996234587 | Dec 24 01:12:58 PM PST 23 | Dec 24 01:13:48 PM PST 23 | 3436668804 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/38.xbar_same_source.2982789756 | Dec 24 01:13:19 PM PST 23 | Dec 24 01:13:35 PM PST 23 | 10078621 ps | ||
| T204 | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2916834375 | Dec 24 01:12:31 PM PST 23 | Dec 24 01:15:24 PM PST 23 | 59451901175 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3970485750 | Dec 24 01:14:05 PM PST 23 | Dec 24 01:15:04 PM PST 23 | 48679084688 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1639083206 | Dec 24 01:12:59 PM PST 23 | Dec 24 01:13:17 PM PST 23 | 1707544756 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.2964351382 | Dec 24 01:12:17 PM PST 23 | Dec 24 01:12:54 PM PST 23 | 4093389900 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3610782236 | Dec 24 01:13:02 PM PST 23 | Dec 24 01:13:18 PM PST 23 | 13818728 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.996271403 | Dec 24 01:12:18 PM PST 23 | Dec 24 01:14:39 PM PST 23 | 39013912248 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.746739302 | Dec 24 01:14:26 PM PST 23 | Dec 24 01:14:39 PM PST 23 | 173412333 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3344323383 | Dec 24 01:14:06 PM PST 23 | Dec 24 01:15:30 PM PST 23 | 4348441783 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1773713735 | Dec 24 01:12:27 PM PST 23 | Dec 24 01:12:44 PM PST 23 | 1444340446 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1839545362 | Dec 24 01:13:23 PM PST 23 | Dec 24 01:13:43 PM PST 23 | 42023801 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3319041166 | Dec 24 01:13:00 PM PST 23 | Dec 24 01:13:29 PM PST 23 | 8380268972 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1504653919 | Dec 24 01:12:32 PM PST 23 | Dec 24 01:12:49 PM PST 23 | 99642285 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2795141491 | Dec 24 01:12:07 PM PST 23 | Dec 24 01:13:51 PM PST 23 | 7216904805 ps | ||
| T230 | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.843901591 | Dec 24 01:14:02 PM PST 23 | Dec 24 01:14:35 PM PST 23 | 5112172282 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.4007418275 | Dec 24 01:13:04 PM PST 23 | Dec 24 01:14:33 PM PST 23 | 330514987 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.4267940198 | Dec 24 01:13:09 PM PST 23 | Dec 24 01:16:12 PM PST 23 | 2574277477 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1952935118 | Dec 24 01:13:27 PM PST 23 | Dec 24 01:14:59 PM PST 23 | 760290407 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3230545558 | Dec 24 01:12:58 PM PST 23 | Dec 24 01:13:18 PM PST 23 | 2352269580 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1102538769 | Dec 24 01:13:58 PM PST 23 | Dec 24 01:14:45 PM PST 23 | 420555438 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2777449734 | Dec 24 01:12:14 PM PST 23 | Dec 24 01:12:31 PM PST 23 | 98580559 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/22.xbar_smoke.1754025468 | Dec 24 01:13:06 PM PST 23 | Dec 24 01:13:23 PM PST 23 | 11122148 ps | ||
| T127 | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4172754725 | Dec 24 01:12:57 PM PST 23 | Dec 24 01:18:27 PM PST 23 | 48281510765 ps | ||
| T208 | /workspace/coverage/xbar_build_mode/3.xbar_same_source.1007308242 | Dec 24 01:12:19 PM PST 23 | Dec 24 01:12:45 PM PST 23 | 1311726204 ps | ||
| T209 | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3672323642 | Dec 24 01:12:52 PM PST 23 | Dec 24 01:13:08 PM PST 23 | 9190974016 ps | ||
| T210 | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.193754589 | Dec 24 01:13:13 PM PST 23 | Dec 24 01:13:33 PM PST 23 | 1423971497 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4092120810 | Dec 24 01:13:54 PM PST 23 | Dec 24 01:14:06 PM PST 23 | 1032334088 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.269431215 | Dec 24 01:12:58 PM PST 23 | Dec 24 01:13:17 PM PST 23 | 1100231373 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3686417224 | Dec 24 01:13:39 PM PST 23 | Dec 24 01:13:50 PM PST 23 | 85893469 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3757983009 | Dec 24 01:14:02 PM PST 23 | Dec 24 01:14:17 PM PST 23 | 8156208 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.863680145 | Dec 24 01:12:58 PM PST 23 | Dec 24 01:13:14 PM PST 23 | 83962984 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.338157258 | Dec 24 01:13:00 PM PST 23 | Dec 24 01:13:30 PM PST 23 | 4216500188 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/9.xbar_random.3863981215 | Dec 24 01:12:15 PM PST 23 | Dec 24 01:12:32 PM PST 23 | 48525231 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2682397053 | Dec 24 01:12:32 PM PST 23 | Dec 24 01:12:48 PM PST 23 | 20987322 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3967561036 | Dec 24 01:12:28 PM PST 23 | Dec 24 01:12:46 PM PST 23 | 85066454 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1902868501 | Dec 24 01:13:17 PM PST 23 | Dec 24 01:13:46 PM PST 23 | 8071716160 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.3916556476 | Dec 24 01:13:13 PM PST 23 | Dec 24 01:14:06 PM PST 23 | 11724781815 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/35.xbar_random.834852961 | Dec 24 01:13:22 PM PST 23 | Dec 24 01:13:48 PM PST 23 | 1475423008 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/30.xbar_smoke.1796905839 | Dec 24 01:13:06 PM PST 23 | Dec 24 01:13:23 PM PST 23 | 7950581 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1715921145 | Dec 24 01:14:42 PM PST 23 | Dec 24 01:17:55 PM PST 23 | 67190145824 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2235348218 | Dec 24 01:14:05 PM PST 23 | Dec 24 01:14:32 PM PST 23 | 2526185545 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1567402540 | Dec 24 01:13:28 PM PST 23 | Dec 24 01:13:58 PM PST 23 | 2549353101 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2775308383 | Dec 24 01:13:17 PM PST 23 | Dec 24 01:14:09 PM PST 23 | 13334633151 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.813655635 | Dec 24 01:12:03 PM PST 23 | Dec 24 01:12:11 PM PST 23 | 29215076 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/38.xbar_smoke.2361676086 | Dec 24 01:14:00 PM PST 23 | Dec 24 01:14:12 PM PST 23 | 98860888 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.4287049186 | Dec 24 01:12:21 PM PST 23 | Dec 24 01:12:35 PM PST 23 | 11679369 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/31.xbar_same_source.609304979 | Dec 24 01:13:11 PM PST 23 | Dec 24 01:13:34 PM PST 23 | 690730679 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1615714212 | Dec 24 01:13:18 PM PST 23 | Dec 24 01:13:47 PM PST 23 | 117230044 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1113040992 | Dec 24 01:14:03 PM PST 23 | Dec 24 01:14:30 PM PST 23 | 3128443725 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.4262525069 | Dec 24 01:12:29 PM PST 23 | Dec 24 01:12:43 PM PST 23 | 8009203 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/49.xbar_smoke.1760313618 | Dec 24 01:14:43 PM PST 23 | Dec 24 01:14:51 PM PST 23 | 268154238 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2086716372 | Dec 24 01:12:52 PM PST 23 | Dec 24 01:13:02 PM PST 23 | 32676990 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2127128487 | Dec 24 01:12:07 PM PST 23 | Dec 24 01:12:25 PM PST 23 | 107635129 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2573472695 | Dec 24 01:14:08 PM PST 23 | Dec 24 01:14:31 PM PST 23 | 354778584 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3817307051 | Dec 24 01:13:40 PM PST 23 | Dec 24 01:13:50 PM PST 23 | 185609730 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3631284638 | Dec 24 01:14:00 PM PST 23 | Dec 24 01:15:49 PM PST 23 | 42131386374 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3633542004 | Dec 24 01:12:54 PM PST 23 | Dec 24 01:14:43 PM PST 23 | 1038721410 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2392091939 | Dec 24 01:12:20 PM PST 23 | Dec 24 01:12:58 PM PST 23 | 4844922625 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.377439756 | Dec 24 01:13:41 PM PST 23 | Dec 24 01:14:47 PM PST 23 | 16386268420 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.576022664 | Dec 24 01:12:31 PM PST 23 | Dec 24 01:13:06 PM PST 23 | 232319006 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.165135633 | Dec 24 01:12:22 PM PST 23 | Dec 24 01:15:00 PM PST 23 | 1062895241 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1705323790 | Dec 24 01:14:00 PM PST 23 | Dec 24 01:14:22 PM PST 23 | 5847358523 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/32.xbar_smoke.3771341495 | Dec 24 01:13:18 PM PST 23 | Dec 24 01:13:34 PM PST 23 | 48207373 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2849629056 | Dec 24 01:12:59 PM PST 23 | Dec 24 01:13:13 PM PST 23 | 94334342 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3532543605 | Dec 24 01:12:28 PM PST 23 | Dec 24 01:12:47 PM PST 23 | 6488496864 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.951035972 | Dec 24 01:12:11 PM PST 23 | Dec 24 01:13:28 PM PST 23 | 18177098032 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3034610088 | Dec 24 01:13:01 PM PST 23 | Dec 24 01:13:23 PM PST 23 | 60058083 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1204276040 | Dec 24 01:13:31 PM PST 23 | Dec 24 01:13:42 PM PST 23 | 20914758 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.3261241583 | Dec 24 01:13:52 PM PST 23 | Dec 24 01:14:13 PM PST 23 | 434961994 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1258033925 | Dec 24 01:12:35 PM PST 23 | Dec 24 01:13:05 PM PST 23 | 183617313 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3692028808 | Dec 24 01:12:07 PM PST 23 | Dec 24 01:12:17 PM PST 23 | 17289560 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.4015534271 | Dec 24 01:13:02 PM PST 23 | Dec 24 01:13:51 PM PST 23 | 6131326697 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/40.xbar_same_source.3305684242 | Dec 24 01:13:28 PM PST 23 | Dec 24 01:13:47 PM PST 23 | 663474085 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.990221497 | Dec 24 01:11:53 PM PST 23 | Dec 24 01:12:03 PM PST 23 | 25267493 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.4073183668 | Dec 24 01:12:33 PM PST 23 | Dec 24 01:13:26 PM PST 23 | 403777199 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3034002866 | Dec 24 01:13:57 PM PST 23 | Dec 24 01:14:09 PM PST 23 | 3926654969 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1972780627 | Dec 24 01:13:31 PM PST 23 | Dec 24 01:13:43 PM PST 23 | 30130162 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.67926510 | Dec 24 01:13:58 PM PST 23 | Dec 24 01:14:18 PM PST 23 | 15217499721 ps | ||
| T128 | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3051699190 | Dec 24 01:14:13 PM PST 23 | Dec 24 01:16:47 PM PST 23 | 94700677804 ps | ||
| T225 | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3746204436 | Dec 24 01:12:08 PM PST 23 | Dec 24 01:16:43 PM PST 23 | 34998897977 ps | ||
| T226 | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1030824945 | Dec 24 01:13:12 PM PST 23 | Dec 24 01:15:52 PM PST 23 | 22724474454 ps | ||
| T227 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.3623798501 | Dec 24 01:13:12 PM PST 23 | Dec 24 01:13:35 PM PST 23 | 1765701923 ps | ||
| T129 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2223559905 | Dec 24 01:13:10 PM PST 23 | Dec 24 01:17:18 PM PST 23 | 7643138335 ps | ||
| T228 | /workspace/coverage/xbar_build_mode/22.xbar_error_random.66313209 | Dec 24 01:13:00 PM PST 23 | Dec 24 01:13:19 PM PST 23 | 69479450 ps | ||
| T130 | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1149827423 | Dec 24 01:12:51 PM PST 23 | Dec 24 01:17:25 PM PST 23 | 106275209521 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2631155408 | Dec 24 01:13:58 PM PST 23 | Dec 24 01:16:09 PM PST 23 | 14220939876 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1605760303 | Dec 24 01:12:56 PM PST 23 | Dec 24 01:13:49 PM PST 23 | 1691438615 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1891399734 | Dec 24 01:12:30 PM PST 23 | Dec 24 01:12:43 PM PST 23 | 23804987 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/41.xbar_same_source.2416472294 | Dec 24 01:13:36 PM PST 23 | Dec 24 01:13:55 PM PST 23 | 1986779154 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.880613594 | Dec 24 01:13:00 PM PST 23 | Dec 24 01:14:55 PM PST 23 | 12981408210 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/9.xbar_same_source.724112772 | Dec 24 01:12:49 PM PST 23 | Dec 24 01:13:08 PM PST 23 | 1818038985 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/12.xbar_random.3930538875 | Dec 24 01:12:38 PM PST 23 | Dec 24 01:12:59 PM PST 23 | 544433171 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.230774428 | Dec 24 01:14:01 PM PST 23 | Dec 24 01:14:29 PM PST 23 | 81223024 ps | ||
| T148 | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1143215222 | Dec 24 01:13:37 PM PST 23 | Dec 24 01:14:21 PM PST 23 | 5448912816 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.353485249 | Dec 24 01:12:34 PM PST 23 | Dec 24 01:12:48 PM PST 23 | 120247405 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/29.xbar_error_random.580979398 | Dec 24 01:13:14 PM PST 23 | Dec 24 01:13:30 PM PST 23 | 223992426 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.879731028 | Dec 24 01:13:07 PM PST 23 | Dec 24 01:13:29 PM PST 23 | 217058973 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/47.xbar_same_source.2659653872 | Dec 24 01:14:06 PM PST 23 | Dec 24 01:14:29 PM PST 23 | 771805725 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1401007696 | Dec 24 01:13:15 PM PST 23 | Dec 24 01:13:33 PM PST 23 | 52955783 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1988781687 | Dec 24 01:13:57 PM PST 23 | Dec 24 01:14:04 PM PST 23 | 11327080 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.642243122 | Dec 24 01:12:57 PM PST 23 | Dec 24 01:13:11 PM PST 23 | 103384722 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/27.xbar_smoke.1639730752 | Dec 24 01:13:03 PM PST 23 | Dec 24 01:13:20 PM PST 23 | 140101809 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.3400554915 | Dec 24 01:12:43 PM PST 23 | Dec 24 01:13:09 PM PST 23 | 3219214656 ps | ||
| T239 | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.956541672 | Dec 24 01:12:01 PM PST 23 | Dec 24 01:12:16 PM PST 23 | 413150775 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/47.xbar_smoke.489426390 | Dec 24 01:14:13 PM PST 23 | Dec 24 01:14:29 PM PST 23 | 55010662 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.418046729 | Dec 24 01:12:43 PM PST 23 | Dec 24 01:12:56 PM PST 23 | 194286788 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/27.xbar_error_random.2418007702 | Dec 24 01:13:12 PM PST 23 | Dec 24 01:13:32 PM PST 23 | 393433558 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.593696326 | Dec 24 01:12:04 PM PST 23 | Dec 24 01:13:08 PM PST 23 | 14193203620 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.354322269 | Dec 24 01:13:08 PM PST 23 | Dec 24 01:13:40 PM PST 23 | 148523084 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/19.xbar_smoke.4268609105 | Dec 24 01:12:39 PM PST 23 | Dec 24 01:12:52 PM PST 23 | 65069196 ps | ||
| T190 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2877285067 | Dec 24 01:12:21 PM PST 23 | Dec 24 01:14:45 PM PST 23 | 5597277251 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1203166913 | Dec 24 01:13:35 PM PST 23 | Dec 24 01:13:49 PM PST 23 | 1561053379 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.870158404 | Dec 24 01:13:59 PM PST 23 | Dec 24 01:14:59 PM PST 23 | 15502250428 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.4148397735 | Dec 24 01:12:29 PM PST 23 | Dec 24 01:12:49 PM PST 23 | 73061797 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1141217213 | Dec 24 01:12:52 PM PST 23 | Dec 24 01:15:51 PM PST 23 | 37951465813 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2140144319 | Dec 24 01:13:02 PM PST 23 | Dec 24 01:13:22 PM PST 23 | 108090362 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3973194845 | Dec 24 01:12:13 PM PST 23 | Dec 24 01:12:40 PM PST 23 | 917112675 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1260387720 | Dec 24 01:12:46 PM PST 23 | Dec 24 01:12:58 PM PST 23 | 75129043 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3484190656 | Dec 24 01:12:12 PM PST 23 | Dec 24 01:12:35 PM PST 23 | 57426561 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.605093592 | Dec 24 01:13:22 PM PST 23 | Dec 24 01:13:45 PM PST 23 | 1048829500 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3955126306 | Dec 24 01:12:52 PM PST 23 | Dec 24 01:13:01 PM PST 23 | 12063720 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.385093604 | Dec 24 01:13:11 PM PST 23 | Dec 24 01:13:47 PM PST 23 | 195031774 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/3.xbar_smoke.1637608261 | Dec 24 01:11:58 PM PST 23 | Dec 24 01:12:07 PM PST 23 | 76117277 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/33.xbar_error_random.2776167762 | Dec 24 01:13:13 PM PST 23 | Dec 24 01:13:30 PM PST 23 | 104565964 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/33.xbar_random.2005729050 | Dec 24 01:13:14 PM PST 23 | Dec 24 01:13:32 PM PST 23 | 77142668 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2994750442 | Dec 24 01:12:34 PM PST 23 | Dec 24 01:12:50 PM PST 23 | 48494386 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2954857254 | Dec 24 01:13:12 PM PST 23 | Dec 24 01:17:15 PM PST 23 | 113381350880 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3014683959 | Dec 24 01:12:32 PM PST 23 | Dec 24 01:12:56 PM PST 23 | 4770562323 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/5.xbar_same_source.4094505265 | Dec 24 01:12:29 PM PST 23 | Dec 24 01:12:52 PM PST 23 | 957258428 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3965884722 | Dec 24 01:12:28 PM PST 23 | Dec 24 01:12:51 PM PST 23 | 1689319492 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.382571173 | Dec 24 01:13:39 PM PST 23 | Dec 24 01:13:52 PM PST 23 | 1370728571 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2959710056 | Dec 24 01:13:21 PM PST 23 | Dec 24 01:13:48 PM PST 23 | 1612803592 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3805582624 | Dec 24 01:13:22 PM PST 23 | Dec 24 01:14:06 PM PST 23 | 123421949 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.4112441150 | Dec 24 01:14:09 PM PST 23 | Dec 24 01:15:41 PM PST 23 | 1368971402 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.2466884591 | Dec 24 01:12:45 PM PST 23 | Dec 24 01:12:57 PM PST 23 | 205203498 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1663411612 | Dec 24 01:13:56 PM PST 23 | Dec 24 01:14:08 PM PST 23 | 4826136026 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.761298161 | Dec 24 01:13:38 PM PST 23 | Dec 24 01:13:53 PM PST 23 | 66048571 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.815498814 | Dec 24 01:12:09 PM PST 23 | Dec 24 01:12:38 PM PST 23 | 3458744933 ps | ||
| T131 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2895364692 | Dec 24 01:13:57 PM PST 23 | Dec 24 01:15:28 PM PST 23 | 5236271120 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.4127114239 | Dec 24 01:13:48 PM PST 23 | Dec 24 01:14:19 PM PST 23 | 271317399 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2232877720 | Dec 24 01:13:38 PM PST 23 | Dec 24 01:15:06 PM PST 23 | 7525503017 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/0.xbar_same_source.3501991242 | Dec 24 01:12:18 PM PST 23 | Dec 24 01:12:31 PM PST 23 | 15485578 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3230030390 | Dec 24 01:12:44 PM PST 23 | Dec 24 01:12:54 PM PST 23 | 11166061 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3584208988 | Dec 24 01:14:08 PM PST 23 | Dec 24 01:14:32 PM PST 23 | 90087245 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/5.xbar_error_random.2517803213 | Dec 24 01:12:27 PM PST 23 | Dec 24 01:12:44 PM PST 23 | 72088232 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3409746416 | Dec 24 01:12:08 PM PST 23 | Dec 24 01:12:19 PM PST 23 | 9384914 ps |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2057912082 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6815289266 ps |
| CPU time | 70.76 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:15:25 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-7efd36ab-5e03-4dba-afca-33394669d755 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2057912082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2057912082 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2535768935 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 54469964427 ps |
| CPU time | 338.96 seconds |
| Started | Dec 24 01:12:34 PM PST 23 |
| Finished | Dec 24 01:18:26 PM PST 23 |
| Peak memory | 203880 kb |
| Host | smart-27e8341e-5121-49a9-985a-bbd958490cd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2535768935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.2535768935 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.423597862 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 160900959193 ps |
| CPU time | 299.88 seconds |
| Started | Dec 24 01:12:32 PM PST 23 |
| Finished | Dec 24 01:17:45 PM PST 23 |
| Peak memory | 203596 kb |
| Host | smart-a97fa04f-8137-422a-bdc9-d9dcec2b6bec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=423597862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow _rsp.423597862 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2472285142 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 33066876597 ps |
| CPU time | 200.55 seconds |
| Started | Dec 24 01:12:21 PM PST 23 |
| Finished | Dec 24 01:15:54 PM PST 23 |
| Peak memory | 201516 kb |
| Host | smart-56a7f00f-a6cd-42f6-ae83-6ec822a226c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2472285142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.2472285142 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1399121846 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 57620454434 ps |
| CPU time | 390.16 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:19:08 PM PST 23 |
| Peak memory | 203084 kb |
| Host | smart-680b1df5-376d-4eb0-b2c9-9c59a2c1bcd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1399121846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.1399121846 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.501480289 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5571499997 ps |
| CPU time | 140.83 seconds |
| Started | Dec 24 01:13:04 PM PST 23 |
| Finished | Dec 24 01:15:41 PM PST 23 |
| Peak memory | 203984 kb |
| Host | smart-d5bf7c63-6eae-4898-acfd-fd0e9356e66e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=501480289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand _reset.501480289 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2798609989 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 234459655876 ps |
| CPU time | 328.56 seconds |
| Started | Dec 24 01:13:34 PM PST 23 |
| Finished | Dec 24 01:19:11 PM PST 23 |
| Peak memory | 202588 kb |
| Host | smart-0658dfe6-2c29-41d2-bc6e-eacb34863236 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2798609989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.2798609989 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.1487936580 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 51948821 ps |
| CPU time | 4.12 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:13:13 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-c3db559e-18a6-4490-9f1d-383097a2ac4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1487936580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1487936580 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.4206186956 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9045007634 ps |
| CPU time | 141.41 seconds |
| Started | Dec 24 01:12:51 PM PST 23 |
| Finished | Dec 24 01:15:20 PM PST 23 |
| Peak memory | 204148 kb |
| Host | smart-cd133d89-6aab-4ecb-9309-c3f65d446752 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4206186956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.4206186956 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.2152091665 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 49994227093 ps |
| CPU time | 112.66 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:14:30 PM PST 23 |
| Peak memory | 201564 kb |
| Host | smart-db6d99f3-e62d-41c9-94b2-4e34938f7fea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152091665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2152091665 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.476009560 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 149354337339 ps |
| CPU time | 260.87 seconds |
| Started | Dec 24 01:12:12 PM PST 23 |
| Finished | Dec 24 01:16:45 PM PST 23 |
| Peak memory | 202832 kb |
| Host | smart-e01b780a-1d9f-4cd1-a2c6-d52235e404b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=476009560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow _rsp.476009560 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.4213988854 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 36805897274 ps |
| CPU time | 257.7 seconds |
| Started | Dec 24 01:12:21 PM PST 23 |
| Finished | Dec 24 01:16:51 PM PST 23 |
| Peak memory | 203912 kb |
| Host | smart-76e799a6-2ae9-4b36-8bcf-099c26daef17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4213988854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.4213988854 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.710142920 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 84548957029 ps |
| CPU time | 141.69 seconds |
| Started | Dec 24 01:12:08 PM PST 23 |
| Finished | Dec 24 01:14:40 PM PST 23 |
| Peak memory | 202284 kb |
| Host | smart-1a4ce60a-bdc6-4605-8fda-96fb1679530d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=710142920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow _rsp.710142920 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2308612754 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1275176514 ps |
| CPU time | 154.62 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:15:40 PM PST 23 |
| Peak memory | 203920 kb |
| Host | smart-2484d83b-27ae-48b6-a542-14594588caf4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2308612754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.2308612754 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.649799475 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 13925363576 ps |
| CPU time | 106.03 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:15:06 PM PST 23 |
| Peak memory | 201120 kb |
| Host | smart-5a27ec99-7e28-4063-8ec9-819520e0e2f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=649799475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slo w_rsp.649799475 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1614618888 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4417469733 ps |
| CPU time | 96.34 seconds |
| Started | Dec 24 01:14:12 PM PST 23 |
| Finished | Dec 24 01:16:04 PM PST 23 |
| Peak memory | 203868 kb |
| Host | smart-2704d378-3675-40e6-ad97-418d4aa42a23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1614618888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.1614618888 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1010081626 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 114464897544 ps |
| CPU time | 274.25 seconds |
| Started | Dec 24 01:13:39 PM PST 23 |
| Finished | Dec 24 01:18:20 PM PST 23 |
| Peak memory | 202588 kb |
| Host | smart-e73ed2f4-7f47-4141-946f-34567588e107 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1010081626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.1010081626 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.4234140710 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 15915926100 ps |
| CPU time | 246.43 seconds |
| Started | Dec 24 01:12:23 PM PST 23 |
| Finished | Dec 24 01:16:41 PM PST 23 |
| Peak memory | 204352 kb |
| Host | smart-9197642f-f67d-455d-8d8b-599f78a67ba5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4234140710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.4234140710 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1873763405 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 322788266973 ps |
| CPU time | 263.72 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:17:33 PM PST 23 |
| Peak memory | 202704 kb |
| Host | smart-85e2ca31-a117-47b9-8798-0b8c02c780e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1873763405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.1873763405 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3360428642 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 31494369013 ps |
| CPU time | 97.86 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:15:00 PM PST 23 |
| Peak memory | 202548 kb |
| Host | smart-5598910c-b39b-4d11-802d-5e2c5bedc47f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3360428642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3360428642 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.379391859 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 360643933 ps |
| CPU time | 40.3 seconds |
| Started | Dec 24 01:12:49 PM PST 23 |
| Finished | Dec 24 01:13:37 PM PST 23 |
| Peak memory | 203476 kb |
| Host | smart-5b76c841-f0c8-4acf-b287-c576844152f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=379391859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand _reset.379391859 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.97960495 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 187828123 ps |
| CPU time | 14.53 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:30 PM PST 23 |
| Peak memory | 202500 kb |
| Host | smart-4f59b2fc-02d6-4c68-84fd-a483c096e7ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=97960495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_ reset.97960495 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.434382381 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3997684492 ps |
| CPU time | 54.51 seconds |
| Started | Dec 24 01:12:19 PM PST 23 |
| Finished | Dec 24 01:13:26 PM PST 23 |
| Peak memory | 202452 kb |
| Host | smart-bc2fb0c2-8695-4554-9ba0-651456a2b52b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=434382381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.434382381 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2392894066 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 11853833204 ps |
| CPU time | 242.18 seconds |
| Started | Dec 24 01:12:24 PM PST 23 |
| Finished | Dec 24 01:16:38 PM PST 23 |
| Peak memory | 207044 kb |
| Host | smart-42d47717-2a38-48d0-8cee-b200fd9d825f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2392894066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.2392894066 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1149827423 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 106275209521 ps |
| CPU time | 266.91 seconds |
| Started | Dec 24 01:12:51 PM PST 23 |
| Finished | Dec 24 01:17:25 PM PST 23 |
| Peak memory | 202484 kb |
| Host | smart-94ba32d7-ad19-4ac4-bbdc-5995ced88416 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1149827423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1149827423 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1618306590 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 16196711 ps |
| CPU time | 3.6 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:12:41 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-cc8109ab-4c4e-40af-980b-418bdecb6164 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1618306590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1618306590 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2899507390 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 258032554 ps |
| CPU time | 1.69 seconds |
| Started | Dec 24 01:12:04 PM PST 23 |
| Finished | Dec 24 01:12:13 PM PST 23 |
| Peak memory | 201372 kb |
| Host | smart-061975b4-5f43-4608-b1b0-a17040b05e0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2899507390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2899507390 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.2288543187 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 83763104 ps |
| CPU time | 3.48 seconds |
| Started | Dec 24 01:12:14 PM PST 23 |
| Finished | Dec 24 01:12:30 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-a5532dcc-fdae-4f6b-8fab-593de3914764 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2288543187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2288543187 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.2624506595 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 16176358 ps |
| CPU time | 1.95 seconds |
| Started | Dec 24 01:12:21 PM PST 23 |
| Finished | Dec 24 01:12:36 PM PST 23 |
| Peak memory | 201368 kb |
| Host | smart-f4d2a4b3-aaef-4cd1-8333-c867ca4ca2f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2624506595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2624506595 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.10400074 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 65851845378 ps |
| CPU time | 76.91 seconds |
| Started | Dec 24 01:12:10 PM PST 23 |
| Finished | Dec 24 01:13:39 PM PST 23 |
| Peak memory | 201504 kb |
| Host | smart-b9134357-fb4d-4574-8532-c129011dbc89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=10400074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.10400074 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2921652765 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 17520288499 ps |
| CPU time | 78.72 seconds |
| Started | Dec 24 01:12:15 PM PST 23 |
| Finished | Dec 24 01:13:46 PM PST 23 |
| Peak memory | 201520 kb |
| Host | smart-fc9c4316-a4a4-4b71-b75a-2ae794fea768 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2921652765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2921652765 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.275971038 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 132482599 ps |
| CPU time | 7.02 seconds |
| Started | Dec 24 01:12:15 PM PST 23 |
| Finished | Dec 24 01:12:35 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-eadb2141-0ba7-4f4b-b449-3f9c3b638d70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275971038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.275971038 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.3501991242 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 15485578 ps |
| CPU time | 1.21 seconds |
| Started | Dec 24 01:12:18 PM PST 23 |
| Finished | Dec 24 01:12:31 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-ce60afa5-0718-474e-ba2a-4bfb01b53e44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3501991242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3501991242 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.4085882443 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 10438419 ps |
| CPU time | 1.29 seconds |
| Started | Dec 24 01:12:14 PM PST 23 |
| Finished | Dec 24 01:12:28 PM PST 23 |
| Peak memory | 201512 kb |
| Host | smart-0aa5bea3-37fd-4491-8637-b6d8da2c2fcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4085882443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4085882443 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1469666698 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 14095726715 ps |
| CPU time | 10.44 seconds |
| Started | Dec 24 01:12:09 PM PST 23 |
| Finished | Dec 24 01:12:31 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-6b64c479-462c-4a58-a374-04b391940274 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469666698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1469666698 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1503125955 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2740313575 ps |
| CPU time | 10.47 seconds |
| Started | Dec 24 01:12:23 PM PST 23 |
| Finished | Dec 24 01:12:45 PM PST 23 |
| Peak memory | 201332 kb |
| Host | smart-79488473-16e7-42b2-b460-d9d10867d41c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1503125955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1503125955 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3692028808 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 17289560 ps |
| CPU time | 1.04 seconds |
| Started | Dec 24 01:12:07 PM PST 23 |
| Finished | Dec 24 01:12:17 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-c9032386-72fb-4fcf-a8ab-52463a6f51b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692028808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3692028808 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.855698546 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1160855484 ps |
| CPU time | 29.28 seconds |
| Started | Dec 24 01:12:13 PM PST 23 |
| Finished | Dec 24 01:12:55 PM PST 23 |
| Peak memory | 202636 kb |
| Host | smart-c4e2ad10-f12a-4fdc-b274-8ca49d6fd64a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=855698546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.855698546 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2657719453 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4610695857 ps |
| CPU time | 65.12 seconds |
| Started | Dec 24 01:12:07 PM PST 23 |
| Finished | Dec 24 01:13:23 PM PST 23 |
| Peak memory | 201564 kb |
| Host | smart-5b6374e1-b055-4acb-8642-59489d96e1a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2657719453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2657719453 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.2076885202 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 92591190 ps |
| CPU time | 9.7 seconds |
| Started | Dec 24 01:12:12 PM PST 23 |
| Finished | Dec 24 01:12:35 PM PST 23 |
| Peak memory | 201388 kb |
| Host | smart-1b1278bf-369f-4a54-b7f4-9781f1061626 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2076885202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.2076885202 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3552818086 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 14549214 ps |
| CPU time | 3.27 seconds |
| Started | Dec 24 01:12:04 PM PST 23 |
| Finished | Dec 24 01:12:15 PM PST 23 |
| Peak memory | 201296 kb |
| Host | smart-5991e7e9-2595-4162-872d-ffeb94a70e51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3552818086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.3552818086 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3104109358 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 50003386 ps |
| CPU time | 4.79 seconds |
| Started | Dec 24 01:12:08 PM PST 23 |
| Finished | Dec 24 01:12:23 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-26d96c10-23ab-4ce7-9dc2-b6df3212df60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3104109358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3104109358 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2277073597 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 47509390 ps |
| CPU time | 2.05 seconds |
| Started | Dec 24 01:12:07 PM PST 23 |
| Finished | Dec 24 01:12:17 PM PST 23 |
| Peak memory | 201376 kb |
| Host | smart-bdaef7b2-1bef-4a5a-a26d-42bdf5152963 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2277073597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2277073597 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2261826321 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 92770450 ps |
| CPU time | 2.16 seconds |
| Started | Dec 24 01:12:21 PM PST 23 |
| Finished | Dec 24 01:12:35 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-8ca84c35-7ad4-4717-8776-c66b52e80205 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2261826321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2261826321 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.3584707154 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 216833322 ps |
| CPU time | 5.73 seconds |
| Started | Dec 24 01:12:08 PM PST 23 |
| Finished | Dec 24 01:12:24 PM PST 23 |
| Peak memory | 201388 kb |
| Host | smart-82b2f93b-01c2-4011-96f0-7c8ee0cf96db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3584707154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3584707154 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.626328175 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 742074781 ps |
| CPU time | 15.49 seconds |
| Started | Dec 24 01:12:08 PM PST 23 |
| Finished | Dec 24 01:12:34 PM PST 23 |
| Peak memory | 201460 kb |
| Host | smart-467371e3-5e1d-4c5f-918b-075a43432d88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=626328175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.626328175 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.996271403 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 39013912248 ps |
| CPU time | 128.22 seconds |
| Started | Dec 24 01:12:18 PM PST 23 |
| Finished | Dec 24 01:14:39 PM PST 23 |
| Peak memory | 201504 kb |
| Host | smart-45477b56-29c0-4b3d-b274-058cc1da2099 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=996271403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.996271403 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.414467431 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 31597599005 ps |
| CPU time | 102.89 seconds |
| Started | Dec 24 01:12:19 PM PST 23 |
| Finished | Dec 24 01:14:14 PM PST 23 |
| Peak memory | 201568 kb |
| Host | smart-961f0d81-c89c-4612-a071-955f2634c597 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=414467431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.414467431 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3049615945 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 33951638 ps |
| CPU time | 1.87 seconds |
| Started | Dec 24 01:12:04 PM PST 23 |
| Finished | Dec 24 01:12:12 PM PST 23 |
| Peak memory | 201368 kb |
| Host | smart-f93fa8d3-54f8-4f55-8779-99b59de0cda5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049615945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3049615945 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.2106377357 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 452169183 ps |
| CPU time | 4.57 seconds |
| Started | Dec 24 01:12:03 PM PST 23 |
| Finished | Dec 24 01:12:14 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-0622e08e-5e0d-4605-a57b-542b5583544c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2106377357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2106377357 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.3116946053 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 285074863 ps |
| CPU time | 1.42 seconds |
| Started | Dec 24 01:12:07 PM PST 23 |
| Finished | Dec 24 01:12:19 PM PST 23 |
| Peak memory | 201380 kb |
| Host | smart-4607f164-09bd-4d70-aa60-1245bf35b925 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3116946053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3116946053 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3686803976 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 1680058487 ps |
| CPU time | 7.27 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:12:45 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-5c41f94f-429c-41b0-a53c-3aed59eb975a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686803976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3686803976 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3069996932 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3057895680 ps |
| CPU time | 11.23 seconds |
| Started | Dec 24 01:12:09 PM PST 23 |
| Finished | Dec 24 01:12:32 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-962feb57-f3fb-4d1e-ba24-928b9909c3a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3069996932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3069996932 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3007086247 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 10886988 ps |
| CPU time | 1.08 seconds |
| Started | Dec 24 01:12:07 PM PST 23 |
| Finished | Dec 24 01:12:18 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-9c6658cd-70f4-42ca-bdb7-6d94096e06be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007086247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3007086247 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2795141491 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 7216904805 ps |
| CPU time | 94.85 seconds |
| Started | Dec 24 01:12:07 PM PST 23 |
| Finished | Dec 24 01:13:51 PM PST 23 |
| Peak memory | 202484 kb |
| Host | smart-d8a39d40-e387-4c36-b672-8750f4c4def2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2795141491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2795141491 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1336506024 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 153517255 ps |
| CPU time | 11.16 seconds |
| Started | Dec 24 01:12:19 PM PST 23 |
| Finished | Dec 24 01:12:42 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-f7eaad60-b761-4ace-800d-19800751a0d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1336506024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1336506024 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.4196203363 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 155456245 ps |
| CPU time | 29.21 seconds |
| Started | Dec 24 01:12:06 PM PST 23 |
| Finished | Dec 24 01:12:43 PM PST 23 |
| Peak memory | 203532 kb |
| Host | smart-8aaa9962-0876-46ab-9d8b-1d6f13e5a627 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4196203363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.4196203363 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3085342046 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 86538150 ps |
| CPU time | 13.36 seconds |
| Started | Dec 24 01:12:21 PM PST 23 |
| Finished | Dec 24 01:12:52 PM PST 23 |
| Peak memory | 201360 kb |
| Host | smart-08f52e04-6085-4ad6-bc5c-a2c7e611f71f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3085342046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.3085342046 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.990221497 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 25267493 ps |
| CPU time | 1.4 seconds |
| Started | Dec 24 01:11:53 PM PST 23 |
| Finished | Dec 24 01:12:03 PM PST 23 |
| Peak memory | 201296 kb |
| Host | smart-42e70c8b-1c3f-42a6-aa20-8afa4fd80e87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=990221497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.990221497 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1640805603 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 290474300 ps |
| CPU time | 6.21 seconds |
| Started | Dec 24 01:12:34 PM PST 23 |
| Finished | Dec 24 01:12:53 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-689a2329-b350-4b53-aba2-965cee0b8f10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1640805603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1640805603 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2150376558 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 54100863358 ps |
| CPU time | 173.99 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:16:02 PM PST 23 |
| Peak memory | 202592 kb |
| Host | smart-02f13a63-6976-4ed0-8105-1efd8d0a6b67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2150376558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.2150376558 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.4287049186 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 11679369 ps |
| CPU time | 1.27 seconds |
| Started | Dec 24 01:12:21 PM PST 23 |
| Finished | Dec 24 01:12:35 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-44b57fa5-286c-45b4-bef6-2c287b8b191d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4287049186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.4287049186 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.2738987599 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 135458299 ps |
| CPU time | 6.46 seconds |
| Started | Dec 24 01:12:34 PM PST 23 |
| Finished | Dec 24 01:12:54 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-525763a3-2930-413d-98c5-53b4a7221265 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2738987599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2738987599 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.2184449152 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2383199520 ps |
| CPU time | 10.7 seconds |
| Started | Dec 24 01:12:20 PM PST 23 |
| Finished | Dec 24 01:12:43 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-3ea6a7cd-ec55-4df7-b031-e78920336f61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2184449152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2184449152 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3061031511 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 64361275812 ps |
| CPU time | 91.03 seconds |
| Started | Dec 24 01:12:18 PM PST 23 |
| Finished | Dec 24 01:14:01 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-8846fc40-06d7-4e08-81a8-a6e6e04f1c50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061031511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3061031511 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.259343190 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 12746899034 ps |
| CPU time | 87.49 seconds |
| Started | Dec 24 01:12:24 PM PST 23 |
| Finished | Dec 24 01:14:04 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-1addc0d0-73fb-4d00-999b-e45b19c01f72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=259343190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.259343190 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.564064332 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 27696424 ps |
| CPU time | 2.4 seconds |
| Started | Dec 24 01:12:25 PM PST 23 |
| Finished | Dec 24 01:12:39 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-939b6d6c-687e-4390-92fd-af000f2e75ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564064332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.564064332 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.2903492721 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 257838629 ps |
| CPU time | 6.22 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:12:52 PM PST 23 |
| Peak memory | 201376 kb |
| Host | smart-d3a6ecdb-fa28-4fd6-a471-29cc9686b009 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2903492721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2903492721 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.3467849224 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 10345162 ps |
| CPU time | 1.23 seconds |
| Started | Dec 24 01:12:17 PM PST 23 |
| Finished | Dec 24 01:12:31 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-a1f2d39c-bfbc-4037-9d3d-cebe22e15096 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3467849224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3467849224 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2728146482 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 4939376782 ps |
| CPU time | 10.56 seconds |
| Started | Dec 24 01:12:29 PM PST 23 |
| Finished | Dec 24 01:12:52 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-624898f9-4168-4e7d-b726-4fe9c5994f88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728146482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2728146482 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1641154774 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1258257460 ps |
| CPU time | 8.48 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:12:47 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-78e81c5c-f6ce-4f48-a871-ce74485eb324 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1641154774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1641154774 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2146886365 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 8967404 ps |
| CPU time | 1.02 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:12:45 PM PST 23 |
| Peak memory | 201440 kb |
| Host | smart-f660b659-8ec5-4014-896d-ed45714a227f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146886365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2146886365 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.163868964 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 640295167 ps |
| CPU time | 20.75 seconds |
| Started | Dec 24 01:12:21 PM PST 23 |
| Finished | Dec 24 01:12:54 PM PST 23 |
| Peak memory | 201368 kb |
| Host | smart-6af1b485-198f-42e0-944a-b603154ad0de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=163868964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.163868964 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.904214984 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 4566108205 ps |
| CPU time | 54.5 seconds |
| Started | Dec 24 01:12:28 PM PST 23 |
| Finished | Dec 24 01:13:35 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-a06cc88d-de0d-4150-8261-0f91e5dd0313 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=904214984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.904214984 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.178399170 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 3689223001 ps |
| CPU time | 128.18 seconds |
| Started | Dec 24 01:12:30 PM PST 23 |
| Finished | Dec 24 01:14:51 PM PST 23 |
| Peak memory | 203764 kb |
| Host | smart-c6d925eb-0ffb-4a5d-a5a3-7356e9bedcd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=178399170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand _reset.178399170 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1260387720 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 75129043 ps |
| CPU time | 3.67 seconds |
| Started | Dec 24 01:12:46 PM PST 23 |
| Finished | Dec 24 01:12:58 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-f0452def-068d-45f8-8603-fe00be5621c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1260387720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1260387720 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3973194845 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 917112675 ps |
| CPU time | 13.35 seconds |
| Started | Dec 24 01:12:13 PM PST 23 |
| Finished | Dec 24 01:12:40 PM PST 23 |
| Peak memory | 201576 kb |
| Host | smart-11bb9b86-fbe3-49ca-95fe-5cacd97227f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3973194845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3973194845 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1462495964 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 5103217632 ps |
| CPU time | 31.1 seconds |
| Started | Dec 24 01:12:36 PM PST 23 |
| Finished | Dec 24 01:13:20 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-1893e99e-4e5a-4f07-91ee-69cf2b741d02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1462495964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.1462495964 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.848689537 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1550267820 ps |
| CPU time | 13.77 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:12:53 PM PST 23 |
| Peak memory | 201408 kb |
| Host | smart-3116d24f-ebb2-47d7-a6e1-4eb3176ecc4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=848689537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.848689537 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.1838905169 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 66644964 ps |
| CPU time | 6.79 seconds |
| Started | Dec 24 01:12:19 PM PST 23 |
| Finished | Dec 24 01:12:38 PM PST 23 |
| Peak memory | 201420 kb |
| Host | smart-eae1db9c-19d2-4993-a774-9f79ecab0526 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1838905169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1838905169 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.3489252326 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 817058641 ps |
| CPU time | 8.4 seconds |
| Started | Dec 24 01:12:24 PM PST 23 |
| Finished | Dec 24 01:12:44 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-6b321a4e-cfb3-4df2-bddd-a801d02edfd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3489252326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3489252326 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3215258868 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 45103303479 ps |
| CPU time | 181.86 seconds |
| Started | Dec 24 01:12:24 PM PST 23 |
| Finished | Dec 24 01:15:38 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-beee63ac-e01e-43d7-bf6b-b665ef41adf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3215258868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3215258868 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2218423832 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 45358214 ps |
| CPU time | 5.22 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:12:43 PM PST 23 |
| Peak memory | 201352 kb |
| Host | smart-5af71bab-4efc-4fa2-9ad0-c0ce9f8c0566 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218423832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2218423832 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.1126283799 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 23869350 ps |
| CPU time | 1.09 seconds |
| Started | Dec 24 01:12:30 PM PST 23 |
| Finished | Dec 24 01:12:44 PM PST 23 |
| Peak memory | 201392 kb |
| Host | smart-fefa4d92-2426-457c-acb3-6fbc4ef26361 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1126283799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1126283799 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.3381271772 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 11084725 ps |
| CPU time | 1.24 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:12:39 PM PST 23 |
| Peak memory | 201428 kb |
| Host | smart-db0fec9c-eca1-4978-ba2e-acc642775f82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3381271772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3381271772 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1773713735 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1444340446 ps |
| CPU time | 6.19 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:12:44 PM PST 23 |
| Peak memory | 201408 kb |
| Host | smart-920830c5-8ff6-46d4-b802-84700178057d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773713735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1773713735 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.222249874 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 2628340133 ps |
| CPU time | 12.18 seconds |
| Started | Dec 24 01:12:25 PM PST 23 |
| Finished | Dec 24 01:12:49 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-b60e8212-820a-408a-a449-20cbcca2d993 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=222249874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.222249874 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2509143260 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 9991507 ps |
| CPU time | 1.03 seconds |
| Started | Dec 24 01:12:45 PM PST 23 |
| Finished | Dec 24 01:12:55 PM PST 23 |
| Peak memory | 201536 kb |
| Host | smart-f8c0947c-f720-4a69-88db-9c6051206583 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509143260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2509143260 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.158239925 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1415761700 ps |
| CPU time | 14.13 seconds |
| Started | Dec 24 01:12:22 PM PST 23 |
| Finished | Dec 24 01:12:48 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-44d65636-62b4-46bb-b4a9-7e9963035a20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=158239925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.158239925 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2643203887 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 7124139067 ps |
| CPU time | 66.17 seconds |
| Started | Dec 24 01:12:38 PM PST 23 |
| Finished | Dec 24 01:13:57 PM PST 23 |
| Peak memory | 201536 kb |
| Host | smart-137fd59f-5ec0-4d84-a0b5-b9b4323ced48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2643203887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2643203887 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1258033925 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 183617313 ps |
| CPU time | 15.94 seconds |
| Started | Dec 24 01:12:35 PM PST 23 |
| Finished | Dec 24 01:13:05 PM PST 23 |
| Peak memory | 202380 kb |
| Host | smart-e22d7f6d-efb3-4400-81da-4849c41f1d57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1258033925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.1258033925 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1294012044 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 137248044 ps |
| CPU time | 11.16 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:12:55 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-5217ebe7-270e-4a2d-9e5f-33b9a31905de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1294012044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1294012044 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.4013313472 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 11647952 ps |
| CPU time | 1.27 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:12:39 PM PST 23 |
| Peak memory | 201460 kb |
| Host | smart-7fd2aa65-66ff-4b7c-9333-9cb88e27da2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4013313472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.4013313472 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1161484123 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 298339050 ps |
| CPU time | 5.29 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:12:44 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-0d39e945-fb87-4bf4-8897-fa983b0baaab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1161484123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1161484123 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.282750757 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2353576447 ps |
| CPU time | 5.49 seconds |
| Started | Dec 24 01:12:40 PM PST 23 |
| Finished | Dec 24 01:12:57 PM PST 23 |
| Peak memory | 201316 kb |
| Host | smart-1d543f33-19f4-4c8d-8cdf-50e491b2167e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=282750757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.282750757 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.431057826 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1194700682 ps |
| CPU time | 11.13 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:15 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-292c215f-3b1f-4297-b43e-b0f31ef1c7c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=431057826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.431057826 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.3930538875 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 544433171 ps |
| CPU time | 8.39 seconds |
| Started | Dec 24 01:12:38 PM PST 23 |
| Finished | Dec 24 01:12:59 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-860f1ab8-3d65-49cf-9e1e-f9d27be3b145 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3930538875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3930538875 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2916834375 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 59451901175 ps |
| CPU time | 159.78 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:15:24 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-9e9a9f86-ab40-4bef-bdb9-182632f38051 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916834375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2916834375 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3021402836 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5375484376 ps |
| CPU time | 36.23 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:13:15 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-d740c6ed-d3ea-49bc-b9ab-dc755eb2381d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3021402836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3021402836 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.585662949 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 52360017 ps |
| CPU time | 2.94 seconds |
| Started | Dec 24 01:12:21 PM PST 23 |
| Finished | Dec 24 01:12:37 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-43091ce1-6a5d-4977-8a8f-8be2466f60a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585662949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.585662949 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.2021687617 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2278596245 ps |
| CPU time | 8.1 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:12:47 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-24c763a7-de6c-4881-be3e-44039c423df4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2021687617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2021687617 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.2260868887 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 40552659 ps |
| CPU time | 1.4 seconds |
| Started | Dec 24 01:12:30 PM PST 23 |
| Finished | Dec 24 01:12:44 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-f9018355-3f25-461a-8e5c-f301f9c60ef2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2260868887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2260868887 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3445086141 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1754316591 ps |
| CPU time | 5.57 seconds |
| Started | Dec 24 01:12:34 PM PST 23 |
| Finished | Dec 24 01:12:52 PM PST 23 |
| Peak memory | 201300 kb |
| Host | smart-3b514312-b511-440f-9015-767c8b99a757 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445086141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3445086141 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.4038707914 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1168332146 ps |
| CPU time | 8.93 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:12:53 PM PST 23 |
| Peak memory | 201408 kb |
| Host | smart-abf82bf2-dd02-43b7-936c-23dc9860bbe3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4038707914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.4038707914 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.598725648 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 12241107 ps |
| CPU time | 1.27 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:12:40 PM PST 23 |
| Peak memory | 201568 kb |
| Host | smart-d86d0df8-9afb-49e0-84fa-95dc0829fabf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598725648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.598725648 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2294006597 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1852835467 ps |
| CPU time | 12.61 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:26 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-069a252d-fe9c-47e6-915a-4e11cdf4f9db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2294006597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2294006597 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1990740756 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 7522942337 ps |
| CPU time | 69.42 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:14:32 PM PST 23 |
| Peak memory | 201536 kb |
| Host | smart-ed0bbe7e-0251-486a-bb18-23cf121a160d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1990740756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1990740756 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.27004650 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 7211908 ps |
| CPU time | 3.95 seconds |
| Started | Dec 24 01:12:40 PM PST 23 |
| Finished | Dec 24 01:12:55 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-ee9f07b9-2c2a-46a3-b9b3-83c0383373bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=27004650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_ reset.27004650 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3005688725 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 14019404665 ps |
| CPU time | 176.1 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:16:04 PM PST 23 |
| Peak memory | 208612 kb |
| Host | smart-e5ab0a8f-b23f-428c-a157-cfbd487c3e14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3005688725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.3005688725 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1771908016 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 456927608 ps |
| CPU time | 5.47 seconds |
| Started | Dec 24 01:12:52 PM PST 23 |
| Finished | Dec 24 01:13:05 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-a061073a-14c4-4699-87b1-2b18aa0a77a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1771908016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1771908016 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.3608766080 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1152988030 ps |
| CPU time | 23.08 seconds |
| Started | Dec 24 01:12:53 PM PST 23 |
| Finished | Dec 24 01:13:23 PM PST 23 |
| Peak memory | 201436 kb |
| Host | smart-355d5e04-7caa-44ad-8028-4932db3e4baf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3608766080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3608766080 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1766857218 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4049948013 ps |
| CPU time | 20.15 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:13:30 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-2d474b9e-4c7a-4e4b-953a-a369195438e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1766857218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.1766857218 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.3918545863 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 488990230 ps |
| CPU time | 5.1 seconds |
| Started | Dec 24 01:12:38 PM PST 23 |
| Finished | Dec 24 01:12:56 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-2c901483-ae9e-4073-99a2-f7460bf4a090 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3918545863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3918545863 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.2103752168 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 90345129 ps |
| CPU time | 7.85 seconds |
| Started | Dec 24 01:13:09 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201460 kb |
| Host | smart-3e4a22c5-f481-4986-bde1-7ee970c945c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2103752168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2103752168 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.3107882381 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 27687768 ps |
| CPU time | 3.14 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:12:49 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-71f55bc2-bac0-4949-844b-57827d49d3ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3107882381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3107882381 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2029442876 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 26927089804 ps |
| CPU time | 62.46 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-e17b18ed-ebbb-4aeb-a9b2-879bfcc5a91b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029442876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2029442876 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.843162612 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 42898803462 ps |
| CPU time | 205.22 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:16:47 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-09ea187a-d857-493e-9149-0072e29dded9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=843162612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.843162612 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.2466884591 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 205203498 ps |
| CPU time | 3.29 seconds |
| Started | Dec 24 01:12:45 PM PST 23 |
| Finished | Dec 24 01:12:57 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-2dc092a4-dc2e-47e9-a661-43437c266fda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466884591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2466884591 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.894574665 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 127242491 ps |
| CPU time | 2 seconds |
| Started | Dec 24 01:12:37 PM PST 23 |
| Finished | Dec 24 01:12:51 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-61db2163-9d5b-40e5-9a09-93a458b8b4ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=894574665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.894574665 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.2319680007 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 46237740 ps |
| CPU time | 1.3 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:12:47 PM PST 23 |
| Peak memory | 201380 kb |
| Host | smart-c780b93b-2295-4145-8a5f-3cb857b581e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2319680007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2319680007 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1525906803 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2462988121 ps |
| CPU time | 7.72 seconds |
| Started | Dec 24 01:12:39 PM PST 23 |
| Finished | Dec 24 01:12:59 PM PST 23 |
| Peak memory | 201612 kb |
| Host | smart-88768541-25d6-4723-b329-83e357ddfa6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525906803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1525906803 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.4181875403 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 1054931162 ps |
| CPU time | 9 seconds |
| Started | Dec 24 01:12:37 PM PST 23 |
| Finished | Dec 24 01:12:58 PM PST 23 |
| Peak memory | 201320 kb |
| Host | smart-c20da150-6b56-424c-b756-4f87bb627a07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4181875403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.4181875403 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3230030390 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 11166061 ps |
| CPU time | 1.27 seconds |
| Started | Dec 24 01:12:44 PM PST 23 |
| Finished | Dec 24 01:12:54 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-9fa3d3d6-47bd-4153-bf84-2f47ac5c2486 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230030390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3230030390 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.599793794 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 138901921 ps |
| CPU time | 3.76 seconds |
| Started | Dec 24 01:12:35 PM PST 23 |
| Finished | Dec 24 01:12:52 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-ee79cc0d-e539-4992-a1dd-1ac1a969e576 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=599793794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.599793794 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.4129343143 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1134394238 ps |
| CPU time | 18.73 seconds |
| Started | Dec 24 01:12:37 PM PST 23 |
| Finished | Dec 24 01:13:08 PM PST 23 |
| Peak memory | 201296 kb |
| Host | smart-79f7a4f4-494b-478e-affc-f4a85a1ebd71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4129343143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4129343143 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1962039876 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 11447774345 ps |
| CPU time | 102.68 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:14:28 PM PST 23 |
| Peak memory | 204056 kb |
| Host | smart-569245d5-c5d6-4ed4-bc62-15a7f1135857 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1962039876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.1962039876 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.4168989167 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 523900076 ps |
| CPU time | 55.51 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:14:02 PM PST 23 |
| Peak memory | 203548 kb |
| Host | smart-ba33a366-76de-4dda-ae03-07dab3289ec7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4168989167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.4168989167 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.812934493 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 32378237 ps |
| CPU time | 2 seconds |
| Started | Dec 24 01:12:43 PM PST 23 |
| Finished | Dec 24 01:12:55 PM PST 23 |
| Peak memory | 201392 kb |
| Host | smart-4e964612-0fe7-4f38-a77d-432441941067 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=812934493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.812934493 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2682397053 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 20987322 ps |
| CPU time | 3.46 seconds |
| Started | Dec 24 01:12:32 PM PST 23 |
| Finished | Dec 24 01:12:48 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-396c0be4-3df9-4341-8b67-36b24253f991 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2682397053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2682397053 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.4102396280 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1428329534 ps |
| CPU time | 11.12 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:15 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-b78772e9-9efe-4f67-be12-1975ce6ae7dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4102396280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.4102396280 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.183205600 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 178275027 ps |
| CPU time | 1.78 seconds |
| Started | Dec 24 01:12:30 PM PST 23 |
| Finished | Dec 24 01:12:44 PM PST 23 |
| Peak memory | 201364 kb |
| Host | smart-4523778f-202c-4f68-bc2f-382cb248b4e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=183205600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.183205600 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.1309902332 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 22155430 ps |
| CPU time | 1.71 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:24 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-c4fd8adc-8a21-44af-939d-7eb36fdb6130 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1309902332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1309902332 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3589888809 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 9100641879 ps |
| CPU time | 29.26 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-697db5a6-1c28-48c4-9839-a9bbb2047b17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589888809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3589888809 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.11181346 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 14658502724 ps |
| CPU time | 84.09 seconds |
| Started | Dec 24 01:12:50 PM PST 23 |
| Finished | Dec 24 01:14:21 PM PST 23 |
| Peak memory | 201584 kb |
| Host | smart-e6dcc3c2-a43f-4573-9b68-6974176f0aa6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=11181346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.11181346 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2849629056 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 94334342 ps |
| CPU time | 4.37 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:13:13 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-c92c5c6e-d53e-4dc4-bc97-e68b5f51e278 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849629056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2849629056 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.683891122 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1389933579 ps |
| CPU time | 12.99 seconds |
| Started | Dec 24 01:12:39 PM PST 23 |
| Finished | Dec 24 01:13:04 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-b5c03cb4-438c-429c-bebe-1b78ed5ddf66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=683891122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.683891122 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.3145710499 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 468128589 ps |
| CPU time | 1.63 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:08 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-289dd3f9-5820-4c88-ab91-dec62630e068 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3145710499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3145710499 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.334292539 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3582399300 ps |
| CPU time | 10.84 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:12:57 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-67b7f87b-67be-42a4-97a1-513502cc24de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=334292539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.334292539 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3319041166 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 8380268972 ps |
| CPU time | 13.77 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:29 PM PST 23 |
| Peak memory | 201544 kb |
| Host | smart-8e60a9b2-1001-45cb-83cd-8241adaf8fb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3319041166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3319041166 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3955126306 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 12063720 ps |
| CPU time | 1.21 seconds |
| Started | Dec 24 01:12:52 PM PST 23 |
| Finished | Dec 24 01:13:01 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-3c7c5304-e368-4c82-9187-e974a95db0e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955126306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3955126306 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.246233694 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2664508132 ps |
| CPU time | 32.74 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:13:43 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-e470f982-41e1-4569-b3c3-e87157e5f59e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=246233694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.246233694 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.355028329 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 4189534444 ps |
| CPU time | 143.95 seconds |
| Started | Dec 24 01:12:52 PM PST 23 |
| Finished | Dec 24 01:15:24 PM PST 23 |
| Peak memory | 206796 kb |
| Host | smart-a7bdd0b5-eb03-4afc-997f-80451bc16f90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=355028329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand _reset.355028329 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3044632394 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 7455561881 ps |
| CPU time | 80.08 seconds |
| Started | Dec 24 01:12:35 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 204256 kb |
| Host | smart-127fb532-21a8-4979-a5de-e996e4f3f468 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3044632394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.3044632394 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.4220078003 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 229612672 ps |
| CPU time | 7.5 seconds |
| Started | Dec 24 01:12:39 PM PST 23 |
| Finished | Dec 24 01:12:58 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-727d122a-8945-48d5-9f37-f2fe5ded6a6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4220078003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.4220078003 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.500172848 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1586792627 ps |
| CPU time | 20.45 seconds |
| Started | Dec 24 01:12:38 PM PST 23 |
| Finished | Dec 24 01:13:11 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-409d2756-bb3f-456e-aa7c-0a0c6bae21ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=500172848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.500172848 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3789379370 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 440413711 ps |
| CPU time | 7.59 seconds |
| Started | Dec 24 01:12:54 PM PST 23 |
| Finished | Dec 24 01:13:10 PM PST 23 |
| Peak memory | 201436 kb |
| Host | smart-d564f9e4-b5c5-45e9-9e69-4b57359d20c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3789379370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3789379370 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2466637900 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 35118721 ps |
| CPU time | 1.53 seconds |
| Started | Dec 24 01:13:02 PM PST 23 |
| Finished | Dec 24 01:13:19 PM PST 23 |
| Peak memory | 201424 kb |
| Host | smart-52242e0f-4a85-48ae-a5db-d537a91ba807 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2466637900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2466637900 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.2357852627 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 692864147 ps |
| CPU time | 6.78 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:12:53 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-ee7de0bb-3828-490e-9b38-94096f60443d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2357852627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2357852627 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1970673989 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 25882652755 ps |
| CPU time | 114.24 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:15:02 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-7ac233de-5747-4ddc-9be0-c32f20f6a802 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970673989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1970673989 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1023770123 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 34960278731 ps |
| CPU time | 54.58 seconds |
| Started | Dec 24 01:12:53 PM PST 23 |
| Finished | Dec 24 01:13:55 PM PST 23 |
| Peak memory | 201572 kb |
| Host | smart-99340fe4-d1c9-44a3-afea-6ec8a1a9b29b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1023770123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1023770123 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1442989208 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 96736442 ps |
| CPU time | 5.68 seconds |
| Started | Dec 24 01:12:54 PM PST 23 |
| Finished | Dec 24 01:13:08 PM PST 23 |
| Peak memory | 201408 kb |
| Host | smart-36939010-48e9-4e72-8965-3b21dd938c70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442989208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1442989208 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.2838219432 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 108033010 ps |
| CPU time | 4.92 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201388 kb |
| Host | smart-d2221f6b-423a-4f56-84c3-c8d85f4a06fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2838219432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2838219432 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.1428457621 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 64578235 ps |
| CPU time | 1.6 seconds |
| Started | Dec 24 01:12:30 PM PST 23 |
| Finished | Dec 24 01:12:44 PM PST 23 |
| Peak memory | 201460 kb |
| Host | smart-c8d28b00-113f-47be-bfe8-2eafc3e674e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1428457621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1428457621 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3441362481 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1899421502 ps |
| CPU time | 10.13 seconds |
| Started | Dec 24 01:12:32 PM PST 23 |
| Finished | Dec 24 01:12:55 PM PST 23 |
| Peak memory | 201508 kb |
| Host | smart-daa4b647-4741-4c08-9d76-366bed340f89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441362481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3441362481 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.544766450 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 907832487 ps |
| CPU time | 7.06 seconds |
| Started | Dec 24 01:12:35 PM PST 23 |
| Finished | Dec 24 01:12:55 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-48ec8e33-9eb0-4240-9c03-f65287920556 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=544766450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.544766450 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.4030588595 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 22132801 ps |
| CPU time | 1.03 seconds |
| Started | Dec 24 01:12:28 PM PST 23 |
| Finished | Dec 24 01:12:42 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-33ce6477-01ec-48be-885c-0d71d3956c55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030588595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.4030588595 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.843717735 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2600687753 ps |
| CPU time | 22.9 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:30 PM PST 23 |
| Peak memory | 201260 kb |
| Host | smart-d69f3441-b375-45a7-b8d0-f40e128713b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=843717735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.843717735 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2025668446 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 6524679408 ps |
| CPU time | 84.73 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:14:28 PM PST 23 |
| Peak memory | 202524 kb |
| Host | smart-146755d4-670f-4d6e-9f09-ba7e6122a6e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2025668446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2025668446 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1951904280 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 3523186712 ps |
| CPU time | 89.26 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:14:38 PM PST 23 |
| Peak memory | 204100 kb |
| Host | smart-bf17d54d-05f9-4a2c-b9e0-b307599c9795 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1951904280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.1951904280 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.353485249 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 120247405 ps |
| CPU time | 1.46 seconds |
| Started | Dec 24 01:12:34 PM PST 23 |
| Finished | Dec 24 01:12:48 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-dbe744c0-504b-44e5-8906-c50de57c3697 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=353485249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.353485249 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1684050201 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 833018839 ps |
| CPU time | 15.11 seconds |
| Started | Dec 24 01:12:46 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-a6789f90-ecc0-4889-b382-3cffa0fbf5b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1684050201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1684050201 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.4145195360 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 538847497 ps |
| CPU time | 4 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:12 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-eae62fe5-b219-4be3-8713-d902edc2c7cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4145195360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.4145195360 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.2422892924 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 397906794 ps |
| CPU time | 5.58 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:13:10 PM PST 23 |
| Peak memory | 201320 kb |
| Host | smart-252cabf2-3d4e-4a41-adca-7ef7a1202cb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2422892924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2422892924 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.1364804280 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1098682903 ps |
| CPU time | 12.31 seconds |
| Started | Dec 24 01:12:51 PM PST 23 |
| Finished | Dec 24 01:13:10 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-280b8888-7736-45aa-977a-5100847b71ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1364804280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1364804280 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3090524640 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 22447186097 ps |
| CPU time | 100.14 seconds |
| Started | Dec 24 01:12:45 PM PST 23 |
| Finished | Dec 24 01:14:34 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-074ae280-30eb-4ab4-a307-54f459ca395f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090524640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3090524640 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1252478506 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 36684747797 ps |
| CPU time | 66.28 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:14:18 PM PST 23 |
| Peak memory | 201512 kb |
| Host | smart-ab707761-d415-42ab-90e4-514c5367d5a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1252478506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1252478506 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.2983872713 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 338492143 ps |
| CPU time | 7.52 seconds |
| Started | Dec 24 01:12:50 PM PST 23 |
| Finished | Dec 24 01:13:05 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-02f65df8-b76f-4a76-ac6a-6fc33e6ff5e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983872713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2983872713 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.1011561872 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 113716177 ps |
| CPU time | 1.56 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-dbfdc839-ca9f-4f29-8def-2386b6927593 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1011561872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1011561872 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.2797542355 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 64951073 ps |
| CPU time | 1.29 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-e587d3ef-7e51-4bd3-ace5-acf41dbfbce9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2797542355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2797542355 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.632396383 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 3318643964 ps |
| CPU time | 9.2 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:12 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-6642a5d5-e6aa-4eb5-aac9-40b5d60dfdf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=632396383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.632396383 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.3623798501 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1765701923 ps |
| CPU time | 8.41 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:35 PM PST 23 |
| Peak memory | 201384 kb |
| Host | smart-9c8c6a38-f301-4d33-9abe-2aa799a4f3be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3623798501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3623798501 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.4275293609 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 9117197 ps |
| CPU time | 1.18 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:08 PM PST 23 |
| Peak memory | 201224 kb |
| Host | smart-006f3ec8-541c-465b-96fc-2038c6c87059 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275293609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.4275293609 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.904436668 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1829156628 ps |
| CPU time | 33.05 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:13:37 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-11332078-0f03-49a9-bf1e-0c08e80001a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=904436668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.904436668 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2396077213 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2742943587 ps |
| CPU time | 23.42 seconds |
| Started | Dec 24 01:13:01 PM PST 23 |
| Finished | Dec 24 01:13:40 PM PST 23 |
| Peak memory | 201568 kb |
| Host | smart-ed92ac69-36f9-4908-b304-e2ca6cd82e59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2396077213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2396077213 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.2662031489 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 287754616 ps |
| CPU time | 30.19 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 203436 kb |
| Host | smart-b171576e-8f65-4113-a1c1-ec782ec8c377 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2662031489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.2662031489 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3025755550 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 387347970 ps |
| CPU time | 49 seconds |
| Started | Dec 24 01:12:47 PM PST 23 |
| Finished | Dec 24 01:13:43 PM PST 23 |
| Peak memory | 203756 kb |
| Host | smart-7b9c6ef3-7be1-4e8c-abd0-f74143e149f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3025755550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.3025755550 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.78518311 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1304819588 ps |
| CPU time | 7.35 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:10 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-964a1ed8-55d7-42cd-af58-aec60975f93d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=78518311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.78518311 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3976793797 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 136660295 ps |
| CPU time | 7.14 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:12:53 PM PST 23 |
| Peak memory | 201384 kb |
| Host | smart-cca8f275-4530-4c4b-a3a7-a8f1ff7bca9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3976793797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3976793797 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1141217213 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 37951465813 ps |
| CPU time | 171.41 seconds |
| Started | Dec 24 01:12:52 PM PST 23 |
| Finished | Dec 24 01:15:51 PM PST 23 |
| Peak memory | 202504 kb |
| Host | smart-f8dae6f8-893e-4834-b991-3a61a730a236 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1141217213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.1141217213 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.418046729 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 194286788 ps |
| CPU time | 2.88 seconds |
| Started | Dec 24 01:12:43 PM PST 23 |
| Finished | Dec 24 01:12:56 PM PST 23 |
| Peak memory | 201280 kb |
| Host | smart-a2701d0f-cf29-4b16-a71b-a2fd27eb470b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=418046729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.418046729 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.1084125375 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1535970440 ps |
| CPU time | 10.69 seconds |
| Started | Dec 24 01:13:01 PM PST 23 |
| Finished | Dec 24 01:13:27 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-e5bc31f8-dc9c-4965-808d-04a5f9451354 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1084125375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1084125375 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.1188280865 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 95099204 ps |
| CPU time | 5.45 seconds |
| Started | Dec 24 01:12:51 PM PST 23 |
| Finished | Dec 24 01:13:03 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-02c7bbb7-2ba6-4787-90dd-43731ecf7d7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1188280865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1188280865 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.2074931926 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 4841824565 ps |
| CPU time | 24.36 seconds |
| Started | Dec 24 01:13:08 PM PST 23 |
| Finished | Dec 24 01:13:47 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-e32227f7-8d32-43fb-b5ad-e25be35ab750 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074931926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2074931926 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2608903855 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 16169978996 ps |
| CPU time | 30.39 seconds |
| Started | Dec 24 01:12:38 PM PST 23 |
| Finished | Dec 24 01:13:21 PM PST 23 |
| Peak memory | 201536 kb |
| Host | smart-58014af8-2c52-43bd-b672-448df75850c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2608903855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2608903855 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3874618080 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 72716482 ps |
| CPU time | 6.3 seconds |
| Started | Dec 24 01:12:42 PM PST 23 |
| Finished | Dec 24 01:12:59 PM PST 23 |
| Peak memory | 201304 kb |
| Host | smart-10272927-075b-458c-91f7-5aa65448ba55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874618080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3874618080 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.472784232 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 263984430 ps |
| CPU time | 3.63 seconds |
| Started | Dec 24 01:12:39 PM PST 23 |
| Finished | Dec 24 01:12:54 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-e9f75ff6-87bd-4f89-9545-4358154519e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=472784232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.472784232 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.747423006 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 9064630 ps |
| CPU time | 1.33 seconds |
| Started | Dec 24 01:13:08 PM PST 23 |
| Finished | Dec 24 01:13:24 PM PST 23 |
| Peak memory | 201388 kb |
| Host | smart-5f336b60-4220-4380-8a62-762f3b687846 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=747423006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.747423006 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2631991847 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 9159065368 ps |
| CPU time | 11.52 seconds |
| Started | Dec 24 01:13:01 PM PST 23 |
| Finished | Dec 24 01:13:27 PM PST 23 |
| Peak memory | 201388 kb |
| Host | smart-b97affe2-8ff9-46e1-a946-b9d84c87e724 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631991847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2631991847 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.4050986309 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1134895004 ps |
| CPU time | 6.4 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201416 kb |
| Host | smart-97bd6ac1-b49c-48e7-9eee-ddb8ffab8075 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4050986309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.4050986309 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3761029009 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 8336114 ps |
| CPU time | 1.04 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:13 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-36389318-a382-4c95-b056-ee24e366b88b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761029009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3761029009 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.2693960315 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 161789603 ps |
| CPU time | 16.89 seconds |
| Started | Dec 24 01:12:34 PM PST 23 |
| Finished | Dec 24 01:13:05 PM PST 23 |
| Peak memory | 201436 kb |
| Host | smart-f1d53c40-e475-497b-bac1-1c272639322a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2693960315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2693960315 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.4148813145 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 4130036926 ps |
| CPU time | 63.1 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:14:10 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-e9b16477-c867-4dfa-90dd-b6be4f24d958 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4148813145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.4148813145 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.4040170837 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 477781557 ps |
| CPU time | 57.29 seconds |
| Started | Dec 24 01:13:08 PM PST 23 |
| Finished | Dec 24 01:14:21 PM PST 23 |
| Peak memory | 203508 kb |
| Host | smart-e9e8a789-53f1-40e5-b9c6-69e3a1ebba1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4040170837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.4040170837 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3952313284 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 10640167955 ps |
| CPU time | 93.81 seconds |
| Started | Dec 24 01:12:29 PM PST 23 |
| Finished | Dec 24 01:14:16 PM PST 23 |
| Peak memory | 204416 kb |
| Host | smart-9aa07dd7-323b-48a4-88de-ec597ac2c326 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3952313284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.3952313284 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2895994218 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 322346086 ps |
| CPU time | 3.34 seconds |
| Started | Dec 24 01:12:53 PM PST 23 |
| Finished | Dec 24 01:13:03 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-5acab940-1a81-4f7e-b3d3-bb67a0f286bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2895994218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2895994218 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.4254894945 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 960104927 ps |
| CPU time | 20.94 seconds |
| Started | Dec 24 01:12:32 PM PST 23 |
| Finished | Dec 24 01:13:05 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-c5143311-6857-4b35-8474-0c4a6891d9e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4254894945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.4254894945 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2451545887 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4344309510 ps |
| CPU time | 34 seconds |
| Started | Dec 24 01:12:32 PM PST 23 |
| Finished | Dec 24 01:13:18 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-742881e5-883d-4855-a0c4-cc600c3226b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2451545887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.2451545887 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3644545299 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1347672729 ps |
| CPU time | 9.75 seconds |
| Started | Dec 24 01:12:49 PM PST 23 |
| Finished | Dec 24 01:13:06 PM PST 23 |
| Peak memory | 201460 kb |
| Host | smart-0c2446ab-f2a9-4670-9e15-42bbf26bf107 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3644545299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3644545299 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.3394792627 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1339650724 ps |
| CPU time | 11.5 seconds |
| Started | Dec 24 01:12:40 PM PST 23 |
| Finished | Dec 24 01:13:03 PM PST 23 |
| Peak memory | 201392 kb |
| Host | smart-067f6fe0-148f-4cf6-bfee-ec81ebb6f4bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3394792627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3394792627 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.692191146 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 510646259 ps |
| CPU time | 7.65 seconds |
| Started | Dec 24 01:12:44 PM PST 23 |
| Finished | Dec 24 01:13:01 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-97f9bf15-ccf5-4d82-ad64-d9174b142104 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=692191146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.692191146 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.3400554915 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 3219214656 ps |
| CPU time | 16.33 seconds |
| Started | Dec 24 01:12:43 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-ea8ced91-112f-4d15-bf62-275fbc0c6ea8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400554915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3400554915 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.416020255 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 17222012322 ps |
| CPU time | 103.91 seconds |
| Started | Dec 24 01:12:32 PM PST 23 |
| Finished | Dec 24 01:14:29 PM PST 23 |
| Peak memory | 201520 kb |
| Host | smart-8b9586a8-b456-4928-9931-2bcdbb12b137 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=416020255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.416020255 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3246211595 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 55577889 ps |
| CPU time | 5.89 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-626ec9ef-55ca-426d-8101-0ec980a30153 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246211595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3246211595 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.4994439 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 59439890 ps |
| CPU time | 3.89 seconds |
| Started | Dec 24 01:12:40 PM PST 23 |
| Finished | Dec 24 01:12:55 PM PST 23 |
| Peak memory | 201240 kb |
| Host | smart-31e5a834-1d13-44c0-bd55-04ef7deef173 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4994439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.4994439 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.601566067 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 8386691 ps |
| CPU time | 1.08 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:13:05 PM PST 23 |
| Peak memory | 201504 kb |
| Host | smart-74460f10-8c46-4f23-ae0a-d4ac0bd4f837 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=601566067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.601566067 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2007095063 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 5139224816 ps |
| CPU time | 8.76 seconds |
| Started | Dec 24 01:12:42 PM PST 23 |
| Finished | Dec 24 01:13:01 PM PST 23 |
| Peak memory | 201532 kb |
| Host | smart-fef27f27-59de-42e3-9efe-77752883862e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007095063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2007095063 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2859933401 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1932041851 ps |
| CPU time | 7.1 seconds |
| Started | Dec 24 01:12:29 PM PST 23 |
| Finished | Dec 24 01:12:48 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-36c2313e-fd09-4095-9614-0479d252c680 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2859933401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2859933401 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.2134113985 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 12566836 ps |
| CPU time | 1.31 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:23 PM PST 23 |
| Peak memory | 201324 kb |
| Host | smart-f1be6096-f7eb-4ce0-ae54-05da61f0d7a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134113985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.2134113985 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.863680145 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 83962984 ps |
| CPU time | 6.26 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:14 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-52216e4a-2ec3-420f-af7a-1c2362b72275 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=863680145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.863680145 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2751697533 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 693455980 ps |
| CPU time | 13.46 seconds |
| Started | Dec 24 01:12:54 PM PST 23 |
| Finished | Dec 24 01:13:15 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-a06180bb-65c9-434d-8f3c-689da7190218 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2751697533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2751697533 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2413330831 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2984027225 ps |
| CPU time | 45.04 seconds |
| Started | Dec 24 01:12:40 PM PST 23 |
| Finished | Dec 24 01:13:36 PM PST 23 |
| Peak memory | 203508 kb |
| Host | smart-94bd4d41-1c8d-4707-8ec3-159db8f9edaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2413330831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.2413330831 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3494661550 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 187121789 ps |
| CPU time | 7.42 seconds |
| Started | Dec 24 01:12:37 PM PST 23 |
| Finished | Dec 24 01:12:57 PM PST 23 |
| Peak memory | 201380 kb |
| Host | smart-69d22eb9-02e2-4492-a83d-2ec9a230d959 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3494661550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.3494661550 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3926542401 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 597432703 ps |
| CPU time | 9.15 seconds |
| Started | Dec 24 01:12:32 PM PST 23 |
| Finished | Dec 24 01:12:54 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-927dbbe7-a3b4-45b3-bb80-bc153ede3502 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3926542401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3926542401 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.863556731 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 118160224 ps |
| CPU time | 2.53 seconds |
| Started | Dec 24 01:12:39 PM PST 23 |
| Finished | Dec 24 01:12:54 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-c264679c-6233-4ba1-b8cc-47b64bfa6679 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=863556731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.863556731 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.2537538928 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 59899406678 ps |
| CPU time | 276.6 seconds |
| Started | Dec 24 01:12:32 PM PST 23 |
| Finished | Dec 24 01:17:22 PM PST 23 |
| Peak memory | 202552 kb |
| Host | smart-7589a2c1-1911-4599-842e-ac88f05ab455 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2537538928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.2537538928 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3575532830 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 416387987 ps |
| CPU time | 6.73 seconds |
| Started | Dec 24 01:12:52 PM PST 23 |
| Finished | Dec 24 01:13:07 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-33717e27-cfb6-4e0f-a80c-4deab04f1e58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3575532830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3575532830 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.1317752306 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3880482079 ps |
| CPU time | 10.41 seconds |
| Started | Dec 24 01:12:45 PM PST 23 |
| Finished | Dec 24 01:13:04 PM PST 23 |
| Peak memory | 201644 kb |
| Host | smart-04117f82-d5c3-4060-b88a-bdd57e66fffd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1317752306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1317752306 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.1118699404 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 53507210 ps |
| CPU time | 4.69 seconds |
| Started | Dec 24 01:12:38 PM PST 23 |
| Finished | Dec 24 01:12:55 PM PST 23 |
| Peak memory | 201376 kb |
| Host | smart-6ad014ec-de71-492f-9fda-19b302874121 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1118699404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1118699404 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.749726483 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 23908359585 ps |
| CPU time | 37.14 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:13:15 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-d2153ce9-b2a2-4c2b-95aa-3614865e8253 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=749726483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.749726483 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.4136207750 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 93404103421 ps |
| CPU time | 92.75 seconds |
| Started | Dec 24 01:12:41 PM PST 23 |
| Finished | Dec 24 01:14:25 PM PST 23 |
| Peak memory | 201576 kb |
| Host | smart-a8f06268-2312-4483-be5c-69c0c0311aaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4136207750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.4136207750 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.2994750442 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 48494386 ps |
| CPU time | 2.88 seconds |
| Started | Dec 24 01:12:34 PM PST 23 |
| Finished | Dec 24 01:12:50 PM PST 23 |
| Peak memory | 201436 kb |
| Host | smart-82605253-ef02-4f17-b253-e7ccdbc36402 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994750442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2994750442 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.762234577 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 29818544 ps |
| CPU time | 2.42 seconds |
| Started | Dec 24 01:12:36 PM PST 23 |
| Finished | Dec 24 01:12:51 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-f925122a-0d87-46af-90d4-2593dc3f0fea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=762234577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.762234577 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.4268609105 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 65069196 ps |
| CPU time | 1.5 seconds |
| Started | Dec 24 01:12:39 PM PST 23 |
| Finished | Dec 24 01:12:52 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-42ebf969-2854-46e1-94bc-f731d6924db3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4268609105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.4268609105 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2290210468 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3450582289 ps |
| CPU time | 10.27 seconds |
| Started | Dec 24 01:12:48 PM PST 23 |
| Finished | Dec 24 01:13:05 PM PST 23 |
| Peak memory | 201532 kb |
| Host | smart-535ae609-bcc1-4660-993c-2823328b01f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290210468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2290210468 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2798670484 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 9013886622 ps |
| CPU time | 12.53 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:12:57 PM PST 23 |
| Peak memory | 201512 kb |
| Host | smart-b2a46ae6-9d5b-450c-8f1a-aaf3f82f46d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2798670484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2798670484 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.131423920 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 34751761 ps |
| CPU time | 1.22 seconds |
| Started | Dec 24 01:12:54 PM PST 23 |
| Finished | Dec 24 01:13:03 PM PST 23 |
| Peak memory | 201436 kb |
| Host | smart-f5b2df09-e736-4242-92eb-97997e100dba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131423920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.131423920 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.3962123787 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 297227481 ps |
| CPU time | 22.4 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:26 PM PST 23 |
| Peak memory | 202496 kb |
| Host | smart-f0e94663-5725-4468-9f8e-7383499f1259 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3962123787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3962123787 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2710875976 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1393386656 ps |
| CPU time | 16.65 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:13:01 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-f6c63d1d-7359-4f1d-a4b3-5c327f18d748 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2710875976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2710875976 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1234169119 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 234173541 ps |
| CPU time | 48.74 seconds |
| Started | Dec 24 01:12:35 PM PST 23 |
| Finished | Dec 24 01:13:37 PM PST 23 |
| Peak memory | 204672 kb |
| Host | smart-8f48ea72-4271-4798-b239-ad19e4dccfd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1234169119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.1234169119 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.383157977 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10111941 ps |
| CPU time | 1.02 seconds |
| Started | Dec 24 01:12:30 PM PST 23 |
| Finished | Dec 24 01:12:43 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-4995dde4-d526-4483-897f-86832c42a555 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=383157977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.383157977 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3484190656 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 57426561 ps |
| CPU time | 9.8 seconds |
| Started | Dec 24 01:12:12 PM PST 23 |
| Finished | Dec 24 01:12:35 PM PST 23 |
| Peak memory | 201376 kb |
| Host | smart-9b5d9da6-6dd5-41c9-8740-a4385b85f978 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3484190656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3484190656 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2913954151 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1052306762 ps |
| CPU time | 6.2 seconds |
| Started | Dec 24 01:12:15 PM PST 23 |
| Finished | Dec 24 01:12:34 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-47a69769-e6ef-4d5e-ba8d-45036381f979 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2913954151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2913954151 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.3228676003 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 57577633 ps |
| CPU time | 1.39 seconds |
| Started | Dec 24 01:12:23 PM PST 23 |
| Finished | Dec 24 01:12:36 PM PST 23 |
| Peak memory | 201256 kb |
| Host | smart-04990cdf-6fcc-4a93-ad42-c946f679a571 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3228676003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3228676003 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.1802099124 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 51551966 ps |
| CPU time | 1.37 seconds |
| Started | Dec 24 01:12:16 PM PST 23 |
| Finished | Dec 24 01:12:30 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-396696d1-2174-475e-a6ef-f55aa88c3ae7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1802099124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1802099124 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.951035972 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 18177098032 ps |
| CPU time | 65.22 seconds |
| Started | Dec 24 01:12:11 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201616 kb |
| Host | smart-3c12dc1c-67ad-4eae-9e60-c2512047e346 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=951035972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.951035972 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.593696326 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 14193203620 ps |
| CPU time | 56.24 seconds |
| Started | Dec 24 01:12:04 PM PST 23 |
| Finished | Dec 24 01:13:08 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-eb9a3fd6-df89-44bb-a2bd-9eeb7b8f03d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=593696326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.593696326 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.794873298 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 24474880 ps |
| CPU time | 2.97 seconds |
| Started | Dec 24 01:12:00 PM PST 23 |
| Finished | Dec 24 01:12:10 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-4e4400ee-8411-48da-ba60-087aa9fdb0b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794873298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.794873298 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.119189785 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 46893626 ps |
| CPU time | 3.81 seconds |
| Started | Dec 24 01:12:09 PM PST 23 |
| Finished | Dec 24 01:12:24 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-53f7bcfa-078e-40b1-a4c1-93717ff17f1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=119189785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.119189785 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.1902455321 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 209353900 ps |
| CPU time | 1.48 seconds |
| Started | Dec 24 01:12:19 PM PST 23 |
| Finished | Dec 24 01:12:33 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-39df99f8-bfd3-4147-94fb-4636552c7064 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1902455321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1902455321 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2484062775 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 8104769547 ps |
| CPU time | 10.84 seconds |
| Started | Dec 24 01:12:28 PM PST 23 |
| Finished | Dec 24 01:12:51 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-b6c64f2e-c634-4d09-b4a4-10e237a6c8e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484062775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2484062775 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3268238069 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1286044163 ps |
| CPU time | 7.66 seconds |
| Started | Dec 24 01:12:24 PM PST 23 |
| Finished | Dec 24 01:12:44 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-e1411010-15a6-442b-ada9-5514f915bebf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3268238069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3268238069 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3409746416 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 9384914 ps |
| CPU time | 1.19 seconds |
| Started | Dec 24 01:12:08 PM PST 23 |
| Finished | Dec 24 01:12:19 PM PST 23 |
| Peak memory | 201368 kb |
| Host | smart-3b460b25-3048-4141-90a9-e15654b9237e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409746416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3409746416 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.815498814 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 3458744933 ps |
| CPU time | 17.52 seconds |
| Started | Dec 24 01:12:09 PM PST 23 |
| Finished | Dec 24 01:12:38 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-2dc03ebd-e85b-4d94-a416-5c05eaf9cd1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=815498814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.815498814 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3612406711 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 134335887 ps |
| CPU time | 12.57 seconds |
| Started | Dec 24 01:12:12 PM PST 23 |
| Finished | Dec 24 01:12:36 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-f3681173-fe8b-495a-8e7c-a7cda642c3bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3612406711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3612406711 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.165135633 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 1062895241 ps |
| CPU time | 145.96 seconds |
| Started | Dec 24 01:12:22 PM PST 23 |
| Finished | Dec 24 01:15:00 PM PST 23 |
| Peak memory | 205200 kb |
| Host | smart-e414eb4c-5d8a-486d-8bce-f1ac27926fd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=165135633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_ reset.165135633 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1141298188 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 7603566 ps |
| CPU time | 3.03 seconds |
| Started | Dec 24 01:12:08 PM PST 23 |
| Finished | Dec 24 01:12:22 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-2bbba9e7-fdcb-4599-8357-4b98dfe24d21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1141298188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.1141298188 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.4275540474 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2797738543 ps |
| CPU time | 7.5 seconds |
| Started | Dec 24 01:12:13 PM PST 23 |
| Finished | Dec 24 01:12:33 PM PST 23 |
| Peak memory | 201536 kb |
| Host | smart-5ef71ac9-f510-4145-9b57-7a24b9b54b1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4275540474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.4275540474 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1797090899 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4680728391 ps |
| CPU time | 14.7 seconds |
| Started | Dec 24 01:12:50 PM PST 23 |
| Finished | Dec 24 01:13:12 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-7e454f21-671a-4fa3-9bc4-a07a1edaf6e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1797090899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1797090899 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.328396691 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 57946247238 ps |
| CPU time | 175.35 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:15:58 PM PST 23 |
| Peak memory | 202380 kb |
| Host | smart-0c88e680-c181-41ae-9ec9-ca6d6d3106e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=328396691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo w_rsp.328396691 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2177731512 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 10364259 ps |
| CPU time | 1.28 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:04 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-f5479e5f-4645-4d32-9f9a-af84f4ae5e79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2177731512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2177731512 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.4122540999 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 87139362 ps |
| CPU time | 5.37 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:17 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-99b922e2-17b3-45ad-afd4-c7df284136df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4122540999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.4122540999 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.2031181221 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 192150267 ps |
| CPU time | 1.37 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:13:10 PM PST 23 |
| Peak memory | 201416 kb |
| Host | smart-dcd34abc-3fde-422f-9a01-1302f25af458 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2031181221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2031181221 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.4023649615 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 8691650854 ps |
| CPU time | 37.82 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:13:21 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-6a3dc28d-84fa-4c6b-bae2-efb78e45385d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023649615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.4023649615 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.781371466 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 158309257101 ps |
| CPU time | 145.74 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:15:32 PM PST 23 |
| Peak memory | 201516 kb |
| Host | smart-1ab9c7fc-7d62-47ad-bcc5-4f7682d0f5c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=781371466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.781371466 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2329755903 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 11084289 ps |
| CPU time | 1.21 seconds |
| Started | Dec 24 01:12:44 PM PST 23 |
| Finished | Dec 24 01:12:54 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-2442b848-b9c2-4a70-a896-35f13afc97ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329755903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2329755903 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.2090245202 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 18079448 ps |
| CPU time | 1.69 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:10 PM PST 23 |
| Peak memory | 201356 kb |
| Host | smart-8810da0d-61b5-4283-ad38-e64165b8080c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2090245202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2090245202 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.3057796824 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 17787563 ps |
| CPU time | 1.21 seconds |
| Started | Dec 24 01:12:43 PM PST 23 |
| Finished | Dec 24 01:12:54 PM PST 23 |
| Peak memory | 201156 kb |
| Host | smart-fe6d29f0-fb24-4f2f-831d-51ec5b7e0de6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3057796824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3057796824 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3014683959 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4770562323 ps |
| CPU time | 11.15 seconds |
| Started | Dec 24 01:12:32 PM PST 23 |
| Finished | Dec 24 01:12:56 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-4d85b3d3-3c51-4988-8814-6688aa15981f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014683959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3014683959 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.626293568 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2285207688 ps |
| CPU time | 7.83 seconds |
| Started | Dec 24 01:12:35 PM PST 23 |
| Finished | Dec 24 01:12:56 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-ff9fd74d-8dfd-451b-85c9-78c547cde281 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=626293568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.626293568 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.62380349 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 14990015 ps |
| CPU time | 1.18 seconds |
| Started | Dec 24 01:12:53 PM PST 23 |
| Finished | Dec 24 01:13:02 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-176799bd-7254-42ed-90d8-d8f28136fb65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62380349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.62380349 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.266655218 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 86364908 ps |
| CPU time | 7.07 seconds |
| Started | Dec 24 01:12:54 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-ad6cede9-37a4-4505-93d6-228f7e8e245e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=266655218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.266655218 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.4264678722 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 544280754 ps |
| CPU time | 56.33 seconds |
| Started | Dec 24 01:12:48 PM PST 23 |
| Finished | Dec 24 01:13:52 PM PST 23 |
| Peak memory | 201648 kb |
| Host | smart-ccae4a21-aed2-4990-97c6-dce9747c25a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4264678722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.4264678722 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1605760303 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1691438615 ps |
| CPU time | 44.33 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 203452 kb |
| Host | smart-60533a3e-d9cd-4262-82da-219242a8ec95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1605760303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.1605760303 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2325503491 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 535947054 ps |
| CPU time | 72.58 seconds |
| Started | Dec 24 01:12:54 PM PST 23 |
| Finished | Dec 24 01:14:14 PM PST 23 |
| Peak memory | 205916 kb |
| Host | smart-1abc9108-8f1a-4104-8164-d5830317502c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2325503491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.2325503491 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.2975442573 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 443505219 ps |
| CPU time | 8.44 seconds |
| Started | Dec 24 01:13:04 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-ea6fb99f-5216-4d72-b611-96cf9b7163e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2975442573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2975442573 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2058083298 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 29206184 ps |
| CPU time | 3.2 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:13:08 PM PST 23 |
| Peak memory | 201424 kb |
| Host | smart-7ac173f5-9ead-4e4b-91d6-96221397635c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2058083298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2058083298 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1264667130 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 10473307549 ps |
| CPU time | 36.75 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:42 PM PST 23 |
| Peak memory | 201568 kb |
| Host | smart-b291d24b-f209-45e8-a875-86c5e8b903dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1264667130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.1264667130 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.269431215 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1100231373 ps |
| CPU time | 9.77 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:17 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-cdeb06da-eada-4d40-838c-fb9dcd21dcc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=269431215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.269431215 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.2307170135 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 845781558 ps |
| CPU time | 15.67 seconds |
| Started | Dec 24 01:13:05 PM PST 23 |
| Finished | Dec 24 01:13:36 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-014f719a-002a-483e-9643-816ef8fcecbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2307170135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2307170135 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.4034805062 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3644557257 ps |
| CPU time | 14.8 seconds |
| Started | Dec 24 01:12:48 PM PST 23 |
| Finished | Dec 24 01:13:10 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-31f33e70-770e-4579-be7f-0c25c19dc3d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4034805062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.4034805062 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.944699996 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8201070498 ps |
| CPU time | 27.04 seconds |
| Started | Dec 24 01:13:08 PM PST 23 |
| Finished | Dec 24 01:13:50 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-b0863601-0ff0-4716-93e0-5a006a35784f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=944699996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.944699996 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.888939979 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 30907626552 ps |
| CPU time | 54.66 seconds |
| Started | Dec 24 01:13:02 PM PST 23 |
| Finished | Dec 24 01:14:12 PM PST 23 |
| Peak memory | 201564 kb |
| Host | smart-32c8cbfe-316f-4a40-af7e-00e9a3df9ff0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=888939979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.888939979 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.2872568521 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 131074047 ps |
| CPU time | 5.75 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:18 PM PST 23 |
| Peak memory | 201312 kb |
| Host | smart-b782cc8f-41be-47ef-846f-694d2c607cb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872568521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2872568521 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.2791812571 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 212086796 ps |
| CPU time | 4.7 seconds |
| Started | Dec 24 01:13:01 PM PST 23 |
| Finished | Dec 24 01:13:20 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-037816ee-fd35-447c-a918-e114f860de56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2791812571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2791812571 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.1085320276 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 78386482 ps |
| CPU time | 1.18 seconds |
| Started | Dec 24 01:12:49 PM PST 23 |
| Finished | Dec 24 01:12:57 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-bbb45eba-303a-450a-959b-3f8e9cd8a13d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1085320276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1085320276 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.406429638 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4482903474 ps |
| CPU time | 8.99 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:15 PM PST 23 |
| Peak memory | 201440 kb |
| Host | smart-1604f063-d556-4190-b7be-9ef34cee2c22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=406429638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.406429638 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1639083206 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 1707544756 ps |
| CPU time | 7.34 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:13:17 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-2e1de9f3-0f7e-47b8-9032-c0f608fbaa64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1639083206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1639083206 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.784239530 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 8230392 ps |
| CPU time | 1.12 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:08 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-0d7d1237-1d09-4a40-b864-968e4efa6741 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784239530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.784239530 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.996234587 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3436668804 ps |
| CPU time | 39.55 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:48 PM PST 23 |
| Peak memory | 201460 kb |
| Host | smart-fcc6a41e-f5d3-48c6-9fec-8bf374142687 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=996234587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.996234587 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3493544492 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 3228366228 ps |
| CPU time | 53.33 seconds |
| Started | Dec 24 01:13:04 PM PST 23 |
| Finished | Dec 24 01:14:14 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-81d641c2-600f-491e-944d-9f5bd756b858 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3493544492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3493544492 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2006598967 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 41116664 ps |
| CPU time | 8.82 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:16 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-cef5405f-ba2f-4fc6-b439-1b30df09f947 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2006598967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.2006598967 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2140144319 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 108090362 ps |
| CPU time | 4.62 seconds |
| Started | Dec 24 01:13:02 PM PST 23 |
| Finished | Dec 24 01:13:22 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-fbd4d69c-4d7e-4976-b27b-c121e6e2d15d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2140144319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2140144319 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.620884474 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 452585105 ps |
| CPU time | 2.75 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:11 PM PST 23 |
| Peak memory | 201440 kb |
| Host | smart-d9d8e2b5-d95a-4b9f-bf47-9748f1aab7c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=620884474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.620884474 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.37691908 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 24205712749 ps |
| CPU time | 167.45 seconds |
| Started | Dec 24 01:13:02 PM PST 23 |
| Finished | Dec 24 01:16:05 PM PST 23 |
| Peak memory | 202548 kb |
| Host | smart-5e62f5fd-922b-43b7-9606-b0d39ac33c09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=37691908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow _rsp.37691908 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.1567530837 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2130572263 ps |
| CPU time | 10.21 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:17 PM PST 23 |
| Peak memory | 201340 kb |
| Host | smart-fba9989b-b6ca-4fe1-a858-4a18349ee2fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1567530837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1567530837 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.66313209 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 69479450 ps |
| CPU time | 6.62 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:19 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-4111cbea-bcc4-451a-807d-041ff2b129fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=66313209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.66313209 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.693003155 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 41371464 ps |
| CPU time | 2.99 seconds |
| Started | Dec 24 01:12:53 PM PST 23 |
| Finished | Dec 24 01:13:03 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-14d7296e-9f92-4843-828a-bfb4eef59005 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=693003155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.693003155 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1661678521 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 12552994240 ps |
| CPU time | 33.37 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:13:53 PM PST 23 |
| Peak memory | 201196 kb |
| Host | smart-4c5fad0a-d4c4-4692-9df2-f30d45208db3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661678521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1661678521 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.4108958773 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 26433252241 ps |
| CPU time | 83.04 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:14:38 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-069a1ab9-241c-4774-8034-79a9814156f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4108958773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.4108958773 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3610782236 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 13818728 ps |
| CPU time | 0.99 seconds |
| Started | Dec 24 01:13:02 PM PST 23 |
| Finished | Dec 24 01:13:18 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-657b75d7-1632-4f1b-bf2c-68c85cb86a6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610782236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3610782236 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.1699234860 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 664958586 ps |
| CPU time | 5.13 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:12 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-cfd48866-c18b-47a4-9d78-4120062ffe0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1699234860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1699234860 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.1754025468 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 11122148 ps |
| CPU time | 1.13 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:23 PM PST 23 |
| Peak memory | 201328 kb |
| Host | smart-8eba1117-0fd1-4f69-aabe-d183453e64b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1754025468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1754025468 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.822623811 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5300920829 ps |
| CPU time | 7.46 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:13:12 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-f0bceaf2-d904-432d-b963-2337ddb4eb12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=822623811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.822623811 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3187738425 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1869834406 ps |
| CPU time | 7.89 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:11 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-f3ddbb06-cc53-4fc8-b04c-f914fb83c555 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3187738425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3187738425 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3411171680 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 14432591 ps |
| CPU time | 1.2 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:23 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-c0ca87ef-8d83-46d7-b1a7-7c55c65cadac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411171680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3411171680 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.2587523386 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 4857595882 ps |
| CPU time | 46.9 seconds |
| Started | Dec 24 01:12:49 PM PST 23 |
| Finished | Dec 24 01:13:43 PM PST 23 |
| Peak memory | 202480 kb |
| Host | smart-32c015fa-c669-4195-81ad-93ac813bc5ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2587523386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2587523386 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1834113069 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 153830823 ps |
| CPU time | 12.54 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-9c39e02d-6c33-471c-9191-a2ac0640b96f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1834113069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1834113069 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3633542004 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 1038721410 ps |
| CPU time | 100.9 seconds |
| Started | Dec 24 01:12:54 PM PST 23 |
| Finished | Dec 24 01:14:43 PM PST 23 |
| Peak memory | 203700 kb |
| Host | smart-3671c590-c30c-428f-a69c-eeb69c1795a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3633542004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3633542004 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3034610088 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 60058083 ps |
| CPU time | 7.21 seconds |
| Started | Dec 24 01:13:01 PM PST 23 |
| Finished | Dec 24 01:13:23 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-50451056-7b44-4aa3-8a91-226f050edad5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3034610088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3034610088 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1452135613 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 716812581 ps |
| CPU time | 17.1 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:20 PM PST 23 |
| Peak memory | 201408 kb |
| Host | smart-12ca58e4-b839-47f0-a791-80a35b60bd6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1452135613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1452135613 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1378390233 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 91416568346 ps |
| CPU time | 221.62 seconds |
| Started | Dec 24 01:13:11 PM PST 23 |
| Finished | Dec 24 01:17:08 PM PST 23 |
| Peak memory | 203468 kb |
| Host | smart-40d142c9-2d71-4a4e-a53a-0a56990cb401 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1378390233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.1378390233 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1773424136 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 220903542 ps |
| CPU time | 4 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:30 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-bad89b9e-b91a-48a8-b363-fc8b4a4405f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1773424136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1773424136 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.2142650115 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 62752813 ps |
| CPU time | 4 seconds |
| Started | Dec 24 01:13:04 PM PST 23 |
| Finished | Dec 24 01:13:24 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-8e033b02-a1f6-44e7-8562-b61814a75338 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2142650115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2142650115 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.1989099799 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1562425953 ps |
| CPU time | 5.02 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:20 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-8cd42c23-dab1-4ddf-afc8-c24e90dbc6bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1989099799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1989099799 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2141132284 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 17607342145 ps |
| CPU time | 85.3 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:14:40 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-57615c35-8e7b-45cd-8af6-274e9a868876 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141132284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2141132284 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1675130749 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 11901669884 ps |
| CPU time | 58.6 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:14:03 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-fbbf8c78-cfb5-401a-9e64-4465a7f12d8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1675130749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1675130749 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1483288883 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 69109844 ps |
| CPU time | 8.42 seconds |
| Started | Dec 24 01:12:52 PM PST 23 |
| Finished | Dec 24 01:13:08 PM PST 23 |
| Peak memory | 201324 kb |
| Host | smart-51ecf515-6df9-48f8-a135-082cbcb228d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483288883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1483288883 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.2005778557 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 103120757 ps |
| CPU time | 6.15 seconds |
| Started | Dec 24 01:13:10 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-dc18d2fa-6b87-4b08-bcf7-675150628e2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2005778557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2005778557 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.3591234652 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 110656760 ps |
| CPU time | 1.48 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:05 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-dc8f3c13-9e42-4962-a186-4b0fc05485b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3591234652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3591234652 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2837888728 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2264071666 ps |
| CPU time | 7.12 seconds |
| Started | Dec 24 01:13:04 PM PST 23 |
| Finished | Dec 24 01:13:27 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-110293b2-dc91-40bd-b00f-1d1598bfbce6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837888728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2837888728 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2627019740 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 632880878 ps |
| CPU time | 5.4 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-42d060c6-9771-48ee-b704-40716b354828 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2627019740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2627019740 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1563993578 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 9101185 ps |
| CPU time | 1.09 seconds |
| Started | Dec 24 01:13:04 PM PST 23 |
| Finished | Dec 24 01:13:21 PM PST 23 |
| Peak memory | 201384 kb |
| Host | smart-1af966f0-fbfc-449d-95b0-40f8597b73fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563993578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1563993578 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3298216883 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 16717438 ps |
| CPU time | 1.7 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:24 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-a50a61e7-3448-4f08-bdf9-98fe17b8ee07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3298216883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3298216883 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.926509725 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 8480380321 ps |
| CPU time | 62.04 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:14:06 PM PST 23 |
| Peak memory | 202628 kb |
| Host | smart-5a92a0e8-7032-4e04-97a7-ab7df21d19c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=926509725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.926509725 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1058119596 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 8481052880 ps |
| CPU time | 48.79 seconds |
| Started | Dec 24 01:13:01 PM PST 23 |
| Finished | Dec 24 01:14:05 PM PST 23 |
| Peak memory | 203660 kb |
| Host | smart-312fc632-55dd-442a-b5ba-9f3a12cbac83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1058119596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.1058119596 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3961040601 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 824755247 ps |
| CPU time | 119.22 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:15:04 PM PST 23 |
| Peak memory | 204504 kb |
| Host | smart-b4fc671b-2a02-490b-98b7-466e6227fc03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3961040601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.3961040601 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2086716372 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 32676990 ps |
| CPU time | 2.75 seconds |
| Started | Dec 24 01:12:52 PM PST 23 |
| Finished | Dec 24 01:13:02 PM PST 23 |
| Peak memory | 201336 kb |
| Host | smart-4d864ce3-9343-4136-a825-e150772bc8bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2086716372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2086716372 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.338157258 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 4216500188 ps |
| CPU time | 17.62 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:30 PM PST 23 |
| Peak memory | 201544 kb |
| Host | smart-469ae455-17d9-4cf1-b0b7-d25c9b858f7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=338157258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.338157258 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1362204863 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 35886896357 ps |
| CPU time | 233.66 seconds |
| Started | Dec 24 01:13:09 PM PST 23 |
| Finished | Dec 24 01:17:19 PM PST 23 |
| Peak memory | 202828 kb |
| Host | smart-fb95b5d5-cf47-485c-8bad-6f5f6557d73a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1362204863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.1362204863 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.447709200 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 27503097 ps |
| CPU time | 3.09 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:13:13 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-485da8f1-ff3c-4459-ba75-80d0b8889f7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=447709200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.447709200 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.3685625209 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 110822140 ps |
| CPU time | 7.11 seconds |
| Started | Dec 24 01:13:09 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-a564e09a-cc0e-4751-99bc-09a5de9e7de7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3685625209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3685625209 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.1450192439 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 405748012 ps |
| CPU time | 6.11 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201332 kb |
| Host | smart-7c5fc904-ead8-4354-849b-297c63812def |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1450192439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1450192439 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1303558954 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 32262362761 ps |
| CPU time | 148.69 seconds |
| Started | Dec 24 01:12:53 PM PST 23 |
| Finished | Dec 24 01:15:30 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-c88ef82f-67a9-4373-b957-2c5d5821e50e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303558954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1303558954 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.914721303 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 34195807026 ps |
| CPU time | 113.71 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:14:58 PM PST 23 |
| Peak memory | 201512 kb |
| Host | smart-3fafb108-908f-491f-b627-d3cda781e6ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=914721303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.914721303 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.642243122 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 103384722 ps |
| CPU time | 4.74 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:11 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-1240234a-dfd0-423f-bcea-72cb4ed55073 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642243122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.642243122 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.708860118 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 44296927 ps |
| CPU time | 3.89 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:16 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-4e46633f-7227-439c-a5c4-41f1a4d8b47c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=708860118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.708860118 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.2826529105 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 56161191 ps |
| CPU time | 1.59 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:14 PM PST 23 |
| Peak memory | 201292 kb |
| Host | smart-08d2fd12-43a4-40e1-aa8b-96fd8c2ecc7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2826529105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2826529105 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3672323642 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 9190974016 ps |
| CPU time | 9.1 seconds |
| Started | Dec 24 01:12:52 PM PST 23 |
| Finished | Dec 24 01:13:08 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-156cf30e-4463-4342-bac8-99081b1c7b22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672323642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3672323642 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2836075657 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 11367578503 ps |
| CPU time | 10.39 seconds |
| Started | Dec 24 01:12:52 PM PST 23 |
| Finished | Dec 24 01:13:10 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-697b4977-83ae-41e6-8e10-c46e3e704e52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2836075657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2836075657 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3751568933 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 10470695 ps |
| CPU time | 1.4 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:15 PM PST 23 |
| Peak memory | 201320 kb |
| Host | smart-9ae3381b-e8a5-4689-96e6-13ff6a40aed5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751568933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3751568933 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.3782501220 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6659286790 ps |
| CPU time | 54.83 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:14:14 PM PST 23 |
| Peak memory | 203188 kb |
| Host | smart-64d1e00c-b985-4c23-a774-71de8507aeb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3782501220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3782501220 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3602268799 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 714234911 ps |
| CPU time | 18.75 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 202464 kb |
| Host | smart-8fbb6a60-ca6d-4fd1-9fe6-8dbffb48997b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3602268799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3602268799 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2199342681 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 14772692979 ps |
| CPU time | 50.52 seconds |
| Started | Dec 24 01:13:09 PM PST 23 |
| Finished | Dec 24 01:14:15 PM PST 23 |
| Peak memory | 202556 kb |
| Host | smart-5ef47414-1c7d-40f3-ab1b-acd58de46bf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2199342681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.2199342681 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1071171674 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 163431601 ps |
| CPU time | 26.55 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:31 PM PST 23 |
| Peak memory | 201436 kb |
| Host | smart-3846017e-8015-4415-b3a3-c2e0e99220ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1071171674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.1071171674 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.3913795027 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 45127544 ps |
| CPU time | 4.41 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-286b8073-12a2-4040-8e8e-8761d10d66b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3913795027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3913795027 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.800821348 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 34950134 ps |
| CPU time | 1.68 seconds |
| Started | Dec 24 01:13:11 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201348 kb |
| Host | smart-e81ed587-b290-426c-8b6f-7b96221222bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=800821348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.800821348 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.541954002 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 80139395 ps |
| CPU time | 4.06 seconds |
| Started | Dec 24 01:13:01 PM PST 23 |
| Finished | Dec 24 01:13:21 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-3b44d9bc-ca37-4b5d-ab98-21d718326824 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=541954002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.541954002 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.2794592363 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 23938947 ps |
| CPU time | 1.52 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:13:11 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-11b4c87f-e562-4df3-b46e-df2ba58eaa93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2794592363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2794592363 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.1367074075 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 677743064 ps |
| CPU time | 8.24 seconds |
| Started | Dec 24 01:13:02 PM PST 23 |
| Finished | Dec 24 01:13:27 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-4f9e1f87-fe09-44cd-810e-d9c3ff15b475 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1367074075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1367074075 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1182812812 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 7219811510 ps |
| CPU time | 8.11 seconds |
| Started | Dec 24 01:13:04 PM PST 23 |
| Finished | Dec 24 01:13:29 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-9df132df-049e-4199-b5d3-ae984ab02d9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182812812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1182812812 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2399458207 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 10884144796 ps |
| CPU time | 80.09 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:14:47 PM PST 23 |
| Peak memory | 201528 kb |
| Host | smart-039b889f-9823-4526-b612-3eb38cf26002 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2399458207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2399458207 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.4284788499 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 65722494 ps |
| CPU time | 7.28 seconds |
| Started | Dec 24 01:13:02 PM PST 23 |
| Finished | Dec 24 01:13:25 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-0d225aa9-e534-468f-b960-dd6fe751e72b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284788499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.4284788499 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.366696496 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 137993715 ps |
| CPU time | 6.31 seconds |
| Started | Dec 24 01:13:10 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201328 kb |
| Host | smart-e15f536f-4f3b-438f-b8bc-1c4d2dd67da3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=366696496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.366696496 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.1816690416 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 8984865 ps |
| CPU time | 1.07 seconds |
| Started | Dec 24 01:13:01 PM PST 23 |
| Finished | Dec 24 01:13:18 PM PST 23 |
| Peak memory | 201356 kb |
| Host | smart-b4081bb9-4292-48a3-b159-f3b22e247d96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1816690416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1816690416 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2894334663 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2406302393 ps |
| CPU time | 7.15 seconds |
| Started | Dec 24 01:13:16 PM PST 23 |
| Finished | Dec 24 01:13:38 PM PST 23 |
| Peak memory | 201564 kb |
| Host | smart-825535c8-e1c7-4eb1-964b-ae1612b4b80c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894334663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2894334663 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2796939364 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1765653596 ps |
| CPU time | 7.64 seconds |
| Started | Dec 24 01:13:10 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-869bf554-f423-4ce9-827b-17fe85bbeb25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2796939364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2796939364 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1528215766 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 30543855 ps |
| CPU time | 1.17 seconds |
| Started | Dec 24 01:13:13 PM PST 23 |
| Finished | Dec 24 01:13:29 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-f81a069a-aede-47e2-a03b-6f913b77de5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528215766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1528215766 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.213605472 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1823153470 ps |
| CPU time | 28.29 seconds |
| Started | Dec 24 01:12:59 PM PST 23 |
| Finished | Dec 24 01:13:38 PM PST 23 |
| Peak memory | 202196 kb |
| Host | smart-3892e0eb-792b-4f2d-995e-c50f41ffc5af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=213605472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.213605472 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.129000719 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 643365128 ps |
| CPU time | 38.34 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:51 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-eddcac27-ff8b-4ac9-800f-bcade6eebbe7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=129000719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.129000719 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2223559905 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 7643138335 ps |
| CPU time | 231.81 seconds |
| Started | Dec 24 01:13:10 PM PST 23 |
| Finished | Dec 24 01:17:18 PM PST 23 |
| Peak memory | 205692 kb |
| Host | smart-00cb32ef-1b0e-4edb-bf55-aeb6efb3ee6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2223559905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.2223559905 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.2877925274 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 2888056456 ps |
| CPU time | 45.76 seconds |
| Started | Dec 24 01:13:16 PM PST 23 |
| Finished | Dec 24 01:14:17 PM PST 23 |
| Peak memory | 202916 kb |
| Host | smart-a73fcd97-6607-4475-aa45-cf5938f97ec8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2877925274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.2877925274 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.413209115 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 50267930 ps |
| CPU time | 7.91 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:13:27 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-568dd6bc-c808-4071-bdba-9694febf1ab2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=413209115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.413209115 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.646429419 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 2945395441 ps |
| CPU time | 15.97 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:24 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-a8649fe7-7ca3-49dc-a329-9858996a7535 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=646429419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo w_rsp.646429419 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3503281493 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 406050626 ps |
| CPU time | 7.03 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:13:26 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-e928f071-2580-4c8b-bc5f-764aaeee21cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3503281493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3503281493 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.3362505032 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 695344491 ps |
| CPU time | 5.91 seconds |
| Started | Dec 24 01:13:08 PM PST 23 |
| Finished | Dec 24 01:13:29 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-02f7c6dd-f84a-4187-8ab0-02c15529590b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3362505032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3362505032 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.3431174537 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 290937875 ps |
| CPU time | 4.12 seconds |
| Started | Dec 24 01:12:54 PM PST 23 |
| Finished | Dec 24 01:13:05 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-45a41711-4ec7-4f5f-8347-6bde53a1b144 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3431174537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3431174537 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.3302513357 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 34573359234 ps |
| CPU time | 160.73 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:15:48 PM PST 23 |
| Peak memory | 201500 kb |
| Host | smart-08c51e1f-b6dd-4942-8bdc-b428261f895f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302513357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3302513357 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.4015534271 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 6131326697 ps |
| CPU time | 34.14 seconds |
| Started | Dec 24 01:13:02 PM PST 23 |
| Finished | Dec 24 01:13:51 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-2f269b78-c770-4088-b2e1-dceaa5691757 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4015534271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.4015534271 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3560660478 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 254565874 ps |
| CPU time | 7.02 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:15 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-c9dd3b51-9c2d-4402-9e4a-b42eec00c1b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560660478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3560660478 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.261542895 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1123994087 ps |
| CPU time | 10.48 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:13:14 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-3df9bdd0-102d-4462-b3f3-641ef060f834 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=261542895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.261542895 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.285449111 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 89899444 ps |
| CPU time | 1.41 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:23 PM PST 23 |
| Peak memory | 201392 kb |
| Host | smart-7e8e29bf-42f2-4fde-b0d8-317afe5c525f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=285449111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.285449111 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2118456785 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 3618780487 ps |
| CPU time | 8.03 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:13:27 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-edcae9b3-52b8-4361-ab41-da5ec066c771 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118456785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2118456785 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.991070858 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 705188904 ps |
| CPU time | 5.4 seconds |
| Started | Dec 24 01:13:01 PM PST 23 |
| Finished | Dec 24 01:13:21 PM PST 23 |
| Peak memory | 201500 kb |
| Host | smart-a280369c-76af-4f49-ad25-2bd13e1247cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=991070858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.991070858 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3395769698 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 28796721 ps |
| CPU time | 1.2 seconds |
| Started | Dec 24 01:13:01 PM PST 23 |
| Finished | Dec 24 01:13:17 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-0ab39f56-0ed8-4263-983f-caacccd68e70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395769698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3395769698 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.656596002 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2114424642 ps |
| CPU time | 21.18 seconds |
| Started | Dec 24 01:13:01 PM PST 23 |
| Finished | Dec 24 01:13:37 PM PST 23 |
| Peak memory | 201388 kb |
| Host | smart-5cfc23e7-4c94-42bb-9eba-a37e179817ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=656596002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.656596002 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1275151224 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 241836307 ps |
| CPU time | 18.87 seconds |
| Started | Dec 24 01:13:02 PM PST 23 |
| Finished | Dec 24 01:13:37 PM PST 23 |
| Peak memory | 201380 kb |
| Host | smart-c2303f13-0d6e-44b1-bd3f-b3bd8868a8e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1275151224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1275151224 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2991115580 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2777582275 ps |
| CPU time | 51.8 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:14:15 PM PST 23 |
| Peak memory | 203580 kb |
| Host | smart-497e26ee-b80a-4716-926a-6656a9aa1227 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2991115580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.2991115580 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.4267940198 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 2574277477 ps |
| CPU time | 167.93 seconds |
| Started | Dec 24 01:13:09 PM PST 23 |
| Finished | Dec 24 01:16:12 PM PST 23 |
| Peak memory | 207656 kb |
| Host | smart-ef4016d1-a5c6-42ba-a7aa-b04a33b8eeb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4267940198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.4267940198 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1168048563 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 55039969 ps |
| CPU time | 4.72 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:13:27 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-a095cf2c-9469-4f51-9a34-99edaa119a81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1168048563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1168048563 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1962404023 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 138358416 ps |
| CPU time | 1.9 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:23 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-4186361e-ba63-4091-bdba-de031c89069f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1962404023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1962404023 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.880613594 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 12981408210 ps |
| CPU time | 102.94 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:14:55 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-18a9c440-5414-410b-a89c-f022978c1531 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=880613594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo w_rsp.880613594 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.348769738 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 74209228 ps |
| CPU time | 5.42 seconds |
| Started | Dec 24 01:13:18 PM PST 23 |
| Finished | Dec 24 01:13:38 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-1e825ffd-b0d9-4ff1-9e93-d0a640fea763 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=348769738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.348769738 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.2418007702 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 393433558 ps |
| CPU time | 5.57 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-e05212dd-5f07-4fea-94fd-827511f56d4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2418007702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2418007702 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.785603043 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 68005278 ps |
| CPU time | 6.16 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:13:25 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-d5f707f4-3788-4049-af55-8a876eb2752b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=785603043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.785603043 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.4283574725 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 74903957936 ps |
| CPU time | 87.88 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:14:50 PM PST 23 |
| Peak memory | 201440 kb |
| Host | smart-208a9ff3-2208-4807-818e-e134c820d930 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283574725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.4283574725 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1795358957 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 34324035566 ps |
| CPU time | 34.77 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:13:53 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-b18e8ce9-ef36-4a06-af8b-c57946ff50b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1795358957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1795358957 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.879731028 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 217058973 ps |
| CPU time | 6.16 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:13:29 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-87e26a49-8c12-4342-a72e-8033392d6c9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879731028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.879731028 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.868865773 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 32605224 ps |
| CPU time | 2.35 seconds |
| Started | Dec 24 01:13:09 PM PST 23 |
| Finished | Dec 24 01:13:27 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-142fb28d-341c-4d29-a05c-4d5431c9c679 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=868865773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.868865773 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.1639730752 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 140101809 ps |
| CPU time | 1.25 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:13:20 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-3526acdf-3aee-4d0b-927e-886b9871d25b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1639730752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1639730752 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1640057846 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 5606861499 ps |
| CPU time | 10.08 seconds |
| Started | Dec 24 01:12:54 PM PST 23 |
| Finished | Dec 24 01:13:12 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-23203b2e-5a74-48b3-aa99-4abc19994091 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640057846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1640057846 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1721009893 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 945089194 ps |
| CPU time | 7.98 seconds |
| Started | Dec 24 01:13:08 PM PST 23 |
| Finished | Dec 24 01:13:31 PM PST 23 |
| Peak memory | 201508 kb |
| Host | smart-c0a4b473-2d58-4d86-b0b7-9081da1eef87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1721009893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1721009893 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2375421418 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 10700366 ps |
| CPU time | 1.12 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:13 PM PST 23 |
| Peak memory | 201420 kb |
| Host | smart-4e628b1d-1476-4e2c-b293-1c1dd3f68137 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375421418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2375421418 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.3154647915 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1527404471 ps |
| CPU time | 12.29 seconds |
| Started | Dec 24 01:13:04 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201376 kb |
| Host | smart-4c5f2355-c4e1-44b1-b272-0af5e00d2cd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3154647915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3154647915 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2084669009 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 317018557 ps |
| CPU time | 21.77 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-7474646e-eece-4b95-8e72-f7d21d36d7a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2084669009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2084669009 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.385093604 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 195031774 ps |
| CPU time | 20.53 seconds |
| Started | Dec 24 01:13:11 PM PST 23 |
| Finished | Dec 24 01:13:47 PM PST 23 |
| Peak memory | 202416 kb |
| Host | smart-a59417a6-60c8-46ba-b474-b8d4e50d1a85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=385093604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res et_error.385093604 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2657045365 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 810411255 ps |
| CPU time | 7.36 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:13:27 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-5557ceea-30fd-4752-a257-f5da0d1be055 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2657045365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2657045365 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2133764666 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 59428298 ps |
| CPU time | 13.13 seconds |
| Started | Dec 24 01:13:08 PM PST 23 |
| Finished | Dec 24 01:13:36 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-a3e7296a-f0be-49ae-a47e-799f4c942ff2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2133764666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2133764666 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4172754725 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 48281510765 ps |
| CPU time | 320.52 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:18:27 PM PST 23 |
| Peak memory | 202568 kb |
| Host | smart-c5552718-73e1-489f-a388-9484b664d6d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4172754725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.4172754725 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.57770900 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 210071443 ps |
| CPU time | 3.16 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:13:25 PM PST 23 |
| Peak memory | 201412 kb |
| Host | smart-4535802f-bf10-4fb4-8373-cfe49c9ef844 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=57770900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.57770900 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.344423850 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 765128021 ps |
| CPU time | 10.71 seconds |
| Started | Dec 24 01:13:05 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-48c508f5-dc5c-482d-a5db-b86417ba48a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=344423850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.344423850 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.2718308540 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 258711793 ps |
| CPU time | 5.3 seconds |
| Started | Dec 24 01:13:00 PM PST 23 |
| Finished | Dec 24 01:13:19 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-fbcc6f84-a2f6-4147-8a79-4ef7d1de5370 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2718308540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2718308540 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1739189419 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 47787725566 ps |
| CPU time | 102.66 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:15:05 PM PST 23 |
| Peak memory | 201544 kb |
| Host | smart-774c769c-d874-4f12-b555-c61ab0be7827 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739189419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1739189419 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1539334956 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 25732199326 ps |
| CPU time | 140.11 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:15:42 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-e84e34d3-b3d7-4109-9089-a9bee45c2b8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1539334956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1539334956 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2429839946 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 22470864 ps |
| CPU time | 2.58 seconds |
| Started | Dec 24 01:12:56 PM PST 23 |
| Finished | Dec 24 01:13:07 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-cc0bc954-51f6-464a-a20e-06eb42801f2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429839946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2429839946 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.3062292764 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 37970584 ps |
| CPU time | 3.79 seconds |
| Started | Dec 24 01:13:09 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201392 kb |
| Host | smart-f9e9c2a5-d35b-44e7-bafa-5d26f307f06b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3062292764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3062292764 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.573389227 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 82061604 ps |
| CPU time | 1.77 seconds |
| Started | Dec 24 01:13:11 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201352 kb |
| Host | smart-6ed25c7e-43c1-4249-9487-d618f63e143f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=573389227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.573389227 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3199851148 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 2399070085 ps |
| CPU time | 9.01 seconds |
| Started | Dec 24 01:13:02 PM PST 23 |
| Finished | Dec 24 01:13:26 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-7e032293-5b79-400c-bb84-439abd9ef71f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199851148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3199851148 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2301645134 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 2951774068 ps |
| CPU time | 10.68 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:38 PM PST 23 |
| Peak memory | 201412 kb |
| Host | smart-9c34d5ea-50a0-4a84-b054-85aa79c3c535 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2301645134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2301645134 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2800058809 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 10160484 ps |
| CPU time | 1.27 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:10 PM PST 23 |
| Peak memory | 201384 kb |
| Host | smart-5badddf2-6b96-4010-83da-ac3b86ac5d47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800058809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2800058809 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.3646196999 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3251134760 ps |
| CPU time | 37.28 seconds |
| Started | Dec 24 01:13:16 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 201536 kb |
| Host | smart-aa6d8946-1978-4889-b9be-40e9d0cd4540 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3646196999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3646196999 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1159213832 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 711607725 ps |
| CPU time | 28.76 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:56 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-e1a2e8fd-dfcf-49a6-80b6-c04b1fc541b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1159213832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1159213832 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.4007418275 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 330514987 ps |
| CPU time | 72.45 seconds |
| Started | Dec 24 01:13:04 PM PST 23 |
| Finished | Dec 24 01:14:33 PM PST 23 |
| Peak memory | 204064 kb |
| Host | smart-a1e036ce-8485-4a0e-ba80-55d13ae36908 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4007418275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.4007418275 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.4049880454 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 11278701635 ps |
| CPU time | 223.99 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:17:11 PM PST 23 |
| Peak memory | 209732 kb |
| Host | smart-ec86307f-464c-4c82-819f-9f2f73fa4811 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4049880454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.4049880454 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3550731248 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 207172295 ps |
| CPU time | 2.76 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:13:25 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-6c8e87a9-cd0f-409b-9cda-50f09d34215c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3550731248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3550731248 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.4139792586 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 96558020 ps |
| CPU time | 7.1 seconds |
| Started | Dec 24 01:13:04 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-cb257d16-661e-420b-80fa-c3382db79efd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4139792586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.4139792586 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.157669693 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 40482838863 ps |
| CPU time | 265.4 seconds |
| Started | Dec 24 01:13:03 PM PST 23 |
| Finished | Dec 24 01:17:45 PM PST 23 |
| Peak memory | 202556 kb |
| Host | smart-1d5f7269-8e04-4dc3-bfb5-3b7fa8d47e47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=157669693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slo w_rsp.157669693 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.108303237 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 50292442 ps |
| CPU time | 4.7 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-3ff9b6b0-33c3-4865-a82e-97e5e26c1593 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=108303237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.108303237 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.580979398 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 223992426 ps |
| CPU time | 2.11 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:13:30 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-3a551f64-9e99-47c0-8085-03c7af444ceb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=580979398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.580979398 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.50167502 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 340892448 ps |
| CPU time | 6.07 seconds |
| Started | Dec 24 01:13:13 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-b141471a-e5ba-4e50-ab28-d7d766e0e7d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=50167502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.50167502 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.3916556476 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 11724781815 ps |
| CPU time | 38.17 seconds |
| Started | Dec 24 01:13:13 PM PST 23 |
| Finished | Dec 24 01:14:06 PM PST 23 |
| Peak memory | 201564 kb |
| Host | smart-0694bb29-12f4-4686-9dc0-d76f3827ba7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916556476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3916556476 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2446260248 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 16465692204 ps |
| CPU time | 58.58 seconds |
| Started | Dec 24 01:13:09 PM PST 23 |
| Finished | Dec 24 01:14:24 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-49249f37-d2ef-4ca2-a0d3-ad6829861746 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2446260248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2446260248 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3178155222 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 109161952 ps |
| CPU time | 8.79 seconds |
| Started | Dec 24 01:13:05 PM PST 23 |
| Finished | Dec 24 01:13:30 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-7fb23953-5933-422d-aa7c-6717924fd7bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178155222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3178155222 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.2811224324 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 824913155 ps |
| CPU time | 3.57 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201392 kb |
| Host | smart-2bcf7fb8-c763-4e05-8232-2057e73bba43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2811224324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2811224324 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.1732348105 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 62732654 ps |
| CPU time | 1.31 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:24 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-27521bdb-1c75-4327-8ba0-e961dd8ec5d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1732348105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1732348105 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.740382406 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 3072143307 ps |
| CPU time | 11.25 seconds |
| Started | Dec 24 01:13:18 PM PST 23 |
| Finished | Dec 24 01:13:44 PM PST 23 |
| Peak memory | 201532 kb |
| Host | smart-88b775e0-dc49-4c30-a94c-0b887af7769b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=740382406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.740382406 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.193754589 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1423971497 ps |
| CPU time | 5.69 seconds |
| Started | Dec 24 01:13:13 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 201500 kb |
| Host | smart-318b0fa9-8803-44d1-a384-5eb2cd40bf76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=193754589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.193754589 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1377491628 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 10608190 ps |
| CPU time | 0.99 seconds |
| Started | Dec 24 01:13:18 PM PST 23 |
| Finished | Dec 24 01:13:34 PM PST 23 |
| Peak memory | 201300 kb |
| Host | smart-59fa3f54-bc32-458b-a533-c51a042dcb64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377491628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1377491628 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.2157378196 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 11998670498 ps |
| CPU time | 104.19 seconds |
| Started | Dec 24 01:13:17 PM PST 23 |
| Finished | Dec 24 01:15:16 PM PST 23 |
| Peak memory | 202536 kb |
| Host | smart-4dd288d6-d26d-41ad-b358-ccb5252bcf4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2157378196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2157378196 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.347408348 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 606066414 ps |
| CPU time | 8.4 seconds |
| Started | Dec 24 01:13:13 PM PST 23 |
| Finished | Dec 24 01:13:36 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-87f82e11-e1ca-44a3-8aa0-375c7fd914f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=347408348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.347408348 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1822983700 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 649846851 ps |
| CPU time | 55.66 seconds |
| Started | Dec 24 01:13:15 PM PST 23 |
| Finished | Dec 24 01:14:25 PM PST 23 |
| Peak memory | 204912 kb |
| Host | smart-1925f97f-b0c9-41ac-bd2e-6c9ae6bb5624 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1822983700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.1822983700 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3258880879 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 58347988 ps |
| CPU time | 5.62 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-5c8c3145-41db-4513-9716-0ba4233ce365 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3258880879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.3258880879 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.605093592 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 1048829500 ps |
| CPU time | 9.55 seconds |
| Started | Dec 24 01:13:22 PM PST 23 |
| Finished | Dec 24 01:13:45 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-6b1e766a-3b81-43bb-ba89-a7078c65f132 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=605093592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.605093592 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1209300083 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 6690236271 ps |
| CPU time | 15.56 seconds |
| Started | Dec 24 01:12:07 PM PST 23 |
| Finished | Dec 24 01:12:33 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-306cd0a0-ad82-446b-ab58-3a93afd61324 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1209300083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1209300083 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2963722239 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 13467695164 ps |
| CPU time | 63.83 seconds |
| Started | Dec 24 01:11:52 PM PST 23 |
| Finished | Dec 24 01:13:04 PM PST 23 |
| Peak memory | 201508 kb |
| Host | smart-a520a36b-3f16-457b-a997-80d058c1aaf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2963722239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.2963722239 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2247328426 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 20664448 ps |
| CPU time | 2.03 seconds |
| Started | Dec 24 01:12:01 PM PST 23 |
| Finished | Dec 24 01:12:10 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-88a4f6e0-e82f-47c0-aedd-5ec59de0ad99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2247328426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2247328426 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.1803547062 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 97098354 ps |
| CPU time | 4.79 seconds |
| Started | Dec 24 01:12:13 PM PST 23 |
| Finished | Dec 24 01:12:31 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-1e46363d-d36e-4c82-98f6-74f43128b158 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1803547062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1803547062 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.2258490067 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 55104785 ps |
| CPU time | 5.9 seconds |
| Started | Dec 24 01:12:14 PM PST 23 |
| Finished | Dec 24 01:12:37 PM PST 23 |
| Peak memory | 201392 kb |
| Host | smart-8840fa9e-abb4-4c8f-aca9-305738993481 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2258490067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2258490067 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2008458993 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 11271005749 ps |
| CPU time | 43.56 seconds |
| Started | Dec 24 01:11:57 PM PST 23 |
| Finished | Dec 24 01:12:48 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-75a6628d-a3b5-497c-8b06-bd25140282c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008458993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2008458993 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1177848627 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 12771811556 ps |
| CPU time | 97.83 seconds |
| Started | Dec 24 01:12:18 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-e9edc051-a5da-4d1b-bf39-969dc3db8ad8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1177848627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1177848627 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3965901132 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 82020475 ps |
| CPU time | 6.09 seconds |
| Started | Dec 24 01:12:12 PM PST 23 |
| Finished | Dec 24 01:12:30 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-b0c77475-2bfb-4d02-b07e-b8b30eb579ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965901132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3965901132 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.1007308242 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1311726204 ps |
| CPU time | 13.58 seconds |
| Started | Dec 24 01:12:19 PM PST 23 |
| Finished | Dec 24 01:12:45 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-8abdd355-cb44-4caa-84d0-26cebcf590ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1007308242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1007308242 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.1637608261 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 76117277 ps |
| CPU time | 1.59 seconds |
| Started | Dec 24 01:11:58 PM PST 23 |
| Finished | Dec 24 01:12:07 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-bdca8807-dc32-4cc9-a6be-b2aaff171992 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1637608261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1637608261 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3131146231 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2808222647 ps |
| CPU time | 8.74 seconds |
| Started | Dec 24 01:12:20 PM PST 23 |
| Finished | Dec 24 01:12:41 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-bf31aaa9-b8fc-4a90-bbd7-a7bfe9e83213 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131146231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3131146231 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.30322648 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2762434862 ps |
| CPU time | 9.92 seconds |
| Started | Dec 24 01:12:13 PM PST 23 |
| Finished | Dec 24 01:12:37 PM PST 23 |
| Peak memory | 201508 kb |
| Host | smart-9827aa20-81d6-4ff7-b150-f04b544cbf13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=30322648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.30322648 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2033563569 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 10395354 ps |
| CPU time | 1.1 seconds |
| Started | Dec 24 01:12:13 PM PST 23 |
| Finished | Dec 24 01:12:28 PM PST 23 |
| Peak memory | 201364 kb |
| Host | smart-50a1908c-27aa-4919-88c8-acebd7648ada |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033563569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2033563569 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.1131317299 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4479957317 ps |
| CPU time | 66.63 seconds |
| Started | Dec 24 01:12:07 PM PST 23 |
| Finished | Dec 24 01:13:22 PM PST 23 |
| Peak memory | 204104 kb |
| Host | smart-4b24f9c8-d15e-44f4-8c0b-b077831e4762 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1131317299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1131317299 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3478875213 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 141740441 ps |
| CPU time | 6.81 seconds |
| Started | Dec 24 01:12:14 PM PST 23 |
| Finished | Dec 24 01:12:39 PM PST 23 |
| Peak memory | 201440 kb |
| Host | smart-a20d1f95-5750-49e1-8f1d-291b55300ae7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3478875213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3478875213 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2877285067 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5597277251 ps |
| CPU time | 131.12 seconds |
| Started | Dec 24 01:12:21 PM PST 23 |
| Finished | Dec 24 01:14:45 PM PST 23 |
| Peak memory | 204136 kb |
| Host | smart-4935a581-d86c-43d1-9a96-dba3df89ea37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2877285067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.2877285067 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.4145701511 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 653666995 ps |
| CPU time | 93.92 seconds |
| Started | Dec 24 01:12:19 PM PST 23 |
| Finished | Dec 24 01:14:05 PM PST 23 |
| Peak memory | 202824 kb |
| Host | smart-a2b389e5-df82-4209-890f-582c917d093f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4145701511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.4145701511 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.956541672 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 413150775 ps |
| CPU time | 8.55 seconds |
| Started | Dec 24 01:12:01 PM PST 23 |
| Finished | Dec 24 01:12:16 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-6de0bad0-b8ee-4703-8e3e-47c1a8ce9cdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=956541672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.956541672 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.469074862 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 8149639 ps |
| CPU time | 1.4 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:13:24 PM PST 23 |
| Peak memory | 201384 kb |
| Host | smart-fa4d9b00-3eaf-49a3-a19b-d6cf3ef726ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=469074862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.469074862 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.925378043 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 36303532005 ps |
| CPU time | 154.95 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:15:57 PM PST 23 |
| Peak memory | 202564 kb |
| Host | smart-760ebf72-ce5c-4f88-8a9e-bae67f7cf18a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=925378043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slo w_rsp.925378043 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3095525889 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 896805346 ps |
| CPU time | 5.7 seconds |
| Started | Dec 24 01:13:17 PM PST 23 |
| Finished | Dec 24 01:13:38 PM PST 23 |
| Peak memory | 201500 kb |
| Host | smart-86f9a235-2de5-4cde-bb45-07ce154c4079 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3095525889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3095525889 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.415433956 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 442136228 ps |
| CPU time | 7.01 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:29 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-74513e7b-2573-4568-97eb-8a2d27f1dadc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=415433956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.415433956 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.1039846797 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 39154932 ps |
| CPU time | 2.58 seconds |
| Started | Dec 24 01:13:04 PM PST 23 |
| Finished | Dec 24 01:13:22 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-c8e0b359-0fab-42f1-bcc4-f1d63d069624 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1039846797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1039846797 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.473262578 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 28994947168 ps |
| CPU time | 123.76 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:15:26 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-3e1ec9d9-ef91-4d36-b0e6-8b6933e37106 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=473262578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.473262578 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3870967037 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 31858035259 ps |
| CPU time | 121.04 seconds |
| Started | Dec 24 01:13:15 PM PST 23 |
| Finished | Dec 24 01:15:31 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-2c996a8a-c3ed-4f37-81fe-77b8ff329ce1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3870967037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3870967037 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3913530469 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 73162543 ps |
| CPU time | 5.56 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-5dedf4d8-e699-4f1d-9a5b-ecbdce9003dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913530469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3913530469 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.2445400502 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 179954647 ps |
| CPU time | 1.63 seconds |
| Started | Dec 24 01:13:16 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-effd9dc9-c398-4632-83b0-063146ea751b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2445400502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2445400502 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.1796905839 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 7950581 ps |
| CPU time | 1.07 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:23 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-edd8c837-148a-449e-8e05-353013eae2f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1796905839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1796905839 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1233943487 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3085730204 ps |
| CPU time | 9.77 seconds |
| Started | Dec 24 01:13:15 PM PST 23 |
| Finished | Dec 24 01:13:40 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-bc6c7428-2adc-4c66-ab68-8f7e01f0778b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233943487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1233943487 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2187190335 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 4180213336 ps |
| CPU time | 6.99 seconds |
| Started | Dec 24 01:13:11 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 201760 kb |
| Host | smart-b92cb75a-1e7c-4bfa-9656-10f33f3cfd63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2187190335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2187190335 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2015109254 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 16149868 ps |
| CPU time | 1.12 seconds |
| Started | Dec 24 01:13:20 PM PST 23 |
| Finished | Dec 24 01:13:36 PM PST 23 |
| Peak memory | 201376 kb |
| Host | smart-5168bf73-b968-4d96-a33e-5a3f70b60a9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015109254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2015109254 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2353402189 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 10471602222 ps |
| CPU time | 68.52 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:14:37 PM PST 23 |
| Peak memory | 202588 kb |
| Host | smart-0b1b3b12-e994-4f35-a7e4-0bb1e00d31b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2353402189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2353402189 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2100012588 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1870065088 ps |
| CPU time | 15.77 seconds |
| Started | Dec 24 01:13:09 PM PST 23 |
| Finished | Dec 24 01:13:40 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-75c3d7c7-3850-4fc5-a211-4e8251cd51f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2100012588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2100012588 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1615714212 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 117230044 ps |
| CPU time | 14.14 seconds |
| Started | Dec 24 01:13:18 PM PST 23 |
| Finished | Dec 24 01:13:47 PM PST 23 |
| Peak memory | 202316 kb |
| Host | smart-8ab8b0b7-6391-4454-a6b6-c3797b252f6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1615714212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.1615714212 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.947626197 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 202041251 ps |
| CPU time | 13.56 seconds |
| Started | Dec 24 01:13:11 PM PST 23 |
| Finished | Dec 24 01:13:40 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-33702bcc-810b-43dc-8f35-fa4f6833f83e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=947626197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_res et_error.947626197 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.1962929099 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 146756877 ps |
| CPU time | 4.13 seconds |
| Started | Dec 24 01:13:10 PM PST 23 |
| Finished | Dec 24 01:13:30 PM PST 23 |
| Peak memory | 201500 kb |
| Host | smart-880fe961-8529-4795-ae28-cdc30c0b2c3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1962929099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1962929099 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1515762107 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 6925676235 ps |
| CPU time | 14.91 seconds |
| Started | Dec 24 01:13:11 PM PST 23 |
| Finished | Dec 24 01:13:41 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-9f567051-7b55-466a-8bcb-aa48005ba91e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1515762107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1515762107 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2954857254 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 113381350880 ps |
| CPU time | 228.27 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:17:15 PM PST 23 |
| Peak memory | 202776 kb |
| Host | smart-e631f5ce-6992-4deb-910c-51ff7ffcbf1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2954857254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.2954857254 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1938416841 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 128794692 ps |
| CPU time | 6.06 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:13:34 PM PST 23 |
| Peak memory | 201332 kb |
| Host | smart-7f5ed5a7-a574-4b00-9106-325887bc267d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1938416841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1938416841 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.23120415 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 253036980 ps |
| CPU time | 5.25 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:27 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-06cab611-9807-4f1e-9912-d66b45106679 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=23120415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.23120415 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.2218395111 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 1361513502 ps |
| CPU time | 16.52 seconds |
| Started | Dec 24 01:13:21 PM PST 23 |
| Finished | Dec 24 01:13:55 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-61614b25-4139-45a0-91a8-45326212cbc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2218395111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2218395111 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.590862066 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 16400665549 ps |
| CPU time | 20.06 seconds |
| Started | Dec 24 01:13:15 PM PST 23 |
| Finished | Dec 24 01:13:50 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-71927906-9466-4ee2-a35b-edaa0bb2598d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=590862066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.590862066 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1206483655 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4127390971 ps |
| CPU time | 21.9 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:13:44 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-561cf5d5-d3a4-4e97-8eef-38817e17948e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1206483655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1206483655 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3511102447 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 36598810 ps |
| CPU time | 3.96 seconds |
| Started | Dec 24 01:13:13 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-f6a5a7e5-3b60-45e0-99fd-c093b65c2bc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511102447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3511102447 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.609304979 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 690730679 ps |
| CPU time | 7.42 seconds |
| Started | Dec 24 01:13:11 PM PST 23 |
| Finished | Dec 24 01:13:34 PM PST 23 |
| Peak memory | 201272 kb |
| Host | smart-a2211177-ca8d-4367-935b-dd97c434943b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=609304979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.609304979 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.74937578 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 10253574 ps |
| CPU time | 1.22 seconds |
| Started | Dec 24 01:13:07 PM PST 23 |
| Finished | Dec 24 01:13:24 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-1eb6575b-6f6d-4530-a145-724989116ac3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=74937578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.74937578 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.4126240412 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3249481455 ps |
| CPU time | 9.43 seconds |
| Started | Dec 24 01:13:06 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-2c1c6e5a-8d95-4c9f-8312-27711257350d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126240412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.4126240412 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1137323137 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1673801271 ps |
| CPU time | 6.27 seconds |
| Started | Dec 24 01:13:17 PM PST 23 |
| Finished | Dec 24 01:13:44 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-842e5b74-b06b-4a74-84e2-d0d4ca5e9787 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1137323137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1137323137 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1779103256 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 19011084 ps |
| CPU time | 1.1 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-2a66bfcf-eb9d-4fb2-a6a5-50ab2eb2161a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779103256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1779103256 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3350457176 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 38466278666 ps |
| CPU time | 83.2 seconds |
| Started | Dec 24 01:13:10 PM PST 23 |
| Finished | Dec 24 01:14:49 PM PST 23 |
| Peak memory | 202488 kb |
| Host | smart-c38d71f6-83ae-4653-90a1-1201db892e69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3350457176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3350457176 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.431731936 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 7111814569 ps |
| CPU time | 56.7 seconds |
| Started | Dec 24 01:13:15 PM PST 23 |
| Finished | Dec 24 01:14:26 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-62058d9c-1c4c-401f-a3bf-8848206765a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=431731936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.431731936 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1455029087 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 249366150 ps |
| CPU time | 62.26 seconds |
| Started | Dec 24 01:13:11 PM PST 23 |
| Finished | Dec 24 01:14:28 PM PST 23 |
| Peak memory | 203808 kb |
| Host | smart-22c9a290-e60c-4e13-8e20-c40a1d13eed5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1455029087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1455029087 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.959500321 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1291479958 ps |
| CPU time | 132.89 seconds |
| Started | Dec 24 01:13:13 PM PST 23 |
| Finished | Dec 24 01:15:41 PM PST 23 |
| Peak memory | 208124 kb |
| Host | smart-51e75099-ee18-4079-be99-fbf77f993996 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=959500321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_res et_error.959500321 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1050853660 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 517216771 ps |
| CPU time | 2.11 seconds |
| Started | Dec 24 01:13:11 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201672 kb |
| Host | smart-7e568c52-1ef0-45c7-a299-b360513368ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1050853660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1050853660 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2640556967 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 83558544 ps |
| CPU time | 12.01 seconds |
| Started | Dec 24 01:13:21 PM PST 23 |
| Finished | Dec 24 01:13:47 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-3e442b75-bd42-46bd-a64d-29fc4e25e3d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2640556967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2640556967 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.505753283 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 34341883268 ps |
| CPU time | 256.2 seconds |
| Started | Dec 24 01:13:16 PM PST 23 |
| Finished | Dec 24 01:17:48 PM PST 23 |
| Peak memory | 203520 kb |
| Host | smart-375c8077-b5f7-4bd4-b086-695eac5a9a1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=505753283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slo w_rsp.505753283 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3670403143 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 991733341 ps |
| CPU time | 5.16 seconds |
| Started | Dec 24 01:13:33 PM PST 23 |
| Finished | Dec 24 01:13:47 PM PST 23 |
| Peak memory | 201336 kb |
| Host | smart-f3f7d3d2-6df1-489c-a7bc-41e62e106f5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3670403143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3670403143 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.2334864058 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 481431866 ps |
| CPU time | 8.99 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:36 PM PST 23 |
| Peak memory | 201388 kb |
| Host | smart-8a1f3935-c062-41d6-ad4c-4f7464ae90ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2334864058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2334864058 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.3720990385 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1581749651 ps |
| CPU time | 10.07 seconds |
| Started | Dec 24 01:13:10 PM PST 23 |
| Finished | Dec 24 01:13:36 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-56832a29-f566-49cf-8cfb-dc41e3a23ce5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3720990385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3720990385 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1663337750 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1435506485 ps |
| CPU time | 7.57 seconds |
| Started | Dec 24 01:13:11 PM PST 23 |
| Finished | Dec 24 01:13:34 PM PST 23 |
| Peak memory | 201504 kb |
| Host | smart-417470d5-d0b1-4e8f-b234-15d5a1e8f303 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663337750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1663337750 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1030824945 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 22724474454 ps |
| CPU time | 145.08 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:15:52 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-2ff2ce0b-ba64-4def-b68e-b029548ead0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1030824945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1030824945 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.2736123182 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 97523266 ps |
| CPU time | 3.8 seconds |
| Started | Dec 24 01:13:15 PM PST 23 |
| Finished | Dec 24 01:13:34 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-a0b90df8-91d0-4e86-b057-6d3847c9bc06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736123182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2736123182 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.1138404949 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 839388194 ps |
| CPU time | 10.81 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:13:39 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-e5b34db2-8877-4fe1-a975-df10cd772470 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1138404949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1138404949 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.3771341495 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 48207373 ps |
| CPU time | 1.6 seconds |
| Started | Dec 24 01:13:18 PM PST 23 |
| Finished | Dec 24 01:13:34 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-bd4574d7-c634-4991-b411-c4063fe54e05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3771341495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3771341495 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.4049961945 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 20978187888 ps |
| CPU time | 14.56 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:42 PM PST 23 |
| Peak memory | 201564 kb |
| Host | smart-52cfa543-10ec-4e0d-8da4-485bd694eb0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049961945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.4049961945 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1913843619 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1094485887 ps |
| CPU time | 6.84 seconds |
| Started | Dec 24 01:13:10 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-86af2f3b-4c51-4527-af39-d03c40c380c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1913843619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1913843619 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1255536148 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 7915553 ps |
| CPU time | 1.1 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:13:28 PM PST 23 |
| Peak memory | 201224 kb |
| Host | smart-3faf9541-366a-406f-b81e-c84f50014b24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255536148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1255536148 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.2301253853 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 874579131 ps |
| CPU time | 4.12 seconds |
| Started | Dec 24 01:13:13 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 201364 kb |
| Host | smart-c246ed24-6e26-4200-a25a-8a167a34367f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2301253853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2301253853 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1002332447 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 5711930080 ps |
| CPU time | 40.58 seconds |
| Started | Dec 24 01:13:23 PM PST 23 |
| Finished | Dec 24 01:14:18 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-84ff2e73-c2d3-4051-b1ed-013016dcc58d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1002332447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1002332447 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3805582624 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 123421949 ps |
| CPU time | 30.69 seconds |
| Started | Dec 24 01:13:22 PM PST 23 |
| Finished | Dec 24 01:14:06 PM PST 23 |
| Peak memory | 203428 kb |
| Host | smart-e663cccb-55fd-42f4-8658-1dacea24c194 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3805582624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.3805582624 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1404427575 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1978427222 ps |
| CPU time | 38.32 seconds |
| Started | Dec 24 01:13:15 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 202392 kb |
| Host | smart-cac308fc-de4f-46b9-98a7-ab4d90dd115a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1404427575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.1404427575 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1972780627 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 30130162 ps |
| CPU time | 1.9 seconds |
| Started | Dec 24 01:13:31 PM PST 23 |
| Finished | Dec 24 01:13:43 PM PST 23 |
| Peak memory | 201360 kb |
| Host | smart-232fb0ae-e9a2-4913-b37e-b627fac0fb3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1972780627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1972780627 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.303555361 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 28485375 ps |
| CPU time | 5.87 seconds |
| Started | Dec 24 01:13:23 PM PST 23 |
| Finished | Dec 24 01:13:42 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-061fa845-1c65-42c5-8694-624d2c55ed90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=303555361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.303555361 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1724916635 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 108707230 ps |
| CPU time | 2.24 seconds |
| Started | Dec 24 01:13:34 PM PST 23 |
| Finished | Dec 24 01:13:44 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-1b22272a-33f1-4c09-a3ab-ab13a2fb2170 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1724916635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1724916635 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.2776167762 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 104565964 ps |
| CPU time | 1.99 seconds |
| Started | Dec 24 01:13:13 PM PST 23 |
| Finished | Dec 24 01:13:30 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-0a8a87ad-fece-46a9-a6e7-fe4cdf8e84ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2776167762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2776167762 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2005729050 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 77142668 ps |
| CPU time | 2.73 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-77bf9e98-bee3-42b5-bd16-51fe73a75c53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2005729050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2005729050 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3928286508 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 74641376065 ps |
| CPU time | 131.51 seconds |
| Started | Dec 24 01:13:17 PM PST 23 |
| Finished | Dec 24 01:15:43 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-572e3406-29b3-4b08-ab83-437d95147e72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928286508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3928286508 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3797733549 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 35522268053 ps |
| CPU time | 150.96 seconds |
| Started | Dec 24 01:13:28 PM PST 23 |
| Finished | Dec 24 01:16:10 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-b25f44a2-94ea-448f-b900-242eb8aa1d83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3797733549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3797733549 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1401007696 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 52955783 ps |
| CPU time | 4.09 seconds |
| Started | Dec 24 01:13:15 PM PST 23 |
| Finished | Dec 24 01:13:33 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-3d8c458e-3a9c-4dd7-80c3-9c4a2fa89bef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401007696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1401007696 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.1724854788 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 95246299 ps |
| CPU time | 3.71 seconds |
| Started | Dec 24 01:13:35 PM PST 23 |
| Finished | Dec 24 01:13:47 PM PST 23 |
| Peak memory | 201428 kb |
| Host | smart-2ee84c4f-6e1a-41d1-bd39-15980eaefd40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1724854788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1724854788 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.1150743279 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 125482765 ps |
| CPU time | 1.39 seconds |
| Started | Dec 24 01:13:23 PM PST 23 |
| Finished | Dec 24 01:13:38 PM PST 23 |
| Peak memory | 201436 kb |
| Host | smart-b02bca33-0cca-4402-8281-885935fb09fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1150743279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1150743279 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.4137583729 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 5900533356 ps |
| CPU time | 8.3 seconds |
| Started | Dec 24 01:13:16 PM PST 23 |
| Finished | Dec 24 01:13:39 PM PST 23 |
| Peak memory | 201436 kb |
| Host | smart-14024a79-3e06-46d9-80a3-fc1b9600cc7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137583729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4137583729 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1546130863 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2314430785 ps |
| CPU time | 11.52 seconds |
| Started | Dec 24 01:13:26 PM PST 23 |
| Finished | Dec 24 01:13:50 PM PST 23 |
| Peak memory | 201460 kb |
| Host | smart-531837bd-ec25-4099-ad29-ec873b7c9ff1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1546130863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1546130863 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3370765053 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 17387504 ps |
| CPU time | 1.31 seconds |
| Started | Dec 24 01:13:20 PM PST 23 |
| Finished | Dec 24 01:13:36 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-72d6a696-0f40-4e71-a204-033bd7a090e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370765053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3370765053 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3204107297 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 3382275683 ps |
| CPU time | 10.96 seconds |
| Started | Dec 24 01:13:19 PM PST 23 |
| Finished | Dec 24 01:13:45 PM PST 23 |
| Peak memory | 201324 kb |
| Host | smart-8a38e6be-c30b-4772-a45c-2b9ba60844e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3204107297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3204107297 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2775308383 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 13334633151 ps |
| CPU time | 38.03 seconds |
| Started | Dec 24 01:13:17 PM PST 23 |
| Finished | Dec 24 01:14:09 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-51d7a261-7c26-40d0-a127-43b2f20b0139 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2775308383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2775308383 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1356850248 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1551234998 ps |
| CPU time | 77.19 seconds |
| Started | Dec 24 01:13:19 PM PST 23 |
| Finished | Dec 24 01:14:50 PM PST 23 |
| Peak memory | 203452 kb |
| Host | smart-16ce7ecb-11e9-4bcc-9b45-586605a638cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1356850248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.1356850248 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.1402246898 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 40773937 ps |
| CPU time | 4.99 seconds |
| Started | Dec 24 01:13:29 PM PST 23 |
| Finished | Dec 24 01:13:44 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-94d79b11-66ef-46c0-8571-473b5148ab2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1402246898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.1402246898 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3325038074 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 930643930 ps |
| CPU time | 5.32 seconds |
| Started | Dec 24 01:13:15 PM PST 23 |
| Finished | Dec 24 01:13:34 PM PST 23 |
| Peak memory | 201384 kb |
| Host | smart-799dec46-ae10-40b5-9ff0-e173e73509e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3325038074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3325038074 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3477385505 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1858127478 ps |
| CPU time | 8.96 seconds |
| Started | Dec 24 01:13:25 PM PST 23 |
| Finished | Dec 24 01:13:47 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-6a4f575f-1b09-4bc8-b9bf-66465f4b859b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3477385505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3477385505 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1143215222 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 5448912816 ps |
| CPU time | 37.26 seconds |
| Started | Dec 24 01:13:37 PM PST 23 |
| Finished | Dec 24 01:14:21 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-409bb374-fd1d-44a0-9270-6303e163e8f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1143215222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.1143215222 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2959710056 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 1612803592 ps |
| CPU time | 10.36 seconds |
| Started | Dec 24 01:13:21 PM PST 23 |
| Finished | Dec 24 01:13:48 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-4ab7de85-80ef-4db7-97ef-751337f22805 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2959710056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2959710056 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.2048337545 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 193520522 ps |
| CPU time | 3.33 seconds |
| Started | Dec 24 01:13:29 PM PST 23 |
| Finished | Dec 24 01:13:43 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-857f7a94-b1d0-4a5e-a7ab-5e295f71c679 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2048337545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2048337545 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.3264594565 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 44681336 ps |
| CPU time | 5.24 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:13:34 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-5e6b1c0e-eb01-4401-9523-e22da3af1d38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3264594565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3264594565 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.170054965 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 29783167743 ps |
| CPU time | 128.46 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:15:36 PM PST 23 |
| Peak memory | 201536 kb |
| Host | smart-34014757-0885-4926-b4ab-01621dc64524 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=170054965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.170054965 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1343846152 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 5552944056 ps |
| CPU time | 22.75 seconds |
| Started | Dec 24 01:13:26 PM PST 23 |
| Finished | Dec 24 01:14:01 PM PST 23 |
| Peak memory | 201572 kb |
| Host | smart-6e34a809-cca5-4139-b81e-e24a3cda8916 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1343846152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1343846152 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3344998392 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 14554608 ps |
| CPU time | 1.43 seconds |
| Started | Dec 24 01:13:16 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-eca92d19-cd18-4c37-a844-5325906758ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344998392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3344998392 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.2291868213 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 763143053 ps |
| CPU time | 10.6 seconds |
| Started | Dec 24 01:13:29 PM PST 23 |
| Finished | Dec 24 01:13:50 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-a2dc8fa5-9b91-4b7a-9a42-a20a3592262e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2291868213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2291868213 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.2758784344 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 255048750 ps |
| CPU time | 1.52 seconds |
| Started | Dec 24 01:13:19 PM PST 23 |
| Finished | Dec 24 01:13:35 PM PST 23 |
| Peak memory | 201268 kb |
| Host | smart-90efb848-afef-44db-b9e6-640e955c8e27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2758784344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2758784344 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1998197102 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1756067592 ps |
| CPU time | 8.08 seconds |
| Started | Dec 24 01:13:27 PM PST 23 |
| Finished | Dec 24 01:13:47 PM PST 23 |
| Peak memory | 201380 kb |
| Host | smart-499bfe06-a502-42cd-888a-d18f36ee4a64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998197102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1998197102 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.868975129 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1230278129 ps |
| CPU time | 7.59 seconds |
| Started | Dec 24 01:13:19 PM PST 23 |
| Finished | Dec 24 01:13:41 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-3798f211-7173-448c-bd25-0e9bc74df7c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=868975129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.868975129 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3236605162 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 9113160 ps |
| CPU time | 1.19 seconds |
| Started | Dec 24 01:13:23 PM PST 23 |
| Finished | Dec 24 01:13:38 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-f690005e-c948-47e2-b068-0a48aa8276f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236605162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3236605162 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.855402460 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 312633679 ps |
| CPU time | 35.44 seconds |
| Started | Dec 24 01:13:12 PM PST 23 |
| Finished | Dec 24 01:14:02 PM PST 23 |
| Peak memory | 202416 kb |
| Host | smart-84ef37d9-f4f6-4b8f-8fc8-11585dba42dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=855402460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.855402460 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1954093291 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 280733650 ps |
| CPU time | 24.04 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:13:53 PM PST 23 |
| Peak memory | 199988 kb |
| Host | smart-e86dce35-5ee9-488b-8489-bf87b8319528 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1954093291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1954093291 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2186355859 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 962137170 ps |
| CPU time | 203.4 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:16:52 PM PST 23 |
| Peak memory | 208584 kb |
| Host | smart-5dd62a1c-f9b7-4a95-9d75-5c232922eb4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2186355859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.2186355859 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.4086431278 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1082332634 ps |
| CPU time | 111.42 seconds |
| Started | Dec 24 01:13:31 PM PST 23 |
| Finished | Dec 24 01:15:32 PM PST 23 |
| Peak memory | 205088 kb |
| Host | smart-a6be6d0b-c9ad-4769-96d0-aca7e50280d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4086431278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.4086431278 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.1941029645 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 927363935 ps |
| CPU time | 10.96 seconds |
| Started | Dec 24 01:13:26 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-7f3479c2-0078-4427-ac4a-a160f7d0ff25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1941029645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1941029645 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2828091770 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 160432697 ps |
| CPU time | 2.86 seconds |
| Started | Dec 24 01:13:23 PM PST 23 |
| Finished | Dec 24 01:13:39 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-df3bda96-e45f-4e4f-8fed-9697c0d78bd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2828091770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2828091770 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.715610255 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 32864103432 ps |
| CPU time | 247.34 seconds |
| Started | Dec 24 01:13:20 PM PST 23 |
| Finished | Dec 24 01:17:42 PM PST 23 |
| Peak memory | 202492 kb |
| Host | smart-fc087171-7803-4d80-baa0-bc8614eaec79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=715610255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slo w_rsp.715610255 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2738239539 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 133260090 ps |
| CPU time | 5.37 seconds |
| Started | Dec 24 01:13:28 PM PST 23 |
| Finished | Dec 24 01:13:44 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-c7a67ce6-c88f-46a2-9f2a-e4349db5a21b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2738239539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2738239539 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.1309121932 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 469714101 ps |
| CPU time | 9.17 seconds |
| Started | Dec 24 01:13:19 PM PST 23 |
| Finished | Dec 24 01:13:43 PM PST 23 |
| Peak memory | 201264 kb |
| Host | smart-c2cfbc11-d457-4196-a7ee-a9f78c20f5ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1309121932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1309121932 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.834852961 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1475423008 ps |
| CPU time | 12.23 seconds |
| Started | Dec 24 01:13:22 PM PST 23 |
| Finished | Dec 24 01:13:48 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-59036839-4a6f-4224-82f5-d0c194306863 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=834852961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.834852961 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.307683663 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 42284896454 ps |
| CPU time | 65.17 seconds |
| Started | Dec 24 01:13:54 PM PST 23 |
| Finished | Dec 24 01:15:03 PM PST 23 |
| Peak memory | 201524 kb |
| Host | smart-e6661ab6-2c41-48b6-87ae-90123f0f5b5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=307683663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.307683663 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3117004038 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 46455460296 ps |
| CPU time | 163.73 seconds |
| Started | Dec 24 01:13:35 PM PST 23 |
| Finished | Dec 24 01:16:26 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-7777c378-1201-4b3e-9ca4-6d09f87d0a30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3117004038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3117004038 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1839545362 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 42023801 ps |
| CPU time | 6.43 seconds |
| Started | Dec 24 01:13:23 PM PST 23 |
| Finished | Dec 24 01:13:43 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-7dab0fe3-e437-4d64-b6f3-a1ea265ab09b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839545362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1839545362 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.3623901126 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 900602352 ps |
| CPU time | 5.74 seconds |
| Started | Dec 24 01:13:37 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-07fadf52-f78c-46ba-bacd-10805b8b512b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3623901126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3623901126 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.2922476071 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 130436573 ps |
| CPU time | 1.52 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:13:30 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-5ca424e7-2633-40b2-be21-18928969dca5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2922476071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2922476071 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1621778226 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2759654813 ps |
| CPU time | 9.1 seconds |
| Started | Dec 24 01:13:27 PM PST 23 |
| Finished | Dec 24 01:13:48 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-e1128e7c-7b5f-4f09-b1c2-6f1a719657bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621778226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1621778226 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.4174785043 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 856670996 ps |
| CPU time | 6.16 seconds |
| Started | Dec 24 01:13:14 PM PST 23 |
| Finished | Dec 24 01:13:35 PM PST 23 |
| Peak memory | 200092 kb |
| Host | smart-216a305a-e08f-46f4-9579-c6aaf703b0ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4174785043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.4174785043 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3876838478 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 10853912 ps |
| CPU time | 1.29 seconds |
| Started | Dec 24 01:13:22 PM PST 23 |
| Finished | Dec 24 01:13:37 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-3a37cc9b-45ff-4a0f-a119-414710d6aa33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876838478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3876838478 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.424489415 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3710923607 ps |
| CPU time | 8.4 seconds |
| Started | Dec 24 01:13:17 PM PST 23 |
| Finished | Dec 24 01:13:40 PM PST 23 |
| Peak memory | 201536 kb |
| Host | smart-dd328278-94a2-4092-86fd-0ec077add803 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=424489415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.424489415 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3767064095 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 748774640 ps |
| CPU time | 11.77 seconds |
| Started | Dec 24 01:13:23 PM PST 23 |
| Finished | Dec 24 01:13:48 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-83f08ab0-c6c2-4009-bb30-36d07d059bce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3767064095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3767064095 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1952935118 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 760290407 ps |
| CPU time | 80.66 seconds |
| Started | Dec 24 01:13:27 PM PST 23 |
| Finished | Dec 24 01:14:59 PM PST 23 |
| Peak memory | 204756 kb |
| Host | smart-5e855935-6d23-4345-8b5a-c351d776e66a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1952935118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.1952935118 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3318390859 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1350724255 ps |
| CPU time | 122.78 seconds |
| Started | Dec 24 01:13:17 PM PST 23 |
| Finished | Dec 24 01:15:34 PM PST 23 |
| Peak memory | 206392 kb |
| Host | smart-da09a2fa-a16a-41d7-b1c0-b396b61d0d4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3318390859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.3318390859 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3569223019 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1111060310 ps |
| CPU time | 10.38 seconds |
| Started | Dec 24 01:13:27 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 201392 kb |
| Host | smart-0cb1cff6-3bd8-487b-99a7-3454066da0c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3569223019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3569223019 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3610321124 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1629167474 ps |
| CPU time | 19.04 seconds |
| Started | Dec 24 01:13:40 PM PST 23 |
| Finished | Dec 24 01:14:05 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-2ea13f70-3341-401a-8ae0-64a73026f9d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3610321124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3610321124 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2220590224 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 20859962736 ps |
| CPU time | 67.42 seconds |
| Started | Dec 24 01:13:37 PM PST 23 |
| Finished | Dec 24 01:14:51 PM PST 23 |
| Peak memory | 201568 kb |
| Host | smart-42ad22be-1fe3-4b96-9506-2524dd40f794 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2220590224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.2220590224 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3202333767 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 157964505 ps |
| CPU time | 3.01 seconds |
| Started | Dec 24 01:13:38 PM PST 23 |
| Finished | Dec 24 01:13:47 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-420ba17c-25fe-4241-94a3-de75bd252367 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3202333767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3202333767 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.629997553 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 435465686 ps |
| CPU time | 4.41 seconds |
| Started | Dec 24 01:13:37 PM PST 23 |
| Finished | Dec 24 01:13:48 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-4f0995df-5821-473f-8880-b559fc4b7ab0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=629997553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.629997553 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.1860992524 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 183810459 ps |
| CPU time | 2.79 seconds |
| Started | Dec 24 01:13:41 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-c162d705-d424-412a-a77b-329f7aa76eb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1860992524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1860992524 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1589694758 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 7417672437 ps |
| CPU time | 25.62 seconds |
| Started | Dec 24 01:13:30 PM PST 23 |
| Finished | Dec 24 01:14:06 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-e0b2115b-478b-4524-835b-86fa57a2d4d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589694758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1589694758 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3683723386 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 15655563274 ps |
| CPU time | 83.52 seconds |
| Started | Dec 24 01:13:54 PM PST 23 |
| Finished | Dec 24 01:15:21 PM PST 23 |
| Peak memory | 201564 kb |
| Host | smart-b23ee4fd-103b-4e96-b505-69fea0643664 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3683723386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3683723386 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.4122076440 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 32808161 ps |
| CPU time | 5.36 seconds |
| Started | Dec 24 01:13:30 PM PST 23 |
| Finished | Dec 24 01:13:46 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-a3650273-7821-41ae-bb0c-2c8c98138f73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122076440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.4122076440 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.2584119027 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 350388925 ps |
| CPU time | 4.66 seconds |
| Started | Dec 24 01:13:55 PM PST 23 |
| Finished | Dec 24 01:14:03 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-0ac8a470-2351-48de-a927-010738ed200f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2584119027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2584119027 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.2168812540 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 20500873 ps |
| CPU time | 1.08 seconds |
| Started | Dec 24 01:13:31 PM PST 23 |
| Finished | Dec 24 01:13:42 PM PST 23 |
| Peak memory | 201388 kb |
| Host | smart-8d3e38a1-003a-4284-b746-05c380f6a0e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2168812540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2168812540 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3446016633 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2299447109 ps |
| CPU time | 8.38 seconds |
| Started | Dec 24 01:13:25 PM PST 23 |
| Finished | Dec 24 01:13:46 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-4042cadb-7557-481e-9b8f-dde003b8d044 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446016633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3446016633 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1842582751 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1003568171 ps |
| CPU time | 5.04 seconds |
| Started | Dec 24 01:13:30 PM PST 23 |
| Finished | Dec 24 01:13:45 PM PST 23 |
| Peak memory | 201372 kb |
| Host | smart-408204f4-cf6f-4066-b4a0-6f5f45225cf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1842582751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1842582751 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.890742185 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 11634046 ps |
| CPU time | 1.22 seconds |
| Started | Dec 24 01:13:27 PM PST 23 |
| Finished | Dec 24 01:13:40 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-14118e9e-755f-4085-8d22-107d6621132b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890742185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.890742185 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.4127114239 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 271317399 ps |
| CPU time | 24.94 seconds |
| Started | Dec 24 01:13:48 PM PST 23 |
| Finished | Dec 24 01:14:19 PM PST 23 |
| Peak memory | 202084 kb |
| Host | smart-93f4db41-1569-4e9c-8807-c3488072f4df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4127114239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.4127114239 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2149627182 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 18483361293 ps |
| CPU time | 58.86 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:15:00 PM PST 23 |
| Peak memory | 202644 kb |
| Host | smart-e14af993-6519-443f-b841-e2cd19307924 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2149627182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2149627182 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2677612184 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1128590566 ps |
| CPU time | 113.24 seconds |
| Started | Dec 24 01:13:39 PM PST 23 |
| Finished | Dec 24 01:15:38 PM PST 23 |
| Peak memory | 203824 kb |
| Host | smart-74ecedea-f543-42e6-8002-eab8c6a18523 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2677612184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.2677612184 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.4169416697 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2187795416 ps |
| CPU time | 80.95 seconds |
| Started | Dec 24 01:13:51 PM PST 23 |
| Finished | Dec 24 01:15:17 PM PST 23 |
| Peak memory | 205176 kb |
| Host | smart-a8211e9d-795e-4412-a01c-d59f65ea1cdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4169416697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.4169416697 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.3456973555 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 83811183 ps |
| CPU time | 4.93 seconds |
| Started | Dec 24 01:13:44 PM PST 23 |
| Finished | Dec 24 01:13:56 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-ce5307dc-6c2c-44f9-98c0-a49484fd3a98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3456973555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3456973555 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1645065972 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 88594983 ps |
| CPU time | 6.69 seconds |
| Started | Dec 24 01:14:00 PM PST 23 |
| Finished | Dec 24 01:14:17 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-74153ac1-605a-40bf-98dc-ff9a2b2d05ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1645065972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1645065972 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.250467237 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 14899040469 ps |
| CPU time | 90.28 seconds |
| Started | Dec 24 01:14:11 PM PST 23 |
| Finished | Dec 24 01:15:57 PM PST 23 |
| Peak memory | 201564 kb |
| Host | smart-9b97e0fd-2742-4250-bb6b-99a6f5ff14fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=250467237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slo w_rsp.250467237 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3863094250 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 929167064 ps |
| CPU time | 5.23 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:12 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-3dd9902f-15ff-450b-b280-60464cb02223 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3863094250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3863094250 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.3612027554 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 970005959 ps |
| CPU time | 12.19 seconds |
| Started | Dec 24 01:14:08 PM PST 23 |
| Finished | Dec 24 01:14:37 PM PST 23 |
| Peak memory | 201360 kb |
| Host | smart-ffc95084-1ebc-4b9b-9d5f-a5fc7c2192fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3612027554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3612027554 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.2020825827 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 37041573 ps |
| CPU time | 5.11 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:14 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-f19392ee-75f8-4db8-b9fe-c403431b9e07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2020825827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2020825827 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1844714523 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2830383110 ps |
| CPU time | 8.02 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-5b8867eb-43b4-4391-8679-875bcd0d6d44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844714523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1844714523 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2761903583 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3569333438 ps |
| CPU time | 12.17 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:18 PM PST 23 |
| Peak memory | 201440 kb |
| Host | smart-ef56a7f6-36c1-42d5-81c4-7de60e5019df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2761903583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2761903583 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3817307051 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 185609730 ps |
| CPU time | 4.17 seconds |
| Started | Dec 24 01:13:40 PM PST 23 |
| Finished | Dec 24 01:13:50 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-34211971-a95d-4bda-a259-a9e1fa7e76fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817307051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3817307051 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.1383415932 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 29662691 ps |
| CPU time | 3.13 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:18 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-b0c0f03c-fab0-4816-97d4-fc93e55bf5ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1383415932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1383415932 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.775077821 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 250333110 ps |
| CPU time | 1.94 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:09 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-bb7ea3c6-bf28-482c-860b-535d7ad352a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=775077821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.775077821 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.291041316 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1188430117 ps |
| CPU time | 6.25 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-252514c9-bb98-4af9-bb9b-035b51d5d346 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=291041316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.291041316 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1971324268 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1152385057 ps |
| CPU time | 8.77 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 201512 kb |
| Host | smart-4377f094-04d2-4a7b-b9b9-33b28a97aea3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1971324268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1971324268 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2816415567 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 11068053 ps |
| CPU time | 1.01 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:02 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-e20c9e1b-5241-4699-91d1-b89c6b50bee2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816415567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2816415567 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3064997871 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 130896799 ps |
| CPU time | 13.25 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:23 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-eed5bba6-64e3-4fa3-8358-9526f15c27ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3064997871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3064997871 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1102538769 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 420555438 ps |
| CPU time | 41.18 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:45 PM PST 23 |
| Peak memory | 202500 kb |
| Host | smart-f3cd56b4-da1e-4f39-86c4-965d9b95928b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1102538769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1102538769 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1799317259 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2965221465 ps |
| CPU time | 115.81 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:16:01 PM PST 23 |
| Peak memory | 203652 kb |
| Host | smart-aa466c00-ca1a-49e9-8802-bc0fabadfbdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1799317259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.1799317259 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1173018299 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 2004918785 ps |
| CPU time | 21.44 seconds |
| Started | Dec 24 01:14:03 PM PST 23 |
| Finished | Dec 24 01:14:40 PM PST 23 |
| Peak memory | 202512 kb |
| Host | smart-de44bfb6-cc1b-47e8-bbe9-c7740e39eebe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1173018299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.1173018299 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2904138569 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 40972148 ps |
| CPU time | 4.36 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:04 PM PST 23 |
| Peak memory | 201376 kb |
| Host | smart-39847f50-e46a-4d47-8498-18746179efe2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2904138569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2904138569 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1567402540 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2549353101 ps |
| CPU time | 18.52 seconds |
| Started | Dec 24 01:13:28 PM PST 23 |
| Finished | Dec 24 01:13:58 PM PST 23 |
| Peak memory | 201536 kb |
| Host | smart-b4b7416e-7230-482c-84de-75c85bacd366 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1567402540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1567402540 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2425894983 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 52903763741 ps |
| CPU time | 203.87 seconds |
| Started | Dec 24 01:13:32 PM PST 23 |
| Finished | Dec 24 01:17:05 PM PST 23 |
| Peak memory | 203816 kb |
| Host | smart-613c7756-0c3f-4441-af73-52bb52d008bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2425894983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.2425894983 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3444598356 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 30427865 ps |
| CPU time | 3.21 seconds |
| Started | Dec 24 01:13:23 PM PST 23 |
| Finished | Dec 24 01:13:40 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-2fec9675-9191-4285-8e3b-66acb0cbe2bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3444598356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3444598356 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2595020337 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 211743131 ps |
| CPU time | 4.11 seconds |
| Started | Dec 24 01:13:25 PM PST 23 |
| Finished | Dec 24 01:13:42 PM PST 23 |
| Peak memory | 201536 kb |
| Host | smart-9129d097-f1b0-46d1-9958-fad540954c89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2595020337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2595020337 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.3958788427 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 365254568 ps |
| CPU time | 6.84 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:13 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-6733abfb-36af-4d58-9d17-bed6628892e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3958788427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3958788427 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2574830575 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 37597933509 ps |
| CPU time | 155.86 seconds |
| Started | Dec 24 01:13:31 PM PST 23 |
| Finished | Dec 24 01:16:17 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-d97c564d-a89e-4039-b7a2-dd6d148c471a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574830575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2574830575 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2904583776 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 47494280012 ps |
| CPU time | 114.24 seconds |
| Started | Dec 24 01:13:22 PM PST 23 |
| Finished | Dec 24 01:15:30 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-f42dd3cc-1580-4fdb-abba-3d8644670d35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2904583776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2904583776 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3143840676 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 59207557 ps |
| CPU time | 7.82 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:23 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-e62a781a-0a51-4a36-8324-0d90920c7c3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143840676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3143840676 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.2982789756 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 10078621 ps |
| CPU time | 1.12 seconds |
| Started | Dec 24 01:13:19 PM PST 23 |
| Finished | Dec 24 01:13:35 PM PST 23 |
| Peak memory | 201260 kb |
| Host | smart-c0067836-fc01-4049-aaaf-15cc1577d5b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2982789756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2982789756 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.2361676086 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 98860888 ps |
| CPU time | 1.72 seconds |
| Started | Dec 24 01:14:00 PM PST 23 |
| Finished | Dec 24 01:14:12 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-40e96528-3ce9-4962-88e7-3324b2d68731 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2361676086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2361676086 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.156617342 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 11784962455 ps |
| CPU time | 9.39 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:16 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-2c6bad02-a3a5-44a5-9358-752df72a6874 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=156617342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.156617342 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1902868501 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 8071716160 ps |
| CPU time | 14.31 seconds |
| Started | Dec 24 01:13:17 PM PST 23 |
| Finished | Dec 24 01:13:46 PM PST 23 |
| Peak memory | 201436 kb |
| Host | smart-e6dd70d4-7c04-4935-9d62-e1a684622aff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1902868501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1902868501 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1773355653 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 8916422 ps |
| CPU time | 1.2 seconds |
| Started | Dec 24 01:14:06 PM PST 23 |
| Finished | Dec 24 01:14:23 PM PST 23 |
| Peak memory | 201364 kb |
| Host | smart-206ffb56-2391-4197-aaec-1c9b4d7cce27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773355653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1773355653 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.1686841044 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 398600438 ps |
| CPU time | 33.96 seconds |
| Started | Dec 24 01:13:31 PM PST 23 |
| Finished | Dec 24 01:14:15 PM PST 23 |
| Peak memory | 201408 kb |
| Host | smart-f6812b2b-e9d6-4c37-a310-0ca198caf895 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1686841044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1686841044 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2672448617 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 673614766 ps |
| CPU time | 29.77 seconds |
| Started | Dec 24 01:13:47 PM PST 23 |
| Finished | Dec 24 01:14:24 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-70ce68d0-b640-4602-a014-2c4f3a44e7e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2672448617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2672448617 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1783477956 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 322624797 ps |
| CPU time | 55.08 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:57 PM PST 23 |
| Peak memory | 204712 kb |
| Host | smart-46295e5e-a91b-402c-957c-adea6517c891 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1783477956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.1783477956 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1092863614 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 370891997 ps |
| CPU time | 45.43 seconds |
| Started | Dec 24 01:13:38 PM PST 23 |
| Finished | Dec 24 01:14:29 PM PST 23 |
| Peak memory | 203232 kb |
| Host | smart-68f95b0c-f140-47d5-8733-3a2b6941ad64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1092863614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.1092863614 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3948367904 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 213462896 ps |
| CPU time | 6.92 seconds |
| Started | Dec 24 01:13:23 PM PST 23 |
| Finished | Dec 24 01:13:44 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-bbc9e43d-8e7f-48d5-890d-5bccc5032460 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3948367904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3948367904 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1871644217 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 910221088 ps |
| CPU time | 19.03 seconds |
| Started | Dec 24 01:13:42 PM PST 23 |
| Finished | Dec 24 01:14:07 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-77776d63-8150-4d47-aca3-beb733bc9327 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1871644217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1871644217 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3852340318 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 31168378008 ps |
| CPU time | 85.18 seconds |
| Started | Dec 24 01:13:29 PM PST 23 |
| Finished | Dec 24 01:15:05 PM PST 23 |
| Peak memory | 201564 kb |
| Host | smart-9bb6d161-3b20-4738-92b2-4d2bdd03498a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3852340318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3852340318 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.4040567505 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 81917009 ps |
| CPU time | 1.96 seconds |
| Started | Dec 24 01:13:44 PM PST 23 |
| Finished | Dec 24 01:13:54 PM PST 23 |
| Peak memory | 201408 kb |
| Host | smart-b9805e19-4404-4405-8a36-43f49c477749 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4040567505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.4040567505 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.3397173829 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1555093662 ps |
| CPU time | 12.32 seconds |
| Started | Dec 24 01:13:34 PM PST 23 |
| Finished | Dec 24 01:13:55 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-ff79e6e7-dd13-4f18-b427-05cacae6f153 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3397173829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3397173829 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.1891063276 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 267740353 ps |
| CPU time | 1.77 seconds |
| Started | Dec 24 01:13:24 PM PST 23 |
| Finished | Dec 24 01:13:39 PM PST 23 |
| Peak memory | 201580 kb |
| Host | smart-4fd55271-d481-4d90-b4af-589ee728f213 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1891063276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1891063276 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.773091662 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 114409696852 ps |
| CPU time | 73.63 seconds |
| Started | Dec 24 01:13:24 PM PST 23 |
| Finished | Dec 24 01:14:51 PM PST 23 |
| Peak memory | 201544 kb |
| Host | smart-96218bb2-0a98-4567-83ad-fe797755fc34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=773091662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.773091662 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.4194145805 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 22046241497 ps |
| CPU time | 111.74 seconds |
| Started | Dec 24 01:13:25 PM PST 23 |
| Finished | Dec 24 01:15:30 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-00297361-32e1-42c6-84f8-ac5686d7b30d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4194145805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4194145805 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1516429611 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 115267448 ps |
| CPU time | 4.44 seconds |
| Started | Dec 24 01:13:31 PM PST 23 |
| Finished | Dec 24 01:13:45 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-6d3b4426-ed75-466f-a51f-6c79b0e417d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516429611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1516429611 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.728354027 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 55137393 ps |
| CPU time | 4.81 seconds |
| Started | Dec 24 01:13:42 PM PST 23 |
| Finished | Dec 24 01:13:53 PM PST 23 |
| Peak memory | 201500 kb |
| Host | smart-5dd819be-879d-4112-b757-b91c994f30ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=728354027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.728354027 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.2967348703 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 221676245 ps |
| CPU time | 1.57 seconds |
| Started | Dec 24 01:13:31 PM PST 23 |
| Finished | Dec 24 01:13:42 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-d9d1f98d-2c09-437d-976c-390b40c760aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2967348703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2967348703 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1203166913 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 1561053379 ps |
| CPU time | 6.24 seconds |
| Started | Dec 24 01:13:35 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-c6bb4a46-dc93-4649-b3f7-f39c77c12647 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203166913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1203166913 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1773397323 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4369890032 ps |
| CPU time | 8.22 seconds |
| Started | Dec 24 01:13:25 PM PST 23 |
| Finished | Dec 24 01:13:46 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-84eca37b-83db-449c-a2cf-4e4cfab29ba7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1773397323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1773397323 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2892581044 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 10639925 ps |
| CPU time | 1.16 seconds |
| Started | Dec 24 01:13:26 PM PST 23 |
| Finished | Dec 24 01:13:39 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-504e7c2d-a6d8-4023-ac19-ec9b273e91b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892581044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2892581044 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.2174498731 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 5103771600 ps |
| CPU time | 62.34 seconds |
| Started | Dec 24 01:13:43 PM PST 23 |
| Finished | Dec 24 01:14:52 PM PST 23 |
| Peak memory | 202548 kb |
| Host | smart-74c2ba3c-a019-4e2c-a06f-c96bbe27c254 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2174498731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2174498731 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2107021981 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 5709382119 ps |
| CPU time | 44.96 seconds |
| Started | Dec 24 01:13:32 PM PST 23 |
| Finished | Dec 24 01:14:26 PM PST 23 |
| Peak memory | 202588 kb |
| Host | smart-cb85d49b-bdb9-4e66-9fec-95154fd44b93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2107021981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2107021981 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2314989664 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1834247541 ps |
| CPU time | 105.26 seconds |
| Started | Dec 24 01:13:29 PM PST 23 |
| Finished | Dec 24 01:15:25 PM PST 23 |
| Peak memory | 203908 kb |
| Host | smart-76359ee8-c73f-4e5b-b37a-0625491b9dc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2314989664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.2314989664 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1384674038 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 917782443 ps |
| CPU time | 97.81 seconds |
| Started | Dec 24 01:13:30 PM PST 23 |
| Finished | Dec 24 01:15:18 PM PST 23 |
| Peak memory | 204776 kb |
| Host | smart-d7dbef06-c576-47fe-88a8-d5950a08cbdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1384674038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.1384674038 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3686574798 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 16052122 ps |
| CPU time | 1.68 seconds |
| Started | Dec 24 01:13:40 PM PST 23 |
| Finished | Dec 24 01:13:48 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-63a7b6d1-6cb6-4573-8041-8225d0b1fc51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3686574798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3686574798 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2127128487 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 107635129 ps |
| CPU time | 8.93 seconds |
| Started | Dec 24 01:12:07 PM PST 23 |
| Finished | Dec 24 01:12:25 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-c74e790d-d3d6-4c63-ac79-d607bc1e466f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2127128487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2127128487 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3746204436 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 34998897977 ps |
| CPU time | 264.08 seconds |
| Started | Dec 24 01:12:08 PM PST 23 |
| Finished | Dec 24 01:16:43 PM PST 23 |
| Peak memory | 202592 kb |
| Host | smart-f7680fca-85d5-4d4c-9e48-6a8b123e67ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3746204436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.3746204436 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1154923893 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 124941504 ps |
| CPU time | 5.79 seconds |
| Started | Dec 24 01:12:11 PM PST 23 |
| Finished | Dec 24 01:12:29 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-02fcb00d-a6af-4d2a-9bf3-f79069aeece5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1154923893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1154923893 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.322337270 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 430802806 ps |
| CPU time | 7.99 seconds |
| Started | Dec 24 01:12:05 PM PST 23 |
| Finished | Dec 24 01:12:21 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-9ea72245-a1e4-4b38-aa2a-467c93107d1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=322337270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.322337270 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.653812829 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 605056491 ps |
| CPU time | 10.56 seconds |
| Started | Dec 24 01:12:19 PM PST 23 |
| Finished | Dec 24 01:12:42 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-8b5afd6d-d5e6-4ccb-b373-e3b6534e60a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=653812829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.653812829 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2113349304 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 44341910763 ps |
| CPU time | 38.82 seconds |
| Started | Dec 24 01:12:08 PM PST 23 |
| Finished | Dec 24 01:12:58 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-f7a0e98b-14de-43ba-b318-c4e674e7c631 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113349304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2113349304 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.238944095 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 7528355760 ps |
| CPU time | 57.1 seconds |
| Started | Dec 24 01:12:06 PM PST 23 |
| Finished | Dec 24 01:13:11 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-b7f81891-a7ef-4890-ba7b-c63c20e93d58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=238944095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.238944095 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3057702081 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 53662275 ps |
| CPU time | 7.04 seconds |
| Started | Dec 24 01:12:09 PM PST 23 |
| Finished | Dec 24 01:12:26 PM PST 23 |
| Peak memory | 201360 kb |
| Host | smart-59f437bf-3df3-464e-bdad-f918a2d268ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057702081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3057702081 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.3749784055 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 586253511 ps |
| CPU time | 7.72 seconds |
| Started | Dec 24 01:12:21 PM PST 23 |
| Finished | Dec 24 01:12:46 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-7fb11b12-c9e1-4f84-9748-df79280c469f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3749784055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3749784055 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.2478462207 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 18942844 ps |
| CPU time | 1.05 seconds |
| Started | Dec 24 01:12:23 PM PST 23 |
| Finished | Dec 24 01:12:36 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-87fff225-585a-4022-8bbc-cf6e649390ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2478462207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2478462207 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1001540241 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 18207893918 ps |
| CPU time | 11.31 seconds |
| Started | Dec 24 01:12:12 PM PST 23 |
| Finished | Dec 24 01:12:35 PM PST 23 |
| Peak memory | 201512 kb |
| Host | smart-e89c68a7-df56-484b-8cbf-2cfa36319249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001540241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1001540241 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.312501543 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3625134910 ps |
| CPU time | 5.87 seconds |
| Started | Dec 24 01:12:08 PM PST 23 |
| Finished | Dec 24 01:12:24 PM PST 23 |
| Peak memory | 201524 kb |
| Host | smart-13b5a4f1-9e80-479f-8bc1-546c639bb3d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=312501543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.312501543 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.813655635 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 29215076 ps |
| CPU time | 1.13 seconds |
| Started | Dec 24 01:12:03 PM PST 23 |
| Finished | Dec 24 01:12:11 PM PST 23 |
| Peak memory | 201572 kb |
| Host | smart-77cea651-9eb1-4cfd-b9a9-fdc7f39b079d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813655635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.813655635 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.2964351382 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4093389900 ps |
| CPU time | 25.3 seconds |
| Started | Dec 24 01:12:17 PM PST 23 |
| Finished | Dec 24 01:12:54 PM PST 23 |
| Peak memory | 201500 kb |
| Host | smart-2110ee2d-f5cd-488a-a184-bf6210cf0fd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2964351382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2964351382 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2128719252 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 582717687 ps |
| CPU time | 34.41 seconds |
| Started | Dec 24 01:12:22 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-31e9052b-64cf-42b8-93d1-6d6235a398ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2128719252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2128719252 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.654867057 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 6768110380 ps |
| CPU time | 102.17 seconds |
| Started | Dec 24 01:12:18 PM PST 23 |
| Finished | Dec 24 01:14:12 PM PST 23 |
| Peak memory | 206516 kb |
| Host | smart-cffa1be3-1b60-4f2b-8388-01bc3909d47a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=654867057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_ reset.654867057 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3725854328 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12965935121 ps |
| CPU time | 217.69 seconds |
| Started | Dec 24 01:12:09 PM PST 23 |
| Finished | Dec 24 01:15:57 PM PST 23 |
| Peak memory | 207572 kb |
| Host | smart-c2916e73-873f-497e-a6e3-f908a1fcea50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3725854328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.3725854328 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1289433219 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 216187569 ps |
| CPU time | 3.33 seconds |
| Started | Dec 24 01:12:19 PM PST 23 |
| Finished | Dec 24 01:12:35 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-b0cdbea7-80a2-4047-8f74-a5b9dd6bc0b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1289433219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1289433219 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.761298161 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 66048571 ps |
| CPU time | 9.64 seconds |
| Started | Dec 24 01:13:38 PM PST 23 |
| Finished | Dec 24 01:13:53 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-4eb23f7c-2476-4bec-a5d1-568456c87e46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=761298161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.761298161 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1899822024 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 41254474746 ps |
| CPU time | 101.97 seconds |
| Started | Dec 24 01:13:28 PM PST 23 |
| Finished | Dec 24 01:15:21 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-cfc75996-3837-48da-ba7b-6a04ac33cfcd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1899822024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.1899822024 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2400060586 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 158241644 ps |
| CPU time | 3.43 seconds |
| Started | Dec 24 01:13:23 PM PST 23 |
| Finished | Dec 24 01:13:40 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-8c7bcefe-635e-47ac-9bfc-4d0d047f157e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2400060586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2400060586 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.2269363362 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 20078074 ps |
| CPU time | 2.49 seconds |
| Started | Dec 24 01:13:22 PM PST 23 |
| Finished | Dec 24 01:13:38 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-7355849e-d8a3-4ffe-b7fc-86490949a523 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2269363362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2269363362 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.1871017591 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 155412770 ps |
| CPU time | 5.06 seconds |
| Started | Dec 24 01:13:24 PM PST 23 |
| Finished | Dec 24 01:13:42 PM PST 23 |
| Peak memory | 201320 kb |
| Host | smart-87e26fa2-6129-48fc-a7dc-a7e43b549505 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1871017591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1871017591 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.317972502 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 74477189516 ps |
| CPU time | 118.73 seconds |
| Started | Dec 24 01:13:33 PM PST 23 |
| Finished | Dec 24 01:15:41 PM PST 23 |
| Peak memory | 201516 kb |
| Host | smart-0d35e39e-f952-4983-bdab-53cdd8a4e0cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=317972502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.317972502 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1918909622 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2588770460 ps |
| CPU time | 11.96 seconds |
| Started | Dec 24 01:13:34 PM PST 23 |
| Finished | Dec 24 01:13:54 PM PST 23 |
| Peak memory | 201580 kb |
| Host | smart-d7241cf0-1bcb-4e24-9b98-23842690ed90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1918909622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1918909622 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.882841762 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 47993293 ps |
| CPU time | 5.38 seconds |
| Started | Dec 24 01:13:34 PM PST 23 |
| Finished | Dec 24 01:13:48 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-b2997b47-d5ff-4ece-891d-640b784755ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882841762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.882841762 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.3305684242 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 663474085 ps |
| CPU time | 7.79 seconds |
| Started | Dec 24 01:13:28 PM PST 23 |
| Finished | Dec 24 01:13:47 PM PST 23 |
| Peak memory | 201660 kb |
| Host | smart-8d9c2bf5-ad47-416b-bfa5-f7eaa33ce870 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3305684242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3305684242 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.3139929385 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 8796771 ps |
| CPU time | 1.09 seconds |
| Started | Dec 24 01:13:27 PM PST 23 |
| Finished | Dec 24 01:13:40 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-c9aa80bf-91a1-41ba-8098-1a7a4f6a3781 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3139929385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3139929385 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.381531016 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 8457961547 ps |
| CPU time | 11.42 seconds |
| Started | Dec 24 01:13:52 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 201516 kb |
| Host | smart-501feaf5-f1c4-4632-9a9a-f23055ad0363 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=381531016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.381531016 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.452069329 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1375904790 ps |
| CPU time | 7.37 seconds |
| Started | Dec 24 01:13:33 PM PST 23 |
| Finished | Dec 24 01:13:50 PM PST 23 |
| Peak memory | 201500 kb |
| Host | smart-a91b554a-1a5e-47dc-baea-d4706bc3ed79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=452069329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.452069329 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.336248661 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 10730504 ps |
| CPU time | 1.1 seconds |
| Started | Dec 24 01:13:29 PM PST 23 |
| Finished | Dec 24 01:13:41 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-e0d1eea3-6ebd-45fb-8d60-ffae463f8377 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336248661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.336248661 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1247594334 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2176164943 ps |
| CPU time | 35 seconds |
| Started | Dec 24 01:13:43 PM PST 23 |
| Finished | Dec 24 01:14:24 PM PST 23 |
| Peak memory | 202484 kb |
| Host | smart-28b85208-d436-413d-ad47-4d41b870cbeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1247594334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1247594334 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2376884860 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 506012493 ps |
| CPU time | 34.37 seconds |
| Started | Dec 24 01:13:41 PM PST 23 |
| Finished | Dec 24 01:14:21 PM PST 23 |
| Peak memory | 201408 kb |
| Host | smart-2564c5f5-6941-4da2-a8ef-0650d2cf074d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2376884860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2376884860 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1804549029 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 712146424 ps |
| CPU time | 125.34 seconds |
| Started | Dec 24 01:13:40 PM PST 23 |
| Finished | Dec 24 01:15:52 PM PST 23 |
| Peak memory | 203752 kb |
| Host | smart-dbf3784b-e50a-4ed1-950c-9982c6408762 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1804549029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.1804549029 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2339578895 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 248999144 ps |
| CPU time | 36.65 seconds |
| Started | Dec 24 01:13:25 PM PST 23 |
| Finished | Dec 24 01:14:14 PM PST 23 |
| Peak memory | 204156 kb |
| Host | smart-25fe3bf9-dfb2-47d0-b0b1-0498212da53b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2339578895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.2339578895 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.2262563415 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 453005117 ps |
| CPU time | 5.23 seconds |
| Started | Dec 24 01:13:25 PM PST 23 |
| Finished | Dec 24 01:13:43 PM PST 23 |
| Peak memory | 201092 kb |
| Host | smart-49512db9-8bff-444a-925d-703234786aab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2262563415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2262563415 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1925008365 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1262364683 ps |
| CPU time | 20.22 seconds |
| Started | Dec 24 01:13:31 PM PST 23 |
| Finished | Dec 24 01:14:01 PM PST 23 |
| Peak memory | 201408 kb |
| Host | smart-7439fe45-42ab-428e-9d8d-e0ce3e169642 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1925008365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1925008365 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3358917906 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 176326562234 ps |
| CPU time | 188.09 seconds |
| Started | Dec 24 01:13:39 PM PST 23 |
| Finished | Dec 24 01:16:53 PM PST 23 |
| Peak memory | 202672 kb |
| Host | smart-efe18fa6-0ed6-48e8-abf3-628db08de489 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3358917906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.3358917906 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.775748945 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 565460974 ps |
| CPU time | 7.36 seconds |
| Started | Dec 24 01:13:38 PM PST 23 |
| Finished | Dec 24 01:13:52 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-a6ae34c4-2c46-49b3-afc3-ccf5b2949cb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=775748945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.775748945 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.928176200 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1306349185 ps |
| CPU time | 6.84 seconds |
| Started | Dec 24 01:13:37 PM PST 23 |
| Finished | Dec 24 01:13:51 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-b0d770b6-01e3-4464-9d53-6f0dfcd3225d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=928176200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.928176200 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.3243736732 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 4160530358 ps |
| CPU time | 8.37 seconds |
| Started | Dec 24 01:13:38 PM PST 23 |
| Finished | Dec 24 01:13:52 PM PST 23 |
| Peak memory | 201416 kb |
| Host | smart-3c11c790-de5c-46f2-9bfc-22edcb67509c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3243736732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3243736732 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.4011942108 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 45805774093 ps |
| CPU time | 59.74 seconds |
| Started | Dec 24 01:13:36 PM PST 23 |
| Finished | Dec 24 01:14:43 PM PST 23 |
| Peak memory | 201568 kb |
| Host | smart-9baa702a-00bb-4fdc-bf3c-7a5298d3a3bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011942108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.4011942108 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2960511219 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 26077777946 ps |
| CPU time | 103.7 seconds |
| Started | Dec 24 01:13:38 PM PST 23 |
| Finished | Dec 24 01:15:28 PM PST 23 |
| Peak memory | 201564 kb |
| Host | smart-821e6bfc-bf2b-492e-862a-a4e299afe6bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2960511219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2960511219 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3686417224 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 85893469 ps |
| CPU time | 5.13 seconds |
| Started | Dec 24 01:13:39 PM PST 23 |
| Finished | Dec 24 01:13:50 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-0f3fb32f-3b3b-4377-8332-c1afb1c0b2e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686417224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3686417224 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.2416472294 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1986779154 ps |
| CPU time | 11.85 seconds |
| Started | Dec 24 01:13:36 PM PST 23 |
| Finished | Dec 24 01:13:55 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-cccc2ddb-6cfe-4b86-851f-e90fd1917bf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2416472294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2416472294 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.3523054974 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 17494871 ps |
| CPU time | 1.04 seconds |
| Started | Dec 24 01:13:36 PM PST 23 |
| Finished | Dec 24 01:13:45 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-0cfbf32a-7c90-4499-8b56-739dc45425c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3523054974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3523054974 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2920930201 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 6559480629 ps |
| CPU time | 9.05 seconds |
| Started | Dec 24 01:13:27 PM PST 23 |
| Finished | Dec 24 01:13:48 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-1e6d5be5-4acf-4ce4-8d44-8044d7fff1bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920930201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2920930201 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.382571173 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 1370728571 ps |
| CPU time | 6.93 seconds |
| Started | Dec 24 01:13:39 PM PST 23 |
| Finished | Dec 24 01:13:52 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-6521694c-3b15-4d4b-869a-81ed46c0f2fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=382571173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.382571173 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1204276040 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 20914758 ps |
| CPU time | 1.07 seconds |
| Started | Dec 24 01:13:31 PM PST 23 |
| Finished | Dec 24 01:13:42 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-c8fedc86-6ac3-454a-97c9-e4bded2c55b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204276040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1204276040 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.4011332571 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 252421379 ps |
| CPU time | 18.19 seconds |
| Started | Dec 24 01:13:34 PM PST 23 |
| Finished | Dec 24 01:14:01 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-70289469-9fba-4a9e-a166-4ec408c8171a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4011332571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.4011332571 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2232877720 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 7525503017 ps |
| CPU time | 82.27 seconds |
| Started | Dec 24 01:13:38 PM PST 23 |
| Finished | Dec 24 01:15:06 PM PST 23 |
| Peak memory | 202632 kb |
| Host | smart-56478a19-f0b6-4724-ba55-34397161c648 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2232877720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2232877720 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1483826491 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 140740565 ps |
| CPU time | 24.08 seconds |
| Started | Dec 24 01:13:43 PM PST 23 |
| Finished | Dec 24 01:14:12 PM PST 23 |
| Peak memory | 202500 kb |
| Host | smart-84c56704-69d5-433f-bfbe-a919ea2cc81d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1483826491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.1483826491 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3752240682 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 271127625 ps |
| CPU time | 24.6 seconds |
| Started | Dec 24 01:13:46 PM PST 23 |
| Finished | Dec 24 01:14:18 PM PST 23 |
| Peak memory | 202464 kb |
| Host | smart-a48a4d24-be3d-4b95-8269-95c98902ae84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3752240682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.3752240682 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3192983319 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 433374690 ps |
| CPU time | 2.16 seconds |
| Started | Dec 24 01:13:42 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-840fdd35-7099-417c-bc6d-447538d89e23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3192983319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3192983319 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.1808532588 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 930012272 ps |
| CPU time | 18.76 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:34 PM PST 23 |
| Peak memory | 201392 kb |
| Host | smart-69cba9a8-2d25-4943-81b5-e3ea33682dd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1808532588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1808532588 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2402016691 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 82085051291 ps |
| CPU time | 139.47 seconds |
| Started | Dec 24 01:13:50 PM PST 23 |
| Finished | Dec 24 01:16:15 PM PST 23 |
| Peak memory | 201520 kb |
| Host | smart-764aed33-2f29-45fa-abce-a789cc098afe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2402016691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.2402016691 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2573472695 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 354778584 ps |
| CPU time | 6.44 seconds |
| Started | Dec 24 01:14:08 PM PST 23 |
| Finished | Dec 24 01:14:31 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-dabbaf1f-f9e3-4a6a-a9d5-8e4ff8c8882e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2573472695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2573472695 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.1264268154 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 61627078 ps |
| CPU time | 4.56 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:04 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-186e20e7-76f5-41aa-95d0-c6e4d8a818bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1264268154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1264268154 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.258453317 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 2193080936 ps |
| CPU time | 14.21 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:29 PM PST 23 |
| Peak memory | 201532 kb |
| Host | smart-a9973db6-44b9-41e6-9b0e-64f706227672 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=258453317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.258453317 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2637339836 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 51007879735 ps |
| CPU time | 192.72 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:17:11 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-461579f4-22e2-48cb-8b3e-c7ebd743a014 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637339836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2637339836 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3954015676 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 13345897937 ps |
| CPU time | 105.79 seconds |
| Started | Dec 24 01:13:54 PM PST 23 |
| Finished | Dec 24 01:15:43 PM PST 23 |
| Peak memory | 201584 kb |
| Host | smart-976c2afc-604b-4e37-9938-c75abbc3fadd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3954015676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3954015676 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.47368477 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 34682683 ps |
| CPU time | 3.96 seconds |
| Started | Dec 24 01:13:39 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 201576 kb |
| Host | smart-3f27bac3-6b94-4713-888f-3e7d15438c68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47368477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.47368477 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.869319420 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 656581446 ps |
| CPU time | 6.71 seconds |
| Started | Dec 24 01:14:00 PM PST 23 |
| Finished | Dec 24 01:14:17 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-94e698b7-112c-4918-b632-45d6fe2d3ff9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=869319420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.869319420 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.1732279375 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 12459683 ps |
| CPU time | 1.26 seconds |
| Started | Dec 24 01:13:44 PM PST 23 |
| Finished | Dec 24 01:13:53 PM PST 23 |
| Peak memory | 201348 kb |
| Host | smart-1a0d6735-c48c-4492-9c02-94dfb69ba077 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1732279375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1732279375 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1663411612 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 4826136026 ps |
| CPU time | 8.44 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 201424 kb |
| Host | smart-7806493c-9e65-45a6-a09e-0f6121467219 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663411612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1663411612 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.4039401710 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 11109193222 ps |
| CPU time | 12.49 seconds |
| Started | Dec 24 01:13:53 PM PST 23 |
| Finished | Dec 24 01:14:09 PM PST 23 |
| Peak memory | 201652 kb |
| Host | smart-4aa14e48-7943-4148-9b80-cc8a760d41fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4039401710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.4039401710 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.486652281 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 10224240 ps |
| CPU time | 1.02 seconds |
| Started | Dec 24 01:13:42 PM PST 23 |
| Finished | Dec 24 01:13:48 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-a9aadaa1-3d73-43de-9777-3eeb34c1aa99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486652281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.486652281 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.2167264659 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3339515907 ps |
| CPU time | 15.63 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:31 PM PST 23 |
| Peak memory | 201452 kb |
| Host | smart-df1a50b7-a870-4bfd-8c6e-7e85219a7375 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2167264659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2167264659 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.288627801 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 125148422 ps |
| CPU time | 19.37 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:19 PM PST 23 |
| Peak memory | 202460 kb |
| Host | smart-3a59997d-deae-428c-8ae3-e3d89fdabeb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=288627801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand _reset.288627801 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3496243273 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 7013002708 ps |
| CPU time | 156.01 seconds |
| Started | Dec 24 01:14:08 PM PST 23 |
| Finished | Dec 24 01:17:01 PM PST 23 |
| Peak memory | 204696 kb |
| Host | smart-36a8972c-d638-4cef-88cc-4ae941469cc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3496243273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.3496243273 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2041852156 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 281848833 ps |
| CPU time | 6.37 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-354ff395-1b6b-45f3-9917-3ac23ba6a5a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2041852156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2041852156 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.4133798409 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 33943515 ps |
| CPU time | 3.75 seconds |
| Started | Dec 24 01:14:22 PM PST 23 |
| Finished | Dec 24 01:14:37 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-7dbb5343-4dbf-4774-a554-e27456f24ce2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4133798409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.4133798409 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.843901591 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 5112172282 ps |
| CPU time | 19.05 seconds |
| Started | Dec 24 01:14:02 PM PST 23 |
| Finished | Dec 24 01:14:35 PM PST 23 |
| Peak memory | 201516 kb |
| Host | smart-504c0543-3485-4a38-ab1f-a090a1e837e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=843901591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo w_rsp.843901591 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3243424334 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 202005619 ps |
| CPU time | 3.42 seconds |
| Started | Dec 24 01:14:17 PM PST 23 |
| Finished | Dec 24 01:14:34 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-cf6feb20-7df3-42c9-bd13-2baaf821648e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3243424334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3243424334 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.4000286831 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 123445385 ps |
| CPU time | 6.26 seconds |
| Started | Dec 24 01:14:06 PM PST 23 |
| Finished | Dec 24 01:14:28 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-07b5209f-0fe9-4422-9dcb-68a6ac757ecf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4000286831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.4000286831 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.13414328 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 79390189 ps |
| CPU time | 1.24 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:10 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-1bc33b92-d3a8-4760-b4eb-16975e46011b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=13414328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.13414328 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1988153243 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 65585846784 ps |
| CPU time | 114.98 seconds |
| Started | Dec 24 01:14:04 PM PST 23 |
| Finished | Dec 24 01:16:15 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-e4832b25-43a7-42d4-afa9-65ce4d6b21b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988153243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1988153243 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.495584912 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 8925971425 ps |
| CPU time | 57.49 seconds |
| Started | Dec 24 01:14:10 PM PST 23 |
| Finished | Dec 24 01:15:24 PM PST 23 |
| Peak memory | 201536 kb |
| Host | smart-eb5dca2c-d732-4eb9-913d-0899ca82d1b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=495584912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.495584912 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.734148766 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 85349783 ps |
| CPU time | 6.81 seconds |
| Started | Dec 24 01:14:02 PM PST 23 |
| Finished | Dec 24 01:14:23 PM PST 23 |
| Peak memory | 201436 kb |
| Host | smart-7463d3af-9e75-4d55-a384-7792c15d945e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734148766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.734148766 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.114741217 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 28972037 ps |
| CPU time | 3.21 seconds |
| Started | Dec 24 01:14:20 PM PST 23 |
| Finished | Dec 24 01:14:36 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-f419d27b-2d56-4fd8-90c2-9775ec1cff12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=114741217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.114741217 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.1965716690 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 9228893 ps |
| CPU time | 1.12 seconds |
| Started | Dec 24 01:14:00 PM PST 23 |
| Finished | Dec 24 01:14:11 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-d7e30bee-1ee7-49ef-ac41-609347631937 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1965716690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1965716690 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.67926510 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 15217499721 ps |
| CPU time | 11.93 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:18 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-c95ece2f-187c-4a2f-bea0-a6545cfdf6c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=67926510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.67926510 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2180792312 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1208853609 ps |
| CPU time | 8.86 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:24 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-c7e442d7-faf2-4650-888c-fe892ad4a11c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2180792312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2180792312 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3680559571 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 13778562 ps |
| CPU time | 1.12 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:03 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-dcf9f1db-d286-4c4a-ad31-7911fa68162a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680559571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3680559571 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.869316240 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1238075546 ps |
| CPU time | 20.57 seconds |
| Started | Dec 24 01:14:06 PM PST 23 |
| Finished | Dec 24 01:14:43 PM PST 23 |
| Peak memory | 201408 kb |
| Host | smart-7b65990f-bc13-4de8-9656-40eada490d11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=869316240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.869316240 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1820352316 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 3299604804 ps |
| CPU time | 18.05 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:27 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-51a14947-c3aa-483c-9f98-1645e163abcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1820352316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1820352316 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2788176174 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6019223012 ps |
| CPU time | 79.01 seconds |
| Started | Dec 24 01:14:07 PM PST 23 |
| Finished | Dec 24 01:15:42 PM PST 23 |
| Peak memory | 203956 kb |
| Host | smart-21892181-7b28-4b43-be99-44fc077afc78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2788176174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.2788176174 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.172719969 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 6069306031 ps |
| CPU time | 78.87 seconds |
| Started | Dec 24 01:13:55 PM PST 23 |
| Finished | Dec 24 01:15:17 PM PST 23 |
| Peak memory | 203856 kb |
| Host | smart-6f0ce8bd-9a2a-4d53-a8d1-60225eebf005 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=172719969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_res et_error.172719969 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1700141708 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 543679141 ps |
| CPU time | 4.94 seconds |
| Started | Dec 24 01:14:10 PM PST 23 |
| Finished | Dec 24 01:14:31 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-26449176-06f3-4620-8ad0-ff6cb7ed7a62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1700141708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1700141708 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2925568479 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 891070951 ps |
| CPU time | 18.13 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:27 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-abaa4403-b7dc-4b39-aec7-9decd4cb3277 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2925568479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2925568479 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3943526445 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 116923459 ps |
| CPU time | 3.56 seconds |
| Started | Dec 24 01:13:47 PM PST 23 |
| Finished | Dec 24 01:13:57 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-369db190-35ee-47dd-8b06-9d9fa4274a27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3943526445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3943526445 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.326278924 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1813784720 ps |
| CPU time | 12.34 seconds |
| Started | Dec 24 01:13:54 PM PST 23 |
| Finished | Dec 24 01:14:10 PM PST 23 |
| Peak memory | 201316 kb |
| Host | smart-f48d4237-7134-4b0d-a55f-8ca3ea370274 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=326278924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.326278924 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.2384290856 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 777770946 ps |
| CPU time | 15.06 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:17 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-490a6719-a934-4d64-b36d-27837cd4d69d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2384290856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2384290856 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.3081991183 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 46257935144 ps |
| CPU time | 138.08 seconds |
| Started | Dec 24 01:13:55 PM PST 23 |
| Finished | Dec 24 01:16:16 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-c232aecf-b019-4f62-93ec-322aadefd952 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081991183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3081991183 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1183949919 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 7692072263 ps |
| CPU time | 57.2 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:57 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-de3fdbec-008c-4eb5-b816-d00652d581ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1183949919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1183949919 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1988781687 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 11327080 ps |
| CPU time | 1.41 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:04 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-a4793ec1-0cad-436a-b803-6613ae7406d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988781687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1988781687 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.1299112747 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 59458217 ps |
| CPU time | 5.32 seconds |
| Started | Dec 24 01:13:54 PM PST 23 |
| Finished | Dec 24 01:14:02 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-067605d6-d604-44fe-9ffb-cfbeed071994 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1299112747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1299112747 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.4061702619 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 16077939 ps |
| CPU time | 1.05 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:07 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-a620a463-6538-4310-92c1-1dbc6386ea81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4061702619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.4061702619 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3034002866 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3926654969 ps |
| CPU time | 8.66 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:09 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-7e64903d-3786-4259-a52d-5800229652d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034002866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3034002866 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1161672258 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 723439930 ps |
| CPU time | 6.39 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:06 PM PST 23 |
| Peak memory | 201436 kb |
| Host | smart-9f68d815-5a76-423a-9939-d1ff63f5ff88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1161672258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1161672258 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1783956439 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 10257768 ps |
| CPU time | 1.12 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:00 PM PST 23 |
| Peak memory | 201500 kb |
| Host | smart-fe256597-75b4-4a4b-bf84-e6681a8c58cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783956439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1783956439 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.3261241583 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 434961994 ps |
| CPU time | 16.27 seconds |
| Started | Dec 24 01:13:52 PM PST 23 |
| Finished | Dec 24 01:14:13 PM PST 23 |
| Peak memory | 202284 kb |
| Host | smart-49cd3fdd-80a1-4f8e-bc33-f14895f6a187 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3261241583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3261241583 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1238981463 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1244000356 ps |
| CPU time | 17.02 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:20 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-eb313c52-daac-497d-bae4-f74bdebc8481 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1238981463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1238981463 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2806457837 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 258827540 ps |
| CPU time | 35.23 seconds |
| Started | Dec 24 01:13:39 PM PST 23 |
| Finished | Dec 24 01:14:21 PM PST 23 |
| Peak memory | 203448 kb |
| Host | smart-56145eb1-0e19-4f99-b791-200d27068e31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2806457837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.2806457837 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2631155408 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 14220939876 ps |
| CPU time | 123.29 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:16:09 PM PST 23 |
| Peak memory | 205652 kb |
| Host | smart-a6db730f-9a21-4cac-81af-e8a23c43f44d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2631155408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.2631155408 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.381980625 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 34116578 ps |
| CPU time | 3.56 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:10 PM PST 23 |
| Peak memory | 201352 kb |
| Host | smart-9ad737d2-15db-47ce-8917-77872ac2b8df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=381980625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.381980625 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.1266068688 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1348146787 ps |
| CPU time | 20.18 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:25 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-3c664b82-a7d0-436e-9613-d0367ea76067 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1266068688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1266068688 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1533544811 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 32980521384 ps |
| CPU time | 165.19 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:16:49 PM PST 23 |
| Peak memory | 202572 kb |
| Host | smart-57f292d6-67fa-433f-bfda-d83b1a2ef2b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1533544811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.1533544811 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4092120810 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 1032334088 ps |
| CPU time | 8.53 seconds |
| Started | Dec 24 01:13:54 PM PST 23 |
| Finished | Dec 24 01:14:06 PM PST 23 |
| Peak memory | 201368 kb |
| Host | smart-3deaa76d-0af5-4a12-ba0d-ebb4c7397b43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4092120810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4092120810 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.1541371884 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 48286401 ps |
| CPU time | 3.31 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:06 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-930c7394-785e-47f8-a391-8206252b1c0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1541371884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1541371884 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.2752552835 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 88111644 ps |
| CPU time | 7.51 seconds |
| Started | Dec 24 01:13:51 PM PST 23 |
| Finished | Dec 24 01:14:04 PM PST 23 |
| Peak memory | 201460 kb |
| Host | smart-af69a83e-134d-47dd-9296-a6fba92c6cfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2752552835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2752552835 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.2005463832 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 39085613268 ps |
| CPU time | 168.8 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:16:49 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-0a616705-6637-4772-a1f3-7a30822fa89a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005463832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2005463832 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3425532785 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 24729316521 ps |
| CPU time | 104.75 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:15:47 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-bde38236-7e45-4390-81fa-0859822b2244 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3425532785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3425532785 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2331801844 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 67783234 ps |
| CPU time | 7.31 seconds |
| Started | Dec 24 01:14:00 PM PST 23 |
| Finished | Dec 24 01:14:18 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-4bb43ab1-d777-4200-bd19-306001ee5c5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331801844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2331801844 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.2645308227 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 270810898 ps |
| CPU time | 4.31 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:09 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-b82ad784-ffd6-4dc6-b6dc-5cc5bd945142 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2645308227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2645308227 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.371974298 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 147981792 ps |
| CPU time | 1.54 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:02 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-ae25816a-7dfa-467f-aea7-36114c838838 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=371974298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.371974298 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1797621305 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 6548184927 ps |
| CPU time | 9.02 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:11 PM PST 23 |
| Peak memory | 201544 kb |
| Host | smart-bad3adce-4574-4e0f-ac09-7d99734bc067 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797621305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1797621305 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3577678832 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 4566706576 ps |
| CPU time | 7.21 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:09 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-4a202a89-111a-4bc3-8749-60d07e3d4e55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3577678832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3577678832 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.531977450 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 19583747 ps |
| CPU time | 1.02 seconds |
| Started | Dec 24 01:13:54 PM PST 23 |
| Finished | Dec 24 01:13:58 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-c6147370-ac50-4881-9d3f-177ca7672547 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531977450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.531977450 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1258788614 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 180976730 ps |
| CPU time | 14.68 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:22 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-4c004d72-13e0-4ea8-96ac-c21993446509 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1258788614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1258788614 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.969248470 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2541890831 ps |
| CPU time | 33.58 seconds |
| Started | Dec 24 01:13:39 PM PST 23 |
| Finished | Dec 24 01:14:19 PM PST 23 |
| Peak memory | 201460 kb |
| Host | smart-e947b2d8-3887-4913-8a4d-d313315b1088 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=969248470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.969248470 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.4112441150 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 1368971402 ps |
| CPU time | 75.6 seconds |
| Started | Dec 24 01:14:09 PM PST 23 |
| Finished | Dec 24 01:15:41 PM PST 23 |
| Peak memory | 203756 kb |
| Host | smart-3b865bd0-9cf5-48f3-a72b-b4dc02d97752 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4112441150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.4112441150 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.230774428 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 81223024 ps |
| CPU time | 13.56 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:29 PM PST 23 |
| Peak memory | 201504 kb |
| Host | smart-9e3123cb-18d8-4b8e-ab27-d0a55870e882 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=230774428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_res et_error.230774428 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.2048706817 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 114868100 ps |
| CPU time | 7.63 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:15 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-e2209258-63c7-4d8c-9c7b-8d4f718e1920 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2048706817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2048706817 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2060529988 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 201253485 ps |
| CPU time | 2.87 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-8098af52-dd1d-479c-973c-ef08fa8d6ab1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2060529988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2060529988 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2402901092 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 10237256382 ps |
| CPU time | 54.46 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:54 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-98633363-7017-474b-a75f-7d8f83176590 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2402901092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.2402901092 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3651433987 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 84385800 ps |
| CPU time | 3.27 seconds |
| Started | Dec 24 01:13:40 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-e3abafb5-7860-4cd4-81f4-9cb0fda35f93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3651433987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3651433987 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.1926704406 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 19390473 ps |
| CPU time | 1.28 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:16 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-fb212f62-7806-44e5-9f0b-7fe1ae5319d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1926704406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1926704406 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.3974259705 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 555387942 ps |
| CPU time | 11.72 seconds |
| Started | Dec 24 01:13:39 PM PST 23 |
| Finished | Dec 24 01:13:57 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-a9032e5d-a8b1-4f84-a6be-69fa6dd8147d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3974259705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3974259705 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.401103056 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 6246046406 ps |
| CPU time | 29.19 seconds |
| Started | Dec 24 01:13:54 PM PST 23 |
| Finished | Dec 24 01:14:27 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-fa307b9a-b6ff-44b0-a7a1-1a2c985e9039 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=401103056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.401103056 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1962475184 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 7716248026 ps |
| CPU time | 53.21 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:54 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-9ff2fa2a-2fa3-4457-a7e9-62d725b8c671 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1962475184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1962475184 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2086294026 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 76214837 ps |
| CPU time | 3.39 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:04 PM PST 23 |
| Peak memory | 201196 kb |
| Host | smart-faf591db-a447-4997-a46d-2be0e50d308d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086294026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2086294026 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.775639391 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 111049028 ps |
| CPU time | 4.59 seconds |
| Started | Dec 24 01:13:49 PM PST 23 |
| Finished | Dec 24 01:14:00 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-263ab1fd-1464-478b-b354-22d64a46c069 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=775639391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.775639391 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.34424591 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 30159192 ps |
| CPU time | 1.14 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:04 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-4dd553a5-14f7-4f7f-ba3f-bf0262c3be74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=34424591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.34424591 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1113040992 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 3128443725 ps |
| CPU time | 11.13 seconds |
| Started | Dec 24 01:14:03 PM PST 23 |
| Finished | Dec 24 01:14:30 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-8008492c-4d0f-4c06-925f-bba33d8bc78e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113040992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1113040992 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.406777579 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 3432799575 ps |
| CPU time | 11.57 seconds |
| Started | Dec 24 01:13:55 PM PST 23 |
| Finished | Dec 24 01:14:09 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-0a9a1db1-75f9-454f-badc-ed128f440374 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=406777579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.406777579 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1699205511 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 18841100 ps |
| CPU time | 1.18 seconds |
| Started | Dec 24 01:13:46 PM PST 23 |
| Finished | Dec 24 01:13:54 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-0dcd5afe-eb38-4b7f-bc92-81b0d03d0532 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699205511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1699205511 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2895364692 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5236271120 ps |
| CPU time | 86.08 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:15:28 PM PST 23 |
| Peak memory | 202568 kb |
| Host | smart-42417f46-375e-43d4-bc50-9cb095ba654e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2895364692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2895364692 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.633546738 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 108260290 ps |
| CPU time | 6.8 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:22 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-ab2a6fb4-cab0-4b9f-ac4a-0cedfc2ac5ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=633546738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.633546738 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3569086629 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 2315373281 ps |
| CPU time | 86.62 seconds |
| Started | Dec 24 01:14:03 PM PST 23 |
| Finished | Dec 24 01:15:45 PM PST 23 |
| Peak memory | 204092 kb |
| Host | smart-3c2f5b6f-5859-4869-ae1b-ae1e396e5738 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3569086629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.3569086629 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3584208988 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 90087245 ps |
| CPU time | 7.54 seconds |
| Started | Dec 24 01:14:08 PM PST 23 |
| Finished | Dec 24 01:14:32 PM PST 23 |
| Peak memory | 201364 kb |
| Host | smart-38ca1fd7-49b0-475f-9298-8b3df5ca96be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3584208988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.3584208988 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1890408702 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1388022567 ps |
| CPU time | 11.34 seconds |
| Started | Dec 24 01:13:55 PM PST 23 |
| Finished | Dec 24 01:14:09 PM PST 23 |
| Peak memory | 201332 kb |
| Host | smart-3b94fe17-056a-4379-a5fa-0bfef1906498 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1890408702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1890408702 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1707671671 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 96793434 ps |
| CPU time | 2.14 seconds |
| Started | Dec 24 01:14:05 PM PST 23 |
| Finished | Dec 24 01:14:23 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-e18a19bf-7cf9-429c-9f2f-227e077817e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1707671671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1707671671 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.96927072 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 106900299441 ps |
| CPU time | 353.31 seconds |
| Started | Dec 24 01:14:06 PM PST 23 |
| Finished | Dec 24 01:20:15 PM PST 23 |
| Peak memory | 202788 kb |
| Host | smart-4306296b-6c66-4a5b-890c-527c2925b068 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=96927072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow _rsp.96927072 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2749809596 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 413067419 ps |
| CPU time | 6.3 seconds |
| Started | Dec 24 01:14:06 PM PST 23 |
| Finished | Dec 24 01:14:29 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-dcf853f9-7c9e-4cc6-8c51-816e51ac99ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2749809596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2749809596 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.2937721784 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 59613920 ps |
| CPU time | 3.16 seconds |
| Started | Dec 24 01:14:02 PM PST 23 |
| Finished | Dec 24 01:14:21 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-78285d3d-54f9-4079-b502-d791c9447a25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2937721784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2937721784 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.4237877190 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 5270282467 ps |
| CPU time | 15.1 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:30 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-a610ae9f-38ed-47c8-8c43-2915dbe7a20b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4237877190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.4237877190 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3631284638 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 42131386374 ps |
| CPU time | 97.83 seconds |
| Started | Dec 24 01:14:00 PM PST 23 |
| Finished | Dec 24 01:15:49 PM PST 23 |
| Peak memory | 201520 kb |
| Host | smart-e562f589-a7e3-42a3-86d6-739bd4858ef3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631284638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3631284638 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.870158404 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 15502250428 ps |
| CPU time | 51.32 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:59 PM PST 23 |
| Peak memory | 201496 kb |
| Host | smart-f58ea8de-667a-4286-a841-15867ea7d310 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=870158404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.870158404 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3798484027 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 79523419 ps |
| CPU time | 5.99 seconds |
| Started | Dec 24 01:14:02 PM PST 23 |
| Finished | Dec 24 01:14:23 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-ba5749b2-14d6-4d20-b2e5-86977f816b0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798484027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3798484027 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.2659653872 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 771805725 ps |
| CPU time | 6.63 seconds |
| Started | Dec 24 01:14:06 PM PST 23 |
| Finished | Dec 24 01:14:29 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-2d4040d7-63e2-4748-9fbe-bacef69221da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2659653872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2659653872 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.489426390 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 55010662 ps |
| CPU time | 1.39 seconds |
| Started | Dec 24 01:14:13 PM PST 23 |
| Finished | Dec 24 01:14:29 PM PST 23 |
| Peak memory | 201364 kb |
| Host | smart-66feb812-385a-4cd2-8fac-27484aed5e27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=489426390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.489426390 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2604473971 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 6472291578 ps |
| CPU time | 10.12 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:10 PM PST 23 |
| Peak memory | 201200 kb |
| Host | smart-6e102f41-15ab-4ab5-8f6a-12f9ecc70a23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604473971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2604473971 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3644944296 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2484337569 ps |
| CPU time | 12.08 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:27 PM PST 23 |
| Peak memory | 201532 kb |
| Host | smart-1fad3921-67db-425b-87d0-3d4907cdc183 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3644944296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3644944296 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3757983009 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 8156208 ps |
| CPU time | 0.96 seconds |
| Started | Dec 24 01:14:02 PM PST 23 |
| Finished | Dec 24 01:14:17 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-7a640e6c-148a-4c3a-b209-7531de7b0c31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757983009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3757983009 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.3007425596 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 777840575 ps |
| CPU time | 41 seconds |
| Started | Dec 24 01:14:07 PM PST 23 |
| Finished | Dec 24 01:15:04 PM PST 23 |
| Peak memory | 203052 kb |
| Host | smart-8f0b1fee-985d-4758-b972-225c801d7333 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3007425596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3007425596 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3344323383 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4348441783 ps |
| CPU time | 68.13 seconds |
| Started | Dec 24 01:14:06 PM PST 23 |
| Finished | Dec 24 01:15:30 PM PST 23 |
| Peak memory | 202500 kb |
| Host | smart-05ca3712-8311-4431-90e9-c401b4a6c9c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3344323383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3344323383 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3415585842 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 658469531 ps |
| CPU time | 123.95 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:16:24 PM PST 23 |
| Peak memory | 205472 kb |
| Host | smart-603de176-334b-4ec4-9207-4ea0741a1c9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3415585842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.3415585842 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1769311371 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 44936726 ps |
| CPU time | 1.36 seconds |
| Started | Dec 24 01:14:20 PM PST 23 |
| Finished | Dec 24 01:14:34 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-bc05c420-4c6d-47ac-976d-71ed50616b25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1769311371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1769311371 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3980734506 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 66750663 ps |
| CPU time | 8.8 seconds |
| Started | Dec 24 01:14:10 PM PST 23 |
| Finished | Dec 24 01:14:35 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-ce3f53ce-ab84-4125-a06c-468ac248644d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3980734506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3980734506 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1715921145 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 67190145824 ps |
| CPU time | 186.82 seconds |
| Started | Dec 24 01:14:42 PM PST 23 |
| Finished | Dec 24 01:17:55 PM PST 23 |
| Peak memory | 202512 kb |
| Host | smart-fa8bc554-5673-4efd-a2af-2a02cf24743d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1715921145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.1715921145 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.746739302 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 173412333 ps |
| CPU time | 4.2 seconds |
| Started | Dec 24 01:14:26 PM PST 23 |
| Finished | Dec 24 01:14:39 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-3e91727f-a93a-4aea-9fc5-8b9af626fa80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=746739302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.746739302 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.3772541872 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 48222100 ps |
| CPU time | 4.77 seconds |
| Started | Dec 24 01:14:21 PM PST 23 |
| Finished | Dec 24 01:14:38 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-7a06bc82-c022-4b2e-8d50-3c23038f1e1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3772541872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3772541872 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.213611 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1813263888 ps |
| CPU time | 7.37 seconds |
| Started | Dec 24 01:14:17 PM PST 23 |
| Finished | Dec 24 01:14:38 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-eb257643-5f68-48b3-8a93-d79c271a40f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=213611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.213611 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3970485750 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 48679084688 ps |
| CPU time | 43.39 seconds |
| Started | Dec 24 01:14:05 PM PST 23 |
| Finished | Dec 24 01:15:04 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-e00e78c4-4220-4f37-b9e2-a323ca355585 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970485750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3970485750 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3051699190 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 94700677804 ps |
| CPU time | 139.41 seconds |
| Started | Dec 24 01:14:13 PM PST 23 |
| Finished | Dec 24 01:16:47 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-223eaf68-10c8-4f04-8fbb-694520b37079 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3051699190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3051699190 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.1467784103 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 122723573 ps |
| CPU time | 4.45 seconds |
| Started | Dec 24 01:14:38 PM PST 23 |
| Finished | Dec 24 01:14:50 PM PST 23 |
| Peak memory | 201440 kb |
| Host | smart-6b781162-77f0-493f-b4e7-2ff65597ee51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467784103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1467784103 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1932911124 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 12893054 ps |
| CPU time | 1.35 seconds |
| Started | Dec 24 01:14:06 PM PST 23 |
| Finished | Dec 24 01:14:23 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-2fbe2155-ab40-450a-9b61-38ed6a6cd5f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1932911124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1932911124 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.797886820 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 88142319 ps |
| CPU time | 1.78 seconds |
| Started | Dec 24 01:13:58 PM PST 23 |
| Finished | Dec 24 01:14:05 PM PST 23 |
| Peak memory | 201384 kb |
| Host | smart-de848760-bc4a-48d5-b4a6-b66a1b2d3cf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=797886820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.797886820 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.3343060134 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1496356753 ps |
| CPU time | 7.37 seconds |
| Started | Dec 24 01:14:05 PM PST 23 |
| Finished | Dec 24 01:14:29 PM PST 23 |
| Peak memory | 201408 kb |
| Host | smart-c57739c8-3a3b-40af-9694-4d27599527b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343060134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3343060134 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1705323790 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 5847358523 ps |
| CPU time | 10.28 seconds |
| Started | Dec 24 01:14:00 PM PST 23 |
| Finished | Dec 24 01:14:22 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-1979564d-cc91-469c-ad8d-1bc6e1984eb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1705323790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1705323790 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.2853094973 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 17941020 ps |
| CPU time | 1.31 seconds |
| Started | Dec 24 01:14:24 PM PST 23 |
| Finished | Dec 24 01:14:35 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-c6c55526-80ef-44c7-b405-5e6c8f9608e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853094973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2853094973 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.2978877825 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 375909316 ps |
| CPU time | 21.44 seconds |
| Started | Dec 24 01:14:33 PM PST 23 |
| Finished | Dec 24 01:15:02 PM PST 23 |
| Peak memory | 202772 kb |
| Host | smart-4fd294ce-91ff-464f-99ad-a087ae0cddec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2978877825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2978877825 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.215644476 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 9516675465 ps |
| CPU time | 58.3 seconds |
| Started | Dec 24 01:14:17 PM PST 23 |
| Finished | Dec 24 01:15:28 PM PST 23 |
| Peak memory | 202560 kb |
| Host | smart-84a57edc-c8e5-4d0e-8540-5b76cec88c26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=215644476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.215644476 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2436930603 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 4562293344 ps |
| CPU time | 154.1 seconds |
| Started | Dec 24 01:14:15 PM PST 23 |
| Finished | Dec 24 01:17:03 PM PST 23 |
| Peak memory | 205488 kb |
| Host | smart-061b1b66-ea1f-4f80-8596-6b3b6bbbae8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2436930603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.2436930603 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1748474761 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 343987527 ps |
| CPU time | 45.55 seconds |
| Started | Dec 24 01:13:55 PM PST 23 |
| Finished | Dec 24 01:14:44 PM PST 23 |
| Peak memory | 202512 kb |
| Host | smart-6ce75b91-d88c-4a61-80f6-595fd126ce09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1748474761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1748474761 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2266788130 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 873216926 ps |
| CPU time | 6.33 seconds |
| Started | Dec 24 01:14:13 PM PST 23 |
| Finished | Dec 24 01:14:34 PM PST 23 |
| Peak memory | 201512 kb |
| Host | smart-1f2445a2-d358-4c7b-ad5a-5f0a7de4dbfd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2266788130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2266788130 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1326620985 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 28156897 ps |
| CPU time | 2.6 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:02 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-5ca8ba52-d91a-411f-88ef-85093fd21ad8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1326620985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1326620985 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2541154998 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 88816741473 ps |
| CPU time | 96.02 seconds |
| Started | Dec 24 01:13:55 PM PST 23 |
| Finished | Dec 24 01:15:34 PM PST 23 |
| Peak memory | 201564 kb |
| Host | smart-288590d9-991a-45b5-8ec8-499744828802 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2541154998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.2541154998 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2235348218 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2526185545 ps |
| CPU time | 11.78 seconds |
| Started | Dec 24 01:14:05 PM PST 23 |
| Finished | Dec 24 01:14:32 PM PST 23 |
| Peak memory | 201532 kb |
| Host | smart-f48ef40a-96ca-4eda-b8b0-4293ecc1674a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2235348218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2235348218 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.1596757887 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 31566710 ps |
| CPU time | 2.75 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:05 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-a47a4cf7-8062-469d-81a3-2992f446a395 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1596757887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1596757887 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.3255074688 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 40128295 ps |
| CPU time | 4.8 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:12 PM PST 23 |
| Peak memory | 201392 kb |
| Host | smart-88f91801-0246-4145-ae40-d5760e2b2208 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3255074688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3255074688 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.1843746873 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 23186295054 ps |
| CPU time | 33.15 seconds |
| Started | Dec 24 01:13:54 PM PST 23 |
| Finished | Dec 24 01:14:31 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-8230ae58-91e6-4a12-89c5-97b2fc2dbdbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843746873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1843746873 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.377439756 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 16386268420 ps |
| CPU time | 60.56 seconds |
| Started | Dec 24 01:13:41 PM PST 23 |
| Finished | Dec 24 01:14:47 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-3370d61d-1a68-4b06-a88b-4e52b2796c92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=377439756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.377439756 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2742592472 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 92550727 ps |
| CPU time | 4.42 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:03 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-4e895792-405d-43d2-9dcd-780054352bf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742592472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2742592472 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.1817152756 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 1021719720 ps |
| CPU time | 10.23 seconds |
| Started | Dec 24 01:13:55 PM PST 23 |
| Finished | Dec 24 01:14:09 PM PST 23 |
| Peak memory | 201456 kb |
| Host | smart-e95e2985-b049-433d-b5da-c6f9b8bd472d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1817152756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1817152756 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.1760313618 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 268154238 ps |
| CPU time | 1.57 seconds |
| Started | Dec 24 01:14:43 PM PST 23 |
| Finished | Dec 24 01:14:51 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-f534603f-3597-41b1-908b-caa8a8a08af6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1760313618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1760313618 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3552259900 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1721231270 ps |
| CPU time | 8.45 seconds |
| Started | Dec 24 01:14:06 PM PST 23 |
| Finished | Dec 24 01:14:31 PM PST 23 |
| Peak memory | 201412 kb |
| Host | smart-104ba2e5-b56f-480d-9041-efae6c8d995b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552259900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3552259900 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1740364199 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1119113613 ps |
| CPU time | 8.96 seconds |
| Started | Dec 24 01:13:56 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 201368 kb |
| Host | smart-eeb025ae-d201-416d-9bf2-8b039acb7df4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1740364199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1740364199 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.4016515012 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 14072803 ps |
| CPU time | 1.15 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:02 PM PST 23 |
| Peak memory | 201472 kb |
| Host | smart-a26ac380-5731-44a8-b305-1bd7d835fbe6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016515012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.4016515012 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3679115224 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 184718035 ps |
| CPU time | 17.15 seconds |
| Started | Dec 24 01:14:01 PM PST 23 |
| Finished | Dec 24 01:14:37 PM PST 23 |
| Peak memory | 201360 kb |
| Host | smart-055bc325-bc01-450e-bfa0-6e48eed6e1bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3679115224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3679115224 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.321505122 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 28603341635 ps |
| CPU time | 47.41 seconds |
| Started | Dec 24 01:13:59 PM PST 23 |
| Finished | Dec 24 01:14:57 PM PST 23 |
| Peak memory | 201516 kb |
| Host | smart-2af9dc1c-5b4a-4862-821d-1acb0877f5f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=321505122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.321505122 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3081607682 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 256966563 ps |
| CPU time | 32.5 seconds |
| Started | Dec 24 01:14:04 PM PST 23 |
| Finished | Dec 24 01:14:53 PM PST 23 |
| Peak memory | 203532 kb |
| Host | smart-a9d63c17-5ad8-43cd-9455-4cd83469192b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3081607682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.3081607682 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1786850178 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2225058445 ps |
| CPU time | 83.22 seconds |
| Started | Dec 24 01:14:14 PM PST 23 |
| Finished | Dec 24 01:15:52 PM PST 23 |
| Peak memory | 204836 kb |
| Host | smart-6f96370e-8d76-4bd6-9cb0-c2114fc2651d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1786850178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.1786850178 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1269672626 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 17059123 ps |
| CPU time | 1.11 seconds |
| Started | Dec 24 01:13:57 PM PST 23 |
| Finished | Dec 24 01:14:03 PM PST 23 |
| Peak memory | 201504 kb |
| Host | smart-098f83fb-2a10-4829-93a5-c6a08b476708 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1269672626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1269672626 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1542743070 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 71001520 ps |
| CPU time | 6.58 seconds |
| Started | Dec 24 01:12:20 PM PST 23 |
| Finished | Dec 24 01:12:39 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-10d8c075-53fc-43b9-955f-9983d485e0ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1542743070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1542743070 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.396115719 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 32199020563 ps |
| CPU time | 101.12 seconds |
| Started | Dec 24 01:12:17 PM PST 23 |
| Finished | Dec 24 01:14:10 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-fe1230f1-637f-40c3-86f5-a216870d43f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=396115719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow _rsp.396115719 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1046483673 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 102271145 ps |
| CPU time | 3.76 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:12:41 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-bf189c75-ac33-40b6-a9e6-9837f11b81c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1046483673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1046483673 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.2517803213 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 72088232 ps |
| CPU time | 5.44 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:12:44 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-6ba45e3a-cb97-4d30-8b7b-a42ed9cc6334 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2517803213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2517803213 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.2123082975 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 13480642 ps |
| CPU time | 1.48 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:12:39 PM PST 23 |
| Peak memory | 201400 kb |
| Host | smart-31c4e9cd-717e-45ea-9e88-c8099371a0f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2123082975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2123082975 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2392091939 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 4844922625 ps |
| CPU time | 24.71 seconds |
| Started | Dec 24 01:12:20 PM PST 23 |
| Finished | Dec 24 01:12:58 PM PST 23 |
| Peak memory | 201432 kb |
| Host | smart-1679f36b-044b-48a2-ac3c-04108e1aba07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392091939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2392091939 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3802134836 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 66391111712 ps |
| CPU time | 170.36 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:15:34 PM PST 23 |
| Peak memory | 201584 kb |
| Host | smart-19bb84c2-9c7d-46ec-bc0b-2d52ed0943b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3802134836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3802134836 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1057648090 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 8308969 ps |
| CPU time | 1.14 seconds |
| Started | Dec 24 01:12:30 PM PST 23 |
| Finished | Dec 24 01:12:44 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-24752b12-5bdb-44f5-840e-f1a96a0dfd99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057648090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1057648090 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.4094505265 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 957258428 ps |
| CPU time | 10.53 seconds |
| Started | Dec 24 01:12:29 PM PST 23 |
| Finished | Dec 24 01:12:52 PM PST 23 |
| Peak memory | 201440 kb |
| Host | smart-08fa994d-12df-4c6e-9dab-f853aa4dc7be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4094505265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.4094505265 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.2465535850 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 52688995 ps |
| CPU time | 1.49 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:12:47 PM PST 23 |
| Peak memory | 201340 kb |
| Host | smart-e1f2ef99-d16d-4196-b779-62382eab139d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2465535850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2465535850 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2959041581 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1768837358 ps |
| CPU time | 8.54 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:12:52 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-9c635cc6-6b92-42ea-9065-265e3240d282 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959041581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2959041581 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1424504674 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2248538307 ps |
| CPU time | 6.18 seconds |
| Started | Dec 24 01:12:12 PM PST 23 |
| Finished | Dec 24 01:12:30 PM PST 23 |
| Peak memory | 201544 kb |
| Host | smart-74320097-7a23-4c8e-989d-4d068f364f9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1424504674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1424504674 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2887181146 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7641639 ps |
| CPU time | 1.11 seconds |
| Started | Dec 24 01:12:50 PM PST 23 |
| Finished | Dec 24 01:12:58 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-a019701b-a40b-4903-ad95-d7f6da96c874 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887181146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2887181146 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2470582326 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2017212765 ps |
| CPU time | 18.52 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:13:04 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-aee9f4f7-cb32-4f9d-952d-be50fada7f53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2470582326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2470582326 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4272016396 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 18665650287 ps |
| CPU time | 74.87 seconds |
| Started | Dec 24 01:12:25 PM PST 23 |
| Finished | Dec 24 01:13:52 PM PST 23 |
| Peak memory | 201544 kb |
| Host | smart-f7ef6124-8ebf-4a88-95e4-0d476371de6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4272016396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4272016396 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1038472655 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 420510225 ps |
| CPU time | 50.9 seconds |
| Started | Dec 24 01:12:24 PM PST 23 |
| Finished | Dec 24 01:13:27 PM PST 23 |
| Peak memory | 203552 kb |
| Host | smart-14591989-0191-4d08-92f7-3af4ac4aa267 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1038472655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.1038472655 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1504653919 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 99642285 ps |
| CPU time | 4.27 seconds |
| Started | Dec 24 01:12:32 PM PST 23 |
| Finished | Dec 24 01:12:49 PM PST 23 |
| Peak memory | 201424 kb |
| Host | smart-57d93c8b-9d82-4834-9195-d48a60da9470 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1504653919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.1504653919 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2589069449 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 240293840 ps |
| CPU time | 7.22 seconds |
| Started | Dec 24 01:12:25 PM PST 23 |
| Finished | Dec 24 01:12:44 PM PST 23 |
| Peak memory | 201384 kb |
| Host | smart-d1651d3a-4f19-490c-bb56-e762dda6d1b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2589069449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2589069449 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.1451030663 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4766443077 ps |
| CPU time | 18.66 seconds |
| Started | Dec 24 01:12:38 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201516 kb |
| Host | smart-0c9eeb4e-5e11-43ba-bbef-22638f382ea6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1451030663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1451030663 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.109183262 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 211285164548 ps |
| CPU time | 196.52 seconds |
| Started | Dec 24 01:12:29 PM PST 23 |
| Finished | Dec 24 01:16:03 PM PST 23 |
| Peak memory | 203536 kb |
| Host | smart-21d34a0e-7215-423d-9b99-58d5b3a10862 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=109183262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow _rsp.109183262 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.757546549 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 395258433 ps |
| CPU time | 7.63 seconds |
| Started | Dec 24 01:12:35 PM PST 23 |
| Finished | Dec 24 01:12:56 PM PST 23 |
| Peak memory | 201448 kb |
| Host | smart-5383b02e-d8e0-4d5a-85dc-f69369dd275d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=757546549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.757546549 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.81241145 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1757556227 ps |
| CPU time | 13.61 seconds |
| Started | Dec 24 01:12:24 PM PST 23 |
| Finished | Dec 24 01:12:49 PM PST 23 |
| Peak memory | 201332 kb |
| Host | smart-b7b71a30-12b1-4795-82ac-5aab84748d82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=81241145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.81241145 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.1002413714 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 694235435 ps |
| CPU time | 13.23 seconds |
| Started | Dec 24 01:12:30 PM PST 23 |
| Finished | Dec 24 01:12:56 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-08280db7-a999-4156-843f-cca7b9c7e18e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1002413714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1002413714 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1091890773 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 29213928721 ps |
| CPU time | 127.21 seconds |
| Started | Dec 24 01:12:24 PM PST 23 |
| Finished | Dec 24 01:14:43 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-19146364-0da2-454b-b1a1-706cf07ac771 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091890773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1091890773 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2339237528 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 6914019279 ps |
| CPU time | 17.41 seconds |
| Started | Dec 24 01:12:53 PM PST 23 |
| Finished | Dec 24 01:13:18 PM PST 23 |
| Peak memory | 201512 kb |
| Host | smart-45aa908e-edbe-418d-a050-e301554e386b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2339237528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2339237528 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.178298319 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 169732064 ps |
| CPU time | 6.56 seconds |
| Started | Dec 24 01:12:25 PM PST 23 |
| Finished | Dec 24 01:12:43 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-d8626dc7-9fb9-4768-a168-90c97b6e8837 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178298319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.178298319 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.3367795546 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 739826367 ps |
| CPU time | 6.9 seconds |
| Started | Dec 24 01:12:45 PM PST 23 |
| Finished | Dec 24 01:13:00 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-a406ed55-c189-41af-b88b-9d15170504c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3367795546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3367795546 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.4257656626 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 49944390 ps |
| CPU time | 1.36 seconds |
| Started | Dec 24 01:12:25 PM PST 23 |
| Finished | Dec 24 01:12:38 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-60435309-580c-491c-8039-5bf9cd964f3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4257656626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.4257656626 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2088966470 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1396486840 ps |
| CPU time | 7.55 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:12:51 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-a64f6f1f-8d6e-4451-95e3-d44256b5d415 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088966470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2088966470 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1139738328 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 2416762487 ps |
| CPU time | 11.2 seconds |
| Started | Dec 24 01:12:23 PM PST 23 |
| Finished | Dec 24 01:12:46 PM PST 23 |
| Peak memory | 201560 kb |
| Host | smart-bf650a2e-acae-4720-abb8-05128503920e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1139738328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1139738328 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.4262525069 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 8009203 ps |
| CPU time | 0.97 seconds |
| Started | Dec 24 01:12:29 PM PST 23 |
| Finished | Dec 24 01:12:43 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-52c63ed3-2693-45aa-b6b2-7dff376bf763 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262525069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.4262525069 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.3688603593 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 108682236 ps |
| CPU time | 12.06 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:12:50 PM PST 23 |
| Peak memory | 201492 kb |
| Host | smart-a575a993-30b1-4a53-b355-9368a0b5b7e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3688603593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3688603593 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2410694758 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1410892368 ps |
| CPU time | 22.6 seconds |
| Started | Dec 24 01:12:29 PM PST 23 |
| Finished | Dec 24 01:13:04 PM PST 23 |
| Peak memory | 201500 kb |
| Host | smart-33fbbedb-9e43-4334-828a-7307dfd6a283 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2410694758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2410694758 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1432641460 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 17108600050 ps |
| CPU time | 189.86 seconds |
| Started | Dec 24 01:12:17 PM PST 23 |
| Finished | Dec 24 01:15:39 PM PST 23 |
| Peak memory | 204052 kb |
| Host | smart-853b8360-49a5-44c6-a6e3-18057f030076 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1432641460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.1432641460 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.3112860527 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1366943010 ps |
| CPU time | 8.06 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:12:46 PM PST 23 |
| Peak memory | 201404 kb |
| Host | smart-c43868f4-87fa-4a52-9b9d-77f829f5da0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3112860527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3112860527 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3167438058 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 458530278 ps |
| CPU time | 6.71 seconds |
| Started | Dec 24 01:12:28 PM PST 23 |
| Finished | Dec 24 01:12:47 PM PST 23 |
| Peak memory | 201428 kb |
| Host | smart-1dada569-2421-4909-a4f3-cfb9b92f1b9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3167438058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3167438058 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.209405256 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 104904465 ps |
| CPU time | 3.56 seconds |
| Started | Dec 24 01:12:21 PM PST 23 |
| Finished | Dec 24 01:12:37 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-4a24bc20-3795-4b0f-b6d7-92ea3792be28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=209405256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.209405256 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.1748685814 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 90202346 ps |
| CPU time | 5.17 seconds |
| Started | Dec 24 01:12:48 PM PST 23 |
| Finished | Dec 24 01:13:01 PM PST 23 |
| Peak memory | 201356 kb |
| Host | smart-fcd956ee-1692-44f2-a2a0-ca7a62ec445d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1748685814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1748685814 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.1135217082 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 797428036 ps |
| CPU time | 11.92 seconds |
| Started | Dec 24 01:12:23 PM PST 23 |
| Finished | Dec 24 01:12:47 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-fe2d0cfd-a860-4ae3-9700-69b83d795875 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1135217082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1135217082 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.733876474 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 90199597686 ps |
| CPU time | 98.09 seconds |
| Started | Dec 24 01:12:18 PM PST 23 |
| Finished | Dec 24 01:14:08 PM PST 23 |
| Peak memory | 201540 kb |
| Host | smart-b5710f5e-b3e1-44f0-ba87-10aa7cb33c67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=733876474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.733876474 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3648256482 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 17016403913 ps |
| CPU time | 85.63 seconds |
| Started | Dec 24 01:12:26 PM PST 23 |
| Finished | Dec 24 01:14:09 PM PST 23 |
| Peak memory | 201576 kb |
| Host | smart-0e64032e-8165-46cd-91cf-450297d1f08b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3648256482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3648256482 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1778178916 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 234511192 ps |
| CPU time | 7.9 seconds |
| Started | Dec 24 01:12:46 PM PST 23 |
| Finished | Dec 24 01:13:02 PM PST 23 |
| Peak memory | 201356 kb |
| Host | smart-90cb55c4-dd16-43ae-9267-d439e3011abe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778178916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1778178916 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.3730408580 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 99180944 ps |
| CPU time | 2.25 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:12:41 PM PST 23 |
| Peak memory | 201428 kb |
| Host | smart-93587e9e-e1f2-4600-9b17-ba373818e2ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3730408580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3730408580 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.2433747551 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 49795488 ps |
| CPU time | 1.45 seconds |
| Started | Dec 24 01:12:46 PM PST 23 |
| Finished | Dec 24 01:12:55 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-dca47ae3-355c-43d3-b522-f08e7f2952a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2433747551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2433747551 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.591916098 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1392636859 ps |
| CPU time | 7.6 seconds |
| Started | Dec 24 01:12:36 PM PST 23 |
| Finished | Dec 24 01:12:57 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-66c649a9-6ce9-462d-b577-e3d8f92ea65f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=591916098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.591916098 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3532543605 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 6488496864 ps |
| CPU time | 6.97 seconds |
| Started | Dec 24 01:12:28 PM PST 23 |
| Finished | Dec 24 01:12:47 PM PST 23 |
| Peak memory | 201460 kb |
| Host | smart-3d943265-10ae-4dd9-befb-a327e9780eac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3532543605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3532543605 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2540674818 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 12275068 ps |
| CPU time | 1.08 seconds |
| Started | Dec 24 01:12:17 PM PST 23 |
| Finished | Dec 24 01:12:30 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-08bff729-21ac-43ba-8d31-f8308021c193 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540674818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2540674818 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.1816476595 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3087338762 ps |
| CPU time | 23.75 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:13:07 PM PST 23 |
| Peak memory | 201552 kb |
| Host | smart-05e35cb2-fb4a-41a6-9a25-f254fa1b82d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1816476595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1816476595 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1489012397 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3480260114 ps |
| CPU time | 66.09 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:13:49 PM PST 23 |
| Peak memory | 201568 kb |
| Host | smart-ffa2ef58-2c9b-45d7-8703-7a8a18926f63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1489012397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1489012397 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1223267593 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 524921179 ps |
| CPU time | 71.46 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:13:51 PM PST 23 |
| Peak memory | 203568 kb |
| Host | smart-d309a2b9-c2f4-47a6-a18f-c87a9b1eb6ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1223267593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.1223267593 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3210957480 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 91888752 ps |
| CPU time | 12.93 seconds |
| Started | Dec 24 01:12:40 PM PST 23 |
| Finished | Dec 24 01:13:04 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-a76eeb1d-0ca3-4d85-b7b0-f18ee2c8a568 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3210957480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.3210957480 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1599614777 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 674705410 ps |
| CPU time | 3.93 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-423e940a-0737-48e4-8a4d-a8ed2b4132d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1599614777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1599614777 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1857685789 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1406029612 ps |
| CPU time | 14.9 seconds |
| Started | Dec 24 01:12:29 PM PST 23 |
| Finished | Dec 24 01:12:57 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-b1c612ce-dae9-4536-9a6c-4dbd572f7a41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1857685789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1857685789 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3967561036 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 85066454 ps |
| CPU time | 5.23 seconds |
| Started | Dec 24 01:12:28 PM PST 23 |
| Finished | Dec 24 01:12:46 PM PST 23 |
| Peak memory | 201380 kb |
| Host | smart-18e423f8-6485-424f-a669-ee70f0c54a6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3967561036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3967561036 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.4089637615 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 997683795 ps |
| CPU time | 10.07 seconds |
| Started | Dec 24 01:12:40 PM PST 23 |
| Finished | Dec 24 01:13:01 PM PST 23 |
| Peak memory | 201396 kb |
| Host | smart-eb28ec6c-232c-4207-a10f-b5364e3f54ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4089637615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.4089637615 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.1069731660 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 40329692 ps |
| CPU time | 4.77 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:12:50 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-eac40868-3e90-4415-baa6-b9461120ec75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1069731660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1069731660 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2738606821 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 29700881639 ps |
| CPU time | 123.9 seconds |
| Started | Dec 24 01:13:08 PM PST 23 |
| Finished | Dec 24 01:15:28 PM PST 23 |
| Peak memory | 201532 kb |
| Host | smart-7b19d4d2-424c-4b96-9ba1-f0f27c866886 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738606821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2738606821 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.4013052386 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 22434162248 ps |
| CPU time | 138 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:15:08 PM PST 23 |
| Peak memory | 201572 kb |
| Host | smart-c16cacbd-4878-4002-835f-82773e04d54f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4013052386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.4013052386 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3691647474 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 354887962 ps |
| CPU time | 9 seconds |
| Started | Dec 24 01:12:27 PM PST 23 |
| Finished | Dec 24 01:12:48 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-881339be-0700-41af-938b-20d62aafe1b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691647474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3691647474 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.573341942 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 73898617 ps |
| CPU time | 5.63 seconds |
| Started | Dec 24 01:12:29 PM PST 23 |
| Finished | Dec 24 01:12:47 PM PST 23 |
| Peak memory | 201392 kb |
| Host | smart-ca488569-30cd-42b1-b6e5-f11491e710d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=573341942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.573341942 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.761751693 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 47456178 ps |
| CPU time | 1.44 seconds |
| Started | Dec 24 01:12:54 PM PST 23 |
| Finished | Dec 24 01:13:03 PM PST 23 |
| Peak memory | 201468 kb |
| Host | smart-79905952-5f2f-4000-9410-1ae241013c1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=761751693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.761751693 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.235068040 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 5338122014 ps |
| CPU time | 7.98 seconds |
| Started | Dec 24 01:12:36 PM PST 23 |
| Finished | Dec 24 01:12:57 PM PST 23 |
| Peak memory | 201528 kb |
| Host | smart-9f3ad0ac-fc07-4cb4-9416-5c10b0b17abc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=235068040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.235068040 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3965884722 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 1689319492 ps |
| CPU time | 11.29 seconds |
| Started | Dec 24 01:12:28 PM PST 23 |
| Finished | Dec 24 01:12:51 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-d8567a54-140c-4d54-96a4-d7f11ad1dd87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3965884722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3965884722 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1891399734 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 23804987 ps |
| CPU time | 1 seconds |
| Started | Dec 24 01:12:30 PM PST 23 |
| Finished | Dec 24 01:12:43 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-8fb3d97c-baad-4f2b-888f-741f2efc6468 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891399734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1891399734 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.354322269 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 148523084 ps |
| CPU time | 16.98 seconds |
| Started | Dec 24 01:13:08 PM PST 23 |
| Finished | Dec 24 01:13:40 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-dcd9bab6-dcf3-436c-91ad-23654f05d217 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=354322269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.354322269 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2528144375 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3824804932 ps |
| CPU time | 60.37 seconds |
| Started | Dec 24 01:12:37 PM PST 23 |
| Finished | Dec 24 01:13:50 PM PST 23 |
| Peak memory | 201556 kb |
| Host | smart-55887a51-2707-4675-a5bd-bbd7de3f546f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2528144375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2528144375 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.4073183668 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 403777199 ps |
| CPU time | 39.95 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:13:26 PM PST 23 |
| Peak memory | 203468 kb |
| Host | smart-600d9a52-ec91-457e-854d-8bf4e492fb7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4073183668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.4073183668 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.80869285 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 8311767 ps |
| CPU time | 3.8 seconds |
| Started | Dec 24 01:12:35 PM PST 23 |
| Finished | Dec 24 01:12:51 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-4d3838af-b8e2-4be9-858a-6ace79fd7222 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=80869285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset _error.80869285 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.270133469 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 82119367 ps |
| CPU time | 2.38 seconds |
| Started | Dec 24 01:12:57 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201476 kb |
| Host | smart-ce6ec7af-d8e2-49da-8be6-782c1fd27705 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=270133469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.270133469 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.316520256 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 354347145 ps |
| CPU time | 3.07 seconds |
| Started | Dec 24 01:12:30 PM PST 23 |
| Finished | Dec 24 01:12:45 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-5997e1d5-3e05-408d-81d8-60c136e2fdb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=316520256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.316520256 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2712328736 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 39599323426 ps |
| CPU time | 299.83 seconds |
| Started | Dec 24 01:12:55 PM PST 23 |
| Finished | Dec 24 01:18:03 PM PST 23 |
| Peak memory | 202600 kb |
| Host | smart-0b887dd2-5d7a-41a3-bebe-0d21685fd86b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2712328736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2712328736 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2777449734 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 98580559 ps |
| CPU time | 4.25 seconds |
| Started | Dec 24 01:12:14 PM PST 23 |
| Finished | Dec 24 01:12:31 PM PST 23 |
| Peak memory | 201480 kb |
| Host | smart-19b7cea6-bf1c-4c75-9b26-9e1e9db39e00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2777449734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2777449734 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.3042204229 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 46920882 ps |
| CPU time | 2.44 seconds |
| Started | Dec 24 01:12:33 PM PST 23 |
| Finished | Dec 24 01:12:48 PM PST 23 |
| Peak memory | 201372 kb |
| Host | smart-88351be9-8cdc-473b-9663-e78cf50531a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3042204229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3042204229 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.3863981215 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 48525231 ps |
| CPU time | 4.07 seconds |
| Started | Dec 24 01:12:15 PM PST 23 |
| Finished | Dec 24 01:12:32 PM PST 23 |
| Peak memory | 201460 kb |
| Host | smart-256ab416-68cf-4e1b-9dda-e436bdab3859 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3863981215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3863981215 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.2864153148 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 13870443103 ps |
| CPU time | 56.62 seconds |
| Started | Dec 24 01:12:23 PM PST 23 |
| Finished | Dec 24 01:13:32 PM PST 23 |
| Peak memory | 201520 kb |
| Host | smart-6b05403c-6f27-4e5f-b200-33d33206845c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864153148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2864153148 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2068291569 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 24212929184 ps |
| CPU time | 26.14 seconds |
| Started | Dec 24 01:12:30 PM PST 23 |
| Finished | Dec 24 01:13:09 PM PST 23 |
| Peak memory | 201568 kb |
| Host | smart-06f14471-998c-4b03-9874-e5c2b5105240 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2068291569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2068291569 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.4148397735 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 73061797 ps |
| CPU time | 7.96 seconds |
| Started | Dec 24 01:12:29 PM PST 23 |
| Finished | Dec 24 01:12:49 PM PST 23 |
| Peak memory | 201488 kb |
| Host | smart-8ac7f2a7-d595-423c-9f8f-dbedb17f80ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148397735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.4148397735 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.724112772 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 1818038985 ps |
| CPU time | 11.67 seconds |
| Started | Dec 24 01:12:49 PM PST 23 |
| Finished | Dec 24 01:13:08 PM PST 23 |
| Peak memory | 201484 kb |
| Host | smart-5d5b53fc-9206-41db-a35f-f2baa1147300 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=724112772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.724112772 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.1091395144 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 94797024 ps |
| CPU time | 1.83 seconds |
| Started | Dec 24 01:12:53 PM PST 23 |
| Finished | Dec 24 01:13:02 PM PST 23 |
| Peak memory | 201376 kb |
| Host | smart-3ddba8a1-a5de-43f2-8f0d-52ddeb628a52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1091395144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1091395144 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3230545558 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 2352269580 ps |
| CPU time | 9.47 seconds |
| Started | Dec 24 01:12:58 PM PST 23 |
| Finished | Dec 24 01:13:18 PM PST 23 |
| Peak memory | 201548 kb |
| Host | smart-e2a9d16c-9fbf-4217-9122-03f814d66f84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230545558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3230545558 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3076095020 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 1185646848 ps |
| CPU time | 7.86 seconds |
| Started | Dec 24 01:12:37 PM PST 23 |
| Finished | Dec 24 01:12:58 PM PST 23 |
| Peak memory | 201428 kb |
| Host | smart-00a5ccac-a5fb-433d-8604-d03b470684fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3076095020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3076095020 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3679087160 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 8069274 ps |
| CPU time | 1.09 seconds |
| Started | Dec 24 01:12:42 PM PST 23 |
| Finished | Dec 24 01:12:54 PM PST 23 |
| Peak memory | 201428 kb |
| Host | smart-2a1d311c-d0cf-4d20-b10d-258e6ea7b85e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679087160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3679087160 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.576022664 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 232319006 ps |
| CPU time | 22.07 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:13:06 PM PST 23 |
| Peak memory | 201464 kb |
| Host | smart-485bec07-ef7d-4afd-8132-6c166237d99b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=576022664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.576022664 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.837762165 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 792871939 ps |
| CPU time | 57.54 seconds |
| Started | Dec 24 01:12:43 PM PST 23 |
| Finished | Dec 24 01:13:50 PM PST 23 |
| Peak memory | 203752 kb |
| Host | smart-3674f04d-a6b4-4244-a2ee-ae92e227fb7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=837762165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_ reset.837762165 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1543542674 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 900396624 ps |
| CPU time | 85.92 seconds |
| Started | Dec 24 01:12:31 PM PST 23 |
| Finished | Dec 24 01:14:10 PM PST 23 |
| Peak memory | 204104 kb |
| Host | smart-59602558-3686-4f91-8a8c-b106b27f70f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1543542674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.1543542674 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.2908583129 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 390105463 ps |
| CPU time | 5.89 seconds |
| Started | Dec 24 01:12:20 PM PST 23 |
| Finished | Dec 24 01:12:39 PM PST 23 |
| Peak memory | 201444 kb |
| Host | smart-393be2a4-e288-4815-bb14-ae78ceca12bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2908583129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2908583129 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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