Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	479	1			T2	1		T6	4		T112	1
all_values[1]	458	1			T112	1		T114	8		T28	1
all_values[2]	460	1			T6	2		T22	1		T112	1
all_values[3]	486	1			T2	1		T6	2		T114	2
all_values[4]	507	1			T6	1		T22	1		T112	1
all_values[5]	486	1			T6	4		T114	4		T44	2
all_values[6]	461	1			T6	1		T17	1		T112	2
all_values[7]	437	1			T6	4		T112	1		T114	1
all_values[8]	459	1			T6	1		T114	8		T33	1
all_values[9]	467	1			T2	2		T6	1		T112	1
all_values[10]	465	1			T6	3		T112	1		T114	5
all_values[11]	435	1			T2	1		T6	1		T112	1
all_values[12]	480	1			T6	1		T112	1		T113	1
all_values[13]	516	1			T6	1		T112	1		T114	4
all_values[14]	477	1			T2	1		T114	8		T28	1
all_values[15]	480	1			T2	1		T6	2		T112	1
all_values[16]	467	1			T6	1		T114	2		T160	2
all_values[17]	462	1			T2	3		T114	7		T160	3
all_values[18]	433	1			T114	3		T33	1		T44	1
all_values[19]	486	1			T6	1		T112	1		T114	5
all_values[20]	467	1			T2	1		T6	4		T17	1
all_values[21]	454	1			T6	2		T22	2		T112	1
all_values[22]	477	1			T6	1		T112	1		T114	5
all_values[23]	434	1			T6	2		T114	2		T44	1
all_values[24]	478	1			T6	1		T112	3		T114	4
all_values[25]	465	1			T2	1		T112	2		T114	9
all_values[26]	471	1			T2	1		T6	2		T22	1