Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	427	1			T2	2		T40	3		T25	1
all_values[1]	412	1			T40	8		T39	1		T301	2
all_values[2]	450	1			T2	5		T40	2		T301	2
all_values[3]	422	1			T2	2		T40	3		T25	1
all_values[4]	398	1			T2	3		T40	4		T39	1
all_values[5]	420	1			T2	3		T40	4		T264	1
all_values[6]	442	1			T2	1		T40	3		T25	2
all_values[7]	451	1			T2	3		T40	4		T264	1
all_values[8]	404	1			T2	4		T40	3		T25	1
all_values[9]	418	1			T2	5		T40	6		T25	1
all_values[10]	426	1			T2	2		T40	4		T25	1
all_values[11]	406	1			T2	9		T40	3		T264	1
all_values[12]	410	1			T2	1		T40	4		T301	3
all_values[13]	430	1			T2	3		T40	4		T25	2
all_values[14]	426	1			T40	2		T264	1		T301	2
all_values[15]	405	1			T2	4		T40	4		T25	2
all_values[16]	422	1			T2	3		T40	3		T39	2
all_values[17]	411	1			T2	1		T14	1		T40	5
all_values[18]	406	1			T2	2		T40	8		T25	1
all_values[19]	385	1			T2	2		T40	3		T25	1
all_values[20]	390	1			T40	9		T264	2		T301	2
all_values[21]	426	1			T2	1		T40	4		T25	1
all_values[22]	407	1			T2	3		T40	2		T27	1
all_values[23]	425	1			T2	1		T40	3		T264	1
all_values[24]	405	1			T40	4		T25	2		T39	3
all_values[25]	420	1			T2	2		T40	1		T264	2
all_values[26]	408	1			T2	3		T40	5		T27	1