| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.22 | 100.00 | 95.34 | 100.00 | 100.00 | 100.00 | 100.00 |
| T759 | /workspace/coverage/xbar_build_mode/19.xbar_error_random.1504320568 | Jan 03 12:39:05 PM PST 24 | Jan 03 12:40:39 PM PST 24 | 326906318 ps | ||
| T760 | /workspace/coverage/xbar_build_mode/4.xbar_smoke.3419886448 | Jan 03 12:38:32 PM PST 24 | Jan 03 12:39:44 PM PST 24 | 9901606 ps | ||
| T761 | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.965198781 | Jan 03 12:39:59 PM PST 24 | Jan 03 12:41:36 PM PST 24 | 1419261375 ps | ||
| T9 | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.650963721 | Jan 03 12:38:29 PM PST 24 | Jan 03 12:42:21 PM PST 24 | 9256431139 ps | ||
| T762 | /workspace/coverage/xbar_build_mode/32.xbar_smoke.2455553084 | Jan 03 12:39:45 PM PST 24 | Jan 03 12:41:09 PM PST 24 | 84584900 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/33.xbar_smoke.2263940486 | Jan 03 12:40:13 PM PST 24 | Jan 03 12:41:41 PM PST 24 | 8838960 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.791753485 | Jan 03 12:38:39 PM PST 24 | Jan 03 12:40:21 PM PST 24 | 1787883828 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/23.xbar_random.3025542612 | Jan 03 12:38:55 PM PST 24 | Jan 03 12:40:24 PM PST 24 | 27525997 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3220459354 | Jan 03 12:38:50 PM PST 24 | Jan 03 12:40:07 PM PST 24 | 11968630 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3027704024 | Jan 03 12:39:57 PM PST 24 | Jan 03 12:42:50 PM PST 24 | 612149530 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2273523663 | Jan 03 12:38:28 PM PST 24 | Jan 03 12:41:51 PM PST 24 | 4897791934 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/14.xbar_smoke.2301830257 | Jan 03 12:39:04 PM PST 24 | Jan 03 12:40:38 PM PST 24 | 84436514 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1810716982 | Jan 03 12:38:39 PM PST 24 | Jan 03 12:39:53 PM PST 24 | 637066449 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1856954612 | Jan 03 12:38:01 PM PST 24 | Jan 03 12:41:28 PM PST 24 | 72505676306 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1442703537 | Jan 03 12:37:57 PM PST 24 | Jan 03 12:39:13 PM PST 24 | 14354709 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3309996357 | Jan 03 12:39:07 PM PST 24 | Jan 03 12:40:34 PM PST 24 | 69429810 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.2668345880 | Jan 03 12:39:56 PM PST 24 | Jan 03 12:41:41 PM PST 24 | 40399875 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.701437904 | Jan 03 12:39:13 PM PST 24 | Jan 03 12:40:43 PM PST 24 | 82636796 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/40.xbar_random.499556481 | Jan 03 12:40:40 PM PST 24 | Jan 03 12:42:26 PM PST 24 | 892789535 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1153743829 | Jan 03 12:38:29 PM PST 24 | Jan 03 12:39:55 PM PST 24 | 350902762 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1501680720 | Jan 03 12:38:54 PM PST 24 | Jan 03 12:41:37 PM PST 24 | 23550789310 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/48.xbar_smoke.365412053 | Jan 03 12:40:23 PM PST 24 | Jan 03 12:41:59 PM PST 24 | 232043610 ps | ||
| T111 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.2221832252 | Jan 03 12:38:46 PM PST 24 | Jan 03 12:41:03 PM PST 24 | 4638605024 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/24.xbar_random.690340209 | Jan 03 12:39:29 PM PST 24 | Jan 03 12:40:56 PM PST 24 | 54058478 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1016591395 | Jan 03 12:38:37 PM PST 24 | Jan 03 12:39:57 PM PST 24 | 6529006945 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3850326952 | Jan 03 12:40:39 PM PST 24 | Jan 03 12:42:09 PM PST 24 | 11884135 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2578343188 | Jan 03 12:40:07 PM PST 24 | Jan 03 12:41:57 PM PST 24 | 18713667 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1883359680 | Jan 03 12:40:02 PM PST 24 | Jan 03 12:41:31 PM PST 24 | 39391105 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/30.xbar_error_random.3756977680 | Jan 03 12:39:51 PM PST 24 | Jan 03 12:41:29 PM PST 24 | 83017614 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.473220569 | Jan 03 12:39:26 PM PST 24 | Jan 03 12:41:12 PM PST 24 | 43701992 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2344659978 | Jan 03 12:40:13 PM PST 24 | Jan 03 12:41:53 PM PST 24 | 3010715925 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2339112309 | Jan 03 12:37:57 PM PST 24 | Jan 03 12:42:27 PM PST 24 | 52397847643 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1908631239 | Jan 03 12:38:05 PM PST 24 | Jan 03 12:39:29 PM PST 24 | 114435344 ps | ||
| T141 | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2587817586 | Jan 03 12:38:30 PM PST 24 | Jan 03 12:39:52 PM PST 24 | 620945564 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3164201755 | Jan 03 12:39:22 PM PST 24 | Jan 03 12:42:20 PM PST 24 | 42844981692 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/8.xbar_same_source.2354218457 | Jan 03 12:38:14 PM PST 24 | Jan 03 12:39:36 PM PST 24 | 950708070 ps | ||
| T125 | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.697544024 | Jan 03 12:38:28 PM PST 24 | Jan 03 12:41:04 PM PST 24 | 25091915287 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2915538512 | Jan 03 12:39:03 PM PST 24 | Jan 03 12:40:48 PM PST 24 | 1652419942 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2448721283 | Jan 03 12:38:49 PM PST 24 | Jan 03 12:39:57 PM PST 24 | 61655029 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2014270784 | Jan 03 12:40:04 PM PST 24 | Jan 03 12:42:49 PM PST 24 | 416814725 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3910058777 | Jan 03 12:38:57 PM PST 24 | Jan 03 12:40:26 PM PST 24 | 18628828 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2916493273 | Jan 03 12:39:09 PM PST 24 | Jan 03 12:41:51 PM PST 24 | 8595212993 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.220185537 | Jan 03 12:39:43 PM PST 24 | Jan 03 12:42:01 PM PST 24 | 522994881 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/42.xbar_same_source.3538273174 | Jan 03 12:40:13 PM PST 24 | Jan 03 12:41:44 PM PST 24 | 437437235 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.4134031413 | Jan 03 12:38:31 PM PST 24 | Jan 03 12:40:54 PM PST 24 | 20663470143 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/8.xbar_random.394755330 | Jan 03 12:38:42 PM PST 24 | Jan 03 12:39:59 PM PST 24 | 559421715 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1454161728 | Jan 03 12:38:44 PM PST 24 | Jan 03 12:40:25 PM PST 24 | 4012109203 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1701395511 | Jan 03 12:40:14 PM PST 24 | Jan 03 12:41:55 PM PST 24 | 9389426 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3917256405 | Jan 03 12:40:24 PM PST 24 | Jan 03 12:42:09 PM PST 24 | 210629169 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2911576459 | Jan 03 12:40:01 PM PST 24 | Jan 03 12:41:28 PM PST 24 | 80755488 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1896076980 | Jan 03 12:38:29 PM PST 24 | Jan 03 12:40:15 PM PST 24 | 15365751619 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2245909005 | Jan 03 12:40:24 PM PST 24 | Jan 03 12:42:07 PM PST 24 | 135642939 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1365091803 | Jan 03 12:39:58 PM PST 24 | Jan 03 12:42:36 PM PST 24 | 8881746629 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.899330268 | Jan 03 12:40:27 PM PST 24 | Jan 03 12:42:20 PM PST 24 | 3433800182 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.4043583023 | Jan 03 12:39:39 PM PST 24 | Jan 03 12:41:42 PM PST 24 | 399969973 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.454232911 | Jan 03 12:40:13 PM PST 24 | Jan 03 12:42:02 PM PST 24 | 605884340 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3356015104 | Jan 03 12:40:23 PM PST 24 | Jan 03 12:43:39 PM PST 24 | 7157363247 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.1705347036 | Jan 03 12:38:47 PM PST 24 | Jan 03 12:41:13 PM PST 24 | 9855433125 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1653037477 | Jan 03 12:39:49 PM PST 24 | Jan 03 12:41:20 PM PST 24 | 96593968 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1780973008 | Jan 03 12:38:09 PM PST 24 | Jan 03 12:39:23 PM PST 24 | 10099555 ps | ||
| T112 | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1941621505 | Jan 03 12:38:18 PM PST 24 | Jan 03 12:40:56 PM PST 24 | 9697991431 ps | ||
| T167 | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.486609482 | Jan 03 12:39:22 PM PST 24 | Jan 03 12:41:00 PM PST 24 | 1161758647 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1107092021 | Jan 03 12:39:08 PM PST 24 | Jan 03 12:40:45 PM PST 24 | 8509480573 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.977122534 | Jan 03 12:39:53 PM PST 24 | Jan 03 12:46:52 PM PST 24 | 59342944804 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/36.xbar_smoke.1097630360 | Jan 03 12:40:01 PM PST 24 | Jan 03 12:41:32 PM PST 24 | 10439470 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.289879816 | Jan 03 12:38:15 PM PST 24 | Jan 03 12:39:40 PM PST 24 | 210140518 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.3008016618 | Jan 03 12:38:23 PM PST 24 | Jan 03 12:40:05 PM PST 24 | 8769183123 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.510123875 | Jan 03 12:37:52 PM PST 24 | Jan 03 12:39:13 PM PST 24 | 54919181 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3224911827 | Jan 03 12:38:19 PM PST 24 | Jan 03 12:40:35 PM PST 24 | 942586080 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3002157599 | Jan 03 12:39:02 PM PST 24 | Jan 03 12:40:19 PM PST 24 | 7837647202 ps | ||
| T113 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.2514607721 | Jan 03 12:40:52 PM PST 24 | Jan 03 12:42:50 PM PST 24 | 2646784668 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.203781708 | Jan 03 12:39:28 PM PST 24 | Jan 03 12:40:53 PM PST 24 | 3994353608 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/6.xbar_same_source.3222293980 | Jan 03 12:38:55 PM PST 24 | Jan 03 12:40:12 PM PST 24 | 43998082 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3746172315 | Jan 03 12:39:07 PM PST 24 | Jan 03 12:40:56 PM PST 24 | 1132674225 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2779094814 | Jan 03 12:38:18 PM PST 24 | Jan 03 12:39:40 PM PST 24 | 890124452 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.104573787 | Jan 03 12:39:34 PM PST 24 | Jan 03 12:41:42 PM PST 24 | 6562487101 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2040186205 | Jan 03 12:39:36 PM PST 24 | Jan 03 12:41:02 PM PST 24 | 28184333 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1081282381 | Jan 03 12:38:56 PM PST 24 | Jan 03 12:40:04 PM PST 24 | 8361965 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.2174532793 | Jan 03 12:39:20 PM PST 24 | Jan 03 12:41:44 PM PST 24 | 6238729759 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3367205579 | Jan 03 12:38:34 PM PST 24 | Jan 03 12:39:51 PM PST 24 | 299150855 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1472188119 | Jan 03 12:38:23 PM PST 24 | Jan 03 12:39:49 PM PST 24 | 17184839 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/15.xbar_same_source.4195987204 | Jan 03 12:38:48 PM PST 24 | Jan 03 12:40:12 PM PST 24 | 993497066 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2774699577 | Jan 03 12:40:39 PM PST 24 | Jan 03 12:42:18 PM PST 24 | 609400108 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/46.xbar_smoke.3728430608 | Jan 03 12:40:20 PM PST 24 | Jan 03 12:41:58 PM PST 24 | 8912190 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2833362905 | Jan 03 12:40:22 PM PST 24 | Jan 03 12:42:09 PM PST 24 | 295393342 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2730420380 | Jan 03 12:38:16 PM PST 24 | Jan 03 12:39:40 PM PST 24 | 1989870927 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.1272516752 | Jan 03 12:40:23 PM PST 24 | Jan 03 12:42:45 PM PST 24 | 12644947244 ps | ||
| T6 | /workspace/coverage/xbar_build_mode/26.xbar_same_source.3793560560 | Jan 03 12:39:19 PM PST 24 | Jan 03 12:40:48 PM PST 24 | 66341801 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1009990122 | Jan 03 12:40:05 PM PST 24 | Jan 03 12:41:34 PM PST 24 | 99141221 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2422170806 | Jan 03 12:39:00 PM PST 24 | Jan 03 12:40:29 PM PST 24 | 157472304 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/2.xbar_error_random.2506365044 | Jan 03 12:38:19 PM PST 24 | Jan 03 12:39:41 PM PST 24 | 2770244329 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1026580988 | Jan 03 12:38:57 PM PST 24 | Jan 03 12:40:27 PM PST 24 | 44417827 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/46.xbar_random.1625890312 | Jan 03 12:40:23 PM PST 24 | Jan 03 12:42:01 PM PST 24 | 1329425264 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1185115561 | Jan 03 12:40:16 PM PST 24 | Jan 03 12:45:10 PM PST 24 | 29349126300 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3647972820 | Jan 03 12:40:06 PM PST 24 | Jan 03 12:42:56 PM PST 24 | 1427187937 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3993105132 | Jan 03 12:40:17 PM PST 24 | Jan 03 12:41:51 PM PST 24 | 57284465 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/9.xbar_same_source.2758637261 | Jan 03 12:38:57 PM PST 24 | Jan 03 12:40:25 PM PST 24 | 197228859 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.50797950 | Jan 03 12:39:01 PM PST 24 | Jan 03 12:40:25 PM PST 24 | 80957741 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/8.xbar_error_random.2896838228 | Jan 03 12:38:18 PM PST 24 | Jan 03 12:40:35 PM PST 24 | 112280120 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1300048528 | Jan 03 12:38:12 PM PST 24 | Jan 03 12:41:41 PM PST 24 | 28605533134 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2103311900 | Jan 03 12:40:25 PM PST 24 | Jan 03 12:42:13 PM PST 24 | 14499691 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.171493194 | Jan 03 12:38:59 PM PST 24 | Jan 03 12:40:30 PM PST 24 | 59051000 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.21219385 | Jan 03 12:38:18 PM PST 24 | Jan 03 12:42:26 PM PST 24 | 53477792747 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1859180151 | Jan 03 12:38:10 PM PST 24 | Jan 03 12:39:34 PM PST 24 | 143453415 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.682219641 | Jan 03 12:40:17 PM PST 24 | Jan 03 12:41:55 PM PST 24 | 47162119 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.790249412 | Jan 03 12:40:05 PM PST 24 | Jan 03 12:45:20 PM PST 24 | 37090579648 ps |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.366911649 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 266394458 ps |
| CPU time | 4.32 seconds |
| Started | Jan 03 12:40:19 PM PST 24 |
| Finished | Jan 03 12:41:47 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-458c0523-8a13-4445-87ad-9119fd23d27b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=366911649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.366911649 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.922461524 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 45029691328 ps |
| CPU time | 333.28 seconds |
| Started | Jan 03 12:38:44 PM PST 24 |
| Finished | Jan 03 12:45:40 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-640b0050-565f-48f1-8790-6f9756103dfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=922461524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slo w_rsp.922461524 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3139266931 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 62110491532 ps |
| CPU time | 335.28 seconds |
| Started | Jan 03 12:39:52 PM PST 24 |
| Finished | Jan 03 12:46:54 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-e28f4809-1fdd-421f-8ae3-b4640a1b4fbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3139266931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.3139266931 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2986240540 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6018844985 ps |
| CPU time | 173.54 seconds |
| Started | Jan 03 12:38:33 PM PST 24 |
| Finished | Jan 03 12:42:36 PM PST 24 |
| Peak memory | 204200 kb |
| Host | smart-02b92906-0aa1-4182-af2e-c61f5a1d87da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2986240540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.2986240540 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.115566752 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 49041252043 ps |
| CPU time | 322.09 seconds |
| Started | Jan 03 12:39:35 PM PST 24 |
| Finished | Jan 03 12:46:28 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-81d6e8fe-408b-4544-9773-0c7d4166d937 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=115566752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo w_rsp.115566752 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3884142538 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 90367360206 ps |
| CPU time | 224.86 seconds |
| Started | Jan 03 12:38:56 PM PST 24 |
| Finished | Jan 03 12:43:52 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-49030120-1daf-4ba3-a9c5-86a2497f366c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3884142538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.3884142538 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2799586310 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 42710561977 ps |
| CPU time | 195.03 seconds |
| Started | Jan 03 12:39:22 PM PST 24 |
| Finished | Jan 03 12:44:10 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-8cc860ea-6575-428c-a944-5c2f93176b07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2799586310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.2799586310 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.267371353 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 251649521 ps |
| CPU time | 62.63 seconds |
| Started | Jan 03 12:39:27 PM PST 24 |
| Finished | Jan 03 12:41:51 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-e78e936f-05d8-4337-90b7-9ac5c1df47cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=267371353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand _reset.267371353 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3449433765 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 6705425022 ps |
| CPU time | 219.46 seconds |
| Started | Jan 03 12:38:44 PM PST 24 |
| Finished | Jan 03 12:43:56 PM PST 24 |
| Peak memory | 204196 kb |
| Host | smart-766bc1e7-126e-4588-ba86-7eb65970f032 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3449433765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3449433765 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.4258429870 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 33251147981 ps |
| CPU time | 222.02 seconds |
| Started | Jan 03 12:39:28 PM PST 24 |
| Finished | Jan 03 12:44:39 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-d83f1e0f-f60f-4103-a671-35c3178bfe96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4258429870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.4258429870 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1877151246 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3434675396 ps |
| CPU time | 196.1 seconds |
| Started | Jan 03 12:40:24 PM PST 24 |
| Finished | Jan 03 12:45:10 PM PST 24 |
| Peak memory | 209632 kb |
| Host | smart-db8f2850-e336-4c1c-8595-b100e2272e29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1877151246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.1877151246 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.4263002368 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 73817397068 ps |
| CPU time | 119.03 seconds |
| Started | Jan 03 12:38:54 PM PST 24 |
| Finished | Jan 03 12:42:42 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-f7c23a1b-a7db-46f6-8b2b-be24c8285794 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263002368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.4263002368 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1498068079 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 30372159723 ps |
| CPU time | 179.83 seconds |
| Started | Jan 03 12:39:36 PM PST 24 |
| Finished | Jan 03 12:44:00 PM PST 24 |
| Peak memory | 202804 kb |
| Host | smart-babe05f1-0c8c-49c0-a165-1855ed323aae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1498068079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.1498068079 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.3793560560 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 66341801 ps |
| CPU time | 3.03 seconds |
| Started | Jan 03 12:39:19 PM PST 24 |
| Finished | Jan 03 12:40:48 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-b96db9e8-d59a-475a-a45e-949f0848f7cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3793560560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3793560560 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2582596153 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 43579907676 ps |
| CPU time | 124.48 seconds |
| Started | Jan 03 12:39:42 PM PST 24 |
| Finished | Jan 03 12:43:07 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-d764c083-7e2b-498f-830b-835a90ac9edd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2582596153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.2582596153 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.812242654 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 5499697508 ps |
| CPU time | 130.91 seconds |
| Started | Jan 03 12:40:21 PM PST 24 |
| Finished | Jan 03 12:44:11 PM PST 24 |
| Peak memory | 205052 kb |
| Host | smart-18633eee-e62e-4652-a622-6e62a6db2d03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=812242654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand _reset.812242654 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.421018027 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 28304187822 ps |
| CPU time | 199.28 seconds |
| Started | Jan 03 12:38:08 PM PST 24 |
| Finished | Jan 03 12:42:44 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-9975ab05-bb82-480e-a215-04f1d7a406ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=421018027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow _rsp.421018027 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3917650673 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 9989619167 ps |
| CPU time | 91.54 seconds |
| Started | Jan 03 12:39:27 PM PST 24 |
| Finished | Jan 03 12:42:15 PM PST 24 |
| Peak memory | 204372 kb |
| Host | smart-8e7480f1-191e-411f-951c-09692bdce28b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3917650673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.3917650673 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1142599197 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 5344564354 ps |
| CPU time | 154.05 seconds |
| Started | Jan 03 12:39:03 PM PST 24 |
| Finished | Jan 03 12:42:57 PM PST 24 |
| Peak memory | 207328 kb |
| Host | smart-07162d77-4051-46ca-aa6d-feade02cb38b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1142599197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.1142599197 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1885872423 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 29848346 ps |
| CPU time | 5.11 seconds |
| Started | Jan 03 12:37:52 PM PST 24 |
| Finished | Jan 03 12:39:19 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-ed4b4959-9796-4bf0-b51f-c928c766625a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1885872423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1885872423 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.4275698587 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 14636750027 ps |
| CPU time | 96.34 seconds |
| Started | Jan 03 12:37:56 PM PST 24 |
| Finished | Jan 03 12:40:48 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-73343922-8974-4edc-be7d-4282227bf962 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4275698587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.4275698587 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.665468658 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 303129239 ps |
| CPU time | 2.86 seconds |
| Started | Jan 03 12:38:08 PM PST 24 |
| Finished | Jan 03 12:39:27 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-f59625fb-90bc-4c01-aec9-774e6752c8ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=665468658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.665468658 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.3793326528 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1846650451 ps |
| CPU time | 9.67 seconds |
| Started | Jan 03 12:37:52 PM PST 24 |
| Finished | Jan 03 12:39:17 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-4f6f2af3-51d5-4a84-a4a7-907a2f7e25f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3793326528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3793326528 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.3454854161 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 300108303 ps |
| CPU time | 5.34 seconds |
| Started | Jan 03 12:38:17 PM PST 24 |
| Finished | Jan 03 12:39:36 PM PST 24 |
| Peak memory | 201328 kb |
| Host | smart-1332dfa5-fe15-4be3-a7f5-f339d758bf0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3454854161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3454854161 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.777699456 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 57465245999 ps |
| CPU time | 105.37 seconds |
| Started | Jan 03 12:38:08 PM PST 24 |
| Finished | Jan 03 12:41:10 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-65ee5c24-c68c-406e-9921-244893ded26e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=777699456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.777699456 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2060098533 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 20748878039 ps |
| CPU time | 139.91 seconds |
| Started | Jan 03 12:40:04 PM PST 24 |
| Finished | Jan 03 12:43:47 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-1c43fa60-61ea-4c97-b271-48ab060388f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2060098533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2060098533 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1137636995 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 46376285 ps |
| CPU time | 5.64 seconds |
| Started | Jan 03 12:38:52 PM PST 24 |
| Finished | Jan 03 12:40:09 PM PST 24 |
| Peak memory | 200900 kb |
| Host | smart-dc71e507-644e-4b27-aff7-4ba99036e903 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137636995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1137636995 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.1556292475 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 252928842 ps |
| CPU time | 3.74 seconds |
| Started | Jan 03 12:38:12 PM PST 24 |
| Finished | Jan 03 12:39:29 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-ffd8aaf1-649c-4b22-83ff-572416d88970 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1556292475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1556292475 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.4052476308 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2867671335 ps |
| CPU time | 9.37 seconds |
| Started | Jan 03 12:38:06 PM PST 24 |
| Finished | Jan 03 12:39:34 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-4d7a1cf6-8b78-4689-a644-096654e2978e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052476308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.4052476308 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1780973008 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 10099555 ps |
| CPU time | 1.15 seconds |
| Started | Jan 03 12:38:09 PM PST 24 |
| Finished | Jan 03 12:39:23 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-1172438c-a273-4ea3-8ec3-f672583b7124 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780973008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1780973008 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.4284195304 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 11490412079 ps |
| CPU time | 32.7 seconds |
| Started | Jan 03 12:38:03 PM PST 24 |
| Finished | Jan 03 12:39:59 PM PST 24 |
| Peak memory | 202564 kb |
| Host | smart-1f68f944-f0cf-41b3-b0c2-5798fe9c0bc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4284195304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.4284195304 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.4063243027 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 28072094283 ps |
| CPU time | 88.86 seconds |
| Started | Jan 03 12:38:25 PM PST 24 |
| Finished | Jan 03 12:41:20 PM PST 24 |
| Peak memory | 204384 kb |
| Host | smart-0ddfde4e-5aed-4baf-89e6-f8e1940347af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4063243027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.4063243027 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.650963721 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9256431139 ps |
| CPU time | 148.17 seconds |
| Started | Jan 03 12:38:29 PM PST 24 |
| Finished | Jan 03 12:42:21 PM PST 24 |
| Peak memory | 206676 kb |
| Host | smart-4f8b400b-5e70-4409-ad6f-2eee542d4fc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=650963721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_ reset.650963721 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2046986200 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 352656170 ps |
| CPU time | 38.36 seconds |
| Started | Jan 03 12:37:54 PM PST 24 |
| Finished | Jan 03 12:39:55 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-900b30ff-f258-4c5e-b639-c0530569fb7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2046986200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.2046986200 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.593996044 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 101936502 ps |
| CPU time | 1.24 seconds |
| Started | Jan 03 12:38:05 PM PST 24 |
| Finished | Jan 03 12:39:23 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-166c05d3-0e31-4a2a-a8b2-68bf8a9877d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=593996044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.593996044 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2587817586 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 620945564 ps |
| CPU time | 8.79 seconds |
| Started | Jan 03 12:38:30 PM PST 24 |
| Finished | Jan 03 12:39:52 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-8b1c3b64-5ab2-4f30-b129-37b50573453e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2587817586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2587817586 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3049967989 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10145068801 ps |
| CPU time | 60.93 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:40:49 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-e05c9a48-027f-4b9f-b391-4a6c768da5b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3049967989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.3049967989 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1587904606 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 36263792 ps |
| CPU time | 3.22 seconds |
| Started | Jan 03 12:38:20 PM PST 24 |
| Finished | Jan 03 12:39:49 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-409dc486-ae7d-411c-a370-ff53a9d7de37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1587904606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1587904606 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.3502152777 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1604640620 ps |
| CPU time | 13.85 seconds |
| Started | Jan 03 12:38:12 PM PST 24 |
| Finished | Jan 03 12:39:43 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-0d64df86-cefa-4a03-9c4a-897452c098d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3502152777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3502152777 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3244308518 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 11283548675 ps |
| CPU time | 44.5 seconds |
| Started | Jan 03 12:38:07 PM PST 24 |
| Finished | Jan 03 12:40:09 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-d3506a8f-2268-4e9d-aa18-721e0b474a37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244308518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3244308518 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2339112309 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 52397847643 ps |
| CPU time | 184.54 seconds |
| Started | Jan 03 12:37:57 PM PST 24 |
| Finished | Jan 03 12:42:27 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-087b657f-b599-4abe-b90f-2f9f78b68b47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2339112309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2339112309 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.510123875 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 54919181 ps |
| CPU time | 5.84 seconds |
| Started | Jan 03 12:37:52 PM PST 24 |
| Finished | Jan 03 12:39:13 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-19f222af-8e47-4cf1-bf0f-41c24679fef3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510123875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.510123875 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.804328408 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 30205261 ps |
| CPU time | 1.14 seconds |
| Started | Jan 03 12:38:26 PM PST 24 |
| Finished | Jan 03 12:39:42 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-c2cac6f4-bb01-4eaa-9ce2-1be7720b166d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=804328408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.804328408 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.1976330339 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 152540294 ps |
| CPU time | 1.51 seconds |
| Started | Jan 03 12:37:59 PM PST 24 |
| Finished | Jan 03 12:39:29 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-4bea1817-2060-4947-9aa7-f9825b6446e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1976330339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1976330339 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1967625371 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3960725709 ps |
| CPU time | 10.28 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:42 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-412c0fdf-30a1-4279-be2e-1debe567db6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967625371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1967625371 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2054505710 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 819478735 ps |
| CPU time | 5.84 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:54 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-f53f0f85-0040-4fc1-85f4-5a4b8796bbbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2054505710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2054505710 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1442703537 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 14354709 ps |
| CPU time | 1.18 seconds |
| Started | Jan 03 12:37:57 PM PST 24 |
| Finished | Jan 03 12:39:13 PM PST 24 |
| Peak memory | 201292 kb |
| Host | smart-55af3c0a-c559-475a-9770-bb9d45af4b27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442703537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1442703537 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.3074561087 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 4205587226 ps |
| CPU time | 70.97 seconds |
| Started | Jan 03 12:38:06 PM PST 24 |
| Finished | Jan 03 12:40:32 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-d3130a43-8213-45f9-9dca-8f4efa64731a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3074561087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3074561087 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1859180151 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 143453415 ps |
| CPU time | 6.61 seconds |
| Started | Jan 03 12:38:10 PM PST 24 |
| Finished | Jan 03 12:39:34 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-ee047987-750d-4c48-832a-868124be362b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1859180151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1859180151 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.712277453 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 514684656 ps |
| CPU time | 66.17 seconds |
| Started | Jan 03 12:38:27 PM PST 24 |
| Finished | Jan 03 12:40:50 PM PST 24 |
| Peak memory | 203968 kb |
| Host | smart-d70e0f2c-a2cd-457e-a928-b34cd9c83a9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=712277453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_ reset.712277453 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.826646513 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1104290510 ps |
| CPU time | 100.77 seconds |
| Started | Jan 03 12:38:26 PM PST 24 |
| Finished | Jan 03 12:41:25 PM PST 24 |
| Peak memory | 204100 kb |
| Host | smart-3cb715ef-0261-4724-8e68-a34714217a67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=826646513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese t_error.826646513 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2484769984 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 54367008 ps |
| CPU time | 5.22 seconds |
| Started | Jan 03 12:38:11 PM PST 24 |
| Finished | Jan 03 12:39:38 PM PST 24 |
| Peak memory | 201328 kb |
| Host | smart-92415c8d-22ca-4584-8145-eb4cc138599f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2484769984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2484769984 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3739262259 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 943604464 ps |
| CPU time | 17.2 seconds |
| Started | Jan 03 12:38:32 PM PST 24 |
| Finished | Jan 03 12:40:14 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-d66b64f4-0405-4b8a-87c7-183a8890bd02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3739262259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3739262259 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1709393006 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 85531139987 ps |
| CPU time | 355.24 seconds |
| Started | Jan 03 12:38:45 PM PST 24 |
| Finished | Jan 03 12:45:58 PM PST 24 |
| Peak memory | 202948 kb |
| Host | smart-3335f914-9d49-4cf1-a3bb-440417ad0750 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1709393006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.1709393006 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.545577636 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 33416262 ps |
| CPU time | 3.2 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:40:06 PM PST 24 |
| Peak memory | 201300 kb |
| Host | smart-1c0ca9a9-e73b-4d9c-b84f-18c825c5b04e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=545577636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.545577636 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.1532980376 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 378709135 ps |
| CPU time | 6.3 seconds |
| Started | Jan 03 12:38:40 PM PST 24 |
| Finished | Jan 03 12:39:57 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-9659cccf-595e-4b14-8553-15e46aea2dce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1532980376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1532980376 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.890864049 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 133882061 ps |
| CPU time | 8.06 seconds |
| Started | Jan 03 12:38:14 PM PST 24 |
| Finished | Jan 03 12:39:50 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-760d5483-8bd5-45b4-84a6-f81cca01d239 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=890864049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.890864049 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.98478076 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 70697535412 ps |
| CPU time | 55.27 seconds |
| Started | Jan 03 12:38:19 PM PST 24 |
| Finished | Jan 03 12:40:41 PM PST 24 |
| Peak memory | 201300 kb |
| Host | smart-51cdd51d-c04c-4c96-95fb-868ef165cbd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=98478076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.98478076 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1770697528 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 16458588511 ps |
| CPU time | 78.26 seconds |
| Started | Jan 03 12:38:06 PM PST 24 |
| Finished | Jan 03 12:40:42 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-b4436674-30ac-4099-9ea5-510df92d31d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1770697528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1770697528 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.1425063844 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 80293742 ps |
| CPU time | 6.7 seconds |
| Started | Jan 03 12:38:28 PM PST 24 |
| Finished | Jan 03 12:40:18 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-cc610c00-1bad-493b-9739-025a665433d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425063844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1425063844 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.920995973 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 477079279 ps |
| CPU time | 4.74 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:40:12 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-ea00afbe-a93d-497f-b66f-d31969b1ddef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=920995973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.920995973 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.3914595262 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 42675421 ps |
| CPU time | 1.38 seconds |
| Started | Jan 03 12:38:14 PM PST 24 |
| Finished | Jan 03 12:39:29 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-4255b28b-aa8a-4141-bf4e-47b168557106 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3914595262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3914595262 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.518644915 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 2103734137 ps |
| CPU time | 5.95 seconds |
| Started | Jan 03 12:38:17 PM PST 24 |
| Finished | Jan 03 12:39:39 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-fdf0ecc3-de11-4a16-a0a4-571540865b40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=518644915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.518644915 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.2797343850 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 580814843 ps |
| CPU time | 5.04 seconds |
| Started | Jan 03 12:38:16 PM PST 24 |
| Finished | Jan 03 12:39:35 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-1555dcde-e7fa-4ae1-a369-0fe3618e41eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2797343850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2797343850 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2382413446 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 23214543 ps |
| CPU time | 1 seconds |
| Started | Jan 03 12:39:00 PM PST 24 |
| Finished | Jan 03 12:40:14 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-281eb26e-2383-4723-b893-4392131a2de8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382413446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2382413446 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.2221832252 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 4638605024 ps |
| CPU time | 66.54 seconds |
| Started | Jan 03 12:38:46 PM PST 24 |
| Finished | Jan 03 12:41:03 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-f18db1c4-6dd7-4980-8adc-02bb397361d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2221832252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2221832252 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1117203073 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 821915541 ps |
| CPU time | 3.12 seconds |
| Started | Jan 03 12:38:32 PM PST 24 |
| Finished | Jan 03 12:40:00 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-4bf0eb70-6d7c-47de-a209-04bce9d2bc06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1117203073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1117203073 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.987134275 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 118138269 ps |
| CPU time | 13.64 seconds |
| Started | Jan 03 12:38:26 PM PST 24 |
| Finished | Jan 03 12:39:51 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-c101e315-f324-463f-9267-d023a738fd44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=987134275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand _reset.987134275 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3717129045 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1390897752 ps |
| CPU time | 133.92 seconds |
| Started | Jan 03 12:38:29 PM PST 24 |
| Finished | Jan 03 12:41:58 PM PST 24 |
| Peak memory | 206204 kb |
| Host | smart-bd45b1e0-0697-4ca7-a89c-9781f44913ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3717129045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.3717129045 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.3568240176 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 99736928 ps |
| CPU time | 1.34 seconds |
| Started | Jan 03 12:38:22 PM PST 24 |
| Finished | Jan 03 12:39:49 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-803b2d20-6413-4f26-810c-1d9188498695 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3568240176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3568240176 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3753463266 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 698120541 ps |
| CPU time | 13.05 seconds |
| Started | Jan 03 12:38:21 PM PST 24 |
| Finished | Jan 03 12:40:00 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-05a34e4a-6927-4b9c-b7d4-b3e5e601d267 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3753463266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3753463266 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1168700135 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 30644150524 ps |
| CPU time | 71.97 seconds |
| Started | Jan 03 12:38:45 PM PST 24 |
| Finished | Jan 03 12:41:14 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-edffbe74-36e2-4aab-8edc-f6eae069f7a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1168700135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.1168700135 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2885380115 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 253133207 ps |
| CPU time | 3.26 seconds |
| Started | Jan 03 12:38:42 PM PST 24 |
| Finished | Jan 03 12:40:04 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-72b597f6-27f8-4225-89a9-c256f2f20092 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2885380115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2885380115 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.2868724793 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1748952329 ps |
| CPU time | 8.39 seconds |
| Started | Jan 03 12:38:52 PM PST 24 |
| Finished | Jan 03 12:40:41 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-a39db429-9bb3-47a4-899c-d8f0d875a8ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2868724793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2868724793 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.2386301810 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 97848272 ps |
| CPU time | 2.87 seconds |
| Started | Jan 03 12:38:34 PM PST 24 |
| Finished | Jan 03 12:39:50 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-bc8ca1e8-dad8-4780-b4fa-bc9d3942e916 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2386301810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2386301810 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1294963802 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 97519821913 ps |
| CPU time | 71.67 seconds |
| Started | Jan 03 12:39:01 PM PST 24 |
| Finished | Jan 03 12:41:49 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-b2a0e738-b84e-4d48-9c31-e1aa98ccd2a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294963802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1294963802 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1949971594 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 27672250355 ps |
| CPU time | 90.97 seconds |
| Started | Jan 03 12:38:35 PM PST 24 |
| Finished | Jan 03 12:41:16 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-527c364e-4bfb-407b-a585-a1a7194fda4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1949971594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1949971594 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1846129520 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 61114855 ps |
| CPU time | 3.52 seconds |
| Started | Jan 03 12:38:23 PM PST 24 |
| Finished | Jan 03 12:39:45 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-1ddfec69-0464-4b47-a4f8-7b9b2e9f9e16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846129520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1846129520 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.2512485753 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 59482037 ps |
| CPU time | 4.79 seconds |
| Started | Jan 03 12:38:54 PM PST 24 |
| Finished | Jan 03 12:40:21 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-499c3fa3-9d91-4225-9f56-3e2f499e3dbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2512485753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2512485753 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.2107133 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 128282250 ps |
| CPU time | 1.58 seconds |
| Started | Jan 03 12:38:50 PM PST 24 |
| Finished | Jan 03 12:40:08 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-8db42088-cc15-4d05-8450-6226eb5d5fa8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2107133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2107133 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3614366412 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2698796842 ps |
| CPU time | 8.55 seconds |
| Started | Jan 03 12:38:19 PM PST 24 |
| Finished | Jan 03 12:39:41 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-26775b87-1713-43d9-9722-5e34c13f7e89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614366412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3614366412 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.852840170 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1510356808 ps |
| CPU time | 9.06 seconds |
| Started | Jan 03 12:38:27 PM PST 24 |
| Finished | Jan 03 12:39:53 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-5062da70-b374-4791-9c94-962436e7762f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=852840170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.852840170 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2243674605 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 8924917 ps |
| CPU time | 1.17 seconds |
| Started | Jan 03 12:38:48 PM PST 24 |
| Finished | Jan 03 12:40:16 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-def7d315-dd19-416e-92e5-f2dc6eb47300 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243674605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2243674605 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.945190202 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 159515914 ps |
| CPU time | 15.14 seconds |
| Started | Jan 03 12:38:52 PM PST 24 |
| Finished | Jan 03 12:40:14 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-f5dd6fe9-04e3-49cc-a5b6-ff88b86fa3bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=945190202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.945190202 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.903476391 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 402028416 ps |
| CPU time | 9.01 seconds |
| Started | Jan 03 12:38:59 PM PST 24 |
| Finished | Jan 03 12:40:34 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-43ad9388-fec1-4153-a11e-9226618dca9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=903476391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.903476391 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1492333619 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 5582028186 ps |
| CPU time | 155.58 seconds |
| Started | Jan 03 12:38:39 PM PST 24 |
| Finished | Jan 03 12:42:24 PM PST 24 |
| Peak memory | 206536 kb |
| Host | smart-ca014b28-3c9c-44c9-b00d-b7a9f8f90770 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1492333619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1492333619 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1075202442 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 13398573 ps |
| CPU time | 1.27 seconds |
| Started | Jan 03 12:38:23 PM PST 24 |
| Finished | Jan 03 12:39:51 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-d18ea8ac-3976-4492-9414-9f4844354751 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1075202442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1075202442 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2040186205 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 28184333 ps |
| CPU time | 5.81 seconds |
| Started | Jan 03 12:39:36 PM PST 24 |
| Finished | Jan 03 12:41:02 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-89f4a7a9-1f31-42bf-959d-e30455473b86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2040186205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2040186205 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.4070412528 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 23774884 ps |
| CPU time | 2.51 seconds |
| Started | Jan 03 12:38:41 PM PST 24 |
| Finished | Jan 03 12:40:20 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-d29c8e48-5e91-48cc-9b02-ab206b933444 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4070412528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.4070412528 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.841180411 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 913442313 ps |
| CPU time | 13.23 seconds |
| Started | Jan 03 12:39:34 PM PST 24 |
| Finished | Jan 03 12:41:18 PM PST 24 |
| Peak memory | 201224 kb |
| Host | smart-33095d89-e368-4955-9e78-a61b7d59498f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=841180411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.841180411 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.1829778292 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 207515139 ps |
| CPU time | 7.71 seconds |
| Started | Jan 03 12:38:50 PM PST 24 |
| Finished | Jan 03 12:40:14 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-9ce7c6e7-da57-426b-ab10-3e39913daee2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1829778292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1829778292 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1056845865 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 17255201680 ps |
| CPU time | 61.13 seconds |
| Started | Jan 03 12:38:47 PM PST 24 |
| Finished | Jan 03 12:41:02 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-4f3cee81-0270-4ea2-8783-ea02f0590120 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056845865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1056845865 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2765973568 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 36906918683 ps |
| CPU time | 133.78 seconds |
| Started | Jan 03 12:38:51 PM PST 24 |
| Finished | Jan 03 12:42:38 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-725be3c6-c740-455d-b628-7049206bf9e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2765973568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2765973568 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.3787693050 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 21379575 ps |
| CPU time | 2.83 seconds |
| Started | Jan 03 12:38:53 PM PST 24 |
| Finished | Jan 03 12:40:13 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-97452a99-3a14-4c26-b92c-5de509c52d5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787693050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3787693050 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.442834001 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1082884902 ps |
| CPU time | 4.7 seconds |
| Started | Jan 03 12:38:50 PM PST 24 |
| Finished | Jan 03 12:40:11 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-2f98cfbe-2e84-4132-8f9b-9a231cff19a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=442834001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.442834001 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.209654334 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 563669033 ps |
| CPU time | 1.77 seconds |
| Started | Jan 03 12:38:25 PM PST 24 |
| Finished | Jan 03 12:39:43 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-85cfbfaf-e200-4b1d-b301-eed0d1572b04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=209654334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.209654334 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2450128144 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 6838680534 ps |
| CPU time | 9.6 seconds |
| Started | Jan 03 12:38:56 PM PST 24 |
| Finished | Jan 03 12:40:13 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-2df4162f-e10a-4a5d-8d9a-f9f256157b73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450128144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2450128144 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.397770141 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 10301773 ps |
| CPU time | 1.01 seconds |
| Started | Jan 03 12:38:38 PM PST 24 |
| Finished | Jan 03 12:40:10 PM PST 24 |
| Peak memory | 201356 kb |
| Host | smart-6919bae5-fb14-44ef-a2fe-d0b3a3453f9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397770141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.397770141 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2311050691 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 390890735 ps |
| CPU time | 32.68 seconds |
| Started | Jan 03 12:38:46 PM PST 24 |
| Finished | Jan 03 12:40:36 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-271a996d-e719-487c-bf88-926103b3f85e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2311050691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2311050691 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2853941707 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2219061720 ps |
| CPU time | 31.53 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:40:34 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-74cde036-22f9-4eeb-9308-fd76ee920a47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2853941707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2853941707 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2847248290 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1538601680 ps |
| CPU time | 60.61 seconds |
| Started | Jan 03 12:38:33 PM PST 24 |
| Finished | Jan 03 12:40:43 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-5ea737da-8542-44a7-bf86-b403b97b48f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2847248290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.2847248290 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2422170806 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 157472304 ps |
| CPU time | 16.24 seconds |
| Started | Jan 03 12:39:00 PM PST 24 |
| Finished | Jan 03 12:40:29 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-2ad58abe-2f5f-4e66-a018-91fd61f54ebc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2422170806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.2422170806 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1895534497 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 60632640 ps |
| CPU time | 7.6 seconds |
| Started | Jan 03 12:38:51 PM PST 24 |
| Finished | Jan 03 12:40:13 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-147ff7d4-ae2c-47c8-b1be-86d50aba423a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1895534497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1895534497 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2282719514 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 129908269 ps |
| CPU time | 2.82 seconds |
| Started | Jan 03 12:38:50 PM PST 24 |
| Finished | Jan 03 12:39:58 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-af4f669a-c66b-4a39-a3ce-6746b86220de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2282719514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2282719514 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3348808022 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 75741236346 ps |
| CPU time | 191.44 seconds |
| Started | Jan 03 12:38:48 PM PST 24 |
| Finished | Jan 03 12:43:22 PM PST 24 |
| Peak memory | 202568 kb |
| Host | smart-b9ab1591-1b98-4a3b-ade4-5192ef991c5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3348808022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.3348808022 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2377698671 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 505224146 ps |
| CPU time | 7.36 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:40:10 PM PST 24 |
| Peak memory | 201276 kb |
| Host | smart-6691ca93-33ab-4b05-90f9-3854114636a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2377698671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2377698671 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.1713835120 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 141180118 ps |
| CPU time | 6.59 seconds |
| Started | Jan 03 12:38:51 PM PST 24 |
| Finished | Jan 03 12:40:23 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-5331ae89-75c8-499d-8019-1ee8ebcc891a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1713835120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1713835120 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3688801860 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 118262705365 ps |
| CPU time | 114.73 seconds |
| Started | Jan 03 12:38:54 PM PST 24 |
| Finished | Jan 03 12:42:33 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-6ce3f83e-30f4-46f5-a090-ecbe97737db3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688801860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3688801860 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2562939735 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 102079348705 ps |
| CPU time | 176.31 seconds |
| Started | Jan 03 12:38:42 PM PST 24 |
| Finished | Jan 03 12:42:51 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-52248102-2a5b-4fb2-ae81-5d60e40a8a44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2562939735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2562939735 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1107149677 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 128614327 ps |
| CPU time | 8.89 seconds |
| Started | Jan 03 12:38:41 PM PST 24 |
| Finished | Jan 03 12:40:20 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-12dec7cd-f548-4a09-bf4d-821a791aa5df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107149677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1107149677 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.2053410671 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 162519812 ps |
| CPU time | 3.92 seconds |
| Started | Jan 03 12:38:59 PM PST 24 |
| Finished | Jan 03 12:40:14 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-5fe2d04a-0255-4bcc-b9ad-37b2994ec9c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2053410671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2053410671 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.2016711822 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 39313225 ps |
| CPU time | 1.31 seconds |
| Started | Jan 03 12:38:50 PM PST 24 |
| Finished | Jan 03 12:39:57 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-0863ef91-5a77-4de9-bbd7-aa689ce38486 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2016711822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2016711822 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1016591395 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 6529006945 ps |
| CPU time | 7.39 seconds |
| Started | Jan 03 12:38:37 PM PST 24 |
| Finished | Jan 03 12:39:57 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-db3fe4f7-cc61-4571-af51-4e873fce0c31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016591395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1016591395 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.202608403 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1165072831 ps |
| CPU time | 7.63 seconds |
| Started | Jan 03 12:38:59 PM PST 24 |
| Finished | Jan 03 12:40:30 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-278ac6eb-1a09-4a4f-a573-96a448ba25db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=202608403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.202608403 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.3004142350 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 9282428 ps |
| CPU time | 1.08 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:40:08 PM PST 24 |
| Peak memory | 201304 kb |
| Host | smart-b9b3b183-c723-4559-aca2-12e615bd2639 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004142350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3004142350 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.1013553159 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 634544582 ps |
| CPU time | 10.38 seconds |
| Started | Jan 03 12:39:04 PM PST 24 |
| Finished | Jan 03 12:40:51 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-85829d7a-93bf-4d65-92ad-0ffbcd4e21bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1013553159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1013553159 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1898617259 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 824529719 ps |
| CPU time | 30.32 seconds |
| Started | Jan 03 12:38:43 PM PST 24 |
| Finished | Jan 03 12:40:30 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-78d41fad-8297-47d6-b8a8-450a61a3d39b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1898617259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1898617259 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.4283599434 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 581062637 ps |
| CPU time | 45.99 seconds |
| Started | Jan 03 12:38:53 PM PST 24 |
| Finished | Jan 03 12:41:03 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-f7299d57-34f6-4669-8486-f403159c6b62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4283599434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.4283599434 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3566301105 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1854343052 ps |
| CPU time | 8.88 seconds |
| Started | Jan 03 12:39:00 PM PST 24 |
| Finished | Jan 03 12:40:21 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-f3acab47-4fb7-4c5a-b20e-5f858d6da1cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3566301105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3566301105 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.198688939 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1145539438 ps |
| CPU time | 16.29 seconds |
| Started | Jan 03 12:39:28 PM PST 24 |
| Finished | Jan 03 12:41:32 PM PST 24 |
| Peak memory | 201236 kb |
| Host | smart-0d5c372f-88ed-4e18-af11-88956eeaabfd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=198688939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.198688939 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1208604523 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 30292262048 ps |
| CPU time | 157.41 seconds |
| Started | Jan 03 12:38:31 PM PST 24 |
| Finished | Jan 03 12:42:27 PM PST 24 |
| Peak memory | 202576 kb |
| Host | smart-d6a965b6-5f2d-48b1-a0fb-f91b7a8f80e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1208604523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1208604523 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.275566445 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 68392855 ps |
| CPU time | 2.21 seconds |
| Started | Jan 03 12:38:34 PM PST 24 |
| Finished | Jan 03 12:39:52 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-5a5f7344-2964-4657-9cc7-0f5ea902671f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=275566445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.275566445 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.2613342697 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 81802283 ps |
| CPU time | 5.61 seconds |
| Started | Jan 03 12:38:52 PM PST 24 |
| Finished | Jan 03 12:40:22 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-c0385f90-2df5-45a9-81b9-a0933847c7c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2613342697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2613342697 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.3948575106 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 20742896 ps |
| CPU time | 2.29 seconds |
| Started | Jan 03 12:38:42 PM PST 24 |
| Finished | Jan 03 12:39:53 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-ef450059-73f9-49b6-8a55-86dda3c2bd8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3948575106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3948575106 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2046745735 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 217891971134 ps |
| CPU time | 180.83 seconds |
| Started | Jan 03 12:38:40 PM PST 24 |
| Finished | Jan 03 12:43:04 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-741e2d4a-5d2f-43e6-b2b4-f1e885421985 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046745735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2046745735 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.697544024 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 25091915287 ps |
| CPU time | 84.5 seconds |
| Started | Jan 03 12:38:28 PM PST 24 |
| Finished | Jan 03 12:41:04 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-388feeae-b2c6-4634-88d1-4d5e7f5342b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=697544024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.697544024 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.1963356573 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 75434315 ps |
| CPU time | 4.89 seconds |
| Started | Jan 03 12:38:24 PM PST 24 |
| Finished | Jan 03 12:40:22 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-c5dc878a-3a30-4238-9d9e-479677e5be2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963356573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1963356573 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.1574015752 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 207265528 ps |
| CPU time | 5.46 seconds |
| Started | Jan 03 12:38:57 PM PST 24 |
| Finished | Jan 03 12:40:24 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-4a61123a-31e2-425b-8077-ec6f6e7e8a06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1574015752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1574015752 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.2301830257 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 84436514 ps |
| CPU time | 1.39 seconds |
| Started | Jan 03 12:39:04 PM PST 24 |
| Finished | Jan 03 12:40:38 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-0c722bf6-2d93-461a-94a8-ab6a7647ae40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2301830257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2301830257 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2823075112 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 13753095881 ps |
| CPU time | 8.37 seconds |
| Started | Jan 03 12:38:45 PM PST 24 |
| Finished | Jan 03 12:40:37 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-067b742f-d6cc-4371-82b6-e17e718e9628 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823075112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2823075112 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3785148150 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 1177678418 ps |
| CPU time | 7.55 seconds |
| Started | Jan 03 12:38:47 PM PST 24 |
| Finished | Jan 03 12:40:05 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-7ce1e75a-59ba-4ea5-96bd-e02af53624ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3785148150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3785148150 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1607141337 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 15940449 ps |
| CPU time | 1.05 seconds |
| Started | Jan 03 12:38:22 PM PST 24 |
| Finished | Jan 03 12:39:36 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-52afe795-3696-4e39-adf9-27041c69f02b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607141337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1607141337 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3367205579 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 299150855 ps |
| CPU time | 4.35 seconds |
| Started | Jan 03 12:38:34 PM PST 24 |
| Finished | Jan 03 12:39:51 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-fe89f815-e9e6-4772-9fa9-821e20eb93ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3367205579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3367205579 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.534086349 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 982161042 ps |
| CPU time | 18.76 seconds |
| Started | Jan 03 12:38:31 PM PST 24 |
| Finished | Jan 03 12:40:24 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-ac62c1b0-cbba-4ea2-b8b8-fb9b22c9f552 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=534086349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.534086349 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.714651081 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 306638278 ps |
| CPU time | 38.93 seconds |
| Started | Jan 03 12:38:48 PM PST 24 |
| Finished | Jan 03 12:41:00 PM PST 24 |
| Peak memory | 203544 kb |
| Host | smart-0f300c0b-d739-4c0e-9fe5-eef051c22e01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=714651081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand _reset.714651081 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.711471430 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 8699876914 ps |
| CPU time | 107.57 seconds |
| Started | Jan 03 12:38:51 PM PST 24 |
| Finished | Jan 03 12:41:57 PM PST 24 |
| Peak memory | 204976 kb |
| Host | smart-7aab4efd-c3d9-42f0-968d-5b880ecbb9b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=711471430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res et_error.711471430 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1508707355 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 68465318 ps |
| CPU time | 6.18 seconds |
| Started | Jan 03 12:39:05 PM PST 24 |
| Finished | Jan 03 12:40:22 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-c250b907-5478-41dd-86f0-2fe28d586b78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1508707355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1508707355 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2916882453 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 397106690 ps |
| CPU time | 6.34 seconds |
| Started | Jan 03 12:38:47 PM PST 24 |
| Finished | Jan 03 12:40:13 PM PST 24 |
| Peak memory | 201252 kb |
| Host | smart-3497c494-ff6e-4f95-a2d6-350cabc97327 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2916882453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2916882453 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2827721804 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 24461891 ps |
| CPU time | 2.81 seconds |
| Started | Jan 03 12:38:45 PM PST 24 |
| Finished | Jan 03 12:40:24 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-18389080-0e5f-4a31-ad81-6341bf39369d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2827721804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2827721804 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.1072407550 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 14621571 ps |
| CPU time | 1.44 seconds |
| Started | Jan 03 12:38:46 PM PST 24 |
| Finished | Jan 03 12:40:08 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-d3e1733e-8d0f-448d-90f0-6f140b8001b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1072407550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1072407550 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.3284501803 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1919713618 ps |
| CPU time | 6.39 seconds |
| Started | Jan 03 12:38:23 PM PST 24 |
| Finished | Jan 03 12:39:45 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-7a9bd5c1-6ed4-4cda-bf8e-4c2d6612e98f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3284501803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3284501803 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2878302661 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 29231204272 ps |
| CPU time | 127.59 seconds |
| Started | Jan 03 12:38:26 PM PST 24 |
| Finished | Jan 03 12:41:48 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-c90780a5-fb87-4e08-b172-0e48c1170425 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878302661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2878302661 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3425520337 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 22816101299 ps |
| CPU time | 115.63 seconds |
| Started | Jan 03 12:38:40 PM PST 24 |
| Finished | Jan 03 12:41:48 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-81d3a78e-5eb1-48f8-b3f6-121ecb37488a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3425520337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3425520337 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3587715682 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 127170093 ps |
| CPU time | 5.29 seconds |
| Started | Jan 03 12:38:53 PM PST 24 |
| Finished | Jan 03 12:40:08 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-01f10f21-4089-437a-a79b-e30e980c2808 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587715682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3587715682 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.4195987204 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 993497066 ps |
| CPU time | 3.62 seconds |
| Started | Jan 03 12:38:48 PM PST 24 |
| Finished | Jan 03 12:40:12 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-288235c7-88d2-40e7-b3a8-fd04e838b099 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4195987204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.4195987204 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.3323610418 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 10298569 ps |
| CPU time | 1.12 seconds |
| Started | Jan 03 12:38:45 PM PST 24 |
| Finished | Jan 03 12:39:54 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-76f8b0ed-1fba-419c-98d5-ee8e4eaca33c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3323610418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3323610418 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3605966514 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2588728843 ps |
| CPU time | 11.49 seconds |
| Started | Jan 03 12:38:27 PM PST 24 |
| Finished | Jan 03 12:40:12 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-d65ca80d-680a-4e42-9df2-f71e20c3fc15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605966514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3605966514 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.650268476 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1891860952 ps |
| CPU time | 13.25 seconds |
| Started | Jan 03 12:38:45 PM PST 24 |
| Finished | Jan 03 12:40:16 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-2286608b-8eb1-4ad7-b5c9-6429cdcdd438 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=650268476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.650268476 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.417834173 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 20989900 ps |
| CPU time | 1.04 seconds |
| Started | Jan 03 12:39:01 PM PST 24 |
| Finished | Jan 03 12:40:10 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-ab501617-90b8-4580-9ff7-74d5d165ba90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417834173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.417834173 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.3680748508 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 57815465 ps |
| CPU time | 4.73 seconds |
| Started | Jan 03 12:38:42 PM PST 24 |
| Finished | Jan 03 12:40:09 PM PST 24 |
| Peak memory | 201280 kb |
| Host | smart-d1113dae-b024-4c8e-b5d3-5b91a12d6847 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3680748508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3680748508 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1002797889 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1095565290 ps |
| CPU time | 10.87 seconds |
| Started | Jan 03 12:38:54 PM PST 24 |
| Finished | Jan 03 12:40:25 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-c140d3a2-1fce-448f-a1c6-3c5ed9bb12b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1002797889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1002797889 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.4108802178 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 5729268975 ps |
| CPU time | 119.26 seconds |
| Started | Jan 03 12:38:58 PM PST 24 |
| Finished | Jan 03 12:42:28 PM PST 24 |
| Peak memory | 205404 kb |
| Host | smart-c82d8c17-daca-42a5-beeb-1e424c2b3f24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4108802178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.4108802178 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1673442559 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 212158448 ps |
| CPU time | 2.05 seconds |
| Started | Jan 03 12:38:59 PM PST 24 |
| Finished | Jan 03 12:40:32 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-ec1c92e7-91e7-49a4-aea6-9f3fccbd6690 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1673442559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1673442559 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2657089246 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 89051744 ps |
| CPU time | 2.54 seconds |
| Started | Jan 03 12:39:02 PM PST 24 |
| Finished | Jan 03 12:40:15 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-461f3852-5fdb-4ee1-aa8c-810b9223a0ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2657089246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2657089246 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.382712052 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 358648244611 ps |
| CPU time | 325.33 seconds |
| Started | Jan 03 12:38:36 PM PST 24 |
| Finished | Jan 03 12:45:14 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-8afce861-b24c-4c07-aba2-1264edd624d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=382712052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slo w_rsp.382712052 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.2448721283 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 61655029 ps |
| CPU time | 1.61 seconds |
| Started | Jan 03 12:38:49 PM PST 24 |
| Finished | Jan 03 12:39:57 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-fb019ac9-618c-4a1d-9a30-8e81f6460e0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2448721283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.2448721283 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.525251017 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 137519267 ps |
| CPU time | 4.07 seconds |
| Started | Jan 03 12:39:05 PM PST 24 |
| Finished | Jan 03 12:40:30 PM PST 24 |
| Peak memory | 201248 kb |
| Host | smart-c4ad9dc3-5378-4116-be77-a5277011bdfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=525251017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.525251017 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.1710725818 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 726990666 ps |
| CPU time | 10.58 seconds |
| Started | Jan 03 12:38:49 PM PST 24 |
| Finished | Jan 03 12:40:06 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-f1f17015-0244-4f67-8ca2-60689c5c9467 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1710725818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1710725818 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1501680720 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 23550789310 ps |
| CPU time | 58.32 seconds |
| Started | Jan 03 12:38:54 PM PST 24 |
| Finished | Jan 03 12:41:37 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-2b40fdac-1288-47d6-acdb-7ce9ba50eae0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501680720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1501680720 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3329674356 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 5503540162 ps |
| CPU time | 36.94 seconds |
| Started | Jan 03 12:39:14 PM PST 24 |
| Finished | Jan 03 12:41:17 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-f87a2139-e103-44c0-9a97-3c0f9273ed29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3329674356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3329674356 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3066455778 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 54807167 ps |
| CPU time | 3.56 seconds |
| Started | Jan 03 12:38:51 PM PST 24 |
| Finished | Jan 03 12:40:21 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-ba0c4cf9-9b19-4752-8105-524c607abb2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066455778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3066455778 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.1034279529 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3660703851 ps |
| CPU time | 12.13 seconds |
| Started | Jan 03 12:38:49 PM PST 24 |
| Finished | Jan 03 12:40:18 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-41799374-0292-437a-a52d-183f77a560d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1034279529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1034279529 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.1098273339 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 17058833 ps |
| CPU time | 1.01 seconds |
| Started | Jan 03 12:39:01 PM PST 24 |
| Finished | Jan 03 12:40:09 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-8e671108-5cc5-447b-b1e8-607e6ccb042a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1098273339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1098273339 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3203286583 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 4585999377 ps |
| CPU time | 7.22 seconds |
| Started | Jan 03 12:39:03 PM PST 24 |
| Finished | Jan 03 12:40:19 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-7c245e13-89ee-4a71-ae2f-59138109a8c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203286583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3203286583 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1810716982 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 637066449 ps |
| CPU time | 5.5 seconds |
| Started | Jan 03 12:38:39 PM PST 24 |
| Finished | Jan 03 12:39:53 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-348c3880-c570-4564-9ae0-87920ff33f17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1810716982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1810716982 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1143521160 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 10369864 ps |
| CPU time | 1.17 seconds |
| Started | Jan 03 12:38:50 PM PST 24 |
| Finished | Jan 03 12:39:57 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-45b2bddb-1d15-48ff-86a9-0d4b21c9df47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143521160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1143521160 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.1705347036 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 9855433125 ps |
| CPU time | 75.95 seconds |
| Started | Jan 03 12:38:47 PM PST 24 |
| Finished | Jan 03 12:41:13 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-b6f6e4e0-dc05-4ddb-a857-82a6a6594be8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1705347036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1705347036 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1688316788 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 456639491 ps |
| CPU time | 48.13 seconds |
| Started | Jan 03 12:38:41 PM PST 24 |
| Finished | Jan 03 12:40:49 PM PST 24 |
| Peak memory | 201300 kb |
| Host | smart-be0cf08d-ea63-4c86-8c4d-e7e880996641 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1688316788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1688316788 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3817901906 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1725650080 ps |
| CPU time | 124.88 seconds |
| Started | Jan 03 12:39:02 PM PST 24 |
| Finished | Jan 03 12:42:17 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-81c1cfc4-c913-450c-8255-d73e53abdde0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3817901906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.3817901906 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1562750064 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 30641834 ps |
| CPU time | 3.42 seconds |
| Started | Jan 03 12:38:49 PM PST 24 |
| Finished | Jan 03 12:40:10 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-2c352916-3d40-422f-82c5-e1a5c09df09b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1562750064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1562750064 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2236714278 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 701829956 ps |
| CPU time | 12.68 seconds |
| Started | Jan 03 12:38:58 PM PST 24 |
| Finished | Jan 03 12:40:18 PM PST 24 |
| Peak memory | 201328 kb |
| Host | smart-28402b13-97da-4702-ae9f-39f52e6a5b64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2236714278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2236714278 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.143025148 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 75095607 ps |
| CPU time | 1.94 seconds |
| Started | Jan 03 12:39:02 PM PST 24 |
| Finished | Jan 03 12:40:15 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-0b609c4c-367e-41e6-9147-e6f16b9119d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=143025148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.143025148 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.1942445356 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 644117917 ps |
| CPU time | 6.29 seconds |
| Started | Jan 03 12:38:53 PM PST 24 |
| Finished | Jan 03 12:40:22 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-79b2ef2e-af67-4ebe-ba52-89e587de4653 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1942445356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1942445356 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.3227933168 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 44377240 ps |
| CPU time | 1.35 seconds |
| Started | Jan 03 12:38:45 PM PST 24 |
| Finished | Jan 03 12:40:23 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-faad24a3-fff1-4062-8f4a-cdaab94c1c0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3227933168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3227933168 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.313089730 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 97005184225 ps |
| CPU time | 142.1 seconds |
| Started | Jan 03 12:39:01 PM PST 24 |
| Finished | Jan 03 12:42:31 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-9126c287-14c3-43e8-bf64-3e466420a2f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=313089730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.313089730 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3920559168 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 18134403661 ps |
| CPU time | 103.14 seconds |
| Started | Jan 03 12:39:11 PM PST 24 |
| Finished | Jan 03 12:43:02 PM PST 24 |
| Peak memory | 201304 kb |
| Host | smart-c2d159e3-faea-468d-93c6-e00e26ed8e92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3920559168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3920559168 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3309996357 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 69429810 ps |
| CPU time | 8.53 seconds |
| Started | Jan 03 12:39:07 PM PST 24 |
| Finished | Jan 03 12:40:34 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-ccd509d5-9dd1-46e4-9ecc-511e87191f2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309996357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3309996357 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.3867494727 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2008243468 ps |
| CPU time | 12.93 seconds |
| Started | Jan 03 12:38:59 PM PST 24 |
| Finished | Jan 03 12:40:24 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-f68704aa-2019-4246-a036-f84490d16627 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3867494727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3867494727 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.899997276 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2227272991 ps |
| CPU time | 11.05 seconds |
| Started | Jan 03 12:38:58 PM PST 24 |
| Finished | Jan 03 12:40:27 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-3daa816e-46c7-45ea-a61f-0c56a2c7fd2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=899997276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.899997276 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2330560598 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 4058585374 ps |
| CPU time | 7.8 seconds |
| Started | Jan 03 12:38:46 PM PST 24 |
| Finished | Jan 03 12:40:14 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-dc44a5fe-5911-48c7-9f9a-f106791a313c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2330560598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2330560598 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2159808570 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 21960450 ps |
| CPU time | 1.13 seconds |
| Started | Jan 03 12:38:47 PM PST 24 |
| Finished | Jan 03 12:39:58 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-625df214-e7ed-4e48-887c-4b68fcfed035 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159808570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2159808570 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.2174532793 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 6238729759 ps |
| CPU time | 58.67 seconds |
| Started | Jan 03 12:39:20 PM PST 24 |
| Finished | Jan 03 12:41:44 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-a2081805-b880-482a-9552-7941ccec9cd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2174532793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2174532793 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1839056980 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 172163600 ps |
| CPU time | 13.12 seconds |
| Started | Jan 03 12:38:52 PM PST 24 |
| Finished | Jan 03 12:40:16 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-78000b73-2d46-44f3-b267-13cd66165842 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1839056980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1839056980 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1536376740 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 642160933 ps |
| CPU time | 63.03 seconds |
| Started | Jan 03 12:38:48 PM PST 24 |
| Finished | Jan 03 12:41:17 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-0d708af0-7123-4031-8e97-6835668a024b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1536376740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.1536376740 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3882329701 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 137808186 ps |
| CPU time | 18.19 seconds |
| Started | Jan 03 12:38:47 PM PST 24 |
| Finished | Jan 03 12:40:11 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-b52c847d-4f29-4462-a76a-0334f1f8f530 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3882329701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.3882329701 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2831262174 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2037362515 ps |
| CPU time | 8.59 seconds |
| Started | Jan 03 12:38:53 PM PST 24 |
| Finished | Jan 03 12:40:07 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-38886ba7-459c-4999-a550-991e492ee054 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2831262174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2831262174 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2404296507 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 614190666 ps |
| CPU time | 8.41 seconds |
| Started | Jan 03 12:38:42 PM PST 24 |
| Finished | Jan 03 12:39:59 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-6adaac58-d126-427b-8eb2-25c5334bdf5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2404296507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2404296507 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1571201341 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 13204158622 ps |
| CPU time | 47.65 seconds |
| Started | Jan 03 12:39:05 PM PST 24 |
| Finished | Jan 03 12:41:10 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-ce6a21ea-274a-4a1d-afd9-c46b051a0312 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1571201341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.1571201341 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3137471310 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 629684190 ps |
| CPU time | 8.01 seconds |
| Started | Jan 03 12:38:35 PM PST 24 |
| Finished | Jan 03 12:39:53 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-8b8f4f2f-c5f8-40c8-8211-17c915135e86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3137471310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3137471310 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.1374352187 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 197366525 ps |
| CPU time | 4.29 seconds |
| Started | Jan 03 12:39:01 PM PST 24 |
| Finished | Jan 03 12:40:23 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-6dc5ec59-660e-44a4-a6a1-7c85a9ccf219 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1374352187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1374352187 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.3887556671 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2331627303 ps |
| CPU time | 13.98 seconds |
| Started | Jan 03 12:39:28 PM PST 24 |
| Finished | Jan 03 12:41:13 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-2354453f-4a85-4893-8c09-8f651880a8ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3887556671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3887556671 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.704620520 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 43266219951 ps |
| CPU time | 129.93 seconds |
| Started | Jan 03 12:39:00 PM PST 24 |
| Finished | Jan 03 12:42:19 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-0bfd5497-734c-497c-90e3-a0fd9a1575ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=704620520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.704620520 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3009992699 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4469556058 ps |
| CPU time | 32.78 seconds |
| Started | Jan 03 12:38:45 PM PST 24 |
| Finished | Jan 03 12:40:35 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-87cae533-4cfa-4b3d-994c-21d7bdf5f481 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3009992699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3009992699 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3057288297 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 82256443 ps |
| CPU time | 7.38 seconds |
| Started | Jan 03 12:38:50 PM PST 24 |
| Finished | Jan 03 12:40:17 PM PST 24 |
| Peak memory | 201300 kb |
| Host | smart-f28a052b-da0f-4120-9110-0c645172a4a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057288297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3057288297 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1304255966 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1816537355 ps |
| CPU time | 8.26 seconds |
| Started | Jan 03 12:38:57 PM PST 24 |
| Finished | Jan 03 12:40:29 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-a9647bc7-e00d-4c53-8335-a03896389499 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1304255966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1304255966 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.2781623900 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 17608476 ps |
| CPU time | 1.24 seconds |
| Started | Jan 03 12:38:59 PM PST 24 |
| Finished | Jan 03 12:40:25 PM PST 24 |
| Peak memory | 201304 kb |
| Host | smart-3fac0d6b-8d2a-47c6-b086-e49759cc2eba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2781623900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2781623900 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1138635122 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2744184038 ps |
| CPU time | 8.43 seconds |
| Started | Jan 03 12:40:05 PM PST 24 |
| Finished | Jan 03 12:41:37 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-36b4a5fc-ac96-4225-bd87-906ccb992270 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138635122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1138635122 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3946598163 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 988561778 ps |
| CPU time | 5.23 seconds |
| Started | Jan 03 12:39:43 PM PST 24 |
| Finished | Jan 03 12:41:20 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-b1f0da6a-0367-49e3-8e21-5bebe1b50013 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3946598163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3946598163 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.44175017 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 12692333 ps |
| CPU time | 1.26 seconds |
| Started | Jan 03 12:38:50 PM PST 24 |
| Finished | Jan 03 12:40:11 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-21f47cc2-5215-41a3-a7ee-c4984d7fd910 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44175017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.44175017 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.3147432597 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 622722997 ps |
| CPU time | 11.62 seconds |
| Started | Jan 03 12:38:54 PM PST 24 |
| Finished | Jan 03 12:40:50 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-c664e39c-a7c1-4ea4-b3e6-5576d7bc5fbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3147432597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3147432597 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3831973516 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 225369983 ps |
| CPU time | 18.08 seconds |
| Started | Jan 03 12:38:56 PM PST 24 |
| Finished | Jan 03 12:40:21 PM PST 24 |
| Peak memory | 201300 kb |
| Host | smart-ab5d5dfb-2862-4a86-8f31-0cc5c89a9d7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3831973516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3831973516 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2642743907 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 6285649675 ps |
| CPU time | 155.36 seconds |
| Started | Jan 03 12:38:52 PM PST 24 |
| Finished | Jan 03 12:42:38 PM PST 24 |
| Peak memory | 206124 kb |
| Host | smart-0b7be780-b331-43ab-8b4e-26ea1e4a07da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2642743907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.2642743907 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1835417103 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 18300456 ps |
| CPU time | 1.68 seconds |
| Started | Jan 03 12:39:44 PM PST 24 |
| Finished | Jan 03 12:41:12 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-e7052287-57c8-48a2-bba0-c908bccc915c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1835417103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1835417103 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1026580988 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 44417827 ps |
| CPU time | 5.69 seconds |
| Started | Jan 03 12:38:57 PM PST 24 |
| Finished | Jan 03 12:40:27 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-1fe07443-7792-4126-8400-39dcbae593a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1026580988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1026580988 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.21851780 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 34921189286 ps |
| CPU time | 156.57 seconds |
| Started | Jan 03 12:38:53 PM PST 24 |
| Finished | Jan 03 12:42:50 PM PST 24 |
| Peak memory | 201620 kb |
| Host | smart-b29bf11c-9c31-411a-8446-677f5b4120b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=21851780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow _rsp.21851780 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.355609443 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1200566501 ps |
| CPU time | 6.82 seconds |
| Started | Jan 03 12:39:15 PM PST 24 |
| Finished | Jan 03 12:40:50 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-974af7c3-2d94-4f02-b8ed-c801aaf349fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=355609443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.355609443 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.1504320568 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 326906318 ps |
| CPU time | 6.45 seconds |
| Started | Jan 03 12:39:05 PM PST 24 |
| Finished | Jan 03 12:40:39 PM PST 24 |
| Peak memory | 201260 kb |
| Host | smart-fb1ad3f5-1b9e-478a-ae46-1e3e4c731372 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1504320568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1504320568 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.1990257547 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 580337813 ps |
| CPU time | 9.01 seconds |
| Started | Jan 03 12:38:53 PM PST 24 |
| Finished | Jan 03 12:40:26 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-bfc81dcc-c549-42f3-a3e3-aea9d887ad94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1990257547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1990257547 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.4134031413 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 20663470143 ps |
| CPU time | 67.91 seconds |
| Started | Jan 03 12:38:31 PM PST 24 |
| Finished | Jan 03 12:40:54 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-fd85bcd3-e9e9-4c8a-8a14-baff78814425 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134031413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.4134031413 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.4240527707 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 11477043142 ps |
| CPU time | 90.68 seconds |
| Started | Jan 03 12:39:47 PM PST 24 |
| Finished | Jan 03 12:42:49 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-9a2bcecb-d677-48f3-aa0a-6bc849f7b27f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4240527707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.4240527707 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.3213498756 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 15509451 ps |
| CPU time | 2.02 seconds |
| Started | Jan 03 12:38:44 PM PST 24 |
| Finished | Jan 03 12:40:19 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-3faf5994-1760-423e-abb3-7c3133a28928 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213498756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3213498756 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.1720283504 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 12352649 ps |
| CPU time | 1.27 seconds |
| Started | Jan 03 12:39:07 PM PST 24 |
| Finished | Jan 03 12:40:22 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-20e61d5c-8098-441d-9ebe-c262c95a408c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1720283504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1720283504 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.1133048052 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 58977051 ps |
| CPU time | 1.54 seconds |
| Started | Jan 03 12:39:02 PM PST 24 |
| Finished | Jan 03 12:40:35 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-82c7ad6d-9eef-482f-8123-18b8158ec326 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1133048052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1133048052 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1454161728 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4012109203 ps |
| CPU time | 8.79 seconds |
| Started | Jan 03 12:38:44 PM PST 24 |
| Finished | Jan 03 12:40:25 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-b7635dc8-7382-44ba-a240-fc883cf0e175 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454161728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1454161728 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.384279539 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 7110987190 ps |
| CPU time | 60.55 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:42:17 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-c928ea40-4e22-43fd-8d9e-f6db8ca09e32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=384279539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.384279539 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1926560047 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1682845646 ps |
| CPU time | 29.88 seconds |
| Started | Jan 03 12:38:52 PM PST 24 |
| Finished | Jan 03 12:40:33 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-1416f917-1029-4040-b595-58759d12b3e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1926560047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1926560047 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1427616170 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 13391582278 ps |
| CPU time | 191.45 seconds |
| Started | Jan 03 12:39:04 PM PST 24 |
| Finished | Jan 03 12:43:27 PM PST 24 |
| Peak memory | 204124 kb |
| Host | smart-111ecb11-426c-4639-a4a6-9df234761ee2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1427616170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.1427616170 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2470600540 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1736175598 ps |
| CPU time | 115.89 seconds |
| Started | Jan 03 12:39:07 PM PST 24 |
| Finished | Jan 03 12:42:26 PM PST 24 |
| Peak memory | 204132 kb |
| Host | smart-596b287b-d7cb-4d87-a62d-1cbdd42d184d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2470600540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.2470600540 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.171493194 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 59051000 ps |
| CPU time | 1.18 seconds |
| Started | Jan 03 12:38:59 PM PST 24 |
| Finished | Jan 03 12:40:30 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-a14086e3-b680-450b-8ebe-8e68f76223ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=171493194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.171493194 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.250980370 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 977154422 ps |
| CPU time | 18.04 seconds |
| Started | Jan 03 12:38:17 PM PST 24 |
| Finished | Jan 03 12:39:51 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-33190133-8f86-487a-bee6-b4482901b5e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=250980370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.250980370 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.4056904747 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 34932607947 ps |
| CPU time | 146.9 seconds |
| Started | Jan 03 12:38:01 PM PST 24 |
| Finished | Jan 03 12:41:44 PM PST 24 |
| Peak memory | 202136 kb |
| Host | smart-224cb92e-cdfb-44d6-82bd-a053d762c4dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4056904747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.4056904747 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3972341499 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 51551697 ps |
| CPU time | 4.77 seconds |
| Started | Jan 03 12:38:23 PM PST 24 |
| Finished | Jan 03 12:39:52 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-d2cc4c4b-e429-4a27-b693-50f08141e31b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3972341499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3972341499 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.2506365044 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 2770244329 ps |
| CPU time | 8.57 seconds |
| Started | Jan 03 12:38:19 PM PST 24 |
| Finished | Jan 03 12:39:41 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-5cdeffc0-f4e3-4318-9a62-b2ee32f6deec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2506365044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2506365044 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.3277045706 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 29772233 ps |
| CPU time | 3.02 seconds |
| Started | Jan 03 12:38:20 PM PST 24 |
| Finished | Jan 03 12:39:41 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-0164ab6c-4747-4911-97af-9280e289d172 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3277045706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3277045706 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3142392441 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 257878285441 ps |
| CPU time | 191.86 seconds |
| Started | Jan 03 12:38:12 PM PST 24 |
| Finished | Jan 03 12:42:40 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-e2b6eaa7-0c2e-42b0-adfe-8a15fc3dd869 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142392441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3142392441 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.21219385 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 53477792747 ps |
| CPU time | 137.77 seconds |
| Started | Jan 03 12:38:18 PM PST 24 |
| Finished | Jan 03 12:42:26 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-a498397e-2050-49cd-9558-c3ced6f9be3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=21219385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.21219385 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.4181780802 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 248302521 ps |
| CPU time | 4.06 seconds |
| Started | Jan 03 12:38:12 PM PST 24 |
| Finished | Jan 03 12:39:29 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-397af1c7-f193-4e74-9977-ae10f544ae3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181780802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.4181780802 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.2850870506 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1242791916 ps |
| CPU time | 10.07 seconds |
| Started | Jan 03 12:38:19 PM PST 24 |
| Finished | Jan 03 12:40:02 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-90cb03ba-3cac-49c4-8138-a72cd86b5d39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2850870506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2850870506 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.2196965854 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 10199400 ps |
| CPU time | 1.09 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:49 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-43fd2375-88cf-499e-a5e1-2837c13bf7a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2196965854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2196965854 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3332917898 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 5910046698 ps |
| CPU time | 10.93 seconds |
| Started | Jan 03 12:38:03 PM PST 24 |
| Finished | Jan 03 12:39:26 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-49872eb0-37d3-4635-87bb-cd90f676ed66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332917898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3332917898 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.1715814495 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 8700754212 ps |
| CPU time | 8.07 seconds |
| Started | Jan 03 12:38:05 PM PST 24 |
| Finished | Jan 03 12:39:30 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-a3da0941-215b-46c3-abb8-14ab250d0d00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1715814495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1715814495 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2159790263 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 13229381 ps |
| CPU time | 1.34 seconds |
| Started | Jan 03 12:38:23 PM PST 24 |
| Finished | Jan 03 12:39:42 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-cbe1b295-7434-493a-900b-b8a68a4ba185 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159790263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2159790263 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.568387410 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2820605731 ps |
| CPU time | 43.73 seconds |
| Started | Jan 03 12:40:05 PM PST 24 |
| Finished | Jan 03 12:42:13 PM PST 24 |
| Peak memory | 200948 kb |
| Host | smart-753395ed-c365-4ec9-948f-7f17006329aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=568387410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.568387410 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.2054639999 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 413496457 ps |
| CPU time | 22.51 seconds |
| Started | Jan 03 12:39:48 PM PST 24 |
| Finished | Jan 03 12:41:30 PM PST 24 |
| Peak memory | 200564 kb |
| Host | smart-55e9af18-462d-48ca-b6cb-b22ce6ca3503 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2054639999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2054639999 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3969137098 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 22727709850 ps |
| CPU time | 199.29 seconds |
| Started | Jan 03 12:38:08 PM PST 24 |
| Finished | Jan 03 12:42:44 PM PST 24 |
| Peak memory | 204420 kb |
| Host | smart-88fef4fd-17f4-4db0-b2fd-27dd7b405a8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3969137098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3969137098 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3993536997 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3579284275 ps |
| CPU time | 119.09 seconds |
| Started | Jan 03 12:37:49 PM PST 24 |
| Finished | Jan 03 12:40:57 PM PST 24 |
| Peak memory | 205148 kb |
| Host | smart-328cf771-c78a-4aad-8055-b0af7c5bc0cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3993536997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.3993536997 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.110349968 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 20906669 ps |
| CPU time | 2.9 seconds |
| Started | Jan 03 12:38:39 PM PST 24 |
| Finished | Jan 03 12:39:51 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-fce9a036-ff13-4b8e-b146-260d0e59b254 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=110349968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.110349968 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.624425005 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 337804054 ps |
| CPU time | 4.93 seconds |
| Started | Jan 03 12:39:27 PM PST 24 |
| Finished | Jan 03 12:40:56 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-ea9ada30-6368-431d-81ef-f8e0d9c2c372 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=624425005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.624425005 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.622374711 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 34155047 ps |
| CPU time | 3.09 seconds |
| Started | Jan 03 12:39:41 PM PST 24 |
| Finished | Jan 03 12:41:11 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-b180d603-9851-4c8b-8557-bac7e721b198 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=622374711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.622374711 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.2552564935 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 241782155 ps |
| CPU time | 5.02 seconds |
| Started | Jan 03 12:39:00 PM PST 24 |
| Finished | Jan 03 12:40:19 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-8d46229c-3ee0-43ea-9587-8154d2f2374b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2552564935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2552564935 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2963716539 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 236423056599 ps |
| CPU time | 179.73 seconds |
| Started | Jan 03 12:39:07 PM PST 24 |
| Finished | Jan 03 12:43:30 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-6826098d-d15f-4c31-89d6-b93ef2f3a374 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963716539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2963716539 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1804866484 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 15190191496 ps |
| CPU time | 68.23 seconds |
| Started | Jan 03 12:39:13 PM PST 24 |
| Finished | Jan 03 12:41:44 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-2d089baf-546d-4478-978e-f71fb939a93c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1804866484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1804866484 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.50797950 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 80957741 ps |
| CPU time | 7.39 seconds |
| Started | Jan 03 12:39:01 PM PST 24 |
| Finished | Jan 03 12:40:25 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-4a9951be-12ee-4c59-a6c3-af4792825e2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50797950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.50797950 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.2261326187 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 35986610 ps |
| CPU time | 1.53 seconds |
| Started | Jan 03 12:38:58 PM PST 24 |
| Finished | Jan 03 12:40:07 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-c89ac587-89cf-4fd7-b6d5-547da9ab3340 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2261326187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2261326187 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.1257313572 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 65565997 ps |
| CPU time | 1.4 seconds |
| Started | Jan 03 12:38:59 PM PST 24 |
| Finished | Jan 03 12:40:39 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-d5e43e31-75c4-44e6-9e82-9b7f4070b4d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1257313572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1257313572 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2069779658 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 11122036853 ps |
| CPU time | 10.3 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:40:31 PM PST 24 |
| Peak memory | 200688 kb |
| Host | smart-19fffcc1-286f-4ea7-8603-f398c4d784ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069779658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2069779658 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.406294089 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1272046986 ps |
| CPU time | 5.12 seconds |
| Started | Jan 03 12:38:57 PM PST 24 |
| Finished | Jan 03 12:40:30 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-29a47186-8834-48a6-90f7-4fd831c33d32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=406294089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.406294089 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3175859806 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 11893500 ps |
| CPU time | 1.2 seconds |
| Started | Jan 03 12:39:03 PM PST 24 |
| Finished | Jan 03 12:40:19 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-515bb26d-12fa-4a05-a429-4df9218c047e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175859806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3175859806 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1721343697 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 6771576117 ps |
| CPU time | 46.56 seconds |
| Started | Jan 03 12:39:22 PM PST 24 |
| Finished | Jan 03 12:41:26 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-ddb1bce0-ede9-48a3-ac11-7acffbefa48d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1721343697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1721343697 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.529767657 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 4364892049 ps |
| CPU time | 47.48 seconds |
| Started | Jan 03 12:39:00 PM PST 24 |
| Finished | Jan 03 12:41:00 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-d7acc4d8-3553-488f-b0ed-54adfb9fcc10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=529767657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.529767657 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.950979759 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 546866944 ps |
| CPU time | 143.41 seconds |
| Started | Jan 03 12:39:16 PM PST 24 |
| Finished | Jan 03 12:43:11 PM PST 24 |
| Peak memory | 206892 kb |
| Host | smart-a5b6b0aa-c2ed-420d-9cbb-edd583a1a010 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=950979759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand _reset.950979759 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1666036545 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 185673898 ps |
| CPU time | 14.47 seconds |
| Started | Jan 03 12:39:11 PM PST 24 |
| Finished | Jan 03 12:40:54 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-2a124619-008a-47eb-9233-039c9c255cb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1666036545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.1666036545 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.486609482 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1161758647 ps |
| CPU time | 4.62 seconds |
| Started | Jan 03 12:39:22 PM PST 24 |
| Finished | Jan 03 12:41:00 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-f4467101-242a-4439-82a7-c6cb4d2ad1cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=486609482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.486609482 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2510524096 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 681019578 ps |
| CPU time | 13.9 seconds |
| Started | Jan 03 12:39:21 PM PST 24 |
| Finished | Jan 03 12:41:09 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-7b0ec5d9-f2ce-453d-b0c1-e19547d6c6ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2510524096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2510524096 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2916271566 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 82648916094 ps |
| CPU time | 215.83 seconds |
| Started | Jan 03 12:39:04 PM PST 24 |
| Finished | Jan 03 12:44:15 PM PST 24 |
| Peak memory | 202716 kb |
| Host | smart-eb970b85-c959-4072-a3ea-ff1b99c9c95b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2916271566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.2916271566 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.4249455700 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 78596076 ps |
| CPU time | 1.96 seconds |
| Started | Jan 03 12:39:59 PM PST 24 |
| Finished | Jan 03 12:41:34 PM PST 24 |
| Peak memory | 201356 kb |
| Host | smart-ad0d53b6-ee0b-4f70-b1b9-50d58fc83134 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4249455700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.4249455700 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.1784884846 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 33238404 ps |
| CPU time | 3.73 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:40:06 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-38b57710-1b87-42e5-809d-f43b5f0f43f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1784884846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1784884846 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.4092200494 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 22400328320 ps |
| CPU time | 46.04 seconds |
| Started | Jan 03 12:40:06 PM PST 24 |
| Finished | Jan 03 12:42:19 PM PST 24 |
| Peak memory | 200960 kb |
| Host | smart-c5e3144a-a471-485e-a7ab-f4befd3156da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092200494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.4092200494 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.2088598342 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 34100515 ps |
| CPU time | 2.92 seconds |
| Started | Jan 03 12:39:16 PM PST 24 |
| Finished | Jan 03 12:40:51 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-3b0eb208-2f04-48dc-9757-a814c53cda50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088598342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2088598342 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.4075129843 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 10962311 ps |
| CPU time | 1.14 seconds |
| Started | Jan 03 12:39:33 PM PST 24 |
| Finished | Jan 03 12:41:06 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-9eb934f7-b0de-48ea-8bbb-f2d72a6fa101 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4075129843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.4075129843 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.4243244597 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 134583174 ps |
| CPU time | 1.4 seconds |
| Started | Jan 03 12:39:44 PM PST 24 |
| Finished | Jan 03 12:41:26 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-b8bc399e-d12e-4857-b31c-60fb2afeaeb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4243244597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.4243244597 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2359625132 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1574470002 ps |
| CPU time | 7.79 seconds |
| Started | Jan 03 12:40:03 PM PST 24 |
| Finished | Jan 03 12:41:50 PM PST 24 |
| Peak memory | 200984 kb |
| Host | smart-277e532a-2c0d-4fce-95aa-13b5be1422df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359625132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2359625132 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.875253693 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 4517813932 ps |
| CPU time | 7.54 seconds |
| Started | Jan 03 12:39:07 PM PST 24 |
| Finished | Jan 03 12:40:28 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-e431a8ca-b4ea-4755-acb7-408c62e4cb09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=875253693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.875253693 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2263253797 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 10010204 ps |
| CPU time | 1.11 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:40:08 PM PST 24 |
| Peak memory | 201256 kb |
| Host | smart-b5d253ec-3eae-433d-a9d2-1f005469f7e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263253797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2263253797 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1087246411 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 5652555096 ps |
| CPU time | 81.64 seconds |
| Started | Jan 03 12:39:07 PM PST 24 |
| Finished | Jan 03 12:41:55 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-774563aa-8472-4d2f-a71e-26d6c5d0e782 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1087246411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1087246411 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1214926633 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4789723932 ps |
| CPU time | 18.41 seconds |
| Started | Jan 03 12:39:05 PM PST 24 |
| Finished | Jan 03 12:40:39 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-a8f936e8-45a6-4ca7-b092-5d440ea537f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1214926633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1214926633 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3746172315 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1132674225 ps |
| CPU time | 36.27 seconds |
| Started | Jan 03 12:39:07 PM PST 24 |
| Finished | Jan 03 12:40:56 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-8d355ed3-02a4-4bf8-b063-d970935ba59f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3746172315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.3746172315 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1808567170 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 157791541 ps |
| CPU time | 3.28 seconds |
| Started | Jan 03 12:40:02 PM PST 24 |
| Finished | Jan 03 12:41:32 PM PST 24 |
| Peak memory | 200352 kb |
| Host | smart-96e9068c-88bf-419c-b230-625ee1ee93c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1808567170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1808567170 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.2461430705 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 82820986 ps |
| CPU time | 4.33 seconds |
| Started | Jan 03 12:38:33 PM PST 24 |
| Finished | Jan 03 12:39:47 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-eeced46c-8723-4ba0-8773-6f3b82f43b5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2461430705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2461430705 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.1703919260 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 106422019 ps |
| CPU time | 3.87 seconds |
| Started | Jan 03 12:39:20 PM PST 24 |
| Finished | Jan 03 12:40:56 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-f43ab198-de91-44b4-b2bf-80fb2b12a92b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1703919260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1703919260 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.1191137582 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 80354847 ps |
| CPU time | 6.18 seconds |
| Started | Jan 03 12:39:48 PM PST 24 |
| Finished | Jan 03 12:41:27 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-326ef606-842d-4867-9fd5-22d5b04d5b9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1191137582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1191137582 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.4078393625 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 8060031472 ps |
| CPU time | 58.66 seconds |
| Started | Jan 03 12:39:03 PM PST 24 |
| Finished | Jan 03 12:41:32 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-a8b8246a-bbe1-40e9-a24b-b1cbda8d5106 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4078393625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.4078393625 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.2273590232 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 188969145 ps |
| CPU time | 6.82 seconds |
| Started | Jan 03 12:38:54 PM PST 24 |
| Finished | Jan 03 12:40:49 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-87bf4b8e-527a-45d8-a1be-90c30d90f229 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273590232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2273590232 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.1819381091 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 11934790 ps |
| CPU time | 1.27 seconds |
| Started | Jan 03 12:39:03 PM PST 24 |
| Finished | Jan 03 12:40:13 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-ba74826d-b6c7-4fc6-b71f-325ab59ae53d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1819381091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1819381091 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.220306952 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 32656108 ps |
| CPU time | 1.23 seconds |
| Started | Jan 03 12:39:28 PM PST 24 |
| Finished | Jan 03 12:40:58 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-606873e0-d330-4707-9ec3-893a3ca44c19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=220306952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.220306952 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1107092021 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 8509480573 ps |
| CPU time | 8.08 seconds |
| Started | Jan 03 12:39:08 PM PST 24 |
| Finished | Jan 03 12:40:45 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-6a598cc9-1eec-42e2-ab0c-21b75651e367 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107092021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1107092021 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1340310524 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3126034854 ps |
| CPU time | 7.22 seconds |
| Started | Jan 03 12:39:16 PM PST 24 |
| Finished | Jan 03 12:40:48 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-6828fe76-2d0c-4b7c-9d92-ce959e728076 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1340310524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1340310524 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2928546131 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 12803111 ps |
| CPU time | 1.11 seconds |
| Started | Jan 03 12:39:02 PM PST 24 |
| Finished | Jan 03 12:40:45 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-9fb44e40-b1f4-44db-8294-ce8ab1d721e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928546131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2928546131 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.2403592356 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 1573937434 ps |
| CPU time | 21.32 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:40:28 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-f20aa57d-b0cc-4228-9551-caab5b12ba97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2403592356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2403592356 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1431696504 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 2654118308 ps |
| CPU time | 14.53 seconds |
| Started | Jan 03 12:39:09 PM PST 24 |
| Finished | Jan 03 12:41:00 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-21a7f3a3-b59d-4aad-ae72-20c92725c737 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1431696504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1431696504 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1081282381 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 8361965 ps |
| CPU time | 2.57 seconds |
| Started | Jan 03 12:38:56 PM PST 24 |
| Finished | Jan 03 12:40:04 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-a7be5a97-f762-4a88-a882-6e26aed9ae67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1081282381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.1081282381 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2833151802 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 233630216 ps |
| CPU time | 34.59 seconds |
| Started | Jan 03 12:38:44 PM PST 24 |
| Finished | Jan 03 12:40:32 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-d2b7ca7e-81aa-452f-8a6f-bc16f8af5f81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2833151802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.2833151802 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3720227788 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 791442880 ps |
| CPU time | 8.12 seconds |
| Started | Jan 03 12:39:54 PM PST 24 |
| Finished | Jan 03 12:41:24 PM PST 24 |
| Peak memory | 201264 kb |
| Host | smart-9f1696d6-2913-40ce-b686-643758574766 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3720227788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3720227788 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1408800867 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 703389694 ps |
| CPU time | 12.66 seconds |
| Started | Jan 03 12:38:59 PM PST 24 |
| Finished | Jan 03 12:40:37 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-ff2c0b1c-e4ea-4c37-abde-15b2ec11f1c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1408800867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1408800867 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2261177344 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 7725045189 ps |
| CPU time | 33.99 seconds |
| Started | Jan 03 12:38:42 PM PST 24 |
| Finished | Jan 03 12:40:34 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-1b2e2f52-8bd2-40f4-8ab8-7e361c45c382 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2261177344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.2261177344 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.4078040552 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1227366994 ps |
| CPU time | 9.83 seconds |
| Started | Jan 03 12:39:24 PM PST 24 |
| Finished | Jan 03 12:41:06 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-99aba04a-0af5-4655-b47c-5b3cbf328c86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4078040552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.4078040552 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.3025542612 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 27525997 ps |
| CPU time | 3.38 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:40:24 PM PST 24 |
| Peak memory | 200740 kb |
| Host | smart-27ff25d7-7f47-4ff9-a660-b5ac77795667 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3025542612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3025542612 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3115634302 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 52314916109 ps |
| CPU time | 130.43 seconds |
| Started | Jan 03 12:38:53 PM PST 24 |
| Finished | Jan 03 12:42:13 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-49362a52-8ec3-40cd-a3e6-c849613981d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115634302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3115634302 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1799852458 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 4409773265 ps |
| CPU time | 16.15 seconds |
| Started | Jan 03 12:38:56 PM PST 24 |
| Finished | Jan 03 12:40:18 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-58c3aa35-c21c-4e55-8c67-182504b34eab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1799852458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1799852458 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2541369384 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 72858559 ps |
| CPU time | 6.64 seconds |
| Started | Jan 03 12:38:58 PM PST 24 |
| Finished | Jan 03 12:40:17 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-2722aabe-8388-49a3-b08f-b9ab02a181ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541369384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2541369384 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.3466736070 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 880184003 ps |
| CPU time | 4.91 seconds |
| Started | Jan 03 12:38:40 PM PST 24 |
| Finished | Jan 03 12:39:56 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-0f539457-cc92-4bb7-930b-a8b0a110ae49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3466736070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3466736070 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.280765587 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 42976318 ps |
| CPU time | 1.32 seconds |
| Started | Jan 03 12:38:50 PM PST 24 |
| Finished | Jan 03 12:39:57 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-951f14a4-1d9f-4c9e-94b9-ea3bceb6117e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=280765587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.280765587 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.1714539017 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 6338806259 ps |
| CPU time | 7.74 seconds |
| Started | Jan 03 12:39:20 PM PST 24 |
| Finished | Jan 03 12:41:00 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-6a02fdc3-f08e-46ed-beae-ff63da90577a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714539017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1714539017 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.4161655585 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2464993865 ps |
| CPU time | 9.85 seconds |
| Started | Jan 03 12:39:21 PM PST 24 |
| Finished | Jan 03 12:41:05 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-45a0d243-0da6-4580-bc7b-985375d601cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4161655585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.4161655585 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3910058777 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 18628828 ps |
| CPU time | 1.12 seconds |
| Started | Jan 03 12:38:57 PM PST 24 |
| Finished | Jan 03 12:40:26 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-cae7df7f-4876-4e38-8052-a331c3e3bedd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910058777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3910058777 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.459412365 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 236072347 ps |
| CPU time | 17.64 seconds |
| Started | Jan 03 12:39:23 PM PST 24 |
| Finished | Jan 03 12:41:01 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-81d84eba-8693-4633-9be2-e28666988f93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=459412365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.459412365 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2244984384 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 6559054415 ps |
| CPU time | 65.21 seconds |
| Started | Jan 03 12:39:37 PM PST 24 |
| Finished | Jan 03 12:42:02 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-cc4c960c-2ac7-46b6-9d73-5becddaa9d5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2244984384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2244984384 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.65809148 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 807880202 ps |
| CPU time | 103.89 seconds |
| Started | Jan 03 12:39:09 PM PST 24 |
| Finished | Jan 03 12:42:19 PM PST 24 |
| Peak memory | 206076 kb |
| Host | smart-f22f971a-3762-49e2-a5e0-0f231c44c915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=65809148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_ reset.65809148 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.282420363 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2488853860 ps |
| CPU time | 110.49 seconds |
| Started | Jan 03 12:39:10 PM PST 24 |
| Finished | Jan 03 12:42:25 PM PST 24 |
| Peak memory | 206444 kb |
| Host | smart-a27213e6-51a4-4b12-834c-bfa1acdbd6d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=282420363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res et_error.282420363 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1439283214 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 404282651 ps |
| CPU time | 6.31 seconds |
| Started | Jan 03 12:39:00 PM PST 24 |
| Finished | Jan 03 12:40:19 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-828eb80d-379f-41b3-a420-cd40828c0ef3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1439283214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1439283214 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2667198953 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3960533780 ps |
| CPU time | 16.12 seconds |
| Started | Jan 03 12:39:21 PM PST 24 |
| Finished | Jan 03 12:41:28 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-70ed6a06-1bac-4ed6-ac16-c2dffd187edc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2667198953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.2667198953 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1046954414 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 38800284 ps |
| CPU time | 3.23 seconds |
| Started | Jan 03 12:39:28 PM PST 24 |
| Finished | Jan 03 12:40:50 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-a1831bb0-84a3-48df-b135-64b0e481d929 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1046954414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1046954414 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.2817164965 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 446090978 ps |
| CPU time | 6.18 seconds |
| Started | Jan 03 12:39:23 PM PST 24 |
| Finished | Jan 03 12:40:58 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-19d4f586-6bc3-4583-8774-5118a69267f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2817164965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2817164965 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.690340209 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 54058478 ps |
| CPU time | 4.47 seconds |
| Started | Jan 03 12:39:29 PM PST 24 |
| Finished | Jan 03 12:40:56 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-ed71a0c6-f50a-4aa3-bb0b-13dcbab2286b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=690340209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.690340209 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.2774798406 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 205354523710 ps |
| CPU time | 124.83 seconds |
| Started | Jan 03 12:39:20 PM PST 24 |
| Finished | Jan 03 12:42:50 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-6344474b-254a-4978-bad2-931814e7f9ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774798406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2774798406 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.809115315 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 4377531160 ps |
| CPU time | 8.1 seconds |
| Started | Jan 03 12:39:35 PM PST 24 |
| Finished | Jan 03 12:41:14 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-fdd2a7f6-0e5c-4d29-9231-42b9b7a4dd36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=809115315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.809115315 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.661822878 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 19983495 ps |
| CPU time | 1.88 seconds |
| Started | Jan 03 12:39:20 PM PST 24 |
| Finished | Jan 03 12:40:46 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-0fdff17c-58ab-4ee5-9225-c0312a09abdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661822878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.661822878 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.468161968 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 51246971 ps |
| CPU time | 2.47 seconds |
| Started | Jan 03 12:39:37 PM PST 24 |
| Finished | Jan 03 12:41:04 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-a02129fe-7847-4a4f-83ff-e7c867ea74cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=468161968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.468161968 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.2812536649 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11692099 ps |
| CPU time | 1.08 seconds |
| Started | Jan 03 12:39:21 PM PST 24 |
| Finished | Jan 03 12:40:47 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-4e061a63-21ce-4f88-b55c-6b0822134c02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2812536649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2812536649 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3002157599 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 7837647202 ps |
| CPU time | 6.74 seconds |
| Started | Jan 03 12:39:02 PM PST 24 |
| Finished | Jan 03 12:40:19 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-54336b21-f643-45b0-86eb-89a3199543fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002157599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3002157599 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.510537715 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 953479425 ps |
| CPU time | 5.5 seconds |
| Started | Jan 03 12:39:24 PM PST 24 |
| Finished | Jan 03 12:41:10 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-2f0c1355-795f-41f0-a7fb-bd3400acc157 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=510537715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.510537715 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1541711969 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 10087774 ps |
| CPU time | 0.97 seconds |
| Started | Jan 03 12:39:12 PM PST 24 |
| Finished | Jan 03 12:40:28 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-ef248c55-4914-480b-8df5-ca91a9bc8532 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541711969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1541711969 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1598828685 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 571990407 ps |
| CPU time | 28.39 seconds |
| Started | Jan 03 12:39:43 PM PST 24 |
| Finished | Jan 03 12:41:35 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-3b574094-e893-471b-aa97-2911cd429542 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1598828685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1598828685 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3485178508 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 7882568300 ps |
| CPU time | 112.2 seconds |
| Started | Jan 03 12:39:04 PM PST 24 |
| Finished | Jan 03 12:42:11 PM PST 24 |
| Peak memory | 204064 kb |
| Host | smart-151bfac8-cfb8-417b-bd4c-a3d225e0974a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3485178508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.3485178508 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.4043583023 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 399969973 ps |
| CPU time | 37.58 seconds |
| Started | Jan 03 12:39:39 PM PST 24 |
| Finished | Jan 03 12:41:42 PM PST 24 |
| Peak memory | 202844 kb |
| Host | smart-dcf4e3b6-f2ee-496e-bdeb-4188a86fe440 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4043583023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.4043583023 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2995327257 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 29227841 ps |
| CPU time | 1.81 seconds |
| Started | Jan 03 12:39:17 PM PST 24 |
| Finished | Jan 03 12:40:47 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-a9404dd2-715c-4ea6-9a49-8021800573ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2995327257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2995327257 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2162259844 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 171081366 ps |
| CPU time | 3.33 seconds |
| Started | Jan 03 12:39:44 PM PST 24 |
| Finished | Jan 03 12:41:31 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-40b015ff-1665-469f-8145-60e8fd04ad62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2162259844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2162259844 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.4065908590 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 106751621 ps |
| CPU time | 2.52 seconds |
| Started | Jan 03 12:39:37 PM PST 24 |
| Finished | Jan 03 12:41:11 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-b5c5ea43-f75b-485f-aec8-dc95d3ef4436 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4065908590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.4065908590 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2916493273 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 8595212993 ps |
| CPU time | 65.5 seconds |
| Started | Jan 03 12:39:09 PM PST 24 |
| Finished | Jan 03 12:41:51 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-85ba8051-efb7-4167-a337-69150285dfde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2916493273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2916493273 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.582023049 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 52029541 ps |
| CPU time | 3.32 seconds |
| Started | Jan 03 12:39:15 PM PST 24 |
| Finished | Jan 03 12:40:43 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-aa13d8a5-1cd5-4b4b-aef5-dacb6399d696 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=582023049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.582023049 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.2327519106 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 10892963 ps |
| CPU time | 1.01 seconds |
| Started | Jan 03 12:39:08 PM PST 24 |
| Finished | Jan 03 12:40:21 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-c524f2ba-a9ac-490a-bac4-fc7e58ecb5e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2327519106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2327519106 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.585033575 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2742888078 ps |
| CPU time | 7.01 seconds |
| Started | Jan 03 12:39:57 PM PST 24 |
| Finished | Jan 03 12:41:52 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-80369fcd-8170-4f8f-8ab9-ae1ac0b7e37e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=585033575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.585033575 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3083586869 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 934438928 ps |
| CPU time | 7.41 seconds |
| Started | Jan 03 12:39:32 PM PST 24 |
| Finished | Jan 03 12:41:03 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-53c5a89f-3d70-41bb-babd-747b256f8622 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3083586869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3083586869 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.820583362 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 10476454 ps |
| CPU time | 1.09 seconds |
| Started | Jan 03 12:38:50 PM PST 24 |
| Finished | Jan 03 12:40:08 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-3241275f-6a2a-4227-bebe-1c21b25d7a54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820583362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.820583362 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.589061990 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 6015121568 ps |
| CPU time | 66.8 seconds |
| Started | Jan 03 12:39:30 PM PST 24 |
| Finished | Jan 03 12:41:59 PM PST 24 |
| Peak memory | 202460 kb |
| Host | smart-eded0543-2f78-4368-9e5b-c82e250ab633 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=589061990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.589061990 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.3667837499 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 13434818361 ps |
| CPU time | 46.57 seconds |
| Started | Jan 03 12:40:26 PM PST 24 |
| Finished | Jan 03 12:42:38 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-37578774-b716-4b3d-9229-feb8c76f29d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3667837499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3667837499 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.1575445112 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 6519761283 ps |
| CPU time | 40.56 seconds |
| Started | Jan 03 12:39:27 PM PST 24 |
| Finished | Jan 03 12:41:36 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-596fc959-783d-49cf-bbce-863da571b205 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1575445112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.1575445112 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.4266277924 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 187623102 ps |
| CPU time | 3.42 seconds |
| Started | Jan 03 12:39:01 PM PST 24 |
| Finished | Jan 03 12:40:12 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-51b1fd2f-8116-475d-b4f4-b1af384a3b05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4266277924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.4266277924 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3439429920 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 4450460228 ps |
| CPU time | 17.81 seconds |
| Started | Jan 03 12:39:36 PM PST 24 |
| Finished | Jan 03 12:41:19 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-3d7b7217-11a0-4ac9-85b1-0c6b2b5ce619 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3439429920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3439429920 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3506035750 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2219312864 ps |
| CPU time | 7.78 seconds |
| Started | Jan 03 12:39:13 PM PST 24 |
| Finished | Jan 03 12:41:00 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-58aa006d-45a1-461f-9cc8-15d64cf2a94f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3506035750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3506035750 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.2183371542 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1227689238 ps |
| CPU time | 10.34 seconds |
| Started | Jan 03 12:39:50 PM PST 24 |
| Finished | Jan 03 12:41:24 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-bd8f8e3d-9eaa-4bf7-8fcb-03613eca556f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2183371542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2183371542 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.2474567881 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 73253824 ps |
| CPU time | 8.75 seconds |
| Started | Jan 03 12:39:41 PM PST 24 |
| Finished | Jan 03 12:41:14 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-1055bf84-9603-4619-b837-1562a2eda328 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2474567881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2474567881 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1918693593 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 35276061161 ps |
| CPU time | 168.85 seconds |
| Started | Jan 03 12:38:53 PM PST 24 |
| Finished | Jan 03 12:42:52 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-e7c64307-f26f-48d3-8943-03bf4f266784 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1918693593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1918693593 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.459170776 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 49688677 ps |
| CPU time | 3.53 seconds |
| Started | Jan 03 12:39:05 PM PST 24 |
| Finished | Jan 03 12:40:25 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-1aa8a016-4f7b-47f1-a4dd-1f36a45db7b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459170776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.459170776 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.1946028100 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 61481337 ps |
| CPU time | 1.35 seconds |
| Started | Jan 03 12:40:06 PM PST 24 |
| Finished | Jan 03 12:41:35 PM PST 24 |
| Peak memory | 200852 kb |
| Host | smart-d2f06cd0-f5ef-40eb-b92f-1c31a7db122c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1946028100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1946028100 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2011940964 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2677464720 ps |
| CPU time | 8.96 seconds |
| Started | Jan 03 12:39:09 PM PST 24 |
| Finished | Jan 03 12:40:42 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-c8bf6555-bcb8-4860-9c7f-9ac72954d1dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011940964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2011940964 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.600102199 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2034005656 ps |
| CPU time | 6.33 seconds |
| Started | Jan 03 12:39:42 PM PST 24 |
| Finished | Jan 03 12:41:18 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-cecd24d1-e701-4fb1-b06e-337d42130bca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=600102199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.600102199 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3505786767 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 18637776 ps |
| CPU time | 1.13 seconds |
| Started | Jan 03 12:40:11 PM PST 24 |
| Finished | Jan 03 12:41:56 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-4f281e51-12b4-4b1a-abb5-87b6dcfb0179 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505786767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3505786767 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3049287878 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 7865289776 ps |
| CPU time | 88.33 seconds |
| Started | Jan 03 12:39:03 PM PST 24 |
| Finished | Jan 03 12:41:41 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-30fd7c79-c90c-4840-b33d-f1c852d5c7f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3049287878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3049287878 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.231720597 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 242202015 ps |
| CPU time | 27.53 seconds |
| Started | Jan 03 12:39:19 PM PST 24 |
| Finished | Jan 03 12:41:08 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-d18fc86c-b9d5-4406-8791-34086aa1a05d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=231720597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.231720597 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2661094252 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1536223677 ps |
| CPU time | 79.1 seconds |
| Started | Jan 03 12:39:01 PM PST 24 |
| Finished | Jan 03 12:41:40 PM PST 24 |
| Peak memory | 204348 kb |
| Host | smart-25d838d3-7da5-4695-91a4-c642fc29caa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2661094252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.2661094252 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.113432254 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 13156001957 ps |
| CPU time | 179.9 seconds |
| Started | Jan 03 12:39:15 PM PST 24 |
| Finished | Jan 03 12:43:31 PM PST 24 |
| Peak memory | 206844 kb |
| Host | smart-a90ebc13-393a-45bc-8e66-e259988fef83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=113432254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res et_error.113432254 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.701437904 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 82636796 ps |
| CPU time | 5.39 seconds |
| Started | Jan 03 12:39:13 PM PST 24 |
| Finished | Jan 03 12:40:43 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-bc72dd93-6686-43db-bc92-ddd8d01406de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=701437904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.701437904 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.277674170 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 324159245 ps |
| CPU time | 5.74 seconds |
| Started | Jan 03 12:39:17 PM PST 24 |
| Finished | Jan 03 12:40:44 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-be9d504e-1cd3-4ae1-b455-2ad888b66482 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=277674170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.277674170 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.3220459354 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 11968630 ps |
| CPU time | 1.11 seconds |
| Started | Jan 03 12:38:50 PM PST 24 |
| Finished | Jan 03 12:40:07 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-13e9a6a7-285a-4f58-9957-63be483039e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3220459354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3220459354 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.2724118651 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 64908061 ps |
| CPU time | 1.76 seconds |
| Started | Jan 03 12:39:44 PM PST 24 |
| Finished | Jan 03 12:41:20 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-6a96b787-cbd5-4521-a3c4-4b927e5f265f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2724118651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2724118651 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.1406512291 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 71117608 ps |
| CPU time | 5.52 seconds |
| Started | Jan 03 12:39:21 PM PST 24 |
| Finished | Jan 03 12:40:44 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-8fd30982-3bae-417d-8faa-3db74c764043 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1406512291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1406512291 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.906925140 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 16459703654 ps |
| CPU time | 68.85 seconds |
| Started | Jan 03 12:39:27 PM PST 24 |
| Finished | Jan 03 12:42:01 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-86ec684e-f0a5-47dc-bf92-1c3052a9fbf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=906925140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.906925140 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.687846754 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 3589950237 ps |
| CPU time | 18.24 seconds |
| Started | Jan 03 12:39:36 PM PST 24 |
| Finished | Jan 03 12:41:27 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-835b7b9d-484e-443a-8aba-75dd32bf3eec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=687846754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.687846754 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.3068905152 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 67076741 ps |
| CPU time | 2.24 seconds |
| Started | Jan 03 12:39:12 PM PST 24 |
| Finished | Jan 03 12:40:46 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-0622587f-0c73-4824-b335-fc1fcff656f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068905152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3068905152 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.2754560959 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 87636432 ps |
| CPU time | 1.29 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:41:17 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-5954e0d0-c176-4a1f-bf05-cbf9f908e407 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2754560959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2754560959 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1588010918 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 7491838400 ps |
| CPU time | 8 seconds |
| Started | Jan 03 12:39:54 PM PST 24 |
| Finished | Jan 03 12:42:03 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-27764bb2-7d6f-4bc7-b0f1-fb4c6d9e7bb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588010918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1588010918 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.4178038195 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3287853591 ps |
| CPU time | 7.9 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:41:13 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-8d919e00-fa0b-488c-b746-efad406dbe77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4178038195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.4178038195 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.93319221 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 29081332 ps |
| CPU time | 1.15 seconds |
| Started | Jan 03 12:39:27 PM PST 24 |
| Finished | Jan 03 12:40:54 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-c60c4741-f9d0-42dd-abe7-563fdfdc2090 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93319221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.93319221 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2915538512 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 1652419942 ps |
| CPU time | 35.65 seconds |
| Started | Jan 03 12:39:03 PM PST 24 |
| Finished | Jan 03 12:40:48 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-7f518200-8f8d-4e0a-aeb7-23f72c29d2c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2915538512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2915538512 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.578330894 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 134313154 ps |
| CPU time | 29.67 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:41:47 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-4215f440-5cec-41f4-99ee-5ccbafbd5887 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=578330894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand _reset.578330894 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3957790319 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1179112145 ps |
| CPU time | 37.11 seconds |
| Started | Jan 03 12:39:32 PM PST 24 |
| Finished | Jan 03 12:41:32 PM PST 24 |
| Peak memory | 202920 kb |
| Host | smart-3d23798f-63f1-4c8c-9d23-313d4fc06f5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3957790319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.3957790319 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2661292639 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2029422860 ps |
| CPU time | 5.71 seconds |
| Started | Jan 03 12:39:57 PM PST 24 |
| Finished | Jan 03 12:41:57 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-f79ee299-991b-4e86-8e5b-4db6a5dad926 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2661292639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2661292639 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.4212480933 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1172084691 ps |
| CPU time | 7.22 seconds |
| Started | Jan 03 12:39:59 PM PST 24 |
| Finished | Jan 03 12:41:36 PM PST 24 |
| Peak memory | 201268 kb |
| Host | smart-6ae768c9-5ac1-4e9a-ad84-adefb0337807 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4212480933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.4212480933 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.104573787 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 6562487101 ps |
| CPU time | 36.01 seconds |
| Started | Jan 03 12:39:34 PM PST 24 |
| Finished | Jan 03 12:41:42 PM PST 24 |
| Peak memory | 201328 kb |
| Host | smart-37b87c97-8d84-4566-a0b8-294fd3efbd11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=104573787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo w_rsp.104573787 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2067143234 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 458795323 ps |
| CPU time | 6.42 seconds |
| Started | Jan 03 12:39:04 PM PST 24 |
| Finished | Jan 03 12:40:25 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-fdaa8feb-4f11-410c-a372-e522c42cd098 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2067143234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2067143234 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.2293287969 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 190055257 ps |
| CPU time | 4.23 seconds |
| Started | Jan 03 12:39:12 PM PST 24 |
| Finished | Jan 03 12:40:43 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-9720adad-9aee-4f47-9c68-c51e3a382d14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2293287969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2293287969 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.4030027156 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2706946702 ps |
| CPU time | 13.34 seconds |
| Started | Jan 03 12:39:09 PM PST 24 |
| Finished | Jan 03 12:40:49 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-eadf900f-e64c-4049-af5c-7df3b745f72a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4030027156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.4030027156 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1397690405 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 19312081368 ps |
| CPU time | 60.48 seconds |
| Started | Jan 03 12:39:13 PM PST 24 |
| Finished | Jan 03 12:41:53 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-a57f735c-ddaa-4f58-91f5-89a895abd93e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397690405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1397690405 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2599045821 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 14615999598 ps |
| CPU time | 74.07 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:43:05 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-ab96238f-b82b-4862-9914-199bd6818324 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2599045821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2599045821 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3138481060 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 59658781 ps |
| CPU time | 6.15 seconds |
| Started | Jan 03 12:39:26 PM PST 24 |
| Finished | Jan 03 12:40:52 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-56b72629-c24d-4a23-9892-2d1b30ff5e13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138481060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3138481060 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.676983844 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 103215230 ps |
| CPU time | 1.61 seconds |
| Started | Jan 03 12:39:17 PM PST 24 |
| Finished | Jan 03 12:40:49 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-4d2e09b7-756b-4032-bd71-7bc9ef78771b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=676983844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.676983844 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2160108234 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3514407311 ps |
| CPU time | 6.03 seconds |
| Started | Jan 03 12:39:20 PM PST 24 |
| Finished | Jan 03 12:40:54 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-21ab1de3-0bbb-4a2b-9e07-707983ef4d64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160108234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2160108234 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3709565466 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 961255161 ps |
| CPU time | 6.83 seconds |
| Started | Jan 03 12:39:12 PM PST 24 |
| Finished | Jan 03 12:40:50 PM PST 24 |
| Peak memory | 201256 kb |
| Host | smart-b4426cb5-8d4c-43ed-9ba2-915bd45f96e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3709565466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3709565466 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1608640617 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 10742222 ps |
| CPU time | 1.08 seconds |
| Started | Jan 03 12:39:04 PM PST 24 |
| Finished | Jan 03 12:40:15 PM PST 24 |
| Peak memory | 201256 kb |
| Host | smart-da8f4633-e50c-4369-9b22-5d527b06b49d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608640617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1608640617 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1710832694 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 97268279 ps |
| CPU time | 10.89 seconds |
| Started | Jan 03 12:39:18 PM PST 24 |
| Finished | Jan 03 12:40:58 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-2abc0585-8cf5-4ebd-a1a3-1f5e50708815 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1710832694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1710832694 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2409841427 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 460576928 ps |
| CPU time | 54.14 seconds |
| Started | Jan 03 12:39:50 PM PST 24 |
| Finished | Jan 03 12:42:08 PM PST 24 |
| Peak memory | 202676 kb |
| Host | smart-b5849e9f-d244-4776-a282-560406055121 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2409841427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2409841427 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.3944263255 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 415102015 ps |
| CPU time | 28.75 seconds |
| Started | Jan 03 12:39:50 PM PST 24 |
| Finished | Jan 03 12:41:42 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-f3d869e2-7b67-448e-823b-4dd2dbd6f973 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3944263255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.3944263255 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1940715534 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 506714983 ps |
| CPU time | 49.37 seconds |
| Started | Jan 03 12:39:56 PM PST 24 |
| Finished | Jan 03 12:42:27 PM PST 24 |
| Peak memory | 203564 kb |
| Host | smart-c878c4f6-4257-4326-bf2a-a77327f83c59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1940715534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.1940715534 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3625144100 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 652659799 ps |
| CPU time | 10.95 seconds |
| Started | Jan 03 12:39:19 PM PST 24 |
| Finished | Jan 03 12:40:56 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-b59312f1-085a-4842-ad1f-259e4dead0e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3625144100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3625144100 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.862654079 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30915734335 ps |
| CPU time | 123.8 seconds |
| Started | Jan 03 12:39:14 PM PST 24 |
| Finished | Jan 03 12:42:42 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-a023858b-8e55-4a8b-91ff-2c25c9a47bf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=862654079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slo w_rsp.862654079 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1949532855 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 105744584 ps |
| CPU time | 1.29 seconds |
| Started | Jan 03 12:39:17 PM PST 24 |
| Finished | Jan 03 12:40:42 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-89203ac5-21f2-44ad-b6e0-a686541d17fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1949532855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1949532855 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.964985352 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 2303761680 ps |
| CPU time | 6.71 seconds |
| Started | Jan 03 12:39:30 PM PST 24 |
| Finished | Jan 03 12:40:56 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-7085eb3c-831f-40d5-86c4-99f6f1358cec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=964985352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.964985352 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.968100811 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1632421124 ps |
| CPU time | 11.17 seconds |
| Started | Jan 03 12:39:48 PM PST 24 |
| Finished | Jan 03 12:41:32 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-a9af40ef-7708-40a5-b5c7-36a09ec436c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=968100811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.968100811 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2086101777 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 49626481778 ps |
| CPU time | 110.31 seconds |
| Started | Jan 03 12:39:33 PM PST 24 |
| Finished | Jan 03 12:42:55 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-6ea985ce-2766-43f1-bfa0-912358838480 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086101777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2086101777 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.31191976 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 9993949032 ps |
| CPU time | 56.71 seconds |
| Started | Jan 03 12:39:09 PM PST 24 |
| Finished | Jan 03 12:41:34 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-41bd88da-c936-4df0-b3bb-d90e9a8b3cc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=31191976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.31191976 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.2383493909 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 11027494 ps |
| CPU time | 1.07 seconds |
| Started | Jan 03 12:39:38 PM PST 24 |
| Finished | Jan 03 12:41:11 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-d656fc67-a266-4ff7-b284-a12af684d96c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383493909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2383493909 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.2210817035 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 921393585 ps |
| CPU time | 4.29 seconds |
| Started | Jan 03 12:40:05 PM PST 24 |
| Finished | Jan 03 12:41:33 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-13d090eb-a57a-4135-8086-053157bdce25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2210817035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2210817035 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.2981697618 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 8213590 ps |
| CPU time | 1.02 seconds |
| Started | Jan 03 12:39:23 PM PST 24 |
| Finished | Jan 03 12:40:53 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-75a27d32-b307-46c7-bb97-a8fdb598a9a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2981697618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2981697618 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3231710155 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 7637857689 ps |
| CPU time | 9.24 seconds |
| Started | Jan 03 12:39:56 PM PST 24 |
| Finished | Jan 03 12:41:45 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-874ef78e-52f8-495b-a3ba-627a4437a631 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231710155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3231710155 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.3133742859 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 3668921191 ps |
| CPU time | 7.29 seconds |
| Started | Jan 03 12:39:52 PM PST 24 |
| Finished | Jan 03 12:41:31 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-6cb99f2f-4cc1-4a86-a5e7-9c32bafdf8f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3133742859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3133742859 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2851415399 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 19062302 ps |
| CPU time | 1.05 seconds |
| Started | Jan 03 12:40:00 PM PST 24 |
| Finished | Jan 03 12:41:38 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-d8ed0de2-35b6-436e-9789-a6eae2a78be9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851415399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2851415399 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3482623141 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 9686914902 ps |
| CPU time | 96.36 seconds |
| Started | Jan 03 12:39:17 PM PST 24 |
| Finished | Jan 03 12:42:18 PM PST 24 |
| Peak memory | 203592 kb |
| Host | smart-5a802f3a-96ed-43f0-a6c4-2dfeff0eb9f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3482623141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3482623141 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.685686776 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 748003926 ps |
| CPU time | 86.2 seconds |
| Started | Jan 03 12:39:28 PM PST 24 |
| Finished | Jan 03 12:42:22 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-dafad048-1d38-4014-bdfc-f20de15b4fc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=685686776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand _reset.685686776 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.397100563 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 261974680 ps |
| CPU time | 26.26 seconds |
| Started | Jan 03 12:39:47 PM PST 24 |
| Finished | Jan 03 12:41:45 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-11f330bd-c4cd-4e92-a175-e402affd221c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=397100563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res et_error.397100563 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.414657334 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 255740496 ps |
| CPU time | 5.68 seconds |
| Started | Jan 03 12:39:16 PM PST 24 |
| Finished | Jan 03 12:40:48 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-756e6f24-7a6a-4959-bbc7-3ba72ffb79c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=414657334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.414657334 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2627075555 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2010761649 ps |
| CPU time | 23.57 seconds |
| Started | Jan 03 12:38:05 PM PST 24 |
| Finished | Jan 03 12:39:45 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-ea07c513-79ad-4cbc-b5c4-fe0d7f27569c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2627075555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2627075555 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1856954612 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 72505676306 ps |
| CPU time | 132.12 seconds |
| Started | Jan 03 12:38:01 PM PST 24 |
| Finished | Jan 03 12:41:28 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-0742cc46-185f-4b91-acd9-d557e069501a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1856954612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1856954612 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.3446265316 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1002614091 ps |
| CPU time | 10.66 seconds |
| Started | Jan 03 12:38:12 PM PST 24 |
| Finished | Jan 03 12:39:36 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-353e7eb3-d799-4b53-a1bb-cd4beaa24d94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3446265316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3446265316 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.4110022619 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 849303912 ps |
| CPU time | 9.57 seconds |
| Started | Jan 03 12:38:29 PM PST 24 |
| Finished | Jan 03 12:39:49 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-63383abe-2c30-4bd3-9430-ace0ab944f50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4110022619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.4110022619 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.4165901911 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 12745068327 ps |
| CPU time | 33.01 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:40:03 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-0a1a3a57-70d1-46b3-9429-eb24a1bdc0e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165901911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.4165901911 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1300048528 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 28605533134 ps |
| CPU time | 131.46 seconds |
| Started | Jan 03 12:38:12 PM PST 24 |
| Finished | Jan 03 12:41:41 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-eeba1a46-edb1-4ee8-9b5b-d5d4937f3940 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1300048528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1300048528 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.4278914380 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 219554135 ps |
| CPU time | 4.81 seconds |
| Started | Jan 03 12:38:04 PM PST 24 |
| Finished | Jan 03 12:39:38 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-11d5597a-5d62-4f3d-9527-5c3a5b5e4085 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278914380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.4278914380 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.1095224410 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4028669822 ps |
| CPU time | 11.19 seconds |
| Started | Jan 03 12:38:00 PM PST 24 |
| Finished | Jan 03 12:39:28 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-f18f29f6-175b-43fe-b483-4373c3dccb96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1095224410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1095224410 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.1562615692 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 111198981 ps |
| CPU time | 1.23 seconds |
| Started | Jan 03 12:38:14 PM PST 24 |
| Finished | Jan 03 12:39:48 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-b4782494-50e3-4e19-9a33-1748c5d886dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1562615692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1562615692 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3192824982 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 5284764863 ps |
| CPU time | 8.47 seconds |
| Started | Jan 03 12:38:05 PM PST 24 |
| Finished | Jan 03 12:39:26 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-bf4fb2d8-68da-4c68-9d9e-c3fc0c125c4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192824982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3192824982 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1267484455 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2592278108 ps |
| CPU time | 7.43 seconds |
| Started | Jan 03 12:37:52 PM PST 24 |
| Finished | Jan 03 12:39:15 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-dfc6e13f-3bf6-4d8b-86b2-82b145ba86f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1267484455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1267484455 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.165984859 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 9725461 ps |
| CPU time | 1.08 seconds |
| Started | Jan 03 12:38:06 PM PST 24 |
| Finished | Jan 03 12:39:23 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-8babbb51-61a9-4fe2-808d-9280b14ce780 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165984859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.165984859 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.2282485149 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1053815655 ps |
| CPU time | 49.34 seconds |
| Started | Jan 03 12:38:01 PM PST 24 |
| Finished | Jan 03 12:40:05 PM PST 24 |
| Peak memory | 202428 kb |
| Host | smart-c7c19731-efa5-4cfd-b2af-0b4558bf5f5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2282485149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2282485149 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3969838496 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 498639376 ps |
| CPU time | 7.22 seconds |
| Started | Jan 03 12:38:09 PM PST 24 |
| Finished | Jan 03 12:39:29 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-f7a16d21-0a6b-4da1-81f5-d3381ae9e8e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3969838496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3969838496 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.887108641 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 929052171 ps |
| CPU time | 165.41 seconds |
| Started | Jan 03 12:38:08 PM PST 24 |
| Finished | Jan 03 12:42:10 PM PST 24 |
| Peak memory | 206108 kb |
| Host | smart-7382140c-0fa0-4c56-bc79-232a35a4ec50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=887108641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_ reset.887108641 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1051782674 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 8364374871 ps |
| CPU time | 152.41 seconds |
| Started | Jan 03 12:38:07 PM PST 24 |
| Finished | Jan 03 12:41:52 PM PST 24 |
| Peak memory | 205160 kb |
| Host | smart-8cc85ec5-85a3-4e25-a9c7-f23663a44742 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1051782674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.1051782674 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.2186932730 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 578726076 ps |
| CPU time | 10.91 seconds |
| Started | Jan 03 12:38:16 PM PST 24 |
| Finished | Jan 03 12:39:44 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-052f75b2-30e3-45e4-b84d-e90ba3dfc1f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2186932730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2186932730 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2375011318 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 195868651 ps |
| CPU time | 9.2 seconds |
| Started | Jan 03 12:39:04 PM PST 24 |
| Finished | Jan 03 12:40:45 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-74d311f8-4995-4bb3-aab0-831df82071d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2375011318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2375011318 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.54710461 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 164158765723 ps |
| CPU time | 246.66 seconds |
| Started | Jan 03 12:39:14 PM PST 24 |
| Finished | Jan 03 12:44:37 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-99bedc17-ff2b-4a04-8fdf-98af179f8880 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=54710461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow _rsp.54710461 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.473220569 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 43701992 ps |
| CPU time | 2.63 seconds |
| Started | Jan 03 12:39:26 PM PST 24 |
| Finished | Jan 03 12:41:12 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-6d8f777a-6d7f-4f99-ba00-dddd9bb4a6c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=473220569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.473220569 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.3756977680 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 83017614 ps |
| CPU time | 5.97 seconds |
| Started | Jan 03 12:39:51 PM PST 24 |
| Finished | Jan 03 12:41:29 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-b42e8c0f-d5dc-4383-b6cc-2ea93afb8248 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3756977680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3756977680 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.2312963613 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 14022541 ps |
| CPU time | 1.45 seconds |
| Started | Jan 03 12:39:38 PM PST 24 |
| Finished | Jan 03 12:41:18 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-73993e6c-dffc-497d-98df-8cba2a9db49c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2312963613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2312963613 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3527219614 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 226808233830 ps |
| CPU time | 149.07 seconds |
| Started | Jan 03 12:39:42 PM PST 24 |
| Finished | Jan 03 12:43:34 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-cb3bc105-14ee-416b-b6f8-4dec42265024 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527219614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3527219614 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3164201755 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 42844981692 ps |
| CPU time | 84.58 seconds |
| Started | Jan 03 12:39:22 PM PST 24 |
| Finished | Jan 03 12:42:20 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-a920010a-30cd-4b65-9159-dae97a56743a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3164201755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3164201755 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3775414347 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 58841441 ps |
| CPU time | 4.66 seconds |
| Started | Jan 03 12:43:33 PM PST 24 |
| Finished | Jan 03 12:45:00 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-d80bebc6-8237-4bb9-bdeb-059e8203665a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775414347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3775414347 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.432367501 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1023494233 ps |
| CPU time | 12.82 seconds |
| Started | Jan 03 12:39:46 PM PST 24 |
| Finished | Jan 03 12:41:32 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-3ac6f0c6-e42b-45cd-9a6a-746c58571aba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=432367501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.432367501 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.3609355304 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 59193857 ps |
| CPU time | 1.25 seconds |
| Started | Jan 03 12:39:24 PM PST 24 |
| Finished | Jan 03 12:41:07 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-48410709-7867-4814-b902-2091feeeb7e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3609355304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3609355304 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2407431450 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 742148709 ps |
| CPU time | 5.79 seconds |
| Started | Jan 03 12:39:24 PM PST 24 |
| Finished | Jan 03 12:41:10 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-67ae7669-f6f2-4c0d-9a72-a59f5e33608a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2407431450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2407431450 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.4151543661 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 10806670 ps |
| CPU time | 1.25 seconds |
| Started | Jan 03 12:39:04 PM PST 24 |
| Finished | Jan 03 12:40:20 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-e6f78e5a-9d12-4be5-9706-6efc9c5eef8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151543661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.4151543661 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.1951045948 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 4981114892 ps |
| CPU time | 61.45 seconds |
| Started | Jan 03 12:39:37 PM PST 24 |
| Finished | Jan 03 12:42:10 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-d50435ed-b0d1-48fd-959e-caedffcf90b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1951045948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1951045948 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.445865873 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 61931921 ps |
| CPU time | 6.97 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:41:12 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-7ddcaa21-737e-488f-b7c2-ccc3c7a08ee0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=445865873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.445865873 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3718211199 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 5725146475 ps |
| CPU time | 72.22 seconds |
| Started | Jan 03 12:40:23 PM PST 24 |
| Finished | Jan 03 12:43:00 PM PST 24 |
| Peak memory | 204396 kb |
| Host | smart-5eeefda9-8c69-41d9-816c-44ef132b6add |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3718211199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.3718211199 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.2534298318 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 18880102 ps |
| CPU time | 2.11 seconds |
| Started | Jan 03 12:39:24 PM PST 24 |
| Finished | Jan 03 12:41:11 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-f1f46667-d10e-4408-b35c-f4cf0606f614 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2534298318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2534298318 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.794028771 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 21161835 ps |
| CPU time | 3.11 seconds |
| Started | Jan 03 12:39:40 PM PST 24 |
| Finished | Jan 03 12:41:18 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-653e3e1f-110b-49f6-9ee5-ad9ae978a427 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=794028771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.794028771 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2855476370 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 37357451322 ps |
| CPU time | 97.55 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:42:55 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-739fd025-e35b-4387-a5db-16a85a6aaf18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2855476370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.2855476370 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.4210945243 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 48155779 ps |
| CPU time | 3.41 seconds |
| Started | Jan 03 12:39:09 PM PST 24 |
| Finished | Jan 03 12:40:49 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-6a14db91-8469-4a4c-8958-decf7a60de1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4210945243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.4210945243 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.1098473527 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 402143667 ps |
| CPU time | 5.72 seconds |
| Started | Jan 03 12:39:34 PM PST 24 |
| Finished | Jan 03 12:40:58 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-65b96d65-89a5-4814-9577-41be0ce45b95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1098473527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1098473527 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.39428533 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 275598821 ps |
| CPU time | 5.63 seconds |
| Started | Jan 03 12:42:49 PM PST 24 |
| Finished | Jan 03 12:44:30 PM PST 24 |
| Peak memory | 200920 kb |
| Host | smart-643d4d34-a925-4cf4-8a71-6a207b49d377 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=39428533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.39428533 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.2722122871 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 82804364161 ps |
| CPU time | 174.52 seconds |
| Started | Jan 03 12:39:29 PM PST 24 |
| Finished | Jan 03 12:43:41 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-2f182065-d401-4f55-91bb-d57614d62c25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722122871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2722122871 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1428445856 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2745215966 ps |
| CPU time | 21.56 seconds |
| Started | Jan 03 12:40:03 PM PST 24 |
| Finished | Jan 03 12:42:03 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-e33d780d-10eb-4c9d-b5dc-c0c0a02e04bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1428445856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1428445856 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.4207269700 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 37670009 ps |
| CPU time | 2.63 seconds |
| Started | Jan 03 12:40:46 PM PST 24 |
| Finished | Jan 03 12:42:17 PM PST 24 |
| Peak memory | 201000 kb |
| Host | smart-83c071bf-d48a-4a11-b2f2-41e964caa1ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207269700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.4207269700 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.4172162189 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 870259768 ps |
| CPU time | 6.17 seconds |
| Started | Jan 03 12:39:06 PM PST 24 |
| Finished | Jan 03 12:40:28 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-d5f308fc-3a2d-4f5c-8b73-da5a11c84031 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4172162189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.4172162189 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.2523988461 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 8370733 ps |
| CPU time | 1.03 seconds |
| Started | Jan 03 12:39:31 PM PST 24 |
| Finished | Jan 03 12:41:13 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-084a8794-156c-4260-9f03-95ed6fd842cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2523988461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2523988461 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2617436223 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2835520190 ps |
| CPU time | 7.3 seconds |
| Started | Jan 03 12:40:42 PM PST 24 |
| Finished | Jan 03 12:42:17 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-008f764a-b811-4e59-a535-ab38d384a182 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617436223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2617436223 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.895558456 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1722364221 ps |
| CPU time | 5.87 seconds |
| Started | Jan 03 12:39:10 PM PST 24 |
| Finished | Jan 03 12:40:36 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-f9876401-38cf-47f7-b7c9-b3dc1e6d1831 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=895558456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.895558456 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3630586943 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 15191668 ps |
| CPU time | 1.08 seconds |
| Started | Jan 03 12:39:39 PM PST 24 |
| Finished | Jan 03 12:41:05 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-6d8d5e57-099a-4339-963f-eaf6818c67db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630586943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3630586943 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3843838356 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 316638511 ps |
| CPU time | 25.08 seconds |
| Started | Jan 03 12:43:28 PM PST 24 |
| Finished | Jan 03 12:45:40 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-ab1aa0bb-ea8f-41b5-858b-7fc27d5e8f01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3843838356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3843838356 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3463527387 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 137794232 ps |
| CPU time | 8.88 seconds |
| Started | Jan 03 12:39:09 PM PST 24 |
| Finished | Jan 03 12:40:39 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-01e204a1-a29f-4620-8ab6-a5dbbb26daf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3463527387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3463527387 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3530281620 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 5730534133 ps |
| CPU time | 115.79 seconds |
| Started | Jan 03 12:39:26 PM PST 24 |
| Finished | Jan 03 12:42:48 PM PST 24 |
| Peak memory | 205892 kb |
| Host | smart-6ce3faa5-b7f2-4dad-9416-d5dd0b5d8294 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3530281620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.3530281620 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2985386496 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1475183841 ps |
| CPU time | 56.17 seconds |
| Started | Jan 03 12:39:34 PM PST 24 |
| Finished | Jan 03 12:41:49 PM PST 24 |
| Peak memory | 202784 kb |
| Host | smart-77e388b7-7197-47ae-b43b-6a0e30d50971 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2985386496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.2985386496 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1074040411 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 204430868 ps |
| CPU time | 4.12 seconds |
| Started | Jan 03 12:39:08 PM PST 24 |
| Finished | Jan 03 12:40:30 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-bdf04f2c-0cfe-45cd-b2b4-789f39a605cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1074040411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1074040411 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.1814667387 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 469794966 ps |
| CPU time | 9.39 seconds |
| Started | Jan 03 12:39:18 PM PST 24 |
| Finished | Jan 03 12:40:53 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-eb04062c-36e8-4f79-9378-826aa90a1347 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1814667387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1814667387 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3777496326 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 95475413094 ps |
| CPU time | 240.01 seconds |
| Started | Jan 03 12:39:28 PM PST 24 |
| Finished | Jan 03 12:44:48 PM PST 24 |
| Peak memory | 202840 kb |
| Host | smart-ff306429-e6b4-42ba-8264-fe8d29f60f83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3777496326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.3777496326 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2774699577 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 609400108 ps |
| CPU time | 9.95 seconds |
| Started | Jan 03 12:40:39 PM PST 24 |
| Finished | Jan 03 12:42:18 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-ac2c46a9-39d9-44d2-9058-e8b47c751a4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2774699577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2774699577 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.587437942 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 565732940 ps |
| CPU time | 7.31 seconds |
| Started | Jan 03 12:39:18 PM PST 24 |
| Finished | Jan 03 12:40:51 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-8083296a-a271-40f9-ad6f-6893d3f4c38f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=587437942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.587437942 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.1576201768 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 873569976 ps |
| CPU time | 11.09 seconds |
| Started | Jan 03 12:39:46 PM PST 24 |
| Finished | Jan 03 12:41:30 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-99fec10a-7269-4f6a-a926-0a087e0f1464 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1576201768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1576201768 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3450885535 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 35728772469 ps |
| CPU time | 110.98 seconds |
| Started | Jan 03 12:39:22 PM PST 24 |
| Finished | Jan 03 12:42:30 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-076b0760-bfff-4aca-a825-830494c599d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450885535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3450885535 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.528941133 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 5369648341 ps |
| CPU time | 15.73 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:41:26 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-d963af08-3e77-4782-9aaa-d795e0898764 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=528941133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.528941133 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.335435549 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 17352093 ps |
| CPU time | 1.57 seconds |
| Started | Jan 03 12:39:54 PM PST 24 |
| Finished | Jan 03 12:41:57 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-c4799974-5461-4edc-ac5c-c75274c5f22f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335435549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.335435549 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.590416041 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 689639972 ps |
| CPU time | 2.77 seconds |
| Started | Jan 03 12:39:26 PM PST 24 |
| Finished | Jan 03 12:40:49 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-b5129f55-9862-4fd6-933d-40d41737a2d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=590416041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.590416041 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.2455553084 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 84584900 ps |
| CPU time | 1.57 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:41:09 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-40f07542-7f9d-4f18-80cf-651c20bc5be0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2455553084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2455553084 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.3839877523 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 14640261427 ps |
| CPU time | 8.16 seconds |
| Started | Jan 03 12:40:15 PM PST 24 |
| Finished | Jan 03 12:41:49 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-345f87ae-4a8d-4d90-8279-66bb084883d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839877523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3839877523 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2463788032 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 12864530 ps |
| CPU time | 1.07 seconds |
| Started | Jan 03 12:39:58 PM PST 24 |
| Finished | Jan 03 12:41:32 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-e2dd7e98-a3ed-45fc-86ee-3fa0a8dd0a14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463788032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2463788032 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.3802799879 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 12639968746 ps |
| CPU time | 61.91 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:42:42 PM PST 24 |
| Peak memory | 202348 kb |
| Host | smart-908c157c-a85e-4b92-8ed0-5799a806a7d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3802799879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3802799879 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1595459358 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 150289714 ps |
| CPU time | 14.58 seconds |
| Started | Jan 03 12:40:20 PM PST 24 |
| Finished | Jan 03 12:42:02 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-0e6b4208-7a4b-4cf9-8599-708991479a98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1595459358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1595459358 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2976871997 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 758598365 ps |
| CPU time | 75.13 seconds |
| Started | Jan 03 12:39:14 PM PST 24 |
| Finished | Jan 03 12:41:51 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-f46935dc-7221-4d73-a740-dda220244cb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2976871997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.2976871997 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.4079685077 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 3788793409 ps |
| CPU time | 43.34 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:42:08 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-d14e1c46-a91f-47aa-a221-1e21dc7afcae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4079685077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.4079685077 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.4180862318 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 49149339 ps |
| CPU time | 4.17 seconds |
| Started | Jan 03 12:39:24 PM PST 24 |
| Finished | Jan 03 12:41:10 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-35323f86-fec4-4b72-b228-0b310397e6d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4180862318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.4180862318 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.390164901 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 99437317 ps |
| CPU time | 3.03 seconds |
| Started | Jan 03 12:39:50 PM PST 24 |
| Finished | Jan 03 12:41:18 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-77bb5193-4a70-494f-b8f8-89be2125a633 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=390164901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.390164901 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.968405308 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 53778447998 ps |
| CPU time | 188.89 seconds |
| Started | Jan 03 12:39:20 PM PST 24 |
| Finished | Jan 03 12:43:50 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-0c0676bf-cffc-4621-9242-3495d247f4a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=968405308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slo w_rsp.968405308 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.4013671708 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 36369183 ps |
| CPU time | 3.94 seconds |
| Started | Jan 03 12:39:41 PM PST 24 |
| Finished | Jan 03 12:41:06 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-849595fe-be5f-4f0f-a441-0630d408a045 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4013671708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.4013671708 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.2864899302 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 3206335403 ps |
| CPU time | 11.23 seconds |
| Started | Jan 03 12:39:31 PM PST 24 |
| Finished | Jan 03 12:41:13 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-351bd04a-9ae7-4436-abe8-213c1140bab5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2864899302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2864899302 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.1228103047 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1553399216 ps |
| CPU time | 13.13 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:41:28 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-9f810814-bce3-47a8-bb53-ce4d2222f7e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1228103047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1228103047 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.1576998322 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10702367482 ps |
| CPU time | 46.82 seconds |
| Started | Jan 03 12:39:32 PM PST 24 |
| Finished | Jan 03 12:41:46 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-29f92e65-7830-4336-9894-2fa118492b6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576998322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1576998322 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.215334134 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 37109637215 ps |
| CPU time | 70.72 seconds |
| Started | Jan 03 12:39:23 PM PST 24 |
| Finished | Jan 03 12:42:03 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-8bb7cd67-e460-4ed5-82fe-667d18782f93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=215334134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.215334134 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2065998448 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 53227795 ps |
| CPU time | 6.4 seconds |
| Started | Jan 03 12:40:00 PM PST 24 |
| Finished | Jan 03 12:42:01 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-e343c90f-8dab-48a7-8b44-54cdf3cc98c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065998448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2065998448 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.2623289012 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3276212618 ps |
| CPU time | 9.93 seconds |
| Started | Jan 03 12:39:29 PM PST 24 |
| Finished | Jan 03 12:41:01 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-79f44cb4-f05f-431c-962b-c54c3bdf7bee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2623289012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2623289012 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.2263940486 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 8838960 ps |
| CPU time | 1.07 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:41:41 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-b152d636-bcd4-41fb-8a8c-9ee1741ae73e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2263940486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2263940486 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3129057612 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3665928003 ps |
| CPU time | 11.72 seconds |
| Started | Jan 03 12:39:22 PM PST 24 |
| Finished | Jan 03 12:40:55 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-68407fe6-3b55-4184-942e-f92a80b892fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129057612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3129057612 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.203781708 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 3994353608 ps |
| CPU time | 9.19 seconds |
| Started | Jan 03 12:39:28 PM PST 24 |
| Finished | Jan 03 12:40:53 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-898b809d-a724-4450-901d-999acb2dfce8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=203781708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.203781708 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2320917920 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 12248199 ps |
| CPU time | 1.18 seconds |
| Started | Jan 03 12:39:23 PM PST 24 |
| Finished | Jan 03 12:40:53 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-33ea8126-4f3a-404d-8042-b643666460a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320917920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2320917920 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.2917539332 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2525857365 ps |
| CPU time | 31.8 seconds |
| Started | Jan 03 12:40:12 PM PST 24 |
| Finished | Jan 03 12:42:14 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-eede9e33-e638-49d3-9866-ba44b4eabd75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2917539332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2917539332 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.2098645928 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3045847479 ps |
| CPU time | 36.45 seconds |
| Started | Jan 03 12:39:47 PM PST 24 |
| Finished | Jan 03 12:42:08 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-e33f96b3-388f-4c15-b410-f9dcbdd1dd82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2098645928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2098645928 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3404917016 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 939158576 ps |
| CPU time | 82.94 seconds |
| Started | Jan 03 12:39:41 PM PST 24 |
| Finished | Jan 03 12:42:25 PM PST 24 |
| Peak memory | 203980 kb |
| Host | smart-a53dc99c-645f-41fd-8780-174b6600d728 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3404917016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.3404917016 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1311625168 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2373131223 ps |
| CPU time | 9.48 seconds |
| Started | Jan 03 12:39:34 PM PST 24 |
| Finished | Jan 03 12:41:02 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-64ff097c-c724-44be-b40c-07569b461a31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1311625168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1311625168 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.790249412 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 37090579648 ps |
| CPU time | 231.11 seconds |
| Started | Jan 03 12:40:05 PM PST 24 |
| Finished | Jan 03 12:45:20 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-eed3cab6-4150-4751-b62a-29a1e342e75d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=790249412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slo w_rsp.790249412 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2489713334 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 208429304 ps |
| CPU time | 4.45 seconds |
| Started | Jan 03 12:40:06 PM PST 24 |
| Finished | Jan 03 12:41:38 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-9cb56ee8-ec62-4025-998f-e3b00932e9ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2489713334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2489713334 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.1901083332 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 750100680 ps |
| CPU time | 10.41 seconds |
| Started | Jan 03 12:40:04 PM PST 24 |
| Finished | Jan 03 12:42:02 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-8153c8fa-ecf7-4723-8b24-62a8fc6b3dc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1901083332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1901083332 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.3476043490 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 66050107544 ps |
| CPU time | 148.92 seconds |
| Started | Jan 03 12:40:33 PM PST 24 |
| Finished | Jan 03 12:44:27 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-e5ce97d6-6f52-4b88-bdd7-8b04d0410ad4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476043490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3476043490 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3867446748 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 189153413993 ps |
| CPU time | 185.09 seconds |
| Started | Jan 03 12:39:40 PM PST 24 |
| Finished | Jan 03 12:44:29 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-07ed6f8d-a4f4-4b40-8c8f-5b82e17f6d3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3867446748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3867446748 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.2234158397 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 71738257 ps |
| CPU time | 2.91 seconds |
| Started | Jan 03 12:39:38 PM PST 24 |
| Finished | Jan 03 12:41:04 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-e10fb19c-1e9b-4cea-b033-885d04b06ba7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234158397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.2234158397 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.494092953 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 108041836 ps |
| CPU time | 1.66 seconds |
| Started | Jan 03 12:39:20 PM PST 24 |
| Finished | Jan 03 12:40:49 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-4a7ad94f-2e08-4ba2-bdf0-092ea326f22b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=494092953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.494092953 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.3348115894 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 57078413 ps |
| CPU time | 1.23 seconds |
| Started | Jan 03 12:39:49 PM PST 24 |
| Finished | Jan 03 12:41:22 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-de119514-4aaf-4c43-b0d0-aaa93415ccf4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3348115894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3348115894 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3165306214 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 3286715354 ps |
| CPU time | 10.71 seconds |
| Started | Jan 03 12:40:32 PM PST 24 |
| Finished | Jan 03 12:42:19 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-d402c7a5-d8d8-4a6e-968b-2aa516741b68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165306214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3165306214 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.4249768984 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 794038621 ps |
| CPU time | 4.55 seconds |
| Started | Jan 03 12:39:39 PM PST 24 |
| Finished | Jan 03 12:41:11 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-3515557d-4d09-4c5c-89fc-a82b9f417259 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4249768984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.4249768984 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3546178938 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 9895876 ps |
| CPU time | 1.09 seconds |
| Started | Jan 03 12:39:30 PM PST 24 |
| Finished | Jan 03 12:40:51 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-dd0ccb10-ecea-4fb0-8869-6694fe382309 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546178938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3546178938 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.849128255 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 15415127963 ps |
| CPU time | 94.81 seconds |
| Started | Jan 03 12:39:30 PM PST 24 |
| Finished | Jan 03 12:42:31 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-92f282b5-1b14-4eab-9266-4a38ef45c0fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=849128255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.849128255 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3917256405 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 210629169 ps |
| CPU time | 12.56 seconds |
| Started | Jan 03 12:40:24 PM PST 24 |
| Finished | Jan 03 12:42:09 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-fd42251f-a208-41d6-be25-dc0a6adbfebd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3917256405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.3917256405 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1762095213 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4367932445 ps |
| CPU time | 107.5 seconds |
| Started | Jan 03 12:39:57 PM PST 24 |
| Finished | Jan 03 12:43:45 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-8eb5d463-95f6-4624-9baf-6573166e6d43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1762095213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.1762095213 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.4049115802 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 16279720 ps |
| CPU time | 1.32 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:41:55 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-878a214c-c155-40da-971e-1681db0ee10f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4049115802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.4049115802 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.3905476578 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 240207918 ps |
| CPU time | 3.76 seconds |
| Started | Jan 03 12:39:55 PM PST 24 |
| Finished | Jan 03 12:41:24 PM PST 24 |
| Peak memory | 201228 kb |
| Host | smart-634abe74-41df-4136-9a4d-e5ecce2a6fb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3905476578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3905476578 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1127444956 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 82928522448 ps |
| CPU time | 326.73 seconds |
| Started | Jan 03 12:39:34 PM PST 24 |
| Finished | Jan 03 12:46:23 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-837685a8-b306-4856-980a-4265348a5e20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1127444956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.1127444956 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.220185537 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 522994881 ps |
| CPU time | 7.5 seconds |
| Started | Jan 03 12:39:43 PM PST 24 |
| Finished | Jan 03 12:42:01 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-e4b0c893-12ad-460e-9599-4278f42f4e82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=220185537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.220185537 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.3582389694 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 23071827 ps |
| CPU time | 2.08 seconds |
| Started | Jan 03 12:39:19 PM PST 24 |
| Finished | Jan 03 12:40:41 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-ffc609e8-48d8-49d0-a597-b61b73c4c241 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3582389694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3582389694 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1979518339 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 38060376304 ps |
| CPU time | 124.59 seconds |
| Started | Jan 03 12:39:51 PM PST 24 |
| Finished | Jan 03 12:43:28 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-61d88f44-992c-41ba-a299-a419a80bd1f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979518339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1979518339 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3034818197 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 5099907377 ps |
| CPU time | 20.67 seconds |
| Started | Jan 03 12:39:34 PM PST 24 |
| Finished | Jan 03 12:41:19 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-8e99edb2-3e0a-46c8-a6f6-c0bae52e2a9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3034818197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3034818197 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1656720659 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 153661067 ps |
| CPU time | 3.98 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:41:09 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-8abc3d15-dd11-4fe4-b451-2a31dcb53ed7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656720659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1656720659 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.1685161448 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 60629843 ps |
| CPU time | 1.28 seconds |
| Started | Jan 03 12:39:34 PM PST 24 |
| Finished | Jan 03 12:41:00 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-26b9dbbd-d352-4b14-aaf1-efb2a6bfdc9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1685161448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1685161448 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2094905603 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 4991837152 ps |
| CPU time | 10.75 seconds |
| Started | Jan 03 12:39:26 PM PST 24 |
| Finished | Jan 03 12:40:55 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-7d2c4c70-0267-4bbe-a0e4-1c0018a31243 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094905603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2094905603 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1724679527 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1370960870 ps |
| CPU time | 10.59 seconds |
| Started | Jan 03 12:39:21 PM PST 24 |
| Finished | Jan 03 12:41:30 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-e106c045-ed85-4d8c-a7c3-460e01c166d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1724679527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1724679527 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.4180462357 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 493365273 ps |
| CPU time | 34.14 seconds |
| Started | Jan 03 12:39:51 PM PST 24 |
| Finished | Jan 03 12:41:55 PM PST 24 |
| Peak memory | 204040 kb |
| Host | smart-8462871a-6635-4a85-a418-2deadf47fbcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4180462357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.4180462357 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3775084170 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 186646009 ps |
| CPU time | 3.08 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:41:42 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-912c15e2-14a8-4c76-b30a-2e5b27e71002 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3775084170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3775084170 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.4187892209 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 424202471 ps |
| CPU time | 33.07 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:41:41 PM PST 24 |
| Peak memory | 203572 kb |
| Host | smart-bb0019c5-2698-458c-985c-aca826a4f478 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4187892209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.4187892209 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2014270784 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 416814725 ps |
| CPU time | 52.85 seconds |
| Started | Jan 03 12:40:04 PM PST 24 |
| Finished | Jan 03 12:42:49 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-97076c59-1eae-4461-859c-ffe8e25a66e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2014270784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.2014270784 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.741520674 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 748519395 ps |
| CPU time | 9.92 seconds |
| Started | Jan 03 12:39:21 PM PST 24 |
| Finished | Jan 03 12:40:57 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-f0ebc3d6-8377-4c16-8bca-ad12ae78cf04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=741520674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.741520674 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.448974810 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2256453736 ps |
| CPU time | 15.87 seconds |
| Started | Jan 03 12:39:40 PM PST 24 |
| Finished | Jan 03 12:41:28 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-ffff166a-34e4-4362-8bcc-61d3e3c1a6fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=448974810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.448974810 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.882277079 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 17802533036 ps |
| CPU time | 98.03 seconds |
| Started | Jan 03 12:39:53 PM PST 24 |
| Finished | Jan 03 12:42:57 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-a0b3608f-76de-4282-98e1-e0ac74314a8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=882277079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo w_rsp.882277079 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.1003396811 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 30586518 ps |
| CPU time | 2.15 seconds |
| Started | Jan 03 12:39:44 PM PST 24 |
| Finished | Jan 03 12:41:13 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-9b7c9c61-6169-4846-a1d3-d5cd055fbd94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1003396811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1003396811 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.485272848 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 934986075 ps |
| CPU time | 8.12 seconds |
| Started | Jan 03 12:40:09 PM PST 24 |
| Finished | Jan 03 12:41:43 PM PST 24 |
| Peak memory | 201304 kb |
| Host | smart-c4fb76b1-ac87-4f20-8e68-628120b9408b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=485272848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.485272848 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1635340348 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 41938327330 ps |
| CPU time | 161.35 seconds |
| Started | Jan 03 12:40:19 PM PST 24 |
| Finished | Jan 03 12:44:25 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-3a5f78ef-444a-4776-bfe4-b4db1934f787 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635340348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1635340348 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1546167401 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 43268770764 ps |
| CPU time | 84.12 seconds |
| Started | Jan 03 12:39:55 PM PST 24 |
| Finished | Jan 03 12:42:44 PM PST 24 |
| Peak memory | 201292 kb |
| Host | smart-fa3c7491-430c-4e36-b503-37e15589cbec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1546167401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1546167401 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2738723699 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 126749904 ps |
| CPU time | 4.74 seconds |
| Started | Jan 03 12:39:55 PM PST 24 |
| Finished | Jan 03 12:41:23 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-aa0c8b92-5b6f-417d-93d9-48d39e9c46bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738723699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2738723699 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.3390721805 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 942875079 ps |
| CPU time | 3.49 seconds |
| Started | Jan 03 12:40:04 PM PST 24 |
| Finished | Jan 03 12:41:59 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-3106c34b-e1fb-4ece-81d3-20a84b698aeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3390721805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3390721805 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.1097630360 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 10439470 ps |
| CPU time | 1.06 seconds |
| Started | Jan 03 12:40:01 PM PST 24 |
| Finished | Jan 03 12:41:32 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-a2a017fa-5e87-40de-8b69-49e99cf1569d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1097630360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1097630360 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.4147017027 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 10198047310 ps |
| CPU time | 9.47 seconds |
| Started | Jan 03 12:39:50 PM PST 24 |
| Finished | Jan 03 12:41:28 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-5dbc7b04-cc4b-44f9-bfcd-9d3ef082b3c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147017027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.4147017027 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1552912818 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1392197870 ps |
| CPU time | 8.26 seconds |
| Started | Jan 03 12:40:25 PM PST 24 |
| Finished | Jan 03 12:42:19 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-270ea7df-440c-44e0-b9fe-1b226563a604 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1552912818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1552912818 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3876117799 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 10163453 ps |
| CPU time | 1.14 seconds |
| Started | Jan 03 12:40:23 PM PST 24 |
| Finished | Jan 03 12:41:50 PM PST 24 |
| Peak memory | 201288 kb |
| Host | smart-c7437ea7-0366-4e51-96be-22686b75111b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876117799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3876117799 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3495168781 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4023916446 ps |
| CPU time | 72.49 seconds |
| Started | Jan 03 12:39:52 PM PST 24 |
| Finished | Jan 03 12:42:36 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-3df9b4f9-1bcb-488f-bca5-1b577c27267c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3495168781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3495168781 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.308917763 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 74131889 ps |
| CPU time | 9.19 seconds |
| Started | Jan 03 12:40:33 PM PST 24 |
| Finished | Jan 03 12:42:09 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-4c986c6c-68db-4be0-96ce-e947d1436a28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=308917763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.308917763 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.3373631543 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 353587411 ps |
| CPU time | 43.78 seconds |
| Started | Jan 03 12:39:57 PM PST 24 |
| Finished | Jan 03 12:42:04 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-d853980f-0539-46bf-8ebb-c1205a0347ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3373631543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.3373631543 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1235109616 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2802298111 ps |
| CPU time | 47.87 seconds |
| Started | Jan 03 12:39:48 PM PST 24 |
| Finished | Jan 03 12:41:55 PM PST 24 |
| Peak memory | 203324 kb |
| Host | smart-84bacd50-e70c-4c2a-8e5f-14c2679685ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1235109616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.1235109616 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2911576459 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 80755488 ps |
| CPU time | 5.2 seconds |
| Started | Jan 03 12:40:01 PM PST 24 |
| Finished | Jan 03 12:41:28 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-7d4a41f6-195d-404c-8490-cb092e1c738e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2911576459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2911576459 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.4172476785 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9097544825 ps |
| CPU time | 21.21 seconds |
| Started | Jan 03 12:40:14 PM PST 24 |
| Finished | Jan 03 12:42:17 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-bebebac0-e9ee-4905-b73b-dbd53cebe3be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4172476785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.4172476785 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1797368978 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 605178723 ps |
| CPU time | 8.12 seconds |
| Started | Jan 03 12:39:58 PM PST 24 |
| Finished | Jan 03 12:41:28 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-3ceb5a27-f633-4b1b-a9da-39ab29792727 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1797368978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1797368978 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.226669047 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 77414739 ps |
| CPU time | 5.3 seconds |
| Started | Jan 03 12:40:09 PM PST 24 |
| Finished | Jan 03 12:41:41 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-72530407-fa6f-4c8d-a440-8472072ba2a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=226669047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.226669047 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.3790841081 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 523312167 ps |
| CPU time | 8.07 seconds |
| Started | Jan 03 12:40:03 PM PST 24 |
| Finished | Jan 03 12:41:54 PM PST 24 |
| Peak memory | 201304 kb |
| Host | smart-3d16d496-e7aa-4b1b-8b4d-418f18e46d58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3790841081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3790841081 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.420425534 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 22108784319 ps |
| CPU time | 95.36 seconds |
| Started | Jan 03 12:40:04 PM PST 24 |
| Finished | Jan 03 12:43:03 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-c60ecf91-5b59-46c9-879d-609969106efd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=420425534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.420425534 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1631362698 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 21111027189 ps |
| CPU time | 52.93 seconds |
| Started | Jan 03 12:40:20 PM PST 24 |
| Finished | Jan 03 12:42:50 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-bca6fac0-7303-4b9f-8c37-24a3bd90d1af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1631362698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1631362698 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.25659648 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 71394804 ps |
| CPU time | 6.37 seconds |
| Started | Jan 03 12:39:55 PM PST 24 |
| Finished | Jan 03 12:41:24 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-c13b386c-fc9e-450f-9e9d-554a60d0880f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25659648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.25659648 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.2393340445 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1377046320 ps |
| CPU time | 11.19 seconds |
| Started | Jan 03 12:40:02 PM PST 24 |
| Finished | Jan 03 12:41:42 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-a4b0fa34-bbaf-4a4d-b953-d4c826f60ca7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2393340445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2393340445 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.3386838122 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 82630395 ps |
| CPU time | 1.16 seconds |
| Started | Jan 03 12:39:55 PM PST 24 |
| Finished | Jan 03 12:41:25 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-8b553997-594e-49dd-bb64-a2e4a56f67de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3386838122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3386838122 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1969967174 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1805676390 ps |
| CPU time | 8.6 seconds |
| Started | Jan 03 12:40:21 PM PST 24 |
| Finished | Jan 03 12:42:09 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-7f29bc01-d8ef-439e-b8bf-32be25836ed8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969967174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1969967174 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.4040623809 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1298565518 ps |
| CPU time | 5.51 seconds |
| Started | Jan 03 12:39:59 PM PST 24 |
| Finished | Jan 03 12:41:35 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-c35e8870-a149-49ba-9774-e666e3ed6d94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4040623809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.4040623809 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.875976626 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 18801858 ps |
| CPU time | 1.02 seconds |
| Started | Jan 03 12:39:41 PM PST 24 |
| Finished | Jan 03 12:41:22 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-9fa81e20-306c-4e73-9898-6ba7f3c22e2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875976626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.875976626 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3767584093 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 865257125 ps |
| CPU time | 31.89 seconds |
| Started | Jan 03 12:39:58 PM PST 24 |
| Finished | Jan 03 12:41:52 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-364096eb-f2e7-4801-8f04-5ee81741b17c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3767584093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3767584093 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2659228520 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 95660904 ps |
| CPU time | 7.79 seconds |
| Started | Jan 03 12:40:32 PM PST 24 |
| Finished | Jan 03 12:42:13 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-3e0be023-abca-4c97-8508-bcad7f9be330 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2659228520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2659228520 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3027704024 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 612149530 ps |
| CPU time | 64.58 seconds |
| Started | Jan 03 12:39:57 PM PST 24 |
| Finished | Jan 03 12:42:50 PM PST 24 |
| Peak memory | 204080 kb |
| Host | smart-7332c697-a911-4348-93a1-832740bad63d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3027704024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.3027704024 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3993105132 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 57284465 ps |
| CPU time | 5.79 seconds |
| Started | Jan 03 12:40:17 PM PST 24 |
| Finished | Jan 03 12:41:51 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-89e0958e-94a9-4155-9e9a-f3a41c160596 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3993105132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3993105132 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1883359680 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 39391105 ps |
| CPU time | 7.63 seconds |
| Started | Jan 03 12:40:02 PM PST 24 |
| Finished | Jan 03 12:41:31 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-dd8c4442-2e60-435d-a772-4fcf836cadef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1883359680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1883359680 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.886065404 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 53775298900 ps |
| CPU time | 191.2 seconds |
| Started | Jan 03 12:40:05 PM PST 24 |
| Finished | Jan 03 12:44:40 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-d06566da-3ecd-4f7b-9155-08c3087034cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=886065404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slo w_rsp.886065404 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3484723153 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2768675500 ps |
| CPU time | 10.27 seconds |
| Started | Jan 03 12:40:20 PM PST 24 |
| Finished | Jan 03 12:41:59 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-77f246ae-bec7-449b-8e7c-4dc6bb4a625f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3484723153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3484723153 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2455016665 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 998972627 ps |
| CPU time | 12.3 seconds |
| Started | Jan 03 12:39:56 PM PST 24 |
| Finished | Jan 03 12:41:42 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-cd00dfbf-cf13-42c7-a615-ff0e7250150f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2455016665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2455016665 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.3944799406 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 28168139 ps |
| CPU time | 2.21 seconds |
| Started | Jan 03 12:40:30 PM PST 24 |
| Finished | Jan 03 12:41:58 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-91c5acb4-a8d6-4537-9169-f4ef529393e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3944799406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3944799406 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.2751061721 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 225236582262 ps |
| CPU time | 152.45 seconds |
| Started | Jan 03 12:39:55 PM PST 24 |
| Finished | Jan 03 12:44:02 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-e8ba0b50-648f-4cf1-8204-38d0621c2a09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751061721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2751061721 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.595460355 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 27415733941 ps |
| CPU time | 164.9 seconds |
| Started | Jan 03 12:40:19 PM PST 24 |
| Finished | Jan 03 12:44:42 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-d73dac78-a0f8-427f-abd2-e37cce2b7867 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=595460355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.595460355 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.455722700 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 40596018 ps |
| CPU time | 3.46 seconds |
| Started | Jan 03 12:39:53 PM PST 24 |
| Finished | Jan 03 12:41:28 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-948c968d-bb43-400c-9aca-2e7f61165134 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455722700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.455722700 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.1139773823 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1008145247 ps |
| CPU time | 12.36 seconds |
| Started | Jan 03 12:40:18 PM PST 24 |
| Finished | Jan 03 12:41:55 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-7187096e-81b7-43d9-82b5-71bdd1309de4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1139773823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1139773823 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.2873649189 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 18247865 ps |
| CPU time | 1.22 seconds |
| Started | Jan 03 12:40:03 PM PST 24 |
| Finished | Jan 03 12:41:43 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-52560d77-0ab3-408f-b964-fa74b4263f54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2873649189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2873649189 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.179725026 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1420960032 ps |
| CPU time | 7.27 seconds |
| Started | Jan 03 12:39:48 PM PST 24 |
| Finished | Jan 03 12:41:29 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-18d84f82-2743-4f4c-bb24-d994705e0806 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=179725026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.179725026 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1127213102 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 16161757958 ps |
| CPU time | 13.18 seconds |
| Started | Jan 03 12:39:52 PM PST 24 |
| Finished | Jan 03 12:41:35 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-00572ae1-5a23-485b-98f8-6dbdac1b10fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1127213102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1127213102 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3850326952 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 11884135 ps |
| CPU time | 1.07 seconds |
| Started | Jan 03 12:40:39 PM PST 24 |
| Finished | Jan 03 12:42:09 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-5f6587cb-fd90-4886-adbf-91ba065ea1f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850326952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3850326952 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.1703302735 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 499560302 ps |
| CPU time | 37.28 seconds |
| Started | Jan 03 12:39:57 PM PST 24 |
| Finished | Jan 03 12:42:09 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-2611372b-74a1-4d4e-b1ed-c1166e4324fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1703302735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1703302735 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1218090330 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1074626308 ps |
| CPU time | 30.32 seconds |
| Started | Jan 03 12:39:50 PM PST 24 |
| Finished | Jan 03 12:41:51 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-165461ad-6b21-479b-a502-22b66ac37579 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1218090330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1218090330 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2191159886 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 43111057 ps |
| CPU time | 12.06 seconds |
| Started | Jan 03 12:40:41 PM PST 24 |
| Finished | Jan 03 12:42:22 PM PST 24 |
| Peak memory | 201300 kb |
| Host | smart-b7c624bc-e3c9-4c3f-900f-366a46a61aed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2191159886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.2191159886 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.75833137 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 3744864071 ps |
| CPU time | 69.06 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:42:25 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-4068d726-78cd-40f0-9dca-3e8ac393790a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=75833137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rese t_error.75833137 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.2187980141 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 24566650 ps |
| CPU time | 2.4 seconds |
| Started | Jan 03 12:40:09 PM PST 24 |
| Finished | Jan 03 12:41:35 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-a5b54916-8c7a-4f85-af7c-a640981c2bc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2187980141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2187980141 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3321021358 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 208573187 ps |
| CPU time | 2.8 seconds |
| Started | Jan 03 12:40:02 PM PST 24 |
| Finished | Jan 03 12:41:26 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-9a0b5776-f574-483f-af7d-9511395542bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3321021358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3321021358 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1140100191 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 26888701585 ps |
| CPU time | 206.55 seconds |
| Started | Jan 03 12:40:32 PM PST 24 |
| Finished | Jan 03 12:45:35 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-b994d9f0-35d8-496d-ad8a-56e37e9e9b27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1140100191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.1140100191 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1653037477 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 96593968 ps |
| CPU time | 5.32 seconds |
| Started | Jan 03 12:39:49 PM PST 24 |
| Finished | Jan 03 12:41:20 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-6d8e7680-8d69-47fd-a4b9-57b0681b42b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1653037477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1653037477 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.4231633382 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 290139384 ps |
| CPU time | 3.2 seconds |
| Started | Jan 03 12:39:53 PM PST 24 |
| Finished | Jan 03 12:41:22 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-2690d023-6d30-4b0a-800c-805237589309 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4231633382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.4231633382 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.1005499059 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 23946287 ps |
| CPU time | 3.06 seconds |
| Started | Jan 03 12:39:51 PM PST 24 |
| Finished | Jan 03 12:41:23 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-d477cc34-eb75-4d1e-a403-1b25bd988764 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1005499059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1005499059 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.593100798 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 34627369643 ps |
| CPU time | 161.67 seconds |
| Started | Jan 03 12:40:37 PM PST 24 |
| Finished | Jan 03 12:44:45 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-7915d45a-550c-40c8-98c3-5fe93ac1bb1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=593100798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.593100798 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.137983402 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 70512805581 ps |
| CPU time | 115.24 seconds |
| Started | Jan 03 12:39:58 PM PST 24 |
| Finished | Jan 03 12:43:16 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-bf34776a-6102-4805-90a4-8f41f72535ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=137983402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.137983402 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3746684059 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 168850569 ps |
| CPU time | 3.76 seconds |
| Started | Jan 03 12:40:04 PM PST 24 |
| Finished | Jan 03 12:42:00 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-6dc804b0-ccd4-4fa7-9f76-4f7ec05cc895 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746684059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3746684059 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.485013862 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 749763763 ps |
| CPU time | 7.25 seconds |
| Started | Jan 03 12:40:08 PM PST 24 |
| Finished | Jan 03 12:41:37 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-f8d99ff1-4120-4d21-83ee-c216327d8d52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=485013862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.485013862 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.840012105 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 112505791 ps |
| CPU time | 1.54 seconds |
| Started | Jan 03 12:40:17 PM PST 24 |
| Finished | Jan 03 12:41:53 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-92660711-4802-43a4-9376-11f40ef7aa15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=840012105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.840012105 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.958124957 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2624066621 ps |
| CPU time | 6.44 seconds |
| Started | Jan 03 12:40:06 PM PST 24 |
| Finished | Jan 03 12:41:35 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-3f330cb3-9425-4ab7-b8e7-2b921b9a24fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=958124957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.958124957 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.652308135 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 4451768032 ps |
| CPU time | 14.67 seconds |
| Started | Jan 03 12:40:03 PM PST 24 |
| Finished | Jan 03 12:42:04 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-355fd5f7-6aec-49cd-906f-9f39155b1b84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=652308135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.652308135 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.4286384806 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 8293938 ps |
| CPU time | 1.08 seconds |
| Started | Jan 03 12:40:07 PM PST 24 |
| Finished | Jan 03 12:41:51 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-ba36e2e1-8862-40eb-8d62-4319b4eda63f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286384806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.4286384806 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.899330268 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3433800182 ps |
| CPU time | 29.04 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:42:20 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-ef3ff210-d0b2-473b-8964-ca8a030ef72f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=899330268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.899330268 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1365091803 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 8881746629 ps |
| CPU time | 75.81 seconds |
| Started | Jan 03 12:39:58 PM PST 24 |
| Finished | Jan 03 12:42:36 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-14b93c2a-3785-4878-acc4-5ae1aa379333 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1365091803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1365091803 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3343800971 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 639724726 ps |
| CPU time | 116.6 seconds |
| Started | Jan 03 12:39:51 PM PST 24 |
| Finished | Jan 03 12:43:53 PM PST 24 |
| Peak memory | 206504 kb |
| Host | smart-f3c4a188-cb9d-46ca-b3d3-eb2154e0a3f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3343800971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.3343800971 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2356361930 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2978742480 ps |
| CPU time | 51.33 seconds |
| Started | Jan 03 12:40:04 PM PST 24 |
| Finished | Jan 03 12:42:47 PM PST 24 |
| Peak memory | 202728 kb |
| Host | smart-9262ab87-7364-41cb-8aa3-48e4ce0c8579 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2356361930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.2356361930 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.1878490183 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2593167100 ps |
| CPU time | 5.82 seconds |
| Started | Jan 03 12:39:45 PM PST 24 |
| Finished | Jan 03 12:41:16 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-25240c87-244f-4b60-bb70-2e4ae0985805 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1878490183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1878490183 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.2986229153 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 855653060 ps |
| CPU time | 7.61 seconds |
| Started | Jan 03 12:38:36 PM PST 24 |
| Finished | Jan 03 12:40:02 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-200bbf03-c36c-4e2e-8892-23f57ec5d8f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2986229153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2986229153 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.586844528 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 303657578 ps |
| CPU time | 4.18 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:52 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-dba22e47-ca05-40b5-b5dc-63705287f98b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=586844528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.586844528 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.4173873795 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 70263831 ps |
| CPU time | 4.25 seconds |
| Started | Jan 03 12:37:59 PM PST 24 |
| Finished | Jan 03 12:39:30 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-ac3f7a0c-9d00-4d84-8f4c-2b13389a7113 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4173873795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.4173873795 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.3306209436 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 118816558 ps |
| CPU time | 8.07 seconds |
| Started | Jan 03 12:38:25 PM PST 24 |
| Finished | Jan 03 12:39:59 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-0c6fd13a-5648-4c2b-815d-8819dad89d3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3306209436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3306209436 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2622906326 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 33641410592 ps |
| CPU time | 153.21 seconds |
| Started | Jan 03 12:37:57 PM PST 24 |
| Finished | Jan 03 12:41:47 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-998c09de-7b40-4c15-9a3f-45ce90be5da8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622906326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2622906326 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3217043679 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 8863969092 ps |
| CPU time | 22.09 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:54 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-eedae929-70e2-4e45-a393-c524593f5b00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3217043679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3217043679 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3971624216 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 140562466 ps |
| CPU time | 7.6 seconds |
| Started | Jan 03 12:38:13 PM PST 24 |
| Finished | Jan 03 12:39:46 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-530aa0b1-b1a7-46c4-a3f9-24c6482ab40e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971624216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3971624216 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.3419886448 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 9901606 ps |
| CPU time | 1.28 seconds |
| Started | Jan 03 12:38:32 PM PST 24 |
| Finished | Jan 03 12:39:44 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-f9d5bc76-5fd6-4583-a72e-ef16240fcf0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3419886448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3419886448 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2070370373 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 3621648519 ps |
| CPU time | 8.08 seconds |
| Started | Jan 03 12:38:11 PM PST 24 |
| Finished | Jan 03 12:39:54 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-06100824-82bf-43b6-82c9-46eefe52b7a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070370373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2070370373 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.791753485 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 1787883828 ps |
| CPU time | 10.96 seconds |
| Started | Jan 03 12:38:39 PM PST 24 |
| Finished | Jan 03 12:40:21 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-f02197e6-fdf3-40fc-b872-fdfa348330db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=791753485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.791753485 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.340127997 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 12827339 ps |
| CPU time | 1.08 seconds |
| Started | Jan 03 12:38:11 PM PST 24 |
| Finished | Jan 03 12:39:30 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-08e379a0-7711-493f-ad1e-710b586ac10f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340127997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.340127997 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1185582768 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1091957676 ps |
| CPU time | 12.07 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:42 PM PST 24 |
| Peak memory | 201328 kb |
| Host | smart-bb755c32-0f2c-4f43-bec1-3b7cf350b9c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1185582768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1185582768 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2790565910 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 9431333089 ps |
| CPU time | 29.9 seconds |
| Started | Jan 03 12:38:04 PM PST 24 |
| Finished | Jan 03 12:39:49 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-7cd5b37b-c833-4965-b2fd-8a25806bd4c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2790565910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2790565910 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1806938273 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 3039275671 ps |
| CPU time | 101.52 seconds |
| Started | Jan 03 12:38:07 PM PST 24 |
| Finished | Jan 03 12:41:06 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-623ae38d-9264-400d-80d6-10969241f841 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1806938273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.1806938273 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3980134370 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 421682210 ps |
| CPU time | 34.74 seconds |
| Started | Jan 03 12:37:59 PM PST 24 |
| Finished | Jan 03 12:40:02 PM PST 24 |
| Peak memory | 202736 kb |
| Host | smart-d4d8fdc8-800a-4ef8-8a3e-d7b2e9aa14fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3980134370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.3980134370 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.887127514 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3216705832 ps |
| CPU time | 8.16 seconds |
| Started | Jan 03 12:37:58 PM PST 24 |
| Finished | Jan 03 12:39:22 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-0b0d89ce-1827-45e4-a0b4-eb9ae9960ffe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=887127514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.887127514 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.2771069017 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 727917936 ps |
| CPU time | 8.69 seconds |
| Started | Jan 03 12:40:09 PM PST 24 |
| Finished | Jan 03 12:41:46 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-78ff63f3-0ac2-4f92-adf7-1237109aad00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2771069017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.2771069017 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1429771101 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1894622759 ps |
| CPU time | 5.25 seconds |
| Started | Jan 03 12:40:03 PM PST 24 |
| Finished | Jan 03 12:41:59 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-5e3a0160-2547-444d-a800-5d9055c2b932 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1429771101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1429771101 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.3747562507 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 18294613 ps |
| CPU time | 2.34 seconds |
| Started | Jan 03 12:39:48 PM PST 24 |
| Finished | Jan 03 12:41:10 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-dcc5c3d9-4ce4-4ec8-a0ee-bf9ffe53d2bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3747562507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3747562507 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.499556481 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 892789535 ps |
| CPU time | 9.73 seconds |
| Started | Jan 03 12:40:40 PM PST 24 |
| Finished | Jan 03 12:42:26 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-6f909a27-5ea8-4391-80f5-ff18ea234fa1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=499556481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.499556481 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.966220361 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 245419073892 ps |
| CPU time | 128.96 seconds |
| Started | Jan 03 12:39:55 PM PST 24 |
| Finished | Jan 03 12:43:25 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-06e4e8fc-b85d-4cb1-a2df-776b397176e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=966220361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.966220361 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1566017812 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 48894240936 ps |
| CPU time | 85.8 seconds |
| Started | Jan 03 12:40:06 PM PST 24 |
| Finished | Jan 03 12:43:03 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-64ccdd6c-98e5-4d35-bc33-506edc2151d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1566017812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1566017812 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.4037462636 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 22641754 ps |
| CPU time | 2.1 seconds |
| Started | Jan 03 12:39:59 PM PST 24 |
| Finished | Jan 03 12:41:25 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-7c0d3cae-1107-43e4-9a25-f9e036773724 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037462636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.4037462636 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.3364651171 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 514580335 ps |
| CPU time | 3.6 seconds |
| Started | Jan 03 12:40:33 PM PST 24 |
| Finished | Jan 03 12:42:02 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-7c0b0efa-1993-4463-9d82-8dadddb0778a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3364651171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3364651171 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.1587407679 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 10486495 ps |
| CPU time | 1.31 seconds |
| Started | Jan 03 12:40:09 PM PST 24 |
| Finished | Jan 03 12:41:37 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-c2a0febe-4606-4990-9b2b-104e32bdb24a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1587407679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1587407679 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3287675728 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1694550680 ps |
| CPU time | 7.66 seconds |
| Started | Jan 03 12:39:49 PM PST 24 |
| Finished | Jan 03 12:41:23 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-af7be600-042a-422a-90ff-1c581ca5b31f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287675728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3287675728 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1212618440 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1445887728 ps |
| CPU time | 10.21 seconds |
| Started | Jan 03 12:40:03 PM PST 24 |
| Finished | Jan 03 12:41:51 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-a5f7f7b3-a32e-4bcd-bd94-b0532b30ee13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1212618440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1212618440 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.715601846 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 8917696 ps |
| CPU time | 1.03 seconds |
| Started | Jan 03 12:39:51 PM PST 24 |
| Finished | Jan 03 12:41:26 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-832653d1-0f05-4661-878a-f261a21f8e34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715601846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.715601846 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.2514607721 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2646784668 ps |
| CPU time | 29.57 seconds |
| Started | Jan 03 12:40:52 PM PST 24 |
| Finished | Jan 03 12:42:50 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-b47e9989-b5bf-4b7b-88e1-a01e7d905b15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2514607721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2514607721 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.876151280 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 5038935443 ps |
| CPU time | 39 seconds |
| Started | Jan 03 12:40:00 PM PST 24 |
| Finished | Jan 03 12:42:20 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-8e6e5b0b-4a91-4544-a181-17385697b844 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=876151280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.876151280 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.626272938 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 387048667 ps |
| CPU time | 37.28 seconds |
| Started | Jan 03 12:39:52 PM PST 24 |
| Finished | Jan 03 12:41:51 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-3ec6108d-3d42-4823-b52b-13b63a954803 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=626272938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand _reset.626272938 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.407880804 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3733796639 ps |
| CPU time | 107.62 seconds |
| Started | Jan 03 12:40:15 PM PST 24 |
| Finished | Jan 03 12:43:25 PM PST 24 |
| Peak memory | 206232 kb |
| Host | smart-d47f8570-a8c9-44f7-9fab-4ac7e824f81d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=407880804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res et_error.407880804 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.2965531837 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 324926711 ps |
| CPU time | 6.1 seconds |
| Started | Jan 03 12:40:42 PM PST 24 |
| Finished | Jan 03 12:42:15 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-375a588c-3701-4535-a6ca-1a4a7f326f73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2965531837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2965531837 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3507260188 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 121257195 ps |
| CPU time | 10.53 seconds |
| Started | Jan 03 12:40:33 PM PST 24 |
| Finished | Jan 03 12:42:11 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-0acaa379-e230-478b-86ac-0a910af59665 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3507260188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3507260188 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1313790551 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 22956181424 ps |
| CPU time | 136.76 seconds |
| Started | Jan 03 12:40:21 PM PST 24 |
| Finished | Jan 03 12:44:14 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-593dab26-1178-45ed-8445-d73cdf5c35b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1313790551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1313790551 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3692344801 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 483805203 ps |
| CPU time | 6.19 seconds |
| Started | Jan 03 12:40:55 PM PST 24 |
| Finished | Jan 03 12:42:32 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-8edde8e2-1df1-4db7-a73d-fbdb38facbcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3692344801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3692344801 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.3347061804 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 798533573 ps |
| CPU time | 11.4 seconds |
| Started | Jan 03 12:40:18 PM PST 24 |
| Finished | Jan 03 12:42:07 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-bdcb896a-a047-4089-aa37-fe527333fcc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3347061804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3347061804 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.2119536305 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 18132641 ps |
| CPU time | 2.14 seconds |
| Started | Jan 03 12:40:05 PM PST 24 |
| Finished | Jan 03 12:41:32 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-14802294-45c3-41be-9e36-6790b556277f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2119536305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2119536305 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.1272516752 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 12644947244 ps |
| CPU time | 58.01 seconds |
| Started | Jan 03 12:40:23 PM PST 24 |
| Finished | Jan 03 12:42:45 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-4b99067d-81b5-45a5-ab88-e976120cebf2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272516752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1272516752 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.88626424 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 107837474006 ps |
| CPU time | 201.39 seconds |
| Started | Jan 03 12:40:10 PM PST 24 |
| Finished | Jan 03 12:44:57 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-de796685-c265-4e6f-b38a-2c17672aa12e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=88626424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.88626424 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3473928168 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 36177278 ps |
| CPU time | 4.13 seconds |
| Started | Jan 03 12:39:55 PM PST 24 |
| Finished | Jan 03 12:41:22 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-24811738-2f70-4b2e-9728-585cf77477dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473928168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3473928168 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.1797890904 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4604231471 ps |
| CPU time | 13.09 seconds |
| Started | Jan 03 12:40:30 PM PST 24 |
| Finished | Jan 03 12:42:16 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-bdaae821-5728-41d1-9354-ab1d9adb9ece |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1797890904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1797890904 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.3897185402 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 97526568 ps |
| CPU time | 1.62 seconds |
| Started | Jan 03 12:39:58 PM PST 24 |
| Finished | Jan 03 12:41:27 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-ff9f57c6-d46b-451d-8118-687c53e566df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3897185402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3897185402 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.316056999 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 7839411056 ps |
| CPU time | 6.41 seconds |
| Started | Jan 03 12:39:55 PM PST 24 |
| Finished | Jan 03 12:41:24 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-4c9895b3-4fec-4dee-8911-f380c136821d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=316056999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.316056999 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.4016075305 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1408047747 ps |
| CPU time | 6.1 seconds |
| Started | Jan 03 12:39:55 PM PST 24 |
| Finished | Jan 03 12:41:35 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-04b7ceeb-b2e3-4f80-a4f4-e9b587bbc5cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4016075305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4016075305 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1331580097 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 8776959 ps |
| CPU time | 1.09 seconds |
| Started | Jan 03 12:40:08 PM PST 24 |
| Finished | Jan 03 12:41:31 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-c8f9dfe2-5d47-4bbb-950d-01df9f0448c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331580097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1331580097 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1639969811 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 8116548200 ps |
| CPU time | 57.33 seconds |
| Started | Jan 03 12:40:29 PM PST 24 |
| Finished | Jan 03 12:43:03 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-2f3304cb-eb24-4c6e-be7d-de3e4c1f2a4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1639969811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1639969811 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1449630653 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1809714594 ps |
| CPU time | 25.65 seconds |
| Started | Jan 03 12:40:06 PM PST 24 |
| Finished | Jan 03 12:41:59 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-6700ed01-5210-4d5e-bb36-0f17cf3ef1e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1449630653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1449630653 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1289402369 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 16097794924 ps |
| CPU time | 73.27 seconds |
| Started | Jan 03 12:40:12 PM PST 24 |
| Finished | Jan 03 12:42:48 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-a9366dd0-621d-4781-9c21-78be5fb735e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1289402369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.1289402369 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2298851151 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 206133815 ps |
| CPU time | 15.26 seconds |
| Started | Jan 03 12:40:20 PM PST 24 |
| Finished | Jan 03 12:42:12 PM PST 24 |
| Peak memory | 202484 kb |
| Host | smart-1160c18b-566c-4ba9-a398-c4823bd3c326 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2298851151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.2298851151 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2356119339 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 200481842 ps |
| CPU time | 3.61 seconds |
| Started | Jan 03 12:40:35 PM PST 24 |
| Finished | Jan 03 12:42:13 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-9330b8b0-8fd6-41ea-a857-b7a47f316d32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2356119339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2356119339 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.706257818 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 52301196 ps |
| CPU time | 11.3 seconds |
| Started | Jan 03 12:40:18 PM PST 24 |
| Finished | Jan 03 12:42:08 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-755286fa-412e-49e9-b04c-019cd3d5a972 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=706257818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.706257818 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.831689912 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 12851853614 ps |
| CPU time | 90.32 seconds |
| Started | Jan 03 12:40:20 PM PST 24 |
| Finished | Jan 03 12:43:14 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-b3726914-5add-4f92-8bdd-8e9ab80407ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=831689912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slo w_rsp.831689912 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2912223277 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 151803522 ps |
| CPU time | 2.72 seconds |
| Started | Jan 03 12:40:00 PM PST 24 |
| Finished | Jan 03 12:41:52 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-d9b6469c-a14b-4247-b321-58979b2add1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2912223277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2912223277 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.697966162 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1603203713 ps |
| CPU time | 11.21 seconds |
| Started | Jan 03 12:39:58 PM PST 24 |
| Finished | Jan 03 12:41:38 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-c841f89c-dabc-4fce-abed-1e6078e222db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=697966162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.697966162 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.3103626215 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 62081722 ps |
| CPU time | 4.17 seconds |
| Started | Jan 03 12:40:59 PM PST 24 |
| Finished | Jan 03 12:42:30 PM PST 24 |
| Peak memory | 201308 kb |
| Host | smart-0945ddee-2037-421a-a1bc-669245abc9a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3103626215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3103626215 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.474626432 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 56797560161 ps |
| CPU time | 105.85 seconds |
| Started | Jan 03 12:40:44 PM PST 24 |
| Finished | Jan 03 12:44:00 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-ed8cafa5-ed35-4f4a-b92e-dfe18e952b4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=474626432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.474626432 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3460463172 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 17786871525 ps |
| CPU time | 73.01 seconds |
| Started | Jan 03 12:40:07 PM PST 24 |
| Finished | Jan 03 12:43:03 PM PST 24 |
| Peak memory | 201616 kb |
| Host | smart-87759bdd-66a1-49f4-b36b-5542f154fba8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3460463172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3460463172 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3742229825 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 72064870 ps |
| CPU time | 2.65 seconds |
| Started | Jan 03 12:40:16 PM PST 24 |
| Finished | Jan 03 12:41:43 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-9bc7ed44-fe0c-47e4-88da-2740876a89ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742229825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3742229825 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.3538273174 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 437437235 ps |
| CPU time | 2.33 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:41:44 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-9255c717-8549-48a7-9293-bba93f753349 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3538273174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3538273174 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.3772108951 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 11477061 ps |
| CPU time | 0.98 seconds |
| Started | Jan 03 12:40:17 PM PST 24 |
| Finished | Jan 03 12:41:52 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-0c39459e-b7d2-4414-806c-85dccb469982 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3772108951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3772108951 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2594366454 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 14425462076 ps |
| CPU time | 12.38 seconds |
| Started | Jan 03 12:40:55 PM PST 24 |
| Finished | Jan 03 12:42:36 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-4a4e6d1c-7a8a-4c27-8508-6fa5d0fed3f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594366454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2594366454 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1616687981 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7574271232 ps |
| CPU time | 7.53 seconds |
| Started | Jan 03 12:40:16 PM PST 24 |
| Finished | Jan 03 12:41:46 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-57364f3f-8711-4900-b676-70dcbfea8b4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1616687981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1616687981 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2680882272 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 11005656 ps |
| CPU time | 1.11 seconds |
| Started | Jan 03 12:40:25 PM PST 24 |
| Finished | Jan 03 12:42:12 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-e5868cc9-590c-4b3c-ba06-491107e700f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680882272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2680882272 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.4055001961 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 355977231 ps |
| CPU time | 12.47 seconds |
| Started | Jan 03 12:40:02 PM PST 24 |
| Finished | Jan 03 12:41:44 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-1ba546eb-6641-4315-a4f9-fa1440810302 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4055001961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.4055001961 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.618541896 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2663127288 ps |
| CPU time | 20.89 seconds |
| Started | Jan 03 12:40:16 PM PST 24 |
| Finished | Jan 03 12:42:00 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-56c0d005-6a8a-41df-a519-9cb4b96268d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=618541896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.618541896 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3806447704 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 258331703 ps |
| CPU time | 39.25 seconds |
| Started | Jan 03 12:40:24 PM PST 24 |
| Finished | Jan 03 12:42:31 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-bae19c47-da10-4eb9-9597-ba993581b789 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3806447704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.3806447704 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.76244663 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1044987515 ps |
| CPU time | 52.67 seconds |
| Started | Jan 03 12:40:14 PM PST 24 |
| Finished | Jan 03 12:42:45 PM PST 24 |
| Peak memory | 202820 kb |
| Host | smart-bd9e8da1-285e-4d97-ad8d-8604b91f929b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=76244663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rese t_error.76244663 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2920547719 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 14452431 ps |
| CPU time | 1.53 seconds |
| Started | Jan 03 12:40:02 PM PST 24 |
| Finished | Jan 03 12:41:30 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-028d3843-0e88-4157-89ce-2b519d7b9714 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2920547719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2920547719 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2578343188 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 18713667 ps |
| CPU time | 3.24 seconds |
| Started | Jan 03 12:40:07 PM PST 24 |
| Finished | Jan 03 12:41:57 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-ff161b08-e134-4fee-96c5-193db8a4f15f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2578343188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2578343188 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.249380116 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 23624261808 ps |
| CPU time | 121.27 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:43:52 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-e8a6e8c3-0ba8-4caf-bea8-3489cc96317e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=249380116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo w_rsp.249380116 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.623488496 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 998915377 ps |
| CPU time | 6.53 seconds |
| Started | Jan 03 12:40:01 PM PST 24 |
| Finished | Jan 03 12:41:36 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-bafd47be-03ca-43dd-9ee5-bcc2860b7435 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=623488496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.623488496 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.1055760772 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1302668120 ps |
| CPU time | 10.43 seconds |
| Started | Jan 03 12:40:14 PM PST 24 |
| Finished | Jan 03 12:42:03 PM PST 24 |
| Peak memory | 201328 kb |
| Host | smart-bfffd437-fcfc-4e14-b39d-56b09c7cb77e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1055760772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1055760772 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.970791666 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 989508027 ps |
| CPU time | 3.69 seconds |
| Started | Jan 03 12:40:04 PM PST 24 |
| Finished | Jan 03 12:41:57 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-b608cd42-3063-4662-9d15-7941f4d09fab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=970791666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.970791666 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.687627487 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 94410363426 ps |
| CPU time | 102.52 seconds |
| Started | Jan 03 12:40:05 PM PST 24 |
| Finished | Jan 03 12:43:10 PM PST 24 |
| Peak memory | 201620 kb |
| Host | smart-1d5db9c1-0698-4c2a-b771-8361986d7492 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=687627487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.687627487 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1446948292 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 7951921212 ps |
| CPU time | 52.83 seconds |
| Started | Jan 03 12:40:12 PM PST 24 |
| Finished | Jan 03 12:42:34 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-6565d1a4-b0c1-4453-b7d0-26199166091f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1446948292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1446948292 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.2668345880 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 40399875 ps |
| CPU time | 4.19 seconds |
| Started | Jan 03 12:39:56 PM PST 24 |
| Finished | Jan 03 12:41:41 PM PST 24 |
| Peak memory | 201292 kb |
| Host | smart-b751d101-84db-41cd-ae90-099fd1eaac7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668345880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2668345880 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.3878477916 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1785892145 ps |
| CPU time | 6.59 seconds |
| Started | Jan 03 12:40:55 PM PST 24 |
| Finished | Jan 03 12:42:30 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-3bf86d15-37e9-4b07-bd12-abb812284c78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3878477916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3878477916 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.156452282 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 20430556 ps |
| CPU time | 1.12 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:41:54 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-c2ca95ab-e74e-48fd-9fe7-f1a1907db5ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=156452282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.156452282 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2974414978 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 6517405610 ps |
| CPU time | 7.9 seconds |
| Started | Jan 03 12:40:03 PM PST 24 |
| Finished | Jan 03 12:41:37 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-5d30c82c-7b20-4f15-8817-d10988ee7927 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974414978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2974414978 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3385985803 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3120707485 ps |
| CPU time | 9.12 seconds |
| Started | Jan 03 12:40:11 PM PST 24 |
| Finished | Jan 03 12:42:09 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-63268b1f-5e48-421a-8c06-58c40ec269d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3385985803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3385985803 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.975293780 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 9378322 ps |
| CPU time | 1 seconds |
| Started | Jan 03 12:40:00 PM PST 24 |
| Finished | Jan 03 12:41:50 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-4f76ac8e-fa04-42b8-91f3-e0c60ef2081a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975293780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.975293780 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.872737657 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 6946321966 ps |
| CPU time | 92.71 seconds |
| Started | Jan 03 12:40:31 PM PST 24 |
| Finished | Jan 03 12:43:33 PM PST 24 |
| Peak memory | 201596 kb |
| Host | smart-223a0509-fb83-48ff-95b5-3fdd66197d3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=872737657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.872737657 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1367060589 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 6144605988 ps |
| CPU time | 65.65 seconds |
| Started | Jan 03 12:40:05 PM PST 24 |
| Finished | Jan 03 12:42:34 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-518a201b-2df6-4da4-abba-8bd306fdedfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1367060589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1367060589 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2503889910 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 400748901 ps |
| CPU time | 66.21 seconds |
| Started | Jan 03 12:40:14 PM PST 24 |
| Finished | Jan 03 12:43:00 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-ec03235b-0a06-49d4-889b-31557bcc9d65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2503889910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.2503889910 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3647972820 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1427187937 ps |
| CPU time | 82.6 seconds |
| Started | Jan 03 12:40:06 PM PST 24 |
| Finished | Jan 03 12:42:56 PM PST 24 |
| Peak memory | 206040 kb |
| Host | smart-f6dbb068-34f6-407e-b8a4-a66bd35bbd6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3647972820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3647972820 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1330462358 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 996621043 ps |
| CPU time | 3.16 seconds |
| Started | Jan 03 12:40:37 PM PST 24 |
| Finished | Jan 03 12:42:06 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-95ac284e-267f-4f0f-9ab4-df0f1302c74d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1330462358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1330462358 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2883075496 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 57693459 ps |
| CPU time | 7.33 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:42:01 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-9e267093-437b-442e-8d64-528e388e7514 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2883075496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2883075496 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.4016969327 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 55830748108 ps |
| CPU time | 207.24 seconds |
| Started | Jan 03 12:40:49 PM PST 24 |
| Finished | Jan 03 12:45:46 PM PST 24 |
| Peak memory | 202636 kb |
| Host | smart-ec2edad9-f253-418e-acc8-2ee54fb6c3e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4016969327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.4016969327 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3838633288 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 39874809 ps |
| CPU time | 2.75 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:41:39 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-6a4be88c-158c-4d47-8233-c3bcbc361d9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3838633288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3838633288 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.1549643709 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1748726557 ps |
| CPU time | 5.79 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:41:43 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-aa53b47b-26ed-47fb-89f2-28a3bc2083a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1549643709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1549643709 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.156109717 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 941782015 ps |
| CPU time | 12.87 seconds |
| Started | Jan 03 12:40:52 PM PST 24 |
| Finished | Jan 03 12:42:33 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-2b280d93-08dc-472e-9727-2fc7e04f3981 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=156109717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.156109717 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1725876276 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3873723213 ps |
| CPU time | 10.47 seconds |
| Started | Jan 03 12:40:54 PM PST 24 |
| Finished | Jan 03 12:42:33 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-68ea4515-6293-4f33-8338-1581a0684cf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725876276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1725876276 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3823804602 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 6631495317 ps |
| CPU time | 28.77 seconds |
| Started | Jan 03 12:40:54 PM PST 24 |
| Finished | Jan 03 12:42:52 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-02e8a524-c2d3-47d1-95b7-013519db9054 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3823804602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3823804602 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.361767578 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 80467716 ps |
| CPU time | 7.02 seconds |
| Started | Jan 03 12:40:14 PM PST 24 |
| Finished | Jan 03 12:42:03 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-e6dcf0fe-7912-4fce-a0da-67b50c63adc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361767578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.361767578 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.4156571202 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 664361494 ps |
| CPU time | 3.7 seconds |
| Started | Jan 03 12:39:59 PM PST 24 |
| Finished | Jan 03 12:41:28 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-9a4952ca-1739-4938-bb11-d771cc4bb02b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4156571202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.4156571202 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.445566691 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 69532253 ps |
| CPU time | 1.62 seconds |
| Started | Jan 03 12:40:17 PM PST 24 |
| Finished | Jan 03 12:41:59 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-1da00f67-82b7-4c49-afcd-7d6304fb5825 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=445566691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.445566691 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.367782930 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1931929921 ps |
| CPU time | 9.69 seconds |
| Started | Jan 03 12:41:04 PM PST 24 |
| Finished | Jan 03 12:42:47 PM PST 24 |
| Peak memory | 201356 kb |
| Host | smart-91027411-4311-4364-971a-21d1aaff1147 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=367782930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.367782930 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.3816117283 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 7130276553 ps |
| CPU time | 10.27 seconds |
| Started | Jan 03 12:40:24 PM PST 24 |
| Finished | Jan 03 12:42:04 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-e0c704fc-7be0-4711-85c1-e7e4d2b0dcd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3816117283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3816117283 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3956215664 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 30718328 ps |
| CPU time | 1.17 seconds |
| Started | Jan 03 12:41:03 PM PST 24 |
| Finished | Jan 03 12:42:36 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-7a13e93f-38c0-41e8-af09-e8be0266aa79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956215664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3956215664 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.876627445 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2656186522 ps |
| CPU time | 34.24 seconds |
| Started | Jan 03 12:40:57 PM PST 24 |
| Finished | Jan 03 12:43:00 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-704aa12c-4366-4ba8-86c5-46c75bd2642d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=876627445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.876627445 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3950285890 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 540062313 ps |
| CPU time | 49.41 seconds |
| Started | Jan 03 12:40:55 PM PST 24 |
| Finished | Jan 03 12:43:15 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-1a14b919-2224-4a7e-b2aa-5a2d15a4f5b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3950285890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3950285890 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.198378609 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 6963958908 ps |
| CPU time | 70.34 seconds |
| Started | Jan 03 12:40:20 PM PST 24 |
| Finished | Jan 03 12:42:54 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-a19e7313-1ccc-4092-ae69-35f3ef502275 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=198378609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand _reset.198378609 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1931081488 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 131313823 ps |
| CPU time | 6.28 seconds |
| Started | Jan 03 12:40:28 PM PST 24 |
| Finished | Jan 03 12:42:13 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-2e25d285-180e-465d-8331-26adec465019 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1931081488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.1931081488 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3507478953 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 49875943 ps |
| CPU time | 4.77 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:41:45 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-00694087-4eb2-4862-a8f6-113e284d57f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3507478953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3507478953 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3614599192 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 171843058 ps |
| CPU time | 10.63 seconds |
| Started | Jan 03 12:39:59 PM PST 24 |
| Finished | Jan 03 12:41:43 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-6b877734-42ce-411a-b9bc-ee1732f07ead |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3614599192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3614599192 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.824668204 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 26083840578 ps |
| CPU time | 197.2 seconds |
| Started | Jan 03 12:40:10 PM PST 24 |
| Finished | Jan 03 12:45:05 PM PST 24 |
| Peak memory | 202656 kb |
| Host | smart-45c1d7e3-e607-4afe-9a52-1047dbf5a12b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=824668204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo w_rsp.824668204 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.250125357 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 602189669 ps |
| CPU time | 5.73 seconds |
| Started | Jan 03 12:40:24 PM PST 24 |
| Finished | Jan 03 12:42:06 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-540f2029-036b-48a2-950a-f16ab320b863 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=250125357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.250125357 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.1071433523 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3510014462 ps |
| CPU time | 8.59 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:42:07 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-3b64da70-ec1a-40cc-9b29-0da6cbf5f99b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1071433523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1071433523 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.1367540830 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 188508092 ps |
| CPU time | 2.57 seconds |
| Started | Jan 03 12:40:44 PM PST 24 |
| Finished | Jan 03 12:42:15 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-727a7f1d-7b86-4efe-a024-a8efb3ef8b46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1367540830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1367540830 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.2704654390 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 28630041898 ps |
| CPU time | 105.75 seconds |
| Started | Jan 03 12:40:17 PM PST 24 |
| Finished | Jan 03 12:43:30 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-7325cec7-3717-431a-bf13-7b209c3927d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704654390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2704654390 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2516063444 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 7923766930 ps |
| CPU time | 47.27 seconds |
| Started | Jan 03 12:40:38 PM PST 24 |
| Finished | Jan 03 12:42:52 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-068be734-1cc6-4653-b07b-27b440bc84fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2516063444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2516063444 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2252239630 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 83289058 ps |
| CPU time | 5.83 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:41:58 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-896ac950-866b-4b00-9ebf-947de516b220 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252239630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2252239630 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.657479799 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 15823520 ps |
| CPU time | 1.81 seconds |
| Started | Jan 03 12:40:17 PM PST 24 |
| Finished | Jan 03 12:41:54 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-eb95f933-dc9b-4166-99fc-e4d51e7a2675 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=657479799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.657479799 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.3426667899 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8864447 ps |
| CPU time | 1.2 seconds |
| Started | Jan 03 12:40:39 PM PST 24 |
| Finished | Jan 03 12:42:07 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-7fa2db42-3545-42e9-aefb-217e423cf0dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3426667899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3426667899 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3264172128 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2327295240 ps |
| CPU time | 8.87 seconds |
| Started | Jan 03 12:40:43 PM PST 24 |
| Finished | Jan 03 12:42:22 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-6b445ad0-1a4e-4b89-9723-897b33a51900 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264172128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3264172128 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3389700197 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4734944608 ps |
| CPU time | 7.85 seconds |
| Started | Jan 03 12:40:03 PM PST 24 |
| Finished | Jan 03 12:41:48 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-11b254d1-6099-40ca-99e9-74a3e5e41b3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3389700197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3389700197 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1761720375 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 9603296 ps |
| CPU time | 1.15 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:41:43 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-360947da-4a87-4b5a-951e-619bdc1cbc09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761720375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1761720375 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.505521394 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 966461917 ps |
| CPU time | 29.71 seconds |
| Started | Jan 03 12:40:05 PM PST 24 |
| Finished | Jan 03 12:41:59 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-aef36149-e728-4c59-87d0-91420e65fd23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=505521394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.505521394 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1523226320 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2098580060 ps |
| CPU time | 22.21 seconds |
| Started | Jan 03 12:40:02 PM PST 24 |
| Finished | Jan 03 12:41:45 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-fbb028aa-e31a-447d-9163-aca1f1b9bd47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1523226320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1523226320 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.614644782 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7157760349 ps |
| CPU time | 42.77 seconds |
| Started | Jan 03 12:39:56 PM PST 24 |
| Finished | Jan 03 12:42:16 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-1977f856-c4d7-4c83-ad44-8803bdc1121a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=614644782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand _reset.614644782 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2108569448 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 357654387 ps |
| CPU time | 56.91 seconds |
| Started | Jan 03 12:40:10 PM PST 24 |
| Finished | Jan 03 12:42:45 PM PST 24 |
| Peak memory | 202960 kb |
| Host | smart-ff19cf0c-1030-44aa-a226-e285ef54f07a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2108569448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.2108569448 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.2446495209 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 59282222 ps |
| CPU time | 3.32 seconds |
| Started | Jan 03 12:40:24 PM PST 24 |
| Finished | Jan 03 12:41:56 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-95110d4a-aa1a-44ff-8cd7-47263888beee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2446495209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2446495209 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2273857013 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 34708503 ps |
| CPU time | 6.6 seconds |
| Started | Jan 03 12:40:17 PM PST 24 |
| Finished | Jan 03 12:42:00 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-1535240a-59d9-4d80-b462-d2329ba34288 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2273857013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2273857013 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.977122534 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 59342944804 ps |
| CPU time | 338.47 seconds |
| Started | Jan 03 12:39:53 PM PST 24 |
| Finished | Jan 03 12:46:52 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-d7a1f2e3-a43f-4934-861d-8a46fbea4edf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=977122534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo w_rsp.977122534 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3532051766 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 39282109 ps |
| CPU time | 1.99 seconds |
| Started | Jan 03 12:40:16 PM PST 24 |
| Finished | Jan 03 12:41:42 PM PST 24 |
| Peak memory | 201264 kb |
| Host | smart-35e6b3dc-064e-4868-8320-d0add6f42383 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3532051766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3532051766 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.4068361843 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 124628338 ps |
| CPU time | 4.18 seconds |
| Started | Jan 03 12:40:47 PM PST 24 |
| Finished | Jan 03 12:42:20 PM PST 24 |
| Peak memory | 201304 kb |
| Host | smart-a03c3ee1-6bbd-4182-b11d-65807b434dbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4068361843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.4068361843 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.1625890312 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1329425264 ps |
| CPU time | 13.45 seconds |
| Started | Jan 03 12:40:23 PM PST 24 |
| Finished | Jan 03 12:42:01 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-9dbeb0ac-7229-40b3-95f4-fbd7ac0e38b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1625890312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1625890312 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3456567804 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 24341869419 ps |
| CPU time | 85.45 seconds |
| Started | Jan 03 12:40:19 PM PST 24 |
| Finished | Jan 03 12:43:08 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-a5cc43da-f746-4b7b-9bf6-2ad96ef402e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456567804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3456567804 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.805907778 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 17945617310 ps |
| CPU time | 94.19 seconds |
| Started | Jan 03 12:40:40 PM PST 24 |
| Finished | Jan 03 12:43:54 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-57df7567-67fd-4558-b0b9-22364b4bfbbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=805907778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.805907778 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.4234073347 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 64214669 ps |
| CPU time | 8.13 seconds |
| Started | Jan 03 12:40:54 PM PST 24 |
| Finished | Jan 03 12:42:31 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-0336effe-7fd8-4085-87de-fb99fd387bae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234073347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.4234073347 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.1489398976 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1083512060 ps |
| CPU time | 9.73 seconds |
| Started | Jan 03 12:39:53 PM PST 24 |
| Finished | Jan 03 12:41:32 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-dec97fc9-f9dc-4710-a46c-9d3953bd9d4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1489398976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1489398976 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.3728430608 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 8912190 ps |
| CPU time | 0.99 seconds |
| Started | Jan 03 12:40:20 PM PST 24 |
| Finished | Jan 03 12:41:58 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-6e13b2e8-338f-48e4-9238-2259ab360a29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3728430608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3728430608 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.965198781 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1419261375 ps |
| CPU time | 7.11 seconds |
| Started | Jan 03 12:39:59 PM PST 24 |
| Finished | Jan 03 12:41:36 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-c602c6a4-db85-45f9-8443-e4801235317a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=965198781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.965198781 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3449640325 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2284469644 ps |
| CPU time | 6.98 seconds |
| Started | Jan 03 12:40:01 PM PST 24 |
| Finished | Jan 03 12:41:36 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-c4876789-74e5-4ae2-8575-8172b70e4812 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3449640325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3449640325 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2272331542 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 11505788 ps |
| CPU time | 1.08 seconds |
| Started | Jan 03 12:40:19 PM PST 24 |
| Finished | Jan 03 12:41:44 PM PST 24 |
| Peak memory | 201252 kb |
| Host | smart-7148b979-0f4d-41f5-9df8-556d9c69b39b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272331542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2272331542 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2833362905 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 295393342 ps |
| CPU time | 19.92 seconds |
| Started | Jan 03 12:40:22 PM PST 24 |
| Finished | Jan 03 12:42:09 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-4ca95a46-7af4-4964-8cea-8f08f3d3d8b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2833362905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2833362905 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.265676076 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 6191658855 ps |
| CPU time | 18.49 seconds |
| Started | Jan 03 12:40:10 PM PST 24 |
| Finished | Jan 03 12:42:06 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-92c0b320-f4c6-410a-aac8-f80463d651e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=265676076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.265676076 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.4055361734 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 572099171 ps |
| CPU time | 53.83 seconds |
| Started | Jan 03 12:40:17 PM PST 24 |
| Finished | Jan 03 12:42:43 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-abe2c3d1-b7b3-4ad6-b861-95a6d4e80502 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4055361734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.4055361734 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.682219641 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 47162119 ps |
| CPU time | 1.2 seconds |
| Started | Jan 03 12:40:17 PM PST 24 |
| Finished | Jan 03 12:41:55 PM PST 24 |
| Peak memory | 201356 kb |
| Host | smart-3a89be60-f919-4d7a-a578-4d8bedfeba4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=682219641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res et_error.682219641 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1354000763 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2729896486 ps |
| CPU time | 9.51 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:41:46 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-eddd1a83-2e3c-485c-afd9-f7caf4da44ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1354000763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1354000763 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.2322061057 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 860322082 ps |
| CPU time | 16.05 seconds |
| Started | Jan 03 12:40:49 PM PST 24 |
| Finished | Jan 03 12:42:34 PM PST 24 |
| Peak memory | 201280 kb |
| Host | smart-c90c156e-653b-41da-9a85-5ab5cac4b579 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2322061057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2322061057 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.55785097 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 116957147088 ps |
| CPU time | 280.1 seconds |
| Started | Jan 03 12:40:32 PM PST 24 |
| Finished | Jan 03 12:46:49 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-dae53511-f3eb-45e2-9ec6-8fce91ec2b49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=55785097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow _rsp.55785097 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.583201517 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 266102662 ps |
| CPU time | 3.84 seconds |
| Started | Jan 03 12:40:19 PM PST 24 |
| Finished | Jan 03 12:41:46 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-5af90dc4-4396-4c87-a3e8-580fa82486f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=583201517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.583201517 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.3715611028 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 41619545 ps |
| CPU time | 3.11 seconds |
| Started | Jan 03 12:40:24 PM PST 24 |
| Finished | Jan 03 12:41:58 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-81108f5a-2314-4672-ab64-0b4172a290ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3715611028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3715611028 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.758744384 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 489126630 ps |
| CPU time | 2.61 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:41:54 PM PST 24 |
| Peak memory | 201280 kb |
| Host | smart-11c2f976-a5d8-40fd-82f4-7ffd5574d0b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=758744384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.758744384 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1124267988 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 38438327521 ps |
| CPU time | 139.27 seconds |
| Started | Jan 03 12:40:55 PM PST 24 |
| Finished | Jan 03 12:44:45 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-8194cb33-db2a-4cb0-b9a6-480d576458e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124267988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1124267988 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3359068188 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 48099789624 ps |
| CPU time | 144.69 seconds |
| Started | Jan 03 12:40:48 PM PST 24 |
| Finished | Jan 03 12:44:42 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-266bfe6e-5a6c-4c48-b0ff-d3876b09695c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3359068188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3359068188 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.1151963771 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 72890224 ps |
| CPU time | 6.64 seconds |
| Started | Jan 03 12:40:20 PM PST 24 |
| Finished | Jan 03 12:42:04 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-d0f4203d-d6b7-4434-817d-7a269551903d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151963771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1151963771 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.1340069210 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 72754364 ps |
| CPU time | 1.52 seconds |
| Started | Jan 03 12:39:58 PM PST 24 |
| Finished | Jan 03 12:41:33 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-7a331e83-8fda-497b-8d7f-46abd587afa0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1340069210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1340069210 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.596686188 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 50975581 ps |
| CPU time | 1.54 seconds |
| Started | Jan 03 12:40:14 PM PST 24 |
| Finished | Jan 03 12:41:55 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-aa31287f-5ba2-4297-84c0-f05221a37f77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=596686188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.596686188 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2344659978 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3010715925 ps |
| CPU time | 12 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:41:53 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-074e2edb-debe-4705-b1c9-cc52fc40a103 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344659978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2344659978 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2624152832 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2408706220 ps |
| CPU time | 10.93 seconds |
| Started | Jan 03 12:40:44 PM PST 24 |
| Finished | Jan 03 12:42:24 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-9db9bf64-ae83-46ec-9717-7d6303ae8b67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2624152832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2624152832 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1701395511 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 9389426 ps |
| CPU time | 1.37 seconds |
| Started | Jan 03 12:40:14 PM PST 24 |
| Finished | Jan 03 12:41:55 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-0694d5e1-67ba-4cdf-ba50-c6111ad109e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701395511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1701395511 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2245909005 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 135642939 ps |
| CPU time | 13.41 seconds |
| Started | Jan 03 12:40:24 PM PST 24 |
| Finished | Jan 03 12:42:07 PM PST 24 |
| Peak memory | 201288 kb |
| Host | smart-a918b881-e657-468f-ae1d-88a6bc1f1297 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2245909005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2245909005 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3779243098 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 63748217 ps |
| CPU time | 1.31 seconds |
| Started | Jan 03 12:40:30 PM PST 24 |
| Finished | Jan 03 12:42:05 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-172d4b2f-1ea7-4276-98f8-12d366e56d9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3779243098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3779243098 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2394379177 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 9013434702 ps |
| CPU time | 102.98 seconds |
| Started | Jan 03 12:40:52 PM PST 24 |
| Finished | Jan 03 12:44:03 PM PST 24 |
| Peak memory | 204132 kb |
| Host | smart-2f467fbd-7422-4929-bf91-2605b487b72e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2394379177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.2394379177 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2220081487 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 474255226 ps |
| CPU time | 42.34 seconds |
| Started | Jan 03 12:40:44 PM PST 24 |
| Finished | Jan 03 12:42:55 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-5f50ab91-a0c9-4c3a-a897-d5da8b25a6e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2220081487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.2220081487 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.539249072 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 9275262 ps |
| CPU time | 1.05 seconds |
| Started | Jan 03 12:40:48 PM PST 24 |
| Finished | Jan 03 12:42:19 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-4979dd63-c001-47ee-9df9-bd64d79bbdd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=539249072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.539249072 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2760076052 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2349755219 ps |
| CPU time | 16.14 seconds |
| Started | Jan 03 12:40:17 PM PST 24 |
| Finished | Jan 03 12:42:06 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-9a318aa7-aecf-4a2f-a7f9-e9c47e4c7724 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2760076052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2760076052 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1185115561 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 29349126300 ps |
| CPU time | 211.82 seconds |
| Started | Jan 03 12:40:16 PM PST 24 |
| Finished | Jan 03 12:45:10 PM PST 24 |
| Peak memory | 202664 kb |
| Host | smart-ba240b11-51ea-49a3-8f92-566a82ca4541 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1185115561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.1185115561 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3428026245 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 117774226 ps |
| CPU time | 3.98 seconds |
| Started | Jan 03 12:40:24 PM PST 24 |
| Finished | Jan 03 12:42:09 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-dff931ec-505c-4cb1-af06-26c69839f016 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3428026245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3428026245 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.1524619742 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2822789005 ps |
| CPU time | 8.39 seconds |
| Started | Jan 03 12:40:47 PM PST 24 |
| Finished | Jan 03 12:42:25 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-c097525d-f277-4d58-9808-384d10ee583a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1524619742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1524619742 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.3243150999 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 742131844 ps |
| CPU time | 10.64 seconds |
| Started | Jan 03 12:40:24 PM PST 24 |
| Finished | Jan 03 12:42:11 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-bcda7f6c-3ea1-48e8-9f06-f91203cc1de1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3243150999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3243150999 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2456925 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 30466865518 ps |
| CPU time | 70.81 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:43:09 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-53191af3-576f-4464-95e9-4b96f8df8014 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2456925 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2835378072 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 18337712237 ps |
| CPU time | 117.63 seconds |
| Started | Jan 03 12:40:47 PM PST 24 |
| Finished | Jan 03 12:44:13 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-88cc548b-b6b3-48e7-b596-b318ee325a92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2835378072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2835378072 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3876593228 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 605906292 ps |
| CPU time | 7.86 seconds |
| Started | Jan 03 12:40:12 PM PST 24 |
| Finished | Jan 03 12:41:50 PM PST 24 |
| Peak memory | 201292 kb |
| Host | smart-7109089e-b1a4-4aa4-a54b-5d0d23c14b7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876593228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3876593228 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.2950828686 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1215665569 ps |
| CPU time | 12.48 seconds |
| Started | Jan 03 12:40:52 PM PST 24 |
| Finished | Jan 03 12:42:33 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-7636bb48-7508-486e-8b67-ab7d0c94abf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2950828686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2950828686 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.365412053 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 232043610 ps |
| CPU time | 1.35 seconds |
| Started | Jan 03 12:40:23 PM PST 24 |
| Finished | Jan 03 12:41:59 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-b0e2703c-61b4-4bfc-956d-c447616f75a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=365412053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.365412053 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.4083675635 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 3269649430 ps |
| CPU time | 9.28 seconds |
| Started | Jan 03 12:40:18 PM PST 24 |
| Finished | Jan 03 12:41:52 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-577b49d8-84f2-4443-8d87-64fd9ef9526f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083675635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.4083675635 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2253650398 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 820577573 ps |
| CPU time | 5.72 seconds |
| Started | Jan 03 12:40:18 PM PST 24 |
| Finished | Jan 03 12:41:52 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-8af385ec-c413-413b-8fca-78ea80680433 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2253650398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2253650398 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1061551716 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 9457140 ps |
| CPU time | 1.18 seconds |
| Started | Jan 03 12:40:17 PM PST 24 |
| Finished | Jan 03 12:41:53 PM PST 24 |
| Peak memory | 201276 kb |
| Host | smart-483b9e0e-d463-406e-8152-5867e8a5bc7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061551716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1061551716 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.272167078 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 990298309 ps |
| CPU time | 14.3 seconds |
| Started | Jan 03 12:40:01 PM PST 24 |
| Finished | Jan 03 12:41:44 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-8122b93c-2dea-489a-b3ba-f83075f5bb3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=272167078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.272167078 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1009990122 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 99141221 ps |
| CPU time | 6.69 seconds |
| Started | Jan 03 12:40:05 PM PST 24 |
| Finished | Jan 03 12:41:34 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-ef670855-978f-4d7c-babb-cfda88549bb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1009990122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1009990122 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3239090866 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1336990664 ps |
| CPU time | 210.53 seconds |
| Started | Jan 03 12:40:38 PM PST 24 |
| Finished | Jan 03 12:45:45 PM PST 24 |
| Peak memory | 203936 kb |
| Host | smart-588ef9df-0906-4a8d-b2bd-71a1e2d4cae8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3239090866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.3239090866 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3317620489 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 428929663 ps |
| CPU time | 46.67 seconds |
| Started | Jan 03 12:39:59 PM PST 24 |
| Finished | Jan 03 12:42:23 PM PST 24 |
| Peak memory | 202744 kb |
| Host | smart-5f783fac-8617-43d6-a55a-98b0d79fd64f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3317620489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.3317620489 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3287048166 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 25677011 ps |
| CPU time | 2.41 seconds |
| Started | Jan 03 12:40:06 PM PST 24 |
| Finished | Jan 03 12:41:36 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-7a6becb2-9f75-4518-8152-131130826060 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3287048166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3287048166 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.454232911 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 605884340 ps |
| CPU time | 12.59 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:42:02 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-a146e285-ca1a-486b-b830-c658010b225f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=454232911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.454232911 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.866242817 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 19730117594 ps |
| CPU time | 78.65 seconds |
| Started | Jan 03 12:41:01 PM PST 24 |
| Finished | Jan 03 12:43:48 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-f16d6331-2844-4173-8ba5-84a1b0c6fbf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=866242817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slo w_rsp.866242817 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2559725949 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 809350815 ps |
| CPU time | 9.3 seconds |
| Started | Jan 03 12:40:37 PM PST 24 |
| Finished | Jan 03 12:42:13 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-24aa7d92-6da7-4bad-a651-79418738a54a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2559725949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2559725949 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.3927262773 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 82031007 ps |
| CPU time | 2.64 seconds |
| Started | Jan 03 12:40:26 PM PST 24 |
| Finished | Jan 03 12:41:53 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-3bf2f7ea-30d6-420e-915c-7daf4fbe285c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3927262773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3927262773 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.3915218287 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 72671784 ps |
| CPU time | 7.53 seconds |
| Started | Jan 03 12:40:15 PM PST 24 |
| Finished | Jan 03 12:41:47 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-75c7aee4-1514-418b-8ab7-147ebc61246a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3915218287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3915218287 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3158870020 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 30463748442 ps |
| CPU time | 141.22 seconds |
| Started | Jan 03 12:40:43 PM PST 24 |
| Finished | Jan 03 12:44:33 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-3ec147be-3783-4dfd-b9f5-cf4033547504 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158870020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3158870020 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2028058943 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1396831728 ps |
| CPU time | 8.01 seconds |
| Started | Jan 03 12:40:19 PM PST 24 |
| Finished | Jan 03 12:42:13 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-df39b7bc-631d-4b55-9e1c-ddb23b98c2c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2028058943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2028058943 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1869830162 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 98351087 ps |
| CPU time | 3.42 seconds |
| Started | Jan 03 12:40:01 PM PST 24 |
| Finished | Jan 03 12:42:00 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-75ecdd29-5d75-48bf-b0b3-2697209964a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869830162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1869830162 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.4273016235 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1935403713 ps |
| CPU time | 6.67 seconds |
| Started | Jan 03 12:41:01 PM PST 24 |
| Finished | Jan 03 12:42:37 PM PST 24 |
| Peak memory | 201356 kb |
| Host | smart-b40be5db-5c6c-44ac-aee9-5e13eb5b7380 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4273016235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.4273016235 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.1808603737 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 8450971 ps |
| CPU time | 1.09 seconds |
| Started | Jan 03 12:40:13 PM PST 24 |
| Finished | Jan 03 12:41:47 PM PST 24 |
| Peak memory | 201256 kb |
| Host | smart-74f91cba-3baf-4cea-be2a-575034393542 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1808603737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1808603737 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2130148837 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2991038968 ps |
| CPU time | 13.22 seconds |
| Started | Jan 03 12:40:06 PM PST 24 |
| Finished | Jan 03 12:41:51 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-f1702aec-3fce-4401-9a18-f7e8ebc25261 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130148837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2130148837 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2342118192 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 5997441730 ps |
| CPU time | 11.34 seconds |
| Started | Jan 03 12:39:59 PM PST 24 |
| Finished | Jan 03 12:41:43 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-4727eae7-2b36-4414-b163-f0a5683a3107 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2342118192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2342118192 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.149089845 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 24762397 ps |
| CPU time | 1.05 seconds |
| Started | Jan 03 12:40:06 PM PST 24 |
| Finished | Jan 03 12:41:30 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-71516643-a6c8-4322-addb-9562f1daefc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149089845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.149089845 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3356015104 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 7157363247 ps |
| CPU time | 110.45 seconds |
| Started | Jan 03 12:40:23 PM PST 24 |
| Finished | Jan 03 12:43:39 PM PST 24 |
| Peak memory | 202992 kb |
| Host | smart-a6f06949-8f54-420e-b06d-9ae02e2cef3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3356015104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3356015104 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3055726898 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2616512589 ps |
| CPU time | 33.05 seconds |
| Started | Jan 03 12:41:03 PM PST 24 |
| Finished | Jan 03 12:43:07 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-192c7af2-eff5-43dd-af83-25c5f83bfe54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3055726898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3055726898 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1347986160 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1664845510 ps |
| CPU time | 86.25 seconds |
| Started | Jan 03 12:40:35 PM PST 24 |
| Finished | Jan 03 12:43:36 PM PST 24 |
| Peak memory | 204000 kb |
| Host | smart-be32c213-38f8-4024-bc84-fedd2007d473 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1347986160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.1347986160 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3756801685 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 142209837 ps |
| CPU time | 7.73 seconds |
| Started | Jan 03 12:40:54 PM PST 24 |
| Finished | Jan 03 12:42:30 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-9451feee-1b70-416f-bd72-84bbbfb8b46b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3756801685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.3756801685 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2103311900 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 14499691 ps |
| CPU time | 1.41 seconds |
| Started | Jan 03 12:40:25 PM PST 24 |
| Finished | Jan 03 12:42:13 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-eb0618ad-2824-45d0-8d83-043e23e54af8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2103311900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2103311900 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.2829068060 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2463855737 ps |
| CPU time | 12.66 seconds |
| Started | Jan 03 12:38:00 PM PST 24 |
| Finished | Jan 03 12:39:29 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-3c8861fb-c84c-49bf-a77c-8e119001abd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2829068060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2829068060 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.4212719742 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 15048926793 ps |
| CPU time | 41.58 seconds |
| Started | Jan 03 12:38:43 PM PST 24 |
| Finished | Jan 03 12:40:32 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-6c468c32-74cb-4ee4-877a-180a4ad7eee8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4212719742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.4212719742 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.148615063 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 53376730 ps |
| CPU time | 4.06 seconds |
| Started | Jan 03 12:38:07 PM PST 24 |
| Finished | Jan 03 12:39:23 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-67e1f968-24a7-4a52-a64c-defafc0c2ba6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=148615063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.148615063 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.1098728482 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 72224931 ps |
| CPU time | 6.17 seconds |
| Started | Jan 03 12:38:35 PM PST 24 |
| Finished | Jan 03 12:39:51 PM PST 24 |
| Peak memory | 201260 kb |
| Host | smart-b27cacc7-30e9-4a39-8e86-3254e645fd33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1098728482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1098728482 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.798282669 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 98190494777 ps |
| CPU time | 110.73 seconds |
| Started | Jan 03 12:38:03 PM PST 24 |
| Finished | Jan 03 12:41:09 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-6194efb4-9403-4637-b89d-2d62f32b97c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=798282669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.798282669 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.207426822 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2976790383 ps |
| CPU time | 6.47 seconds |
| Started | Jan 03 12:38:18 PM PST 24 |
| Finished | Jan 03 12:40:27 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-a07a935d-a448-43ef-9b46-913e5a45cb4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=207426822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.207426822 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1908631239 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 114435344 ps |
| CPU time | 7.67 seconds |
| Started | Jan 03 12:38:05 PM PST 24 |
| Finished | Jan 03 12:39:29 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-3dbba9b7-00dd-4cde-9cb1-2fe6ab8a43ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908631239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1908631239 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.1925566961 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 195160204 ps |
| CPU time | 5.53 seconds |
| Started | Jan 03 12:38:35 PM PST 24 |
| Finished | Jan 03 12:39:51 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-394c8add-9b3f-4dd0-b756-57a9a497414c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1925566961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1925566961 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.1784802929 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 129492057 ps |
| CPU time | 1.3 seconds |
| Started | Jan 03 12:38:04 PM PST 24 |
| Finished | Jan 03 12:39:34 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-dc6a0ee2-8b6b-4d04-88a8-d44cd274e8e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1784802929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1784802929 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.397938736 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3963160606 ps |
| CPU time | 7.14 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:42 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-8baf0341-163d-4fa7-9c05-f80c57252a9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=397938736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.397938736 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.4231032563 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2479728448 ps |
| CPU time | 9.06 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:39 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-c6dcb2c7-0c49-4d64-8267-8c391eacf3ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4231032563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.4231032563 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3700736062 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11108413 ps |
| CPU time | 1.29 seconds |
| Started | Jan 03 12:37:55 PM PST 24 |
| Finished | Jan 03 12:39:11 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-bdc571cb-b0c3-4e12-8949-3e0e82fc0e2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700736062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3700736062 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2492459967 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 7027765404 ps |
| CPU time | 64.78 seconds |
| Started | Jan 03 12:37:57 PM PST 24 |
| Finished | Jan 03 12:40:17 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-bf2f6096-fd3a-4626-a041-d146a4f908c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2492459967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2492459967 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.525398594 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 420015111 ps |
| CPU time | 27.55 seconds |
| Started | Jan 03 12:38:51 PM PST 24 |
| Finished | Jan 03 12:40:37 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-fcc5fd41-8137-423d-9c0b-6d89f9ded723 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=525398594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.525398594 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3224911827 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 942586080 ps |
| CPU time | 62.53 seconds |
| Started | Jan 03 12:38:19 PM PST 24 |
| Finished | Jan 03 12:40:35 PM PST 24 |
| Peak memory | 203876 kb |
| Host | smart-d5278344-b97d-4e2f-b118-7349413c1a7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3224911827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.3224911827 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.903561031 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2605775483 ps |
| CPU time | 109.38 seconds |
| Started | Jan 03 12:38:35 PM PST 24 |
| Finished | Jan 03 12:42:25 PM PST 24 |
| Peak memory | 207260 kb |
| Host | smart-d16886c6-64e6-4b5a-b05a-86c57c46d3c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=903561031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese t_error.903561031 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.274861118 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 213389975 ps |
| CPU time | 3.48 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:46 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-23077d3e-e6bd-4994-9230-ce947055a571 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=274861118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.274861118 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.1505145888 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 151903677 ps |
| CPU time | 3.08 seconds |
| Started | Jan 03 12:38:43 PM PST 24 |
| Finished | Jan 03 12:39:57 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-38cc1cc7-79c3-4b92-8ff7-48b231145724 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1505145888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1505145888 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3594320678 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 98496172967 ps |
| CPU time | 324.53 seconds |
| Started | Jan 03 12:38:27 PM PST 24 |
| Finished | Jan 03 12:45:14 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-2b525210-7581-466a-a405-9af5e353c923 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3594320678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.3594320678 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.4113636801 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 19245240 ps |
| CPU time | 1.55 seconds |
| Started | Jan 03 12:38:26 PM PST 24 |
| Finished | Jan 03 12:39:39 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-c3102ccc-634c-4b3e-8a51-c19384bbc651 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4113636801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.4113636801 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.3052576657 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1609718001 ps |
| CPU time | 6.87 seconds |
| Started | Jan 03 12:38:33 PM PST 24 |
| Finished | Jan 03 12:39:55 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-90ad3e97-93ad-4508-b92d-99c2736a34b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3052576657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3052576657 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.3165815773 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 618738221 ps |
| CPU time | 6.94 seconds |
| Started | Jan 03 12:38:22 PM PST 24 |
| Finished | Jan 03 12:39:42 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-f21f7a48-066b-455d-b7c5-ef531a2679c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3165815773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3165815773 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1896076980 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 15365751619 ps |
| CPU time | 30.89 seconds |
| Started | Jan 03 12:38:29 PM PST 24 |
| Finished | Jan 03 12:40:15 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-a8eb0b2b-8a96-4916-b504-ecddfa5db551 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896076980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1896076980 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2010725288 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 3223823193 ps |
| CPU time | 17.15 seconds |
| Started | Jan 03 12:38:38 PM PST 24 |
| Finished | Jan 03 12:40:05 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-e6312d80-0945-4707-94b6-2fca4a24a97e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2010725288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2010725288 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1472188119 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 17184839 ps |
| CPU time | 1.7 seconds |
| Started | Jan 03 12:38:23 PM PST 24 |
| Finished | Jan 03 12:39:49 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-480b12fd-4dc8-4078-a8da-8938f5c21e43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472188119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1472188119 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.3222293980 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 43998082 ps |
| CPU time | 4.77 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:40:12 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-6700bdae-8ff9-414c-ab63-806cef9f49e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3222293980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3222293980 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.2964161370 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 70286122 ps |
| CPU time | 1.7 seconds |
| Started | Jan 03 12:38:20 PM PST 24 |
| Finished | Jan 03 12:39:49 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-44e7d11d-097e-4dff-9118-ee8088e73822 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2964161370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2964161370 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.917752930 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4678774850 ps |
| CPU time | 10.01 seconds |
| Started | Jan 03 12:38:08 PM PST 24 |
| Finished | Jan 03 12:39:45 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-66c68685-a447-412f-8dfc-132d0cf276bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=917752930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.917752930 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2779094814 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 890124452 ps |
| CPU time | 7.58 seconds |
| Started | Jan 03 12:38:18 PM PST 24 |
| Finished | Jan 03 12:39:40 PM PST 24 |
| Peak memory | 201280 kb |
| Host | smart-2dfb46ab-dd05-443e-831e-30725e45d857 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2779094814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2779094814 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3422974677 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 7991928 ps |
| CPU time | 1.02 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:31 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-045ab37a-9431-446a-a638-41d1eeda6681 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422974677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3422974677 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1941621505 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 9697991431 ps |
| CPU time | 70.06 seconds |
| Started | Jan 03 12:38:18 PM PST 24 |
| Finished | Jan 03 12:40:56 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-f481fc7a-6633-4362-8cb3-eaa5bedda279 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1941621505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1941621505 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1732551114 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1924831791 ps |
| CPU time | 12.75 seconds |
| Started | Jan 03 12:38:22 PM PST 24 |
| Finished | Jan 03 12:40:04 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-3083331e-9c29-4540-8346-4d18ed8e6c44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1732551114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1732551114 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3128979404 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 467134742 ps |
| CPU time | 34.99 seconds |
| Started | Jan 03 12:39:04 PM PST 24 |
| Finished | Jan 03 12:41:14 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-1a2f8541-9375-42fd-88a1-813e586dfa9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3128979404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.3128979404 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1834366246 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1813550767 ps |
| CPU time | 83.64 seconds |
| Started | Jan 03 12:38:22 PM PST 24 |
| Finished | Jan 03 12:41:12 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-76333f0d-0e46-4edc-8887-0cf297a9fba7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1834366246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.1834366246 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.881423581 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 106975258 ps |
| CPU time | 5.38 seconds |
| Started | Jan 03 12:38:26 PM PST 24 |
| Finished | Jan 03 12:39:46 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-f9847f25-b380-4948-bceb-ace1be008c4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=881423581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.881423581 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1901619504 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 74529364 ps |
| CPU time | 10.61 seconds |
| Started | Jan 03 12:38:30 PM PST 24 |
| Finished | Jan 03 12:39:58 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-f6a59e01-28b4-4937-a39e-415f3dd0bfc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1901619504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1901619504 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1785008846 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 30794564879 ps |
| CPU time | 61.17 seconds |
| Started | Jan 03 12:38:41 PM PST 24 |
| Finished | Jan 03 12:42:26 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-68f7e63c-55e0-46b6-9e27-6344ffba1852 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1785008846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.1785008846 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2730420380 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1989870927 ps |
| CPU time | 9.39 seconds |
| Started | Jan 03 12:38:16 PM PST 24 |
| Finished | Jan 03 12:39:40 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-f18babdc-129d-4779-89bc-0e28f01bea95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2730420380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2730420380 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.696032044 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 569117871 ps |
| CPU time | 9.61 seconds |
| Started | Jan 03 12:38:27 PM PST 24 |
| Finished | Jan 03 12:39:54 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-dc186a77-3e74-434c-b435-07ae27634d89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=696032044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.696032044 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3523535450 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 26713565940 ps |
| CPU time | 96.62 seconds |
| Started | Jan 03 12:38:25 PM PST 24 |
| Finished | Jan 03 12:41:18 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-5e055128-8751-4d1a-89bb-5af9d44205e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523535450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3523535450 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4228240139 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 25550457401 ps |
| CPU time | 33 seconds |
| Started | Jan 03 12:38:18 PM PST 24 |
| Finished | Jan 03 12:40:19 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-c7a81a77-8f2c-4f9d-86ae-d6665214f090 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4228240139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4228240139 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1200869229 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 109576270 ps |
| CPU time | 3.47 seconds |
| Started | Jan 03 12:38:43 PM PST 24 |
| Finished | Jan 03 12:39:54 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-8b93e506-88d0-4157-bf8e-4afef3b270de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200869229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1200869229 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.1452022688 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 817628559 ps |
| CPU time | 9.16 seconds |
| Started | Jan 03 12:38:53 PM PST 24 |
| Finished | Jan 03 12:40:27 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-2719827c-cf67-426b-ba67-e68344c681fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1452022688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1452022688 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.540662901 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 45668711 ps |
| CPU time | 1.49 seconds |
| Started | Jan 03 12:38:29 PM PST 24 |
| Finished | Jan 03 12:39:45 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-7adacfdd-5439-46bb-b56b-83a3ecc4f135 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=540662901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.540662901 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.452709368 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2025929795 ps |
| CPU time | 7.87 seconds |
| Started | Jan 03 12:38:25 PM PST 24 |
| Finished | Jan 03 12:39:49 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-2595f1a0-a8e0-4778-b826-c6f47b5e6ea2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=452709368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.452709368 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2742342740 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 919117064 ps |
| CPU time | 5.22 seconds |
| Started | Jan 03 12:38:42 PM PST 24 |
| Finished | Jan 03 12:40:05 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-3c504a28-e28d-420a-8de8-0a5a931aab14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2742342740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2742342740 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.1148303156 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 9630186 ps |
| CPU time | 1.24 seconds |
| Started | Jan 03 12:38:26 PM PST 24 |
| Finished | Jan 03 12:39:38 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-463056a4-6a6e-4a4a-8ed2-bc8ae61f6956 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148303156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.1148303156 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.3609394515 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2470064128 ps |
| CPU time | 26.1 seconds |
| Started | Jan 03 12:38:44 PM PST 24 |
| Finished | Jan 03 12:40:29 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-1def054a-a621-4ecb-be60-840cd98d2375 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3609394515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3609394515 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.189105073 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1510111762 ps |
| CPU time | 46.59 seconds |
| Started | Jan 03 12:38:21 PM PST 24 |
| Finished | Jan 03 12:40:33 PM PST 24 |
| Peak memory | 204136 kb |
| Host | smart-d83139ba-a2ae-43c4-99c4-9f9b60b8c3bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=189105073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_ reset.189105073 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2273523663 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 4897791934 ps |
| CPU time | 130.71 seconds |
| Started | Jan 03 12:38:28 PM PST 24 |
| Finished | Jan 03 12:41:51 PM PST 24 |
| Peak memory | 205860 kb |
| Host | smart-b89d83bb-8fa5-4d9b-8722-0a24dcc9e27d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2273523663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.2273523663 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2395251963 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 78325625 ps |
| CPU time | 4.82 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:36 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-ef6bb073-7997-4832-a8b9-520a7a1172b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2395251963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2395251963 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.2281676316 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 26351888 ps |
| CPU time | 3.46 seconds |
| Started | Jan 03 12:38:27 PM PST 24 |
| Finished | Jan 03 12:39:48 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-a6f61679-ae8f-47d5-a101-158be4815d0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2281676316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2281676316 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3189022569 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 10007000949 ps |
| CPU time | 19.35 seconds |
| Started | Jan 03 12:38:17 PM PST 24 |
| Finished | Jan 03 12:39:53 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-cffced3f-6912-4de4-87a4-fba16eeb20dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3189022569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.3189022569 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3056908733 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 92299293 ps |
| CPU time | 5.53 seconds |
| Started | Jan 03 12:38:22 PM PST 24 |
| Finished | Jan 03 12:39:55 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-0ec94a9c-dbea-4d32-9eef-75d3729e2eb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3056908733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3056908733 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.2896838228 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 112280120 ps |
| CPU time | 6.17 seconds |
| Started | Jan 03 12:38:18 PM PST 24 |
| Finished | Jan 03 12:40:35 PM PST 24 |
| Peak memory | 201264 kb |
| Host | smart-a690c0b4-b279-4afd-a5cf-9cdb290f6694 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2896838228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2896838228 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.394755330 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 559421715 ps |
| CPU time | 9.26 seconds |
| Started | Jan 03 12:38:42 PM PST 24 |
| Finished | Jan 03 12:39:59 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-79946c6a-4308-4963-8755-d3ab246d18d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=394755330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.394755330 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.4107649932 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 131187766705 ps |
| CPU time | 81.98 seconds |
| Started | Jan 03 12:38:25 PM PST 24 |
| Finished | Jan 03 12:41:03 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-46f0d413-110d-4e75-a832-9beb0a8b172d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107649932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.4107649932 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.316380532 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4615968262 ps |
| CPU time | 28.87 seconds |
| Started | Jan 03 12:38:18 PM PST 24 |
| Finished | Jan 03 12:40:01 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-38bdacb8-de3c-4263-9a90-d481d9664743 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=316380532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.316380532 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1691913511 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 64706370 ps |
| CPU time | 8.7 seconds |
| Started | Jan 03 12:38:43 PM PST 24 |
| Finished | Jan 03 12:40:12 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-fae4cb02-506e-4daa-a553-9faa63431503 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691913511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1691913511 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.2354218457 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 950708070 ps |
| CPU time | 8.85 seconds |
| Started | Jan 03 12:38:14 PM PST 24 |
| Finished | Jan 03 12:39:36 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-8e5d19b3-8fc5-41d4-9646-3f1b46f25c12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2354218457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2354218457 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.3710155646 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 243456890 ps |
| CPU time | 1.7 seconds |
| Started | Jan 03 12:38:18 PM PST 24 |
| Finished | Jan 03 12:39:47 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-baea6c1f-b9b6-499a-b4eb-b9ec70a450ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3710155646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3710155646 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.4178171371 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1986952316 ps |
| CPU time | 8.1 seconds |
| Started | Jan 03 12:38:48 PM PST 24 |
| Finished | Jan 03 12:40:19 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-692db528-a58d-4c9a-b743-21a82ee8192f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178171371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.4178171371 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2565575808 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 945938623 ps |
| CPU time | 6.85 seconds |
| Started | Jan 03 12:38:25 PM PST 24 |
| Finished | Jan 03 12:39:48 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-c443aecc-4b8c-44f9-b12f-f968aff1e0ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2565575808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2565575808 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3861617250 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 10016595 ps |
| CPU time | 1.18 seconds |
| Started | Jan 03 12:38:20 PM PST 24 |
| Finished | Jan 03 12:39:40 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-807d5c2e-13ff-436e-895a-2bf3e472910c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861617250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3861617250 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.2344559222 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 156731450 ps |
| CPU time | 14.18 seconds |
| Started | Jan 03 12:38:01 PM PST 24 |
| Finished | Jan 03 12:39:30 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-af0a7baa-295d-4687-a6c7-ff97b213f735 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2344559222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2344559222 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4055806406 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 12293372200 ps |
| CPU time | 92.53 seconds |
| Started | Jan 03 12:38:05 PM PST 24 |
| Finished | Jan 03 12:41:02 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-64ccdf8f-10ed-4616-b19c-95cd87bd8a96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4055806406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4055806406 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1690164435 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 633122261 ps |
| CPU time | 75.68 seconds |
| Started | Jan 03 12:38:55 PM PST 24 |
| Finished | Jan 03 12:41:38 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-a55a9c0a-0b25-443b-8aa9-4a84224069af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1690164435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.1690164435 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1920523467 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 6011022434 ps |
| CPU time | 47.87 seconds |
| Started | Jan 03 12:38:29 PM PST 24 |
| Finished | Jan 03 12:40:28 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-0654515e-71a0-4c85-92fe-f443ef80154e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1920523467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.1920523467 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1153743829 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 350902762 ps |
| CPU time | 6.82 seconds |
| Started | Jan 03 12:38:29 PM PST 24 |
| Finished | Jan 03 12:39:55 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-6284524b-9965-43b4-9eea-a0a8ac1f01d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1153743829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1153743829 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.3008016618 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 8769183123 ps |
| CPU time | 20.73 seconds |
| Started | Jan 03 12:38:23 PM PST 24 |
| Finished | Jan 03 12:40:05 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-e77e3f98-c235-4b25-89c4-2f8e17280080 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3008016618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3008016618 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1516685907 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 60851206114 ps |
| CPU time | 89.31 seconds |
| Started | Jan 03 12:38:14 PM PST 24 |
| Finished | Jan 03 12:41:01 PM PST 24 |
| Peak memory | 201624 kb |
| Host | smart-4eef4c04-953c-4885-a0d2-e490addb4378 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1516685907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.1516685907 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3151575425 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 151358888 ps |
| CPU time | 2.37 seconds |
| Started | Jan 03 12:38:51 PM PST 24 |
| Finished | Jan 03 12:40:03 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-5c1cf46e-eb18-4898-af39-450c449391fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3151575425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3151575425 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.4116165440 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 48596968 ps |
| CPU time | 3.57 seconds |
| Started | Jan 03 12:38:28 PM PST 24 |
| Finished | Jan 03 12:40:14 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-4bb9dbf5-3fa4-4ed4-8d30-f00bf52a2c54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4116165440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.4116165440 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.1052811375 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 148032801 ps |
| CPU time | 1.65 seconds |
| Started | Jan 03 12:38:14 PM PST 24 |
| Finished | Jan 03 12:39:29 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-51c8a311-f50d-45ab-ba99-7ff4da1c48a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1052811375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1052811375 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.773611450 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 17668478747 ps |
| CPU time | 36.05 seconds |
| Started | Jan 03 12:38:40 PM PST 24 |
| Finished | Jan 03 12:40:46 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-5bc08b0b-ca68-4029-b29e-8d9e994acaa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=773611450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.773611450 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2610259590 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2541231756 ps |
| CPU time | 13.96 seconds |
| Started | Jan 03 12:38:19 PM PST 24 |
| Finished | Jan 03 12:39:53 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-b8085157-2469-4769-9548-6486ea3f7e25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2610259590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2610259590 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.289879816 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 210140518 ps |
| CPU time | 8.71 seconds |
| Started | Jan 03 12:38:15 PM PST 24 |
| Finished | Jan 03 12:39:40 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-3601e2c6-f88b-4b30-8d37-a6d940bfa860 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289879816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.289879816 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.2758637261 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 197228859 ps |
| CPU time | 3.98 seconds |
| Started | Jan 03 12:38:57 PM PST 24 |
| Finished | Jan 03 12:40:25 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-654c9367-6b58-442b-94bd-5ae07005994d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2758637261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2758637261 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.777119987 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 175327695 ps |
| CPU time | 1.48 seconds |
| Started | Jan 03 12:38:19 PM PST 24 |
| Finished | Jan 03 12:39:37 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-ae525d2a-8bc2-47e8-96c5-ba87cf82d8ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=777119987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.777119987 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3558158953 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1302393671 ps |
| CPU time | 8.56 seconds |
| Started | Jan 03 12:38:33 PM PST 24 |
| Finished | Jan 03 12:39:55 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-9fd64cf0-ff4a-4683-807c-f96694e22c50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3558158953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3558158953 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3804787367 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 15648603 ps |
| CPU time | 1.14 seconds |
| Started | Jan 03 12:38:22 PM PST 24 |
| Finished | Jan 03 12:39:36 PM PST 24 |
| Peak memory | 201304 kb |
| Host | smart-37dd8b77-4e5e-4dad-9ec4-79a42d6ac36f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804787367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3804787367 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3477759478 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 952652434 ps |
| CPU time | 26.76 seconds |
| Started | Jan 03 12:38:30 PM PST 24 |
| Finished | Jan 03 12:40:11 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-5f1c6c36-817f-45a1-af6d-90633770a581 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3477759478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3477759478 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.4256129719 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1803653600 ps |
| CPU time | 24.62 seconds |
| Started | Jan 03 12:38:18 PM PST 24 |
| Finished | Jan 03 12:40:36 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-bcd54839-8298-413c-8613-16e8de2cd6ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4256129719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.4256129719 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2827951916 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 6508107617 ps |
| CPU time | 143.48 seconds |
| Started | Jan 03 12:38:24 PM PST 24 |
| Finished | Jan 03 12:42:18 PM PST 24 |
| Peak memory | 204532 kb |
| Host | smart-675081cd-dfac-43fc-a027-6f7b218f3a0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2827951916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.2827951916 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.930315238 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 977413111 ps |
| CPU time | 78.85 seconds |
| Started | Jan 03 12:38:08 PM PST 24 |
| Finished | Jan 03 12:40:43 PM PST 24 |
| Peak memory | 204940 kb |
| Host | smart-66133cb3-8266-49d8-83ec-16f8ccd7de29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=930315238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese t_error.930315238 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1811440353 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 766262296 ps |
| CPU time | 11.73 seconds |
| Started | Jan 03 12:38:40 PM PST 24 |
| Finished | Jan 03 12:40:21 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-803a0fbe-9690-420b-8294-bd388932d6b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1811440353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1811440353 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |