| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.28 | 100.00 | 95.71 | 100.00 | 100.00 | 100.00 | 100.00 |
| T761 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1123953903 | Jan 07 01:40:25 PM PST 24 | Jan 07 01:42:49 PM PST 24 | 2439944078 ps | ||
| T762 | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1742147995 | Jan 07 01:39:36 PM PST 24 | Jan 07 01:39:55 PM PST 24 | 1016262985 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.2979817497 | Jan 07 01:39:52 PM PST 24 | Jan 07 01:41:07 PM PST 24 | 1509062956 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.4646131 | Jan 07 01:37:59 PM PST 24 | Jan 07 01:38:12 PM PST 24 | 3287655997 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/41.xbar_same_source.2974172507 | Jan 07 01:40:20 PM PST 24 | Jan 07 01:40:49 PM PST 24 | 398362736 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.89787784 | Jan 07 01:39:42 PM PST 24 | Jan 07 01:40:03 PM PST 24 | 138233682 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2664694589 | Jan 07 01:39:26 PM PST 24 | Jan 07 01:39:41 PM PST 24 | 555364479 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3549800000 | Jan 07 01:40:17 PM PST 24 | Jan 07 01:40:48 PM PST 24 | 719145383 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3734506821 | Jan 07 01:37:53 PM PST 24 | Jan 07 01:40:26 PM PST 24 | 1381614587 ps | ||
| T116 | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2322275452 | Jan 07 01:39:46 PM PST 24 | Jan 07 01:40:18 PM PST 24 | 1510115498 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/24.xbar_error_random.3752934997 | Jan 07 01:38:31 PM PST 24 | Jan 07 01:38:40 PM PST 24 | 66629221 ps | ||
| T105 | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.44742398 | Jan 07 01:38:49 PM PST 24 | Jan 07 01:41:27 PM PST 24 | 30498427864 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/45.xbar_same_source.2863355435 | Jan 07 01:40:09 PM PST 24 | Jan 07 01:40:48 PM PST 24 | 2267133749 ps | ||
| T97 | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.411894194 | Jan 07 01:40:11 PM PST 24 | Jan 07 01:45:35 PM PST 24 | 53939631904 ps | ||
| T135 | /workspace/coverage/xbar_build_mode/38.xbar_random.2224292396 | Jan 07 01:39:39 PM PST 24 | Jan 07 01:40:05 PM PST 24 | 839133131 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.4082705370 | Jan 07 01:38:46 PM PST 24 | Jan 07 01:39:37 PM PST 24 | 2749100153 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3249161761 | Jan 07 01:39:36 PM PST 24 | Jan 07 01:39:58 PM PST 24 | 2260786612 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2740920163 | Jan 07 01:39:44 PM PST 24 | Jan 07 01:40:09 PM PST 24 | 66008894 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3569434023 | Jan 07 01:38:48 PM PST 24 | Jan 07 01:38:54 PM PST 24 | 115486342 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/22.xbar_same_source.342779863 | Jan 07 01:39:45 PM PST 24 | Jan 07 01:40:07 PM PST 24 | 93740750 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3949818103 | Jan 07 01:37:46 PM PST 24 | Jan 07 01:38:59 PM PST 24 | 654470098 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1951882368 | Jan 07 01:40:19 PM PST 24 | Jan 07 01:40:46 PM PST 24 | 23737833 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3379282878 | Jan 07 01:39:25 PM PST 24 | Jan 07 01:39:59 PM PST 24 | 258168569 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/9.xbar_smoke.1258446739 | Jan 07 01:38:51 PM PST 24 | Jan 07 01:38:54 PM PST 24 | 10593460 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/21.xbar_error_random.4255584348 | Jan 07 01:38:49 PM PST 24 | Jan 07 01:38:54 PM PST 24 | 66708495 ps | ||
| T155 | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.2022787986 | Jan 07 01:39:48 PM PST 24 | Jan 07 01:40:53 PM PST 24 | 14523146079 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2096969745 | Jan 07 01:40:35 PM PST 24 | Jan 07 01:42:45 PM PST 24 | 7060456718 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2212753150 | Jan 07 01:39:46 PM PST 24 | Jan 07 01:40:28 PM PST 24 | 422118305 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/42.xbar_error_random.4078131940 | Jan 07 01:39:28 PM PST 24 | Jan 07 01:39:43 PM PST 24 | 91436502 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.4143802125 | Jan 07 01:39:18 PM PST 24 | Jan 07 01:39:59 PM PST 24 | 10602440625 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.3813164664 | Jan 07 01:38:54 PM PST 24 | Jan 07 01:39:49 PM PST 24 | 12989763734 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2980524758 | Jan 07 01:39:33 PM PST 24 | Jan 07 01:39:48 PM PST 24 | 83534631 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3538293168 | Jan 07 01:46:04 PM PST 24 | Jan 07 01:47:03 PM PST 24 | 4508691042 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/25.xbar_same_source.1939077450 | Jan 07 01:39:47 PM PST 24 | Jan 07 01:40:16 PM PST 24 | 1087678678 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1478533367 | Jan 07 01:38:09 PM PST 24 | Jan 07 01:38:19 PM PST 24 | 3653848852 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.548490177 | Jan 07 01:39:58 PM PST 24 | Jan 07 01:40:38 PM PST 24 | 17533095031 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.2427057601 | Jan 07 01:39:50 PM PST 24 | Jan 07 01:40:16 PM PST 24 | 52773574 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.460629658 | Jan 07 01:40:36 PM PST 24 | Jan 07 01:42:04 PM PST 24 | 329007249 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1670012575 | Jan 07 01:39:39 PM PST 24 | Jan 07 01:40:06 PM PST 24 | 2752041783 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/0.xbar_same_source.3938256518 | Jan 07 01:38:51 PM PST 24 | Jan 07 01:39:00 PM PST 24 | 573379434 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/8.xbar_smoke.1976507778 | Jan 07 01:39:44 PM PST 24 | Jan 07 01:40:02 PM PST 24 | 47958183 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2320438555 | Jan 07 01:40:22 PM PST 24 | Jan 07 01:41:53 PM PST 24 | 30692162550 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2930485246 | Jan 07 01:39:40 PM PST 24 | Jan 07 01:39:56 PM PST 24 | 10527362 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1070878722 | Jan 07 01:39:23 PM PST 24 | Jan 07 01:39:57 PM PST 24 | 18398515479 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2622555314 | Jan 07 01:39:48 PM PST 24 | Jan 07 01:42:18 PM PST 24 | 194582016323 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/29.xbar_error_random.626199841 | Jan 07 01:39:27 PM PST 24 | Jan 07 01:39:46 PM PST 24 | 4780437804 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.4070057856 | Jan 07 01:38:54 PM PST 24 | Jan 07 01:40:08 PM PST 24 | 21098153095 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2730889304 | Jan 07 01:40:00 PM PST 24 | Jan 07 01:41:07 PM PST 24 | 3812041666 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.4134409452 | Jan 07 01:39:53 PM PST 24 | Jan 07 01:40:20 PM PST 24 | 34232282 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.51356861 | Jan 07 01:38:42 PM PST 24 | Jan 07 01:38:49 PM PST 24 | 145499865 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.740454521 | Jan 07 01:39:54 PM PST 24 | Jan 07 01:40:25 PM PST 24 | 1623595330 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3769050494 | Jan 07 01:43:12 PM PST 24 | Jan 07 01:44:24 PM PST 24 | 29103449351 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2479398358 | Jan 07 01:40:12 PM PST 24 | Jan 07 01:41:06 PM PST 24 | 1998987522 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2769950899 | Jan 07 01:39:49 PM PST 24 | Jan 07 01:45:11 PM PST 24 | 199934827804 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1721711569 | Jan 07 01:38:54 PM PST 24 | Jan 07 01:39:34 PM PST 24 | 380962091 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2786805794 | Jan 07 01:39:32 PM PST 24 | Jan 07 01:41:32 PM PST 24 | 7052896395 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3102096101 | Jan 07 01:38:29 PM PST 24 | Jan 07 01:38:41 PM PST 24 | 47275916 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.186991354 | Jan 07 01:40:42 PM PST 24 | Jan 07 01:41:18 PM PST 24 | 1808516750 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1850812824 | Jan 07 01:40:00 PM PST 24 | Jan 07 01:41:10 PM PST 24 | 5007662845 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/44.xbar_same_source.931879751 | Jan 07 01:39:56 PM PST 24 | Jan 07 01:40:25 PM PST 24 | 287795102 ps | ||
| T12 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.339426579 | Jan 07 01:39:53 PM PST 24 | Jan 07 01:44:00 PM PST 24 | 2080809646 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1742235755 | Jan 07 01:39:53 PM PST 24 | Jan 07 01:40:30 PM PST 24 | 7445624610 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.52281083 | Jan 07 01:40:41 PM PST 24 | Jan 07 01:41:15 PM PST 24 | 100351180 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3104604046 | Jan 07 01:40:15 PM PST 24 | Jan 07 01:42:26 PM PST 24 | 67268460491 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3109747404 | Jan 07 01:39:14 PM PST 24 | Jan 07 01:39:23 PM PST 24 | 1739705819 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1749164712 | Jan 07 01:38:39 PM PST 24 | Jan 07 01:38:57 PM PST 24 | 2288726620 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/41.xbar_smoke.3342260715 | Jan 07 01:39:46 PM PST 24 | Jan 07 01:40:05 PM PST 24 | 89313274 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2902176477 | Jan 07 01:40:21 PM PST 24 | Jan 07 01:40:49 PM PST 24 | 196268950 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3329028779 | Jan 07 01:39:21 PM PST 24 | Jan 07 01:40:20 PM PST 24 | 13326434737 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/43.xbar_error_random.3683035247 | Jan 07 01:39:47 PM PST 24 | Jan 07 01:40:09 PM PST 24 | 44758224 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.734774954 | Jan 07 01:39:55 PM PST 24 | Jan 07 01:41:22 PM PST 24 | 3923537928 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/49.xbar_smoke.3201594146 | Jan 07 01:40:20 PM PST 24 | Jan 07 01:40:51 PM PST 24 | 49364420 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.330071479 | Jan 07 01:38:28 PM PST 24 | Jan 07 01:38:37 PM PST 24 | 6954954432 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1224887510 | Jan 07 01:39:31 PM PST 24 | Jan 07 01:41:02 PM PST 24 | 32800140554 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.587079272 | Jan 07 01:39:30 PM PST 24 | Jan 07 01:41:29 PM PST 24 | 81205756791 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2465604180 | Jan 07 01:39:53 PM PST 24 | Jan 07 01:41:08 PM PST 24 | 6240137981 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2888055373 | Jan 07 01:39:49 PM PST 24 | Jan 07 01:41:00 PM PST 24 | 446701578 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3097417585 | Jan 07 01:40:21 PM PST 24 | Jan 07 01:40:55 PM PST 24 | 70750325 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.2214962902 | Jan 07 01:38:41 PM PST 24 | Jan 07 01:38:50 PM PST 24 | 53948857 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3874880295 | Jan 07 01:40:20 PM PST 24 | Jan 07 01:40:54 PM PST 24 | 1470008058 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.49211247 | Jan 07 01:39:19 PM PST 24 | Jan 07 01:40:35 PM PST 24 | 6004567498 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/43.xbar_random.1695115654 | Jan 07 01:39:37 PM PST 24 | Jan 07 01:40:05 PM PST 24 | 889047599 ps | ||
| T98 | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3705343573 | Jan 07 01:38:42 PM PST 24 | Jan 07 01:38:46 PM PST 24 | 159329429 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1547634430 | Jan 07 01:39:41 PM PST 24 | Jan 07 01:40:05 PM PST 24 | 9404867000 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.180948451 | Jan 07 01:39:49 PM PST 24 | Jan 07 01:40:22 PM PST 24 | 4008607663 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2749730512 | Jan 07 01:41:38 PM PST 24 | Jan 07 01:41:52 PM PST 24 | 126178129 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1861539873 | Jan 07 01:39:50 PM PST 24 | Jan 07 01:40:20 PM PST 24 | 324254528 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2005542306 | Jan 07 01:39:37 PM PST 24 | Jan 07 01:41:26 PM PST 24 | 27206608340 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1740744617 | Jan 07 01:39:58 PM PST 24 | Jan 07 01:41:05 PM PST 24 | 14861378840 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3673673023 | Jan 07 01:40:27 PM PST 24 | Jan 07 01:40:53 PM PST 24 | 227063775 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.890477849 | Jan 07 01:39:05 PM PST 24 | Jan 07 01:39:08 PM PST 24 | 15768201 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.41125504 | Jan 07 01:39:48 PM PST 24 | Jan 07 01:40:14 PM PST 24 | 981522008 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1721424552 | Jan 07 01:38:49 PM PST 24 | Jan 07 01:44:27 PM PST 24 | 67948254101 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/16.xbar_same_source.695568487 | Jan 07 01:40:33 PM PST 24 | Jan 07 01:41:05 PM PST 24 | 49114254 ps | ||
| T147 | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2599854941 | Jan 07 01:39:39 PM PST 24 | Jan 07 01:42:53 PM PST 24 | 192300408611 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/33.xbar_same_source.972030371 | Jan 07 01:40:17 PM PST 24 | Jan 07 01:40:48 PM PST 24 | 611450117 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/2.xbar_error_random.1226529808 | Jan 07 01:38:43 PM PST 24 | Jan 07 01:38:52 PM PST 24 | 206938938 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.4102455068 | Jan 07 01:38:01 PM PST 24 | Jan 07 01:38:13 PM PST 24 | 2285971747 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.301717054 | Jan 07 01:39:38 PM PST 24 | Jan 07 01:40:02 PM PST 24 | 940228040 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.497280763 | Jan 07 01:38:57 PM PST 24 | Jan 07 01:39:59 PM PST 24 | 6036631481 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3841513593 | Jan 07 01:39:32 PM PST 24 | Jan 07 01:41:44 PM PST 24 | 39443492477 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.512646486 | Jan 07 01:39:05 PM PST 24 | Jan 07 01:39:09 PM PST 24 | 34974585 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1420983976 | Jan 07 01:39:44 PM PST 24 | Jan 07 01:40:09 PM PST 24 | 1507271278 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2230002948 | Jan 07 01:39:37 PM PST 24 | Jan 07 01:42:06 PM PST 24 | 4020849391 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.838203431 | Jan 07 01:39:04 PM PST 24 | Jan 07 01:40:30 PM PST 24 | 48435356779 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/12.xbar_error_random.3484992939 | Jan 07 01:39:43 PM PST 24 | Jan 07 01:40:12 PM PST 24 | 57711176 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2662425687 | Jan 07 01:40:03 PM PST 24 | Jan 07 01:40:42 PM PST 24 | 1072036894 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1969824235 | Jan 07 01:38:43 PM PST 24 | Jan 07 01:38:52 PM PST 24 | 2650125160 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2496324644 | Jan 07 01:40:11 PM PST 24 | Jan 07 01:40:47 PM PST 24 | 813905856 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/6.xbar_same_source.1149488313 | Jan 07 01:38:54 PM PST 24 | Jan 07 01:39:00 PM PST 24 | 467609445 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1528425940 | Jan 07 01:39:47 PM PST 24 | Jan 07 01:41:00 PM PST 24 | 440061423 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1396062114 | Jan 07 01:38:44 PM PST 24 | Jan 07 01:38:54 PM PST 24 | 2607891425 ps | ||
| T103 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2600003946 | Jan 07 01:39:40 PM PST 24 | Jan 07 01:43:32 PM PST 24 | 65483938535 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.629510380 | Jan 07 01:40:36 PM PST 24 | Jan 07 01:41:08 PM PST 24 | 121844178 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3544560920 | Jan 07 01:38:38 PM PST 24 | Jan 07 01:39:55 PM PST 24 | 9536195222 ps | ||
| T154 | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3751686891 | Jan 07 01:37:49 PM PST 24 | Jan 07 01:40:48 PM PST 24 | 44557303902 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/38.xbar_error_random.678540657 | Jan 07 01:39:58 PM PST 24 | Jan 07 01:40:40 PM PST 24 | 1781573764 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.1771340785 | Jan 07 01:46:36 PM PST 24 | Jan 07 01:47:33 PM PST 24 | 496740227 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3446396097 | Jan 07 01:46:06 PM PST 24 | Jan 07 01:46:46 PM PST 24 | 11128569 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.923801577 | Jan 07 01:37:52 PM PST 24 | Jan 07 01:37:56 PM PST 24 | 18357562 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/11.xbar_smoke.2975415561 | Jan 07 01:37:59 PM PST 24 | Jan 07 01:38:03 PM PST 24 | 51604659 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2014369808 | Jan 07 01:39:39 PM PST 24 | Jan 07 01:41:46 PM PST 24 | 21380390158 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3807816151 | Jan 07 01:39:38 PM PST 24 | Jan 07 01:40:06 PM PST 24 | 1521837111 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1171825881 | Jan 07 01:38:00 PM PST 24 | Jan 07 01:38:14 PM PST 24 | 10483902526 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2800341189 | Jan 07 01:40:09 PM PST 24 | Jan 07 01:42:15 PM PST 24 | 8250929106 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/6.xbar_error_random.141554033 | Jan 07 01:38:45 PM PST 24 | Jan 07 01:38:48 PM PST 24 | 14107460 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/17.xbar_same_source.1756780197 | Jan 07 01:40:42 PM PST 24 | Jan 07 01:41:22 PM PST 24 | 2715306423 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/45.xbar_random.3379401650 | Jan 07 01:40:17 PM PST 24 | Jan 07 01:40:56 PM PST 24 | 3543664154 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/37.xbar_smoke.2295649158 | Jan 07 01:39:25 PM PST 24 | Jan 07 01:39:32 PM PST 24 | 31331382 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/39.xbar_same_source.2187780377 | Jan 07 01:40:11 PM PST 24 | Jan 07 01:40:42 PM PST 24 | 44962957 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2914846449 | Jan 07 01:39:50 PM PST 24 | Jan 07 01:40:21 PM PST 24 | 1901976367 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2461106450 | Jan 07 01:38:59 PM PST 24 | Jan 07 01:39:08 PM PST 24 | 108730392 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2708988612 | Jan 07 01:39:45 PM PST 24 | Jan 07 01:40:10 PM PST 24 | 3313329180 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2622349274 | Jan 07 01:39:02 PM PST 24 | Jan 07 01:39:41 PM PST 24 | 9046152012 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/46.xbar_smoke.1292904507 | Jan 07 01:40:16 PM PST 24 | Jan 07 01:40:44 PM PST 24 | 14952331 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2538547855 | Jan 07 01:37:15 PM PST 24 | Jan 07 01:38:12 PM PST 24 | 394784318 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.868915029 | Jan 07 01:39:40 PM PST 24 | Jan 07 01:40:05 PM PST 24 | 740049961 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3610702010 | Jan 07 01:39:33 PM PST 24 | Jan 07 01:40:57 PM PST 24 | 5320700670 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/19.xbar_smoke.532721186 | Jan 07 01:38:52 PM PST 24 | Jan 07 01:38:55 PM PST 24 | 275445831 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.3109606909 | Jan 07 01:39:32 PM PST 24 | Jan 07 01:39:45 PM PST 24 | 424066262 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3240593675 | Jan 07 01:39:36 PM PST 24 | Jan 07 01:45:21 PM PST 24 | 119787616204 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1055715502 | Jan 07 01:37:51 PM PST 24 | Jan 07 01:37:55 PM PST 24 | 9814758 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/40.xbar_random.2011522392 | Jan 07 01:39:28 PM PST 24 | Jan 07 01:39:44 PM PST 24 | 3098433288 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1138623756 | Jan 07 01:39:10 PM PST 24 | Jan 07 01:40:05 PM PST 24 | 939797390 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3813246680 | Jan 07 01:39:41 PM PST 24 | Jan 07 01:39:59 PM PST 24 | 136182702 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1636776649 | Jan 07 01:38:48 PM PST 24 | Jan 07 01:40:02 PM PST 24 | 2233222932 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1445343026 | Jan 07 01:40:32 PM PST 24 | Jan 07 01:42:41 PM PST 24 | 20266019038 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2202448272 | Jan 07 01:40:34 PM PST 24 | Jan 07 01:41:01 PM PST 24 | 9807636 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/23.xbar_same_source.2950219265 | Jan 07 01:39:18 PM PST 24 | Jan 07 01:39:22 PM PST 24 | 29174126 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2775721727 | Jan 07 01:40:16 PM PST 24 | Jan 07 01:40:43 PM PST 24 | 9154243 ps |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1209735620 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 384165063 ps |
| CPU time | 5.74 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:40:14 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-97bde6b2-d391-45bf-b355-0ff1b954550f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1209735620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1209735620 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.100118897 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 78149205841 ps |
| CPU time | 297.12 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:44:33 PM PST 24 |
| Peak memory | 203912 kb |
| Host | smart-31444d66-cd51-43ce-9bbb-d667d001701a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=100118897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow _rsp.100118897 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1475077504 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 34908307814 ps |
| CPU time | 178.31 seconds |
| Started | Jan 07 01:38:46 PM PST 24 |
| Finished | Jan 07 01:41:46 PM PST 24 |
| Peak memory | 202724 kb |
| Host | smart-788b371f-8eaa-43b4-852b-91e0d0b6fd81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1475077504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1475077504 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.4166144222 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 56922580727 ps |
| CPU time | 317.22 seconds |
| Started | Jan 07 01:39:55 PM PST 24 |
| Finished | Jan 07 01:45:37 PM PST 24 |
| Peak memory | 203528 kb |
| Host | smart-5c47a34f-e10c-41a0-aa36-f01fd01474fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4166144222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.4166144222 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1848458969 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 61455226392 ps |
| CPU time | 291.72 seconds |
| Started | Jan 07 01:39:34 PM PST 24 |
| Finished | Jan 07 01:44:36 PM PST 24 |
| Peak memory | 202584 kb |
| Host | smart-7dfb29ff-c047-4af2-ad29-655f70b1950b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1848458969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.1848458969 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2187112792 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 629981885 ps |
| CPU time | 72.27 seconds |
| Started | Jan 07 01:39:02 PM PST 24 |
| Finished | Jan 07 01:40:15 PM PST 24 |
| Peak memory | 204040 kb |
| Host | smart-e0609cf7-82d5-4b73-9791-c10e7f24e427 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2187112792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.2187112792 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.176628137 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 149236853 ps |
| CPU time | 11.91 seconds |
| Started | Jan 07 01:39:30 PM PST 24 |
| Finished | Jan 07 01:39:49 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-a4b09bae-41bb-45e6-8466-90a4e436b09c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=176628137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.176628137 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2600003946 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 65483938535 ps |
| CPU time | 217.2 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:43:32 PM PST 24 |
| Peak memory | 202788 kb |
| Host | smart-c871564d-473e-44a2-ae17-f07f7093c5a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2600003946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.2600003946 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.3763659738 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 16716709115 ps |
| CPU time | 90.86 seconds |
| Started | Jan 07 01:39:59 PM PST 24 |
| Finished | Jan 07 01:41:58 PM PST 24 |
| Peak memory | 202452 kb |
| Host | smart-d2af7994-325e-4f89-952b-93aea7e79962 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3763659738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3763659738 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1915619865 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 110791073828 ps |
| CPU time | 363.65 seconds |
| Started | Jan 07 01:40:03 PM PST 24 |
| Finished | Jan 07 01:46:35 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-91d4bb63-0536-4ca5-85ed-6e503620f950 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1915619865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1915619865 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2121661353 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 56594203097 ps |
| CPU time | 205.04 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:43:14 PM PST 24 |
| Peak memory | 203544 kb |
| Host | smart-cfcf659a-0b41-4cb1-ab86-b809af629399 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2121661353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.2121661353 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3260794443 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1146780269 ps |
| CPU time | 173.82 seconds |
| Started | Jan 07 01:39:26 PM PST 24 |
| Finished | Jan 07 01:42:26 PM PST 24 |
| Peak memory | 206972 kb |
| Host | smart-9c171a9f-b2f2-40aa-9631-0e7b035376b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3260794443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3260794443 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.682258897 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 26719221947 ps |
| CPU time | 117.9 seconds |
| Started | Jan 07 01:40:25 PM PST 24 |
| Finished | Jan 07 01:42:54 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-d7799c22-b7db-4e5f-ade5-9b7fedfe473b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=682258897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.682258897 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1916453261 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 192903268 ps |
| CPU time | 29.98 seconds |
| Started | Jan 07 01:40:22 PM PST 24 |
| Finished | Jan 07 01:41:16 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-15a37b20-50b9-4531-ba88-eef12a08135a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1916453261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.1916453261 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3491588513 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 338097883 ps |
| CPU time | 37.1 seconds |
| Started | Jan 07 01:38:53 PM PST 24 |
| Finished | Jan 07 01:39:32 PM PST 24 |
| Peak memory | 204044 kb |
| Host | smart-efb0ddd7-42d0-484f-9a4e-a20525d99ed1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3491588513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.3491588513 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2559120579 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 603279124 ps |
| CPU time | 80.79 seconds |
| Started | Jan 07 01:40:15 PM PST 24 |
| Finished | Jan 07 01:42:02 PM PST 24 |
| Peak memory | 205192 kb |
| Host | smart-7dbb2011-7b65-4158-a4d2-032da14b3a7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2559120579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.2559120579 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.905467155 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 341220961 ps |
| CPU time | 57.73 seconds |
| Started | Jan 07 01:40:09 PM PST 24 |
| Finished | Jan 07 01:41:35 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-1b53c72f-a81a-48e9-89da-02558abedb10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=905467155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand _reset.905467155 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.411894194 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 53939631904 ps |
| CPU time | 295.97 seconds |
| Started | Jan 07 01:40:11 PM PST 24 |
| Finished | Jan 07 01:45:35 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-002f3c14-f3a0-41ee-9a1e-b3c188d3d7a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=411894194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo w_rsp.411894194 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2307054356 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 5379373108 ps |
| CPU time | 124.53 seconds |
| Started | Jan 07 01:38:34 PM PST 24 |
| Finished | Jan 07 01:40:41 PM PST 24 |
| Peak memory | 204336 kb |
| Host | smart-77f05d52-10bf-4d46-ad09-9e6f6ca2f4e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2307054356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.2307054356 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.4249977702 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4421245409 ps |
| CPU time | 120.46 seconds |
| Started | Jan 07 01:40:18 PM PST 24 |
| Finished | Jan 07 01:42:44 PM PST 24 |
| Peak memory | 203884 kb |
| Host | smart-4237279c-c926-4499-a772-33a39ff7f162 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4249977702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.4249977702 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2389727120 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3535165812 ps |
| CPU time | 64.91 seconds |
| Started | Jan 07 01:40:40 PM PST 24 |
| Finished | Jan 07 01:42:12 PM PST 24 |
| Peak memory | 203192 kb |
| Host | smart-74bcd993-7fcc-43eb-8b95-233e4a42c3de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2389727120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.2389727120 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3430664329 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 7194750447 ps |
| CPU time | 119.62 seconds |
| Started | Jan 07 01:45:37 PM PST 24 |
| Finished | Jan 07 01:48:17 PM PST 24 |
| Peak memory | 204092 kb |
| Host | smart-b0aeceab-59ea-4c3b-a8a9-ad272db63582 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3430664329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.3430664329 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1086269076 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 9481197440 ps |
| CPU time | 57.66 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:40:46 PM PST 24 |
| Peak memory | 203556 kb |
| Host | smart-644feac7-3f9d-4e05-b7c8-736d219a3aa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1086269076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.1086269076 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3265824528 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 116816297132 ps |
| CPU time | 179.91 seconds |
| Started | Jan 07 01:38:44 PM PST 24 |
| Finished | Jan 07 01:41:46 PM PST 24 |
| Peak memory | 203592 kb |
| Host | smart-791f016d-9325-4972-9726-554d0a95293c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3265824528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.3265824528 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.799602473 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1533419329 ps |
| CPU time | 16.92 seconds |
| Started | Jan 07 01:38:54 PM PST 24 |
| Finished | Jan 07 01:39:13 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-dd187e1a-1423-4a73-a23f-2643b6f17172 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=799602473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.799602473 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3527368573 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 392522406 ps |
| CPU time | 7.19 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:39:45 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-b0280dd8-a17f-4475-90da-a37c59ba66e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3527368573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3527368573 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.2076823549 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1414620945 ps |
| CPU time | 9.25 seconds |
| Started | Jan 07 01:38:49 PM PST 24 |
| Finished | Jan 07 01:39:00 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-978cde83-e3df-4e3e-9b1e-70a3720be1c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2076823549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2076823549 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.199815971 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 29940977 ps |
| CPU time | 3.32 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:38:57 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-afb4a4c7-38c0-41f3-8c9d-d4b3b879e34b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=199815971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.199815971 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.1535667930 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 27963420086 ps |
| CPU time | 53.36 seconds |
| Started | Jan 07 01:38:38 PM PST 24 |
| Finished | Jan 07 01:39:34 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-8301de55-bcb8-4e53-a3d1-3842fc53c74a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535667930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1535667930 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1871349653 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 11666042334 ps |
| CPU time | 79.51 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:40:13 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-927480f2-981e-40c1-b58f-c1319445fb26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1871349653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1871349653 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.993027747 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 13306594 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 01:38:32 PM PST 24 |
| Finished | Jan 07 01:38:35 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-6c23aa9d-5f8c-4e00-a502-2cb95a6223a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993027747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.993027747 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.3938256518 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 573379434 ps |
| CPU time | 8.25 seconds |
| Started | Jan 07 01:38:51 PM PST 24 |
| Finished | Jan 07 01:39:00 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-5d4f1a35-c202-443d-b933-392f6a25acb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3938256518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3938256518 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.3960268429 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 246611678 ps |
| CPU time | 1.53 seconds |
| Started | Jan 07 01:37:53 PM PST 24 |
| Finished | Jan 07 01:37:58 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-bd076503-3dcf-41c5-a9de-1720a55fedb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3960268429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3960268429 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3338326603 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3310448009 ps |
| CPU time | 9.26 seconds |
| Started | Jan 07 01:38:29 PM PST 24 |
| Finished | Jan 07 01:38:39 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-41fba558-22f0-49e4-b550-5629398f0c16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338326603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3338326603 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1478533367 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 3653848852 ps |
| CPU time | 10.05 seconds |
| Started | Jan 07 01:38:09 PM PST 24 |
| Finished | Jan 07 01:38:19 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-dd0034ca-5551-4dfb-a106-35e72994635d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1478533367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1478533367 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.677724572 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 19545320 ps |
| CPU time | 1.14 seconds |
| Started | Jan 07 01:38:09 PM PST 24 |
| Finished | Jan 07 01:38:10 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-0768e7a5-0001-4ea7-b453-2f0640c61233 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677724572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.677724572 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3611733696 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 574287785 ps |
| CPU time | 46.9 seconds |
| Started | Jan 07 01:38:34 PM PST 24 |
| Finished | Jan 07 01:39:23 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-4078197d-aec0-4f25-be43-a1efa37466ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3611733696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3611733696 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1919731245 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2150270698 ps |
| CPU time | 31.56 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:40:19 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-54f603e2-c779-4670-bf12-f043b773aec6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1919731245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1919731245 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3329513085 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 225340888 ps |
| CPU time | 28.49 seconds |
| Started | Jan 07 01:39:30 PM PST 24 |
| Finished | Jan 07 01:40:06 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-4ee3259e-c586-423e-9e59-a4c209a3b00e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3329513085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.3329513085 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3481405383 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 184938238 ps |
| CPU time | 27.45 seconds |
| Started | Jan 07 01:39:21 PM PST 24 |
| Finished | Jan 07 01:39:53 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-0ae938fd-c688-456e-a39e-d9291a1a3d55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3481405383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.3481405383 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.812009501 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 51156533 ps |
| CPU time | 4.54 seconds |
| Started | Jan 07 01:39:18 PM PST 24 |
| Finished | Jan 07 01:39:25 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-c58bd2ef-3a36-49dc-b977-2c85e84bb596 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=812009501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.812009501 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1861539873 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 324254528 ps |
| CPU time | 8.73 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:20 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-c5a3a119-0303-4440-bef3-99314e36e801 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1861539873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1861539873 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2701942832 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 11580588799 ps |
| CPU time | 47.06 seconds |
| Started | Jan 07 01:39:48 PM PST 24 |
| Finished | Jan 07 01:40:54 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-85519073-6aff-485c-acd7-051e5af27dd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2701942832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.2701942832 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2259802971 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 29762632 ps |
| CPU time | 3.91 seconds |
| Started | Jan 07 01:37:44 PM PST 24 |
| Finished | Jan 07 01:37:49 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-307ef1a5-0709-4a43-9d45-0495c3576c35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2259802971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2259802971 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.3788216279 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 682435916 ps |
| CPU time | 8.64 seconds |
| Started | Jan 07 01:39:47 PM PST 24 |
| Finished | Jan 07 01:40:14 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-d5379275-9d93-4fa7-8428-bc362a049435 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3788216279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3788216279 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.87811157 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1420226979 ps |
| CPU time | 11.75 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:51 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-feb2a05c-952e-4b97-b695-5176f530fcc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=87811157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.87811157 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2027954397 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 8694675953 ps |
| CPU time | 33.58 seconds |
| Started | Jan 07 01:39:26 PM PST 24 |
| Finished | Jan 07 01:40:06 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-e12bce61-18cd-4f8f-b2fb-abaf592b8840 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027954397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2027954397 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2068016466 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 110929860199 ps |
| CPU time | 159.12 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:42:34 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-3835f0b2-81f8-4dbf-af74-7d45354d296a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2068016466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2068016466 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3820448319 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 84732471 ps |
| CPU time | 7.38 seconds |
| Started | Jan 07 01:39:14 PM PST 24 |
| Finished | Jan 07 01:39:24 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-bf75e752-08e5-4cc6-9609-3fd0ba90f1c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820448319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3820448319 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.2251718142 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 116806154 ps |
| CPU time | 5.31 seconds |
| Started | Jan 07 01:39:24 PM PST 24 |
| Finished | Jan 07 01:39:35 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-f0e0f574-04ad-4f7f-bf24-1dedec069137 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2251718142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2251718142 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.3119960933 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 39725143 ps |
| CPU time | 1.3 seconds |
| Started | Jan 07 01:39:24 PM PST 24 |
| Finished | Jan 07 01:39:32 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-47f380a7-9704-4abe-9dca-6e310c444fc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3119960933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3119960933 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2744347340 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 7896571774 ps |
| CPU time | 11.09 seconds |
| Started | Jan 07 01:39:34 PM PST 24 |
| Finished | Jan 07 01:39:56 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-2b92001b-9ba8-44bd-94d4-288d45ed8e43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744347340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2744347340 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.4174982076 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4172590069 ps |
| CPU time | 7.73 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-31ed247c-6e59-4e59-bf8f-3053e8640057 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4174982076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.4174982076 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2891886490 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 16420533 ps |
| CPU time | 1.23 seconds |
| Started | Jan 07 01:38:59 PM PST 24 |
| Finished | Jan 07 01:39:01 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-9a9f811c-99c0-4818-8317-b1c4c7c90b17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891886490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2891886490 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1727806526 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 343135364 ps |
| CPU time | 32 seconds |
| Started | Jan 07 01:37:22 PM PST 24 |
| Finished | Jan 07 01:37:55 PM PST 24 |
| Peak memory | 202600 kb |
| Host | smart-5e358a9a-0520-4720-bc46-5c9e5a3ff09e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1727806526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1727806526 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2277946578 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1426993558 ps |
| CPU time | 21.68 seconds |
| Started | Jan 07 01:37:48 PM PST 24 |
| Finished | Jan 07 01:38:11 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-baa45502-f303-4a3c-8765-478eeecb51b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2277946578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2277946578 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2538547855 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 394784318 ps |
| CPU time | 54.19 seconds |
| Started | Jan 07 01:37:15 PM PST 24 |
| Finished | Jan 07 01:38:12 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-d760d98d-cac3-4100-9aac-fa83308b4db8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2538547855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.2538547855 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3949818103 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 654470098 ps |
| CPU time | 71.61 seconds |
| Started | Jan 07 01:37:46 PM PST 24 |
| Finished | Jan 07 01:38:59 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-6661576e-ea2d-4005-8e99-00e2b479d25e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3949818103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.3949818103 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3897204066 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3360396678 ps |
| CPU time | 10.51 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:39:47 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-3f530e6a-e719-481f-bda5-63458a5e072d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3897204066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3897204066 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2182568954 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 785408249 ps |
| CPU time | 13.71 seconds |
| Started | Jan 07 01:39:24 PM PST 24 |
| Finished | Jan 07 01:39:43 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-3832be5d-2ead-4a8d-9343-0c00bf96c237 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2182568954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2182568954 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.4044036665 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 27092572407 ps |
| CPU time | 157.16 seconds |
| Started | Jan 07 01:39:47 PM PST 24 |
| Finished | Jan 07 01:42:42 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-78a48c73-5222-49ba-a0a1-4af7688f74f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4044036665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.4044036665 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.4176046085 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 571582639 ps |
| CPU time | 9.51 seconds |
| Started | Jan 07 01:39:57 PM PST 24 |
| Finished | Jan 07 01:40:32 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-4858d8fc-7620-4911-bda2-ec9291eaeefe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4176046085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.4176046085 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.2152442090 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 24058885 ps |
| CPU time | 3.22 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:39:53 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-849c1127-518d-4662-badb-86dbe545023c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2152442090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2152442090 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.73245048 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2245164055 ps |
| CPU time | 12.72 seconds |
| Started | Jan 07 01:39:57 PM PST 24 |
| Finished | Jan 07 01:40:36 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-e41f2e1b-5570-4bcd-8844-26a23d5161f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=73245048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.73245048 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.361152493 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 13494656660 ps |
| CPU time | 68.15 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:41:09 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-4c3ae151-51b5-49c9-b1f0-2fda15fbe9d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=361152493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.361152493 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1525899423 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1747272942 ps |
| CPU time | 8 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:39:58 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-90ed62d4-9b2f-4f84-971d-fe0a4d866bbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1525899423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1525899423 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2585175687 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 84334214 ps |
| CPU time | 6.77 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:40:00 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-584ef312-3994-4bb6-9aa6-5aee96a5cda7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585175687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2585175687 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.1494951523 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 539417051 ps |
| CPU time | 5.72 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:39:54 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-982857e3-b7f7-4efd-bcaf-020cbb7425bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1494951523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1494951523 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.625975075 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 8217768 ps |
| CPU time | 1.04 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:39:56 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-0da3dd8a-8b91-4587-b8b6-f2371795997c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=625975075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.625975075 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3723038177 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 4267846217 ps |
| CPU time | 10.93 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:40:00 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-bf542c7b-b4e1-4c80-a101-49c0474e6dbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723038177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3723038177 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.2010344486 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2904009663 ps |
| CPU time | 5.49 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:39:58 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-76d38d34-26fd-4351-bcc9-bb0a468d5dc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2010344486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2010344486 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3899748387 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 15325044 ps |
| CPU time | 1.22 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:41 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-0c5ee57f-66a9-4b05-81b3-ca3468d70de5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899748387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3899748387 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.360667572 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 95972527 ps |
| CPU time | 14.3 seconds |
| Started | Jan 07 01:40:02 PM PST 24 |
| Finished | Jan 07 01:40:45 PM PST 24 |
| Peak memory | 202156 kb |
| Host | smart-4e5a649e-3d87-481d-ac31-a8f4fec88e61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=360667572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.360667572 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.700798605 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2882355481 ps |
| CPU time | 56.03 seconds |
| Started | Jan 07 01:37:55 PM PST 24 |
| Finished | Jan 07 01:38:53 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-d81dcbd0-6d9e-4ad6-9344-880e1bd89b8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=700798605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.700798605 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3734506821 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 1381614587 ps |
| CPU time | 149.98 seconds |
| Started | Jan 07 01:37:53 PM PST 24 |
| Finished | Jan 07 01:40:26 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-cdcfdd47-bc6d-4a6c-8a20-b75d2a8bece0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3734506821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.3734506821 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3102096101 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 47275916 ps |
| CPU time | 10.45 seconds |
| Started | Jan 07 01:38:29 PM PST 24 |
| Finished | Jan 07 01:38:41 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-8cfb89ca-131c-48ae-984a-5265d15c4b10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3102096101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.3102096101 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2148060975 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 116094511 ps |
| CPU time | 7.34 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:39:45 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-b70084ef-7948-4806-8f61-c8143c285b3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2148060975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2148060975 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3221570631 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 829065994 ps |
| CPU time | 16.51 seconds |
| Started | Jan 07 01:38:50 PM PST 24 |
| Finished | Jan 07 01:39:07 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-18902a4a-234a-4030-a3fe-47d3c9e37a5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3221570631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3221570631 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.581578165 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 27328113409 ps |
| CPU time | 84.95 seconds |
| Started | Jan 07 01:38:34 PM PST 24 |
| Finished | Jan 07 01:40:01 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-48716937-de13-4bdd-b973-e8a4b9fca99f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=581578165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo w_rsp.581578165 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2722531938 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 51382739 ps |
| CPU time | 4.28 seconds |
| Started | Jan 07 01:38:50 PM PST 24 |
| Finished | Jan 07 01:38:56 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-572729a3-9fbd-4b7b-8347-b88f6d9d4299 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2722531938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2722531938 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.2860709020 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 52480539 ps |
| CPU time | 3.31 seconds |
| Started | Jan 07 01:38:57 PM PST 24 |
| Finished | Jan 07 01:39:02 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-7796b332-0a05-4f06-989e-385a4c8bf81c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2860709020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2860709020 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.3375470333 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 49043162 ps |
| CPU time | 7.37 seconds |
| Started | Jan 07 01:38:39 PM PST 24 |
| Finished | Jan 07 01:38:49 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-b3188de5-17f3-487a-8753-35ea73d305e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3375470333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3375470333 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3751686891 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 44557303902 ps |
| CPU time | 177.18 seconds |
| Started | Jan 07 01:37:49 PM PST 24 |
| Finished | Jan 07 01:40:48 PM PST 24 |
| Peak memory | 201636 kb |
| Host | smart-b15fb5e9-2ad5-4a94-8513-c7475042f878 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751686891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3751686891 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3534008020 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4113035533 ps |
| CPU time | 29.78 seconds |
| Started | Jan 07 01:38:26 PM PST 24 |
| Finished | Jan 07 01:38:56 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-200f2ef8-ac2f-46f1-8541-68121da5713b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3534008020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3534008020 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.4170228506 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 40374687 ps |
| CPU time | 2.62 seconds |
| Started | Jan 07 01:37:49 PM PST 24 |
| Finished | Jan 07 01:37:54 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-1cf8fb4b-39ba-4cdf-9790-d5435738be5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170228506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.4170228506 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.2719890726 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1245427562 ps |
| CPU time | 3.32 seconds |
| Started | Jan 07 01:38:33 PM PST 24 |
| Finished | Jan 07 01:38:38 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-c709d15f-4180-40dd-9e3f-3dbe2767978a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2719890726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2719890726 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.2975415561 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 51604659 ps |
| CPU time | 1.55 seconds |
| Started | Jan 07 01:37:59 PM PST 24 |
| Finished | Jan 07 01:38:03 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-6083b717-8860-424f-a1e3-e4f36ff1ec39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2975415561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2975415561 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1171825881 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 10483902526 ps |
| CPU time | 11.98 seconds |
| Started | Jan 07 01:38:00 PM PST 24 |
| Finished | Jan 07 01:38:14 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-63bed0dd-c5d2-4deb-81db-2e99f5d22056 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171825881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1171825881 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1640080244 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2509490459 ps |
| CPU time | 11.89 seconds |
| Started | Jan 07 01:38:05 PM PST 24 |
| Finished | Jan 07 01:38:18 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-1196df29-4430-4865-9169-f4bbda6f5707 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1640080244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1640080244 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.923801577 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 18357562 ps |
| CPU time | 1.18 seconds |
| Started | Jan 07 01:37:52 PM PST 24 |
| Finished | Jan 07 01:37:56 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-b3d0e1f2-682e-461b-9a3d-f65337d80f1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923801577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.923801577 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.1601039806 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 93112784 ps |
| CPU time | 7.02 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:39:43 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-6da68239-d2cc-4f29-adfb-66ce562aedda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1601039806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1601039806 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.588439321 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 5117772212 ps |
| CPU time | 58.42 seconds |
| Started | Jan 07 01:39:20 PM PST 24 |
| Finished | Jan 07 01:40:23 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-8731ae6a-f86f-4b83-87b5-c59930e69c90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=588439321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.588439321 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1184730765 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1591736371 ps |
| CPU time | 83.47 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:40:17 PM PST 24 |
| Peak memory | 203536 kb |
| Host | smart-a7c95756-9b03-45eb-980e-ad2d863fc36d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1184730765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.1184730765 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2692792012 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1157863338 ps |
| CPU time | 166.7 seconds |
| Started | Jan 07 01:38:57 PM PST 24 |
| Finished | Jan 07 01:41:46 PM PST 24 |
| Peak memory | 208140 kb |
| Host | smart-22be707f-947f-41ff-b287-1937862b4419 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2692792012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.2692792012 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2474294196 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 43629882 ps |
| CPU time | 2.25 seconds |
| Started | Jan 07 01:38:50 PM PST 24 |
| Finished | Jan 07 01:38:53 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-1aceb38c-93d1-44ce-978c-1daa7321466f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2474294196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2474294196 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.945857062 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 231709351 ps |
| CPU time | 5.33 seconds |
| Started | Jan 07 01:39:45 PM PST 24 |
| Finished | Jan 07 01:40:08 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-2601c9f7-b33d-42de-9df6-177b945d893e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=945857062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.945857062 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1100257663 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 121602587962 ps |
| CPU time | 222.75 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:43:51 PM PST 24 |
| Peak memory | 202732 kb |
| Host | smart-4bc03bbc-9bc3-4a11-8d3a-78f2ed687a5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1100257663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.1100257663 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1599248185 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 178040874 ps |
| CPU time | 2.22 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:40:19 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-f710a5e1-3ff5-4f02-bbde-5747c52f32fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1599248185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1599248185 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.3484992939 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 57711176 ps |
| CPU time | 6.08 seconds |
| Started | Jan 07 01:39:43 PM PST 24 |
| Finished | Jan 07 01:40:12 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-19a5a3ab-9085-4b23-92f9-8699e5e8503d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3484992939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3484992939 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.2431863419 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 847469162 ps |
| CPU time | 14.96 seconds |
| Started | Jan 07 01:39:18 PM PST 24 |
| Finished | Jan 07 01:39:36 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-d1fd6e0d-1e08-4387-991f-d3bb49723888 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2431863419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2431863419 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2477255080 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 64409691629 ps |
| CPU time | 109.23 seconds |
| Started | Jan 07 01:38:58 PM PST 24 |
| Finished | Jan 07 01:40:49 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-d777600b-5b06-4bc5-984f-43916d68b32c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477255080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2477255080 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2426967707 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 32462967634 ps |
| CPU time | 178.08 seconds |
| Started | Jan 07 01:38:57 PM PST 24 |
| Finished | Jan 07 01:41:56 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-41cfce10-c5ac-40d7-b271-fefcfb838a78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2426967707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2426967707 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.2158485036 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 176854626 ps |
| CPU time | 8.78 seconds |
| Started | Jan 07 01:39:00 PM PST 24 |
| Finished | Jan 07 01:39:11 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-2d857957-8c8a-4397-a72e-2b7c205766de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158485036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2158485036 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.706494037 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1178466396 ps |
| CPU time | 11.45 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:23 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-25417d2d-8d82-46d3-bfa4-ccd8986f18af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=706494037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.706494037 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.3802126635 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 87582640 ps |
| CPU time | 1.51 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:39:39 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-b489cd6c-86ff-4b4a-a37c-5865139ddefb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3802126635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3802126635 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.4061805920 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 3412130319 ps |
| CPU time | 7.5 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:39:02 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-53703a4d-d192-43a8-bf19-9276c179f823 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061805920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.4061805920 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.405268888 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2122710810 ps |
| CPU time | 4.72 seconds |
| Started | Jan 07 01:38:47 PM PST 24 |
| Finished | Jan 07 01:38:53 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-565edf62-e6b7-4295-94d2-8fc53b086a19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=405268888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.405268888 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3036747469 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 12062251 ps |
| CPU time | 1.15 seconds |
| Started | Jan 07 01:38:47 PM PST 24 |
| Finished | Jan 07 01:38:50 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-812daf3d-7064-4689-a4ac-2113bd15b8ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036747469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3036747469 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.627799593 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 7646879922 ps |
| CPU time | 112.47 seconds |
| Started | Jan 07 01:39:42 PM PST 24 |
| Finished | Jan 07 01:41:50 PM PST 24 |
| Peak memory | 203572 kb |
| Host | smart-7c5371dd-2d46-4870-ad44-46aa3d72aa17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=627799593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.627799593 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3807816151 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1521837111 ps |
| CPU time | 12.81 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:40:06 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-3ff3019d-13d9-4935-b634-be83fc73f076 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3807816151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3807816151 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3369288922 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 378000535 ps |
| CPU time | 59.11 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:40:41 PM PST 24 |
| Peak memory | 204136 kb |
| Host | smart-a1c6a032-49e3-4320-b504-765959fe2309 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3369288922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.3369288922 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3200471575 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 8932082686 ps |
| CPU time | 106.82 seconds |
| Started | Jan 07 01:39:42 PM PST 24 |
| Finished | Jan 07 01:41:44 PM PST 24 |
| Peak memory | 206268 kb |
| Host | smart-7e2d659a-19bf-4e01-82d7-1d2f6aac5121 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3200471575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.3200471575 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.2993693111 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 323701527 ps |
| CPU time | 6 seconds |
| Started | Jan 07 01:39:26 PM PST 24 |
| Finished | Jan 07 01:39:38 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-60dd582d-9e28-45a6-a4e6-97f2cc8bc6d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2993693111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2993693111 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2611876327 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 67537612 ps |
| CPU time | 8.7 seconds |
| Started | Jan 07 01:37:55 PM PST 24 |
| Finished | Jan 07 01:38:06 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-2db031a9-2c0d-424e-8f49-756f3b7d8aff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2611876327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2611876327 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1050504324 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 32820410786 ps |
| CPU time | 149.86 seconds |
| Started | Jan 07 01:37:49 PM PST 24 |
| Finished | Jan 07 01:40:20 PM PST 24 |
| Peak memory | 202060 kb |
| Host | smart-d7abdb95-7ad6-4213-9bf7-ce2845e590c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1050504324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.1050504324 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2542923721 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 11678476 ps |
| CPU time | 1.14 seconds |
| Started | Jan 07 01:38:00 PM PST 24 |
| Finished | Jan 07 01:38:03 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-03727d09-76c4-494c-ac0d-1ddb0b4d3157 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2542923721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2542923721 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.3750604106 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 51064625 ps |
| CPU time | 3.53 seconds |
| Started | Jan 07 01:37:58 PM PST 24 |
| Finished | Jan 07 01:38:04 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-261617ee-525e-4980-bcb3-f3f5d07b438f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3750604106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3750604106 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.3269542334 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 442495444 ps |
| CPU time | 8.97 seconds |
| Started | Jan 07 01:37:58 PM PST 24 |
| Finished | Jan 07 01:38:09 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-2143f285-51d3-4eee-91b5-585b7b7d38c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3269542334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3269542334 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2032228195 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 17929212761 ps |
| CPU time | 10.47 seconds |
| Started | Jan 07 01:38:03 PM PST 24 |
| Finished | Jan 07 01:38:15 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-cd58ccca-7f43-4a21-bd8f-57c03df0f64a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032228195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2032228195 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1415352414 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 13603515621 ps |
| CPU time | 77.21 seconds |
| Started | Jan 07 01:37:59 PM PST 24 |
| Finished | Jan 07 01:39:19 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-ac4fb7b5-2eec-401f-a895-889d0ed6ca6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1415352414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1415352414 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.203375784 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 248018629 ps |
| CPU time | 7.76 seconds |
| Started | Jan 07 01:37:45 PM PST 24 |
| Finished | Jan 07 01:37:54 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-3857818e-f960-410a-a04c-c3217852c04b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203375784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.203375784 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.1810616915 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 74666127 ps |
| CPU time | 5.6 seconds |
| Started | Jan 07 01:38:16 PM PST 24 |
| Finished | Jan 07 01:38:22 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-218bc22e-854c-4346-b269-721c4420799c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1810616915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1810616915 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.4097782834 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 51473148 ps |
| CPU time | 1.6 seconds |
| Started | Jan 07 01:37:51 PM PST 24 |
| Finished | Jan 07 01:37:56 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-aa478f66-b746-494a-b7d8-e83f730dc41e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4097782834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4097782834 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.4646131 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 3287655997 ps |
| CPU time | 10.59 seconds |
| Started | Jan 07 01:37:59 PM PST 24 |
| Finished | Jan 07 01:38:12 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-578329f8-7159-4d32-b12f-d0586e940405 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4646131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.4646131 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2763437955 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1708477839 ps |
| CPU time | 9.67 seconds |
| Started | Jan 07 01:38:01 PM PST 24 |
| Finished | Jan 07 01:38:13 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-a7d4471f-7e31-414f-a1ba-96e88b6e07ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2763437955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2763437955 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1871912578 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 11358983 ps |
| CPU time | 1.02 seconds |
| Started | Jan 07 01:38:36 PM PST 24 |
| Finished | Jan 07 01:38:39 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-dc3d527c-b001-4b96-a2bf-586a8aa8079b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871912578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1871912578 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.439603458 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 196752945 ps |
| CPU time | 17.29 seconds |
| Started | Jan 07 01:38:39 PM PST 24 |
| Finished | Jan 07 01:38:59 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-d5603c77-041e-4c57-a564-03ade3a8fb51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=439603458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.439603458 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3123900902 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 711897693 ps |
| CPU time | 44.59 seconds |
| Started | Jan 07 01:39:08 PM PST 24 |
| Finished | Jan 07 01:39:55 PM PST 24 |
| Peak memory | 202436 kb |
| Host | smart-48451a31-e605-4903-bc9a-58e645aabc28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3123900902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3123900902 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1590078395 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2175735559 ps |
| CPU time | 89.86 seconds |
| Started | Jan 07 01:38:33 PM PST 24 |
| Finished | Jan 07 01:40:04 PM PST 24 |
| Peak memory | 203272 kb |
| Host | smart-9ea1545c-fa1b-462c-80bc-6d8bcac586db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1590078395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.1590078395 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1242802900 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 36979822 ps |
| CPU time | 8.4 seconds |
| Started | Jan 07 01:39:05 PM PST 24 |
| Finished | Jan 07 01:39:15 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-2cdbe67d-d8f5-49d5-b87a-9f91cbc43e31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1242802900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.1242802900 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3081017967 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 486201350 ps |
| CPU time | 8.18 seconds |
| Started | Jan 07 01:37:55 PM PST 24 |
| Finished | Jan 07 01:38:06 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-90d859de-92ea-45b8-9a94-bd51feb8028f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3081017967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3081017967 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1495782556 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 130919562 ps |
| CPU time | 4.08 seconds |
| Started | Jan 07 01:38:56 PM PST 24 |
| Finished | Jan 07 01:39:01 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-fdd179d7-5f44-425b-b64b-ad670df9c7fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1495782556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1495782556 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.4106381016 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 102385113 ps |
| CPU time | 3.18 seconds |
| Started | Jan 07 01:39:19 PM PST 24 |
| Finished | Jan 07 01:39:25 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-f098b708-9c6c-4060-8776-063eba152fc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4106381016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.4106381016 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.2382832979 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 5870008572 ps |
| CPU time | 15.22 seconds |
| Started | Jan 07 01:39:20 PM PST 24 |
| Finished | Jan 07 01:39:39 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-c64052ff-49b5-4511-946a-6795eea3ae6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2382832979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2382832979 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.1176332523 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 908993306 ps |
| CPU time | 12.58 seconds |
| Started | Jan 07 01:38:37 PM PST 24 |
| Finished | Jan 07 01:38:51 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-d754edf0-0b05-4a12-bbb5-6b7c5dbb194d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1176332523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1176332523 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3942653183 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 40339378713 ps |
| CPU time | 71.2 seconds |
| Started | Jan 07 01:38:35 PM PST 24 |
| Finished | Jan 07 01:39:48 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-3d5225c6-1f1d-4848-8036-f4b6199e79b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942653183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3942653183 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.4037660133 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 22163792698 ps |
| CPU time | 89.19 seconds |
| Started | Jan 07 01:38:58 PM PST 24 |
| Finished | Jan 07 01:40:28 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-3a5e6e36-adfa-4c61-b7ae-551895f63f60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4037660133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.4037660133 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2461106450 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 108730392 ps |
| CPU time | 6.88 seconds |
| Started | Jan 07 01:38:59 PM PST 24 |
| Finished | Jan 07 01:39:08 PM PST 24 |
| Peak memory | 201356 kb |
| Host | smart-27e094d2-a1fe-4bf7-95a9-2fc993fad64e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461106450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2461106450 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.3783658251 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 198406063 ps |
| CPU time | 3.01 seconds |
| Started | Jan 07 01:39:03 PM PST 24 |
| Finished | Jan 07 01:39:07 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-a9ae6158-16df-43bb-96c8-d6b1593f9d5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3783658251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3783658251 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.3219379456 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 8699153 ps |
| CPU time | 1.02 seconds |
| Started | Jan 07 01:38:45 PM PST 24 |
| Finished | Jan 07 01:38:47 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-61824c9d-d8c0-48f3-99d9-241e96952bb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3219379456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3219379456 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2660531662 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3918508984 ps |
| CPU time | 8.52 seconds |
| Started | Jan 07 01:38:57 PM PST 24 |
| Finished | Jan 07 01:39:06 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-56e5d86b-c8bb-463e-a576-57283effbdd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660531662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2660531662 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.352436341 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 5745692807 ps |
| CPU time | 7.45 seconds |
| Started | Jan 07 01:38:42 PM PST 24 |
| Finished | Jan 07 01:38:51 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-653d780b-0c49-41ad-b45b-397e1cc052d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=352436341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.352436341 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3846244157 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 9432248 ps |
| CPU time | 1.12 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:38:54 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-3d58a8c7-8824-4329-9ccd-e82f41cfe568 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846244157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3846244157 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.4001747159 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 143822939 ps |
| CPU time | 9.99 seconds |
| Started | Jan 07 01:38:44 PM PST 24 |
| Finished | Jan 07 01:38:56 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-b12913c4-cf87-40a6-bb86-3fc9c3d6f0e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4001747159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.4001747159 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1276244357 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5715474195 ps |
| CPU time | 63.08 seconds |
| Started | Jan 07 01:38:50 PM PST 24 |
| Finished | Jan 07 01:39:54 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-2cc4d405-ef7e-4bdb-95b2-78d6c8c1be0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1276244357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1276244357 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3288943164 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 541441299 ps |
| CPU time | 25.58 seconds |
| Started | Jan 07 01:38:44 PM PST 24 |
| Finished | Jan 07 01:39:11 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-182d0740-4cf4-4f16-a65d-3f69e32a4245 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3288943164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.3288943164 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2786805794 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 7052896395 ps |
| CPU time | 113.25 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:41:32 PM PST 24 |
| Peak memory | 205648 kb |
| Host | smart-9d11d6ee-0e2e-49d4-8ca8-f06aec821e8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2786805794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.2786805794 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1844983019 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 871482026 ps |
| CPU time | 11.7 seconds |
| Started | Jan 07 01:39:20 PM PST 24 |
| Finished | Jan 07 01:39:36 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-3677c0c9-86e6-40e0-9596-d0a8338a5b2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1844983019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1844983019 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.47567995 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 356345194 ps |
| CPU time | 6.13 seconds |
| Started | Jan 07 01:39:59 PM PST 24 |
| Finished | Jan 07 01:40:33 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-32f88f5f-1a20-4987-b52a-9a85e6568cbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=47567995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.47567995 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2274337061 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 43376387816 ps |
| CPU time | 221.14 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:43:37 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-e2e06106-7a3e-4b0b-afdc-92ce69c706a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2274337061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.2274337061 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3201010710 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1886021934 ps |
| CPU time | 10.17 seconds |
| Started | Jan 07 01:39:54 PM PST 24 |
| Finished | Jan 07 01:40:28 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-95040ea5-259e-412e-a50e-63c30bd7661f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3201010710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3201010710 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.599649289 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1745122328 ps |
| CPU time | 8.55 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-4bd5f5fe-ef4d-4b16-afff-ab6fea6e912e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=599649289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.599649289 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.3161955799 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 230391790 ps |
| CPU time | 3.29 seconds |
| Started | Jan 07 01:38:50 PM PST 24 |
| Finished | Jan 07 01:38:55 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-3fcb27ea-49b1-4d66-a7d7-a5a75ea34ed3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3161955799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3161955799 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1882905337 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 28964061417 ps |
| CPU time | 79.48 seconds |
| Started | Jan 07 01:38:44 PM PST 24 |
| Finished | Jan 07 01:40:05 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-5416a2f3-c0b9-4014-a177-74b87aa5eac5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882905337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1882905337 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.91079659 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 27254109224 ps |
| CPU time | 172.59 seconds |
| Started | Jan 07 01:38:50 PM PST 24 |
| Finished | Jan 07 01:41:44 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-080314d1-0dd0-42ae-b402-dddd490217b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=91079659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.91079659 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2980524758 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 83534631 ps |
| CPU time | 6.44 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:39:48 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-da500a3f-440d-4aa5-9dd0-4f78eeeb6afa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980524758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2980524758 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.438140791 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 130134801 ps |
| CPU time | 1.64 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:21 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-10bb6d81-087d-4fec-ba88-ee31c2334229 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=438140791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.438140791 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.2115555990 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 8617800 ps |
| CPU time | 1.13 seconds |
| Started | Jan 07 01:39:30 PM PST 24 |
| Finished | Jan 07 01:39:38 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-a3a4fec4-3091-46dd-a9a3-818f6a007bca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2115555990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2115555990 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.400055056 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1892410983 ps |
| CPU time | 6.29 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:39:42 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-b496b9f1-7f8c-444a-b93f-460e549c530b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=400055056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.400055056 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3033646373 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1330453869 ps |
| CPU time | 8.33 seconds |
| Started | Jan 07 01:39:05 PM PST 24 |
| Finished | Jan 07 01:39:17 PM PST 24 |
| Peak memory | 201356 kb |
| Host | smart-c6ac79da-2c38-4691-89ba-7ec427ac4663 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3033646373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3033646373 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1583039336 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 23185639 ps |
| CPU time | 1.14 seconds |
| Started | Jan 07 01:38:57 PM PST 24 |
| Finished | Jan 07 01:39:00 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-260d89b4-162c-4d30-a42a-b3d6b9e3bfb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583039336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1583039336 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.3134302667 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1497448385 ps |
| CPU time | 27.19 seconds |
| Started | Jan 07 01:43:27 PM PST 24 |
| Finished | Jan 07 01:44:13 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-62faae58-a29a-47a0-991c-f322c8adf8a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3134302667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3134302667 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3538293168 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 4508691042 ps |
| CPU time | 20.08 seconds |
| Started | Jan 07 01:46:04 PM PST 24 |
| Finished | Jan 07 01:47:03 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-e5427ce6-17b7-43c6-b712-c0ff4dd28fdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3538293168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3538293168 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1421844245 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 520535202 ps |
| CPU time | 60.53 seconds |
| Started | Jan 07 01:40:26 PM PST 24 |
| Finished | Jan 07 01:41:50 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-6d92b983-65d1-4287-a42f-5e0d88d19ee8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1421844245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.1421844245 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3539482034 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 682870783 ps |
| CPU time | 124.07 seconds |
| Started | Jan 07 01:40:23 PM PST 24 |
| Finished | Jan 07 01:42:51 PM PST 24 |
| Peak memory | 206516 kb |
| Host | smart-f1d4c957-9a1c-4619-966f-5e1d80ff6a25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3539482034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.3539482034 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.4118374380 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 587820714 ps |
| CPU time | 8.64 seconds |
| Started | Jan 07 01:39:54 PM PST 24 |
| Finished | Jan 07 01:40:26 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-ff964c19-f52d-4126-8d2a-1f5216b0f513 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4118374380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.4118374380 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.246968756 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1170526128 ps |
| CPU time | 12.1 seconds |
| Started | Jan 07 01:40:43 PM PST 24 |
| Finished | Jan 07 01:41:21 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-be2e792a-017b-46a3-89b5-3a83d83f26fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=246968756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.246968756 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2795536489 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 85565116216 ps |
| CPU time | 288.22 seconds |
| Started | Jan 07 01:40:45 PM PST 24 |
| Finished | Jan 07 01:45:59 PM PST 24 |
| Peak memory | 202864 kb |
| Host | smart-3012ef16-0c77-4409-bf34-8926ef1d1091 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2795536489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.2795536489 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.825806901 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 770560861 ps |
| CPU time | 8.43 seconds |
| Started | Jan 07 01:40:36 PM PST 24 |
| Finished | Jan 07 01:41:10 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-9b70bf62-feed-4e1d-9ff9-d54f1416a6c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=825806901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.825806901 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.188814301 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 28369122 ps |
| CPU time | 2.79 seconds |
| Started | Jan 07 01:40:27 PM PST 24 |
| Finished | Jan 07 01:40:52 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-15349bd5-c244-4531-a1fa-19bffefeecf2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=188814301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.188814301 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.473344605 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 882599997 ps |
| CPU time | 9.44 seconds |
| Started | Jan 07 01:40:14 PM PST 24 |
| Finished | Jan 07 01:40:50 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-a598503a-7218-43ce-8209-d004defff27a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=473344605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.473344605 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3674848746 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 27370339820 ps |
| CPU time | 116.79 seconds |
| Started | Jan 07 01:40:43 PM PST 24 |
| Finished | Jan 07 01:43:06 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-1d79fff9-79c5-448e-87a1-dc94712e3031 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674848746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3674848746 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.273813370 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 105175414743 ps |
| CPU time | 149.59 seconds |
| Started | Jan 07 01:43:23 PM PST 24 |
| Finished | Jan 07 01:46:09 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-f06c8739-4fe3-4ef6-9e3f-dba843e6d192 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=273813370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.273813370 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.215156971 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 150961730 ps |
| CPU time | 4.97 seconds |
| Started | Jan 07 01:40:30 PM PST 24 |
| Finished | Jan 07 01:41:01 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-118033d2-dd3b-4c51-a6ba-a316090653cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215156971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.215156971 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.695568487 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 49114254 ps |
| CPU time | 5.05 seconds |
| Started | Jan 07 01:40:33 PM PST 24 |
| Finished | Jan 07 01:41:05 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-f7b1f59f-4ab3-4c8e-9ffa-e6d25951c790 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=695568487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.695568487 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.3679693002 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 23852001 ps |
| CPU time | 1.17 seconds |
| Started | Jan 07 01:46:36 PM PST 24 |
| Finished | Jan 07 01:47:15 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-fcd7932f-2bfe-40e2-a0bf-34d38d11d509 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3679693002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3679693002 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2049185651 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6634321327 ps |
| CPU time | 10.25 seconds |
| Started | Jan 07 01:40:43 PM PST 24 |
| Finished | Jan 07 01:41:20 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-e4a7c0ad-679d-4914-99b5-4386a059f021 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049185651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2049185651 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1897431711 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2898100922 ps |
| CPU time | 7.23 seconds |
| Started | Jan 07 01:44:04 PM PST 24 |
| Finished | Jan 07 01:44:19 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-ddeea1fd-74ed-431c-852a-6d9ba59c0041 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1897431711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1897431711 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3097421088 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 11230855 ps |
| CPU time | 1.32 seconds |
| Started | Jan 07 01:43:17 PM PST 24 |
| Finished | Jan 07 01:43:33 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-f335927d-0e34-4890-adff-438964abf3a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097421088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3097421088 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.1771340785 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 496740227 ps |
| CPU time | 18.74 seconds |
| Started | Jan 07 01:46:36 PM PST 24 |
| Finished | Jan 07 01:47:33 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-ca2f7361-8439-41fa-96d6-932e4205acb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1771340785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1771340785 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.945791819 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1246185949 ps |
| CPU time | 33.2 seconds |
| Started | Jan 07 01:45:39 PM PST 24 |
| Finished | Jan 07 01:46:53 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-3503f438-1791-4c95-97b7-2f851082ec12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=945791819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.945791819 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2073482503 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 430271452 ps |
| CPU time | 8.45 seconds |
| Started | Jan 07 01:41:02 PM PST 24 |
| Finished | Jan 07 01:41:27 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-bc9e556f-19a9-4f7d-92b5-74155aa1e259 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2073482503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2073482503 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2749730512 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 126178129 ps |
| CPU time | 2.8 seconds |
| Started | Jan 07 01:41:38 PM PST 24 |
| Finished | Jan 07 01:41:52 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-35fd29af-0af5-4088-bbe8-8a2be81f3494 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2749730512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2749730512 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1255958927 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 46510523123 ps |
| CPU time | 333.51 seconds |
| Started | Jan 07 01:47:18 PM PST 24 |
| Finished | Jan 07 01:53:13 PM PST 24 |
| Peak memory | 202540 kb |
| Host | smart-b6fc82ab-9f7f-4238-a4a7-aeb10e74c222 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1255958927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.1255958927 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.4284848228 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 195845731 ps |
| CPU time | 2.94 seconds |
| Started | Jan 07 01:43:16 PM PST 24 |
| Finished | Jan 07 01:43:34 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-ddd6a953-d1d1-42ff-8f68-8e004deed0bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4284848228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.4284848228 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.1435224001 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 576901598 ps |
| CPU time | 8.37 seconds |
| Started | Jan 07 01:43:16 PM PST 24 |
| Finished | Jan 07 01:43:40 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-d6cafff2-af2a-4228-827d-323b42bb4652 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1435224001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1435224001 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.4229164887 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 47380018 ps |
| CPU time | 3.13 seconds |
| Started | Jan 07 01:40:45 PM PST 24 |
| Finished | Jan 07 01:41:14 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-788a0f62-46f4-48ed-8735-6e08235abf34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4229164887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.4229164887 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3399697627 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 30152930138 ps |
| CPU time | 72.76 seconds |
| Started | Jan 07 01:40:35 PM PST 24 |
| Finished | Jan 07 01:42:13 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-b11ac4c4-0ce4-4ac6-8c31-7933b20c4cd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399697627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3399697627 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3769050494 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 29103449351 ps |
| CPU time | 59.29 seconds |
| Started | Jan 07 01:43:12 PM PST 24 |
| Finished | Jan 07 01:44:24 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-efec165e-5ae4-4e5c-96a7-ded94d214b17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3769050494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3769050494 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.587196053 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 40515680 ps |
| CPU time | 3.08 seconds |
| Started | Jan 07 01:40:36 PM PST 24 |
| Finished | Jan 07 01:41:06 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-f1f42330-6adf-4c77-a983-7588e80656e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587196053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.587196053 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.1756780197 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2715306423 ps |
| CPU time | 12.86 seconds |
| Started | Jan 07 01:40:42 PM PST 24 |
| Finished | Jan 07 01:41:22 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-b0cb2e0e-9623-4369-8ea9-301a75ce882f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1756780197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1756780197 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.1746925773 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 67025667 ps |
| CPU time | 1.52 seconds |
| Started | Jan 07 01:46:56 PM PST 24 |
| Finished | Jan 07 01:47:31 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-62fcc3bc-8b18-4359-ba80-1cf66c2466f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1746925773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1746925773 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.163029127 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3301709280 ps |
| CPU time | 6.9 seconds |
| Started | Jan 07 01:40:31 PM PST 24 |
| Finished | Jan 07 01:41:03 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-cd651ef6-9357-4045-85d4-be7bc715ec4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=163029127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.163029127 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.709081322 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 856390039 ps |
| CPU time | 6.13 seconds |
| Started | Jan 07 01:40:45 PM PST 24 |
| Finished | Jan 07 01:41:17 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-16431d59-f49d-4a0a-9536-73efea93a33b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=709081322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.709081322 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3446396097 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 11128569 ps |
| CPU time | 1.05 seconds |
| Started | Jan 07 01:46:06 PM PST 24 |
| Finished | Jan 07 01:46:46 PM PST 24 |
| Peak memory | 201300 kb |
| Host | smart-57166819-3a12-41bf-9cdd-dbe507079e64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446396097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3446396097 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.132923858 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2977123113 ps |
| CPU time | 19.56 seconds |
| Started | Jan 07 01:40:42 PM PST 24 |
| Finished | Jan 07 01:41:29 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-f1bdaea1-f45e-42b0-a12c-df4f67f09bcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=132923858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.132923858 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1618871998 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 45785232 ps |
| CPU time | 4.9 seconds |
| Started | Jan 07 01:41:25 PM PST 24 |
| Finished | Jan 07 01:41:35 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-babc1aa0-eef6-41fe-9223-419d0646f9ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1618871998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1618871998 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1947018780 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 412473990 ps |
| CPU time | 62.23 seconds |
| Started | Jan 07 01:45:25 PM PST 24 |
| Finished | Jan 07 01:47:03 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-89a52978-93f9-4382-bf85-f39291a3ccca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1947018780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.1947018780 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2149812023 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 5218534586 ps |
| CPU time | 111.96 seconds |
| Started | Jan 07 01:48:03 PM PST 24 |
| Finished | Jan 07 01:50:00 PM PST 24 |
| Peak memory | 205280 kb |
| Host | smart-3111b9af-856f-4e82-984e-117c8b9eaaea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2149812023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.2149812023 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2991786182 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 265258851 ps |
| CPU time | 3.67 seconds |
| Started | Jan 07 01:43:09 PM PST 24 |
| Finished | Jan 07 01:43:24 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-548dc7b9-3945-4448-b640-fbc233a4b0b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2991786182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2991786182 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.4058743150 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 3805691954 ps |
| CPU time | 17.55 seconds |
| Started | Jan 07 01:40:35 PM PST 24 |
| Finished | Jan 07 01:41:18 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-1b1be1c0-43ec-43a5-adf8-cd640312139e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4058743150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.4058743150 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.4008011025 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 165489845403 ps |
| CPU time | 267.79 seconds |
| Started | Jan 07 01:39:24 PM PST 24 |
| Finished | Jan 07 01:43:59 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-2318da28-3bd4-460b-a765-1a50b8a6e402 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4008011025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.4008011025 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3647189996 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 22140222 ps |
| CPU time | 2.45 seconds |
| Started | Jan 07 01:38:48 PM PST 24 |
| Finished | Jan 07 01:38:52 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-92b10b80-eb61-4189-b09e-f7c79733cc95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3647189996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3647189996 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.2829914367 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 695952756 ps |
| CPU time | 7.28 seconds |
| Started | Jan 07 01:38:57 PM PST 24 |
| Finished | Jan 07 01:39:05 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-fa2f93d6-885a-4d50-a3ad-6af6a355df79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2829914367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2829914367 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.2265423438 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1449287568 ps |
| CPU time | 11.14 seconds |
| Started | Jan 07 01:40:25 PM PST 24 |
| Finished | Jan 07 01:41:00 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-c5fc3ffa-1ecf-4a46-a1a4-23525dd29711 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2265423438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2265423438 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1008395962 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 13319792241 ps |
| CPU time | 61.38 seconds |
| Started | Jan 07 01:40:33 PM PST 24 |
| Finished | Jan 07 01:42:00 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-ac520197-136c-4186-b93a-bb5c0175461f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008395962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1008395962 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2507653610 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 22346612747 ps |
| CPU time | 90.03 seconds |
| Started | Jan 07 01:42:46 PM PST 24 |
| Finished | Jan 07 01:44:36 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-69da30bb-6bf0-44ac-a522-a506b082bbb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2507653610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2507653610 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3007336872 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 263714059 ps |
| CPU time | 6.37 seconds |
| Started | Jan 07 01:46:36 PM PST 24 |
| Finished | Jan 07 01:47:21 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-51f31ad6-0748-47a0-a3af-52d317886523 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007336872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3007336872 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.3942954524 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 58622938 ps |
| CPU time | 6.08 seconds |
| Started | Jan 07 01:38:43 PM PST 24 |
| Finished | Jan 07 01:38:51 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-a1624e19-8db5-456d-b36c-d4950bde71b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3942954524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3942954524 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.3229439799 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 72211347 ps |
| CPU time | 1.56 seconds |
| Started | Jan 07 01:40:30 PM PST 24 |
| Finished | Jan 07 01:40:58 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-48301fea-0b04-40de-a601-4c987ded64a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3229439799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3229439799 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1486388846 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2215220106 ps |
| CPU time | 10.37 seconds |
| Started | Jan 07 01:46:04 PM PST 24 |
| Finished | Jan 07 01:46:53 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-03035894-cefb-47da-9d4b-fe912e3d51a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486388846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1486388846 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2019018849 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 503028582 ps |
| CPU time | 4.69 seconds |
| Started | Jan 07 01:40:39 PM PST 24 |
| Finished | Jan 07 01:41:11 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-6b162cda-a782-40f8-8f3d-5905da5908b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2019018849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2019018849 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3636929900 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 14746955 ps |
| CPU time | 1.42 seconds |
| Started | Jan 07 01:43:12 PM PST 24 |
| Finished | Jan 07 01:43:26 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-19d5438e-9fa2-4cb7-b3fc-5754ac5966fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636929900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3636929900 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.49211247 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 6004567498 ps |
| CPU time | 73.47 seconds |
| Started | Jan 07 01:39:19 PM PST 24 |
| Finished | Jan 07 01:40:35 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-e4f572ea-b6d6-4d3a-a736-aee6730df87b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=49211247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.49211247 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1721711569 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 380962091 ps |
| CPU time | 38.16 seconds |
| Started | Jan 07 01:38:54 PM PST 24 |
| Finished | Jan 07 01:39:34 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-17d33274-8dd2-4322-985a-fd9188dee07d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1721711569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1721711569 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.862187858 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 862254398 ps |
| CPU time | 103.83 seconds |
| Started | Jan 07 01:39:21 PM PST 24 |
| Finished | Jan 07 01:41:11 PM PST 24 |
| Peak memory | 204400 kb |
| Host | smart-9df44369-a4b4-4770-bfb2-84dd0d982e50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=862187858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand _reset.862187858 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3366438328 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 428807051 ps |
| CPU time | 46.73 seconds |
| Started | Jan 07 01:38:46 PM PST 24 |
| Finished | Jan 07 01:39:34 PM PST 24 |
| Peak memory | 202616 kb |
| Host | smart-61ab668a-7517-4f85-bfe9-adb8327b8849 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3366438328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.3366438328 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3024936887 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2046975289 ps |
| CPU time | 7.02 seconds |
| Started | Jan 07 01:38:48 PM PST 24 |
| Finished | Jan 07 01:38:57 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-552220b4-2c5a-4920-a2bb-86b5a2c020da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3024936887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3024936887 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.3193875869 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 23902423 ps |
| CPU time | 4.83 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:40:00 PM PST 24 |
| Peak memory | 200600 kb |
| Host | smart-6c022423-7408-499d-a0b6-718a0a7f3e88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3193875869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3193875869 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3037944994 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 220916490216 ps |
| CPU time | 305.27 seconds |
| Started | Jan 07 01:38:53 PM PST 24 |
| Finished | Jan 07 01:44:00 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-4507fe89-b999-4d3b-af1b-d7821095bf57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3037944994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.3037944994 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3109747404 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1739705819 ps |
| CPU time | 5.89 seconds |
| Started | Jan 07 01:39:14 PM PST 24 |
| Finished | Jan 07 01:39:23 PM PST 24 |
| Peak memory | 201292 kb |
| Host | smart-3c18c4b3-c7fc-4f26-952b-162c309e3c88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3109747404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3109747404 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.922195887 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 179375342 ps |
| CPU time | 2.32 seconds |
| Started | Jan 07 01:39:22 PM PST 24 |
| Finished | Jan 07 01:39:30 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-11f69ce5-371d-4df1-97f8-e26ea29a3d86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=922195887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.922195887 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.3870411877 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 645687354 ps |
| CPU time | 10.55 seconds |
| Started | Jan 07 01:38:50 PM PST 24 |
| Finished | Jan 07 01:39:02 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-6dd3a0fc-938f-40b1-b003-42336efb0c35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3870411877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3870411877 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2491024381 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 5484857602 ps |
| CPU time | 6.93 seconds |
| Started | Jan 07 01:38:47 PM PST 24 |
| Finished | Jan 07 01:38:55 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-8051c74f-6257-4e19-83c9-da2a17d5311a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491024381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2491024381 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1749164712 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2288726620 ps |
| CPU time | 14.9 seconds |
| Started | Jan 07 01:38:39 PM PST 24 |
| Finished | Jan 07 01:38:57 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-233204f0-5b9b-4cca-a67a-eda5f9f066a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1749164712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1749164712 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.216236946 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 16947603 ps |
| CPU time | 2.5 seconds |
| Started | Jan 07 01:38:57 PM PST 24 |
| Finished | Jan 07 01:39:01 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-4faa55ab-d309-4735-82d3-6379d897c2b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216236946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.216236946 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.344514220 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 217019094 ps |
| CPU time | 4.55 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:39:58 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-efab0067-0499-404e-a4d6-3503b6a86d2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=344514220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.344514220 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.532721186 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 275445831 ps |
| CPU time | 1.49 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:38:55 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-a006c61b-e380-4e94-81e1-40ea629bd456 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=532721186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.532721186 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3612454863 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1737310273 ps |
| CPU time | 7.8 seconds |
| Started | Jan 07 01:39:13 PM PST 24 |
| Finished | Jan 07 01:39:29 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-512ce187-a79b-4938-a44e-802a8ca63864 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612454863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3612454863 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1053140083 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1210586884 ps |
| CPU time | 7.42 seconds |
| Started | Jan 07 01:38:35 PM PST 24 |
| Finished | Jan 07 01:38:45 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-254d594b-f0be-4306-8ca9-625096e32974 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1053140083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1053140083 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3643116470 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 15207074 ps |
| CPU time | 1.04 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:39:39 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-56a669ee-c149-49da-8ef6-b22e17c25454 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643116470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3643116470 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1359557851 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 80046669 ps |
| CPU time | 9.27 seconds |
| Started | Jan 07 01:39:15 PM PST 24 |
| Finished | Jan 07 01:39:27 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-fb9b757d-3135-40bb-af96-28a6dfa05fc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1359557851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1359557851 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2465604180 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 6240137981 ps |
| CPU time | 51.36 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:41:08 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-bd90d884-d8eb-49a9-8a3b-429ab56a6c09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2465604180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2465604180 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2230002948 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 4020849391 ps |
| CPU time | 133.57 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:42:06 PM PST 24 |
| Peak memory | 203912 kb |
| Host | smart-9a79d49d-d66b-4ba6-bc99-1d5b39836a59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2230002948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.2230002948 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3085241966 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 189892966 ps |
| CPU time | 20.24 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:32 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-e67fb738-abca-4641-8ede-b74f080c4f63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3085241966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.3085241966 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2212563249 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 754527004 ps |
| CPU time | 9.78 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:39:48 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-f1cd5147-6d11-41cc-8c34-d25461081b09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2212563249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2212563249 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.821029939 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 511661245 ps |
| CPU time | 1.98 seconds |
| Started | Jan 07 01:38:37 PM PST 24 |
| Finished | Jan 07 01:38:41 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-31f50458-cde4-4dde-9720-0e15a1654183 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=821029939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.821029939 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1067468070 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 83970258514 ps |
| CPU time | 196.79 seconds |
| Started | Jan 07 01:38:33 PM PST 24 |
| Finished | Jan 07 01:41:52 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-f1c1123c-e3ef-4a7e-b42d-1d4110dff6f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1067468070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.1067468070 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2630073208 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 405187216 ps |
| CPU time | 4.64 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:38:58 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-f7ef3c8f-075c-4859-b000-c50d6ad1d3b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2630073208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2630073208 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.1226529808 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 206938938 ps |
| CPU time | 7.35 seconds |
| Started | Jan 07 01:38:43 PM PST 24 |
| Finished | Jan 07 01:38:52 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-e80cfbae-35de-4d0c-b13f-4315de0981a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1226529808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1226529808 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.3409275268 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 32193570 ps |
| CPU time | 2.49 seconds |
| Started | Jan 07 01:39:14 PM PST 24 |
| Finished | Jan 07 01:39:19 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-d73b6999-aaa2-434d-90e3-295f555aa6d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3409275268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3409275268 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1964294900 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 36184042036 ps |
| CPU time | 80.23 seconds |
| Started | Jan 07 01:38:38 PM PST 24 |
| Finished | Jan 07 01:40:00 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-c37a76ee-25dc-4bb1-8a20-a22ee0c6f97c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964294900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1964294900 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1291773112 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 20977108409 ps |
| CPU time | 77.11 seconds |
| Started | Jan 07 01:38:13 PM PST 24 |
| Finished | Jan 07 01:39:31 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-c0f19e5c-bd4b-49a2-9844-bb1e8e43ed39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1291773112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1291773112 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.4144971542 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 26112508 ps |
| CPU time | 2.77 seconds |
| Started | Jan 07 01:37:58 PM PST 24 |
| Finished | Jan 07 01:38:03 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-69cfa610-d7db-460b-a408-e90296dfc827 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144971542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.4144971542 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.4079145889 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 825696229 ps |
| CPU time | 12.17 seconds |
| Started | Jan 07 01:39:03 PM PST 24 |
| Finished | Jan 07 01:39:17 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-4f675d72-4a65-4210-8f2b-0a1cc2f84b22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4079145889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.4079145889 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.746408928 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 48174523 ps |
| CPU time | 1.42 seconds |
| Started | Jan 07 01:37:51 PM PST 24 |
| Finished | Jan 07 01:37:55 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-60f66a9b-5d42-4c70-877d-f08517051718 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=746408928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.746408928 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1850298022 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1287511034 ps |
| CPU time | 6.56 seconds |
| Started | Jan 07 01:37:45 PM PST 24 |
| Finished | Jan 07 01:37:52 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-0652fb02-1851-49c8-8434-34de9a974ad6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850298022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1850298022 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.330071479 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 6954954432 ps |
| CPU time | 8.36 seconds |
| Started | Jan 07 01:38:28 PM PST 24 |
| Finished | Jan 07 01:38:37 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-1aa461be-287c-43af-86e1-12f29cffc55e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=330071479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.330071479 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1055715502 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 9814758 ps |
| CPU time | 1.18 seconds |
| Started | Jan 07 01:37:51 PM PST 24 |
| Finished | Jan 07 01:37:55 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-97a79688-9375-4ce3-a515-a4b788a0c8d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055715502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1055715502 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2259106080 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2305317023 ps |
| CPU time | 50.67 seconds |
| Started | Jan 07 01:38:46 PM PST 24 |
| Finished | Jan 07 01:39:38 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-08d50791-8c9f-4211-b666-11ab279f0a97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2259106080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2259106080 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1884721161 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 643596244 ps |
| CPU time | 28.66 seconds |
| Started | Jan 07 01:38:38 PM PST 24 |
| Finished | Jan 07 01:39:09 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-e6562218-6adb-403c-85a2-b24c071c1931 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1884721161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1884721161 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2159146463 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 197894999 ps |
| CPU time | 3.29 seconds |
| Started | Jan 07 01:38:25 PM PST 24 |
| Finished | Jan 07 01:38:29 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-78f98b92-b4d2-4c39-90f5-b6dbdac6b756 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2159146463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2159146463 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.3970722621 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2846604054 ps |
| CPU time | 19.56 seconds |
| Started | Jan 07 01:39:54 PM PST 24 |
| Finished | Jan 07 01:40:37 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-8a005ae3-2374-4ea9-91c4-2272580d87f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3970722621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3970722621 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2757912611 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 8777326796 ps |
| CPU time | 56.3 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:41:13 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-e013baaf-aba8-465c-ab07-c3d345e842cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2757912611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.2757912611 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1420983976 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 1507271278 ps |
| CPU time | 7.37 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:09 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-2ccef8c5-e488-4ce4-a974-189eebb66b67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1420983976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1420983976 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.3007564220 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 167631441 ps |
| CPU time | 10.53 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:40:05 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-f83a59dd-8c41-4f3c-953d-b34a0d7082d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3007564220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3007564220 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.1801666111 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 142684672 ps |
| CPU time | 8.94 seconds |
| Started | Jan 07 01:39:51 PM PST 24 |
| Finished | Jan 07 01:40:22 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-2a7f3277-956f-41af-a88b-ca4c64e389c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1801666111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1801666111 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2509822389 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 46864468727 ps |
| CPU time | 169.33 seconds |
| Started | Jan 07 01:39:30 PM PST 24 |
| Finished | Jan 07 01:42:26 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-a559fb0b-fdb9-4cfc-abd7-d752f3322a3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509822389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2509822389 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1115334658 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 16133168062 ps |
| CPU time | 27.29 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:40:14 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-5b020cad-5661-4ce0-90c4-b78f7dca1235 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1115334658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1115334658 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2351685202 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 227238103 ps |
| CPU time | 5.41 seconds |
| Started | Jan 07 01:39:46 PM PST 24 |
| Finished | Jan 07 01:40:09 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-ea58b52f-a5cc-4696-9972-42ff23f1f632 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351685202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2351685202 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.1232184999 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1326151624 ps |
| CPU time | 7.03 seconds |
| Started | Jan 07 01:39:46 PM PST 24 |
| Finished | Jan 07 01:40:11 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-36e825c3-fbca-46bc-b5e5-608925d1b120 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1232184999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1232184999 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.3122059368 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 16619379 ps |
| CPU time | 1.08 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:11 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-4e62f891-ba71-4e80-a01c-dfe2a62ab104 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3122059368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3122059368 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2633568395 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3372563165 ps |
| CPU time | 6.39 seconds |
| Started | Jan 07 01:39:17 PM PST 24 |
| Finished | Jan 07 01:39:26 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-2231bd1f-d5f6-4faf-aae8-1a75b3c30dd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633568395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2633568395 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3629188198 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 4547145750 ps |
| CPU time | 11.82 seconds |
| Started | Jan 07 01:39:42 PM PST 24 |
| Finished | Jan 07 01:40:09 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-cebdb046-115d-4505-b611-0ed38a768826 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3629188198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3629188198 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1919901395 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 13915748 ps |
| CPU time | 1.18 seconds |
| Started | Jan 07 01:39:19 PM PST 24 |
| Finished | Jan 07 01:39:25 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-320e0ea8-3a7f-4f5e-9d6f-f9f4b474d24f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919901395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1919901395 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.2155476904 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5898591381 ps |
| CPU time | 96.63 seconds |
| Started | Jan 07 01:40:20 PM PST 24 |
| Finished | Jan 07 01:42:22 PM PST 24 |
| Peak memory | 202588 kb |
| Host | smart-9a93e20a-7b61-440a-9d3d-a15c9d8cb257 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2155476904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2155476904 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2594456687 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 557074870 ps |
| CPU time | 30.1 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:31 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-5df23639-ca8d-4314-9b1c-369a3c0564ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2594456687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2594456687 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.92016743 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 671800515 ps |
| CPU time | 97.54 seconds |
| Started | Jan 07 01:40:03 PM PST 24 |
| Finished | Jan 07 01:42:09 PM PST 24 |
| Peak memory | 204016 kb |
| Host | smart-4757fd13-a1f3-4ee7-bbfe-4540ca982827 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=92016743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_ reset.92016743 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.4283741311 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 241276885 ps |
| CPU time | 17.56 seconds |
| Started | Jan 07 01:39:57 PM PST 24 |
| Finished | Jan 07 01:40:41 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-194fbb01-b4a7-40b3-8458-990563434224 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4283741311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.4283741311 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.897766502 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 72888062 ps |
| CPU time | 1.87 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-aae3f974-d7b3-4f58-af4a-0e93c1183c79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=897766502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.897766502 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3862953022 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 981799581 ps |
| CPU time | 22.36 seconds |
| Started | Jan 07 01:38:50 PM PST 24 |
| Finished | Jan 07 01:39:14 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-0c51ee6e-bd38-4d27-9faa-367036f6e978 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3862953022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3862953022 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.83346555 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 19739579877 ps |
| CPU time | 99.56 seconds |
| Started | Jan 07 01:38:41 PM PST 24 |
| Finished | Jan 07 01:40:22 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-8ce035da-c8ef-491c-9895-96a51456d920 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=83346555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow _rsp.83346555 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.635606929 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1750379620 ps |
| CPU time | 8.25 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:48 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-2b1672db-5ca3-4f1b-ba18-3097cd17a10f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=635606929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.635606929 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.4255584348 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 66708495 ps |
| CPU time | 3.98 seconds |
| Started | Jan 07 01:38:49 PM PST 24 |
| Finished | Jan 07 01:38:54 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-2ad729c5-493f-4ec8-ad89-a88d22da6285 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4255584348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.4255584348 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.3331790779 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 8616975 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:38:51 PM PST 24 |
| Finished | Jan 07 01:38:54 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-0274ea9b-087f-4b8c-85ae-800416e17586 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3331790779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3331790779 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2793522243 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 18262173962 ps |
| CPU time | 32.61 seconds |
| Started | Jan 07 01:39:11 PM PST 24 |
| Finished | Jan 07 01:39:46 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-75cfd815-223a-4bdf-a167-e2d3b5a096a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793522243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2793522243 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3714335698 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 16792387206 ps |
| CPU time | 115.36 seconds |
| Started | Jan 07 01:39:03 PM PST 24 |
| Finished | Jan 07 01:41:00 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-cee0ca4f-8cc0-4d71-bc95-f7f7229d67ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3714335698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3714335698 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.2098458857 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 66521207 ps |
| CPU time | 4.29 seconds |
| Started | Jan 07 01:39:10 PM PST 24 |
| Finished | Jan 07 01:39:17 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-6fca8b17-1e28-469e-8e88-52cd418f2123 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098458857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2098458857 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.391466873 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 70589310 ps |
| CPU time | 4.13 seconds |
| Started | Jan 07 01:39:02 PM PST 24 |
| Finished | Jan 07 01:39:07 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-9c1af7cd-369d-489c-abb1-83593b3dea2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=391466873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.391466873 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.2862082816 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 13373417 ps |
| CPU time | 1.24 seconds |
| Started | Jan 07 01:39:54 PM PST 24 |
| Finished | Jan 07 01:40:18 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-bcfa4aa4-c21f-4c85-a6b0-10e716be09a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2862082816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2862082816 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1742235755 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 7445624610 ps |
| CPU time | 13.52 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:40:30 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-2cf8e26c-acfd-41af-b71a-45f65cf33496 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742235755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1742235755 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2941218888 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1290739790 ps |
| CPU time | 8.92 seconds |
| Started | Jan 07 01:38:37 PM PST 24 |
| Finished | Jan 07 01:38:48 PM PST 24 |
| Peak memory | 201292 kb |
| Host | smart-e3884fce-4ff4-48f7-894b-3d545121dfcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2941218888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2941218888 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3704696227 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 9660485 ps |
| CPU time | 1.13 seconds |
| Started | Jan 07 01:39:55 PM PST 24 |
| Finished | Jan 07 01:40:20 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-7515c49e-ae9b-4e31-bbc4-f4207a89396c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704696227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3704696227 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.2449733286 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3540622260 ps |
| CPU time | 66.97 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:40:01 PM PST 24 |
| Peak memory | 202580 kb |
| Host | smart-e26ee3f0-8647-464a-a5fa-8d2f63987b35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2449733286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2449733286 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2402719404 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 383081514 ps |
| CPU time | 6.78 seconds |
| Started | Jan 07 01:39:20 PM PST 24 |
| Finished | Jan 07 01:39:31 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-e7fecb31-4b09-4d6f-908b-9191feb7254e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2402719404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2402719404 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.77045285 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 4044920636 ps |
| CPU time | 87.57 seconds |
| Started | Jan 07 01:39:10 PM PST 24 |
| Finished | Jan 07 01:40:40 PM PST 24 |
| Peak memory | 204204 kb |
| Host | smart-13e677b4-88ce-47fd-936c-38de44695668 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=77045285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_ reset.77045285 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3407596250 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 329127649 ps |
| CPU time | 20.69 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:40:16 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-ee204b00-351e-4577-b223-24f4da29d9f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3407596250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.3407596250 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1994679539 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 366366818 ps |
| CPU time | 4 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:38:58 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-d021a944-ce9c-459b-96ec-1d4c0f772f61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1994679539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1994679539 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1752366672 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 289432071 ps |
| CPU time | 6.26 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:40:00 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-a1e0cc48-a3de-4902-8390-30fe5e2b302b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1752366672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1752366672 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.242728192 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 260572934 ps |
| CPU time | 4.02 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:39:59 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-83f481c0-97d4-401b-b115-7b74b291e0ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=242728192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.242728192 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.105063318 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1118112746 ps |
| CPU time | 10.13 seconds |
| Started | Jan 07 01:39:43 PM PST 24 |
| Finished | Jan 07 01:40:08 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-11a2e746-9a2a-4db5-ba05-91a8c9863884 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=105063318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.105063318 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.2759347646 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 87582474 ps |
| CPU time | 6.23 seconds |
| Started | Jan 07 01:39:18 PM PST 24 |
| Finished | Jan 07 01:39:26 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-eebccb1c-fa42-4534-ab3a-aa949fb2fca7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2759347646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2759347646 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1736649633 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 143678829282 ps |
| CPU time | 155.18 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:42:31 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-d57a9f62-02f4-40da-a446-dac70eba30d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736649633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1736649633 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1603225449 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 8611415650 ps |
| CPU time | 60.07 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:40:52 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-a72f3dc1-4895-4752-93fe-ba2213bf8c78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1603225449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1603225449 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.1396327405 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 77876333 ps |
| CPU time | 2.01 seconds |
| Started | Jan 07 01:39:24 PM PST 24 |
| Finished | Jan 07 01:39:32 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-c237be2b-d3cf-4798-9361-193da959a4db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396327405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1396327405 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.342779863 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 93740750 ps |
| CPU time | 5.27 seconds |
| Started | Jan 07 01:39:45 PM PST 24 |
| Finished | Jan 07 01:40:07 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-76655120-b3f3-48b2-b137-a9cd3631f305 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=342779863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.342779863 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.1949208038 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 59283469 ps |
| CPU time | 1.29 seconds |
| Started | Jan 07 01:39:30 PM PST 24 |
| Finished | Jan 07 01:39:38 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-31543493-4ef9-4d54-8322-c393a32fb7ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1949208038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1949208038 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.795926047 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 16130822816 ps |
| CPU time | 14.18 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:14 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-260d88f3-1453-41ee-a942-ac8c436a423f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=795926047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.795926047 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3123956416 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1049335006 ps |
| CPU time | 6.9 seconds |
| Started | Jan 07 01:39:25 PM PST 24 |
| Finished | Jan 07 01:39:39 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-e86b28ba-5c83-4dd2-9c13-83c414271133 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3123956416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3123956416 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1988040557 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 8614713 ps |
| CPU time | 1.2 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:39:54 PM PST 24 |
| Peak memory | 201320 kb |
| Host | smart-594cbd22-a686-4154-a92c-9843a97ee3b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988040557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1988040557 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.100098683 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3966682379 ps |
| CPU time | 33.95 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:40:42 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-535d9817-267f-4400-831e-778159d43797 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=100098683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.100098683 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.362008557 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4020675237 ps |
| CPU time | 68.33 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:41:09 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-91aed573-d69e-4f5f-8fd5-d68ee04c0172 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=362008557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.362008557 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1579672481 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1226139072 ps |
| CPU time | 106.77 seconds |
| Started | Jan 07 01:39:30 PM PST 24 |
| Finished | Jan 07 01:41:24 PM PST 24 |
| Peak memory | 206972 kb |
| Host | smart-371be5f7-60f5-4a1d-892d-72915456e78b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1579672481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.1579672481 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3739301375 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 4936507002 ps |
| CPU time | 74.04 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:41:22 PM PST 24 |
| Peak memory | 204048 kb |
| Host | smart-7450dd66-2922-406c-94bd-06fba23caa29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3739301375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3739301375 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3107961938 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 456832412 ps |
| CPU time | 6.15 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:18 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-2dd241a0-6d2a-4d93-af39-042fd46803fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3107961938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3107961938 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.4282434996 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 15126274 ps |
| CPU time | 2.55 seconds |
| Started | Jan 07 01:38:53 PM PST 24 |
| Finished | Jan 07 01:38:58 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-6319ef34-b9c3-4832-b6d4-939003dfdbae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4282434996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.4282434996 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.4070057856 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 21098153095 ps |
| CPU time | 72.18 seconds |
| Started | Jan 07 01:38:54 PM PST 24 |
| Finished | Jan 07 01:40:08 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-4bf2cbbf-4d84-48c3-8e00-52c4b0d2e819 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4070057856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.4070057856 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1527432622 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 249820661 ps |
| CPU time | 4.88 seconds |
| Started | Jan 07 01:38:40 PM PST 24 |
| Finished | Jan 07 01:38:47 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-495cfd1b-acc6-43da-b50a-4776abcea251 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1527432622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1527432622 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.4292156967 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 409835412 ps |
| CPU time | 7.65 seconds |
| Started | Jan 07 01:38:39 PM PST 24 |
| Finished | Jan 07 01:38:49 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-c903de46-95fa-460d-87f6-3641f2ff150c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4292156967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.4292156967 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.3715630887 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 368245825 ps |
| CPU time | 6.33 seconds |
| Started | Jan 07 01:39:57 PM PST 24 |
| Finished | Jan 07 01:40:29 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-d9bddfeb-1dab-4ffd-a724-ccd96c28fde3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3715630887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3715630887 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.4259006294 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 29555076392 ps |
| CPU time | 129.77 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:42:26 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-4cc7d90e-4ad9-4bdb-9646-13da86de4700 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259006294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.4259006294 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3271685923 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 120197256109 ps |
| CPU time | 109.26 seconds |
| Started | Jan 07 01:39:11 PM PST 24 |
| Finished | Jan 07 01:41:03 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-0ce8eaed-112f-4a94-b979-5d404efd3577 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3271685923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3271685923 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.4134409452 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 34232282 ps |
| CPU time | 3.21 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:40:20 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-338e9517-07e2-41cb-bb74-ee267de30c95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134409452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.4134409452 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.2950219265 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 29174126 ps |
| CPU time | 1.48 seconds |
| Started | Jan 07 01:39:18 PM PST 24 |
| Finished | Jan 07 01:39:22 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-55b56358-56f5-463d-b3fe-cf358dd68bb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2950219265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2950219265 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.1379577049 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 154904775 ps |
| CPU time | 1.56 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-a64b7d1e-efc5-49ee-a350-bdf87670bdbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1379577049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1379577049 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2357320028 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2792497171 ps |
| CPU time | 8.9 seconds |
| Started | Jan 07 01:39:55 PM PST 24 |
| Finished | Jan 07 01:40:29 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-6e85cf0b-08f5-4dbb-88c5-ff92352e1e05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357320028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2357320028 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.688037682 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2798050744 ps |
| CPU time | 13.41 seconds |
| Started | Jan 07 01:39:52 PM PST 24 |
| Finished | Jan 07 01:40:28 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-5ad90d4a-de76-462a-bbcd-539aaa60271a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=688037682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.688037682 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.842056597 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 9141145 ps |
| CPU time | 1.07 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:39:51 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-c8d98b68-6f3f-48c2-a2c8-f3dd291bb957 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842056597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.842056597 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.460375028 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 147674384 ps |
| CPU time | 9.91 seconds |
| Started | Jan 07 01:39:23 PM PST 24 |
| Finished | Jan 07 01:39:38 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-11eea6e5-a2f6-4922-a341-3dcb44d1dcdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=460375028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.460375028 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2120939797 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2904886017 ps |
| CPU time | 39.5 seconds |
| Started | Jan 07 01:38:42 PM PST 24 |
| Finished | Jan 07 01:39:23 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-1274c7a2-37bd-4a4a-be1b-b606ac361127 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2120939797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2120939797 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1138623756 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 939797390 ps |
| CPU time | 52.39 seconds |
| Started | Jan 07 01:39:10 PM PST 24 |
| Finished | Jan 07 01:40:05 PM PST 24 |
| Peak memory | 205156 kb |
| Host | smart-d8e95af3-17f7-40c2-ac30-7c5ad1d68ee6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1138623756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.1138623756 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.93533886 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4891253787 ps |
| CPU time | 101.42 seconds |
| Started | Jan 07 01:39:17 PM PST 24 |
| Finished | Jan 07 01:41:01 PM PST 24 |
| Peak memory | 204092 kb |
| Host | smart-c911a7d3-5098-46e4-803e-91f01698b0c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=93533886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rese t_error.93533886 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1801954107 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1639350592 ps |
| CPU time | 5.84 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:45 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-16a4267e-ea56-4a90-85fb-0ccdbffb41d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1801954107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1801954107 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1121556045 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 93056430 ps |
| CPU time | 7 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:39:00 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-f08a91fe-79bb-4e2d-b677-e0d435fdb328 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1121556045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1121556045 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.679023048 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 140791215676 ps |
| CPU time | 302.85 seconds |
| Started | Jan 07 01:39:08 PM PST 24 |
| Finished | Jan 07 01:44:15 PM PST 24 |
| Peak memory | 203560 kb |
| Host | smart-c79b67a9-a4c2-4c5d-af20-8df2ca21b14e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=679023048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.679023048 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.195395444 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 672269081 ps |
| CPU time | 3.99 seconds |
| Started | Jan 07 01:38:55 PM PST 24 |
| Finished | Jan 07 01:39:00 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-66feb0b9-2e38-4cee-bbe9-cd594720ad0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=195395444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.195395444 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.3752934997 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 66629221 ps |
| CPU time | 7.98 seconds |
| Started | Jan 07 01:38:31 PM PST 24 |
| Finished | Jan 07 01:38:40 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-005a9094-5ee6-4fb1-828c-f23a6042742b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3752934997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3752934997 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.1508812404 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1442757972 ps |
| CPU time | 14.62 seconds |
| Started | Jan 07 01:39:20 PM PST 24 |
| Finished | Jan 07 01:39:38 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-a16a6153-9ca9-4405-a54f-6d8de1f75b68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1508812404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1508812404 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3329028779 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 13326434737 ps |
| CPU time | 54.51 seconds |
| Started | Jan 07 01:39:21 PM PST 24 |
| Finished | Jan 07 01:40:20 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-bc01d44b-cc43-4c8f-b613-29b5dfa061c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329028779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3329028779 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.838203431 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 48435356779 ps |
| CPU time | 85.16 seconds |
| Started | Jan 07 01:39:04 PM PST 24 |
| Finished | Jan 07 01:40:30 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-fcbc75c4-7259-4c30-8d82-a099a98b1e08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=838203431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.838203431 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.51356861 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 145499865 ps |
| CPU time | 6.24 seconds |
| Started | Jan 07 01:38:42 PM PST 24 |
| Finished | Jan 07 01:38:49 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-a4e4813b-9c98-493b-b23c-1565823eb6a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51356861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.51356861 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.3347961064 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 69252851 ps |
| CPU time | 5.91 seconds |
| Started | Jan 07 01:38:45 PM PST 24 |
| Finished | Jan 07 01:38:52 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-60f068d0-fb34-4e32-bade-1142b815c1f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3347961064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3347961064 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.3893868643 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 59314167 ps |
| CPU time | 1.43 seconds |
| Started | Jan 07 01:39:18 PM PST 24 |
| Finished | Jan 07 01:39:22 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-7979d9cd-7aaf-4306-8df2-e7ae5d1097c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3893868643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3893868643 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.187928550 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1641714540 ps |
| CPU time | 8.28 seconds |
| Started | Jan 07 01:38:45 PM PST 24 |
| Finished | Jan 07 01:38:55 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-e7171fbf-d856-4263-aadb-a87c2e2e1395 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=187928550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.187928550 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.538935453 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 1076447558 ps |
| CPU time | 6.3 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:39:45 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-cde90931-de2c-4507-aec7-bcf06f5477e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=538935453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.538935453 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3232301856 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 11341693 ps |
| CPU time | 1.02 seconds |
| Started | Jan 07 01:38:39 PM PST 24 |
| Finished | Jan 07 01:38:43 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-46691d0c-cfa3-4436-9b95-0682e79eacdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232301856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3232301856 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.1205343607 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4260180552 ps |
| CPU time | 40.95 seconds |
| Started | Jan 07 01:38:44 PM PST 24 |
| Finished | Jan 07 01:39:26 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-001e643d-882c-46f8-bced-a52d6d1b2e9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1205343607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1205343607 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1915946036 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 47527617095 ps |
| CPU time | 98.12 seconds |
| Started | Jan 07 01:38:53 PM PST 24 |
| Finished | Jan 07 01:40:33 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-ab0be5d9-3310-4bfc-8f3b-501f56458440 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1915946036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1915946036 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2795057441 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 201991013 ps |
| CPU time | 50.19 seconds |
| Started | Jan 07 01:39:18 PM PST 24 |
| Finished | Jan 07 01:40:11 PM PST 24 |
| Peak memory | 203184 kb |
| Host | smart-851e8d0f-105f-4086-8b8c-304f7852e2cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2795057441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.2795057441 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.525583713 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1455747639 ps |
| CPU time | 85.21 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:41:08 PM PST 24 |
| Peak memory | 206344 kb |
| Host | smart-2fa44b4b-56fc-49ea-9269-ea74303007a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=525583713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_res et_error.525583713 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1325301697 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 128188226 ps |
| CPU time | 3.09 seconds |
| Started | Jan 07 01:39:04 PM PST 24 |
| Finished | Jan 07 01:39:08 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-04c36056-cda1-4281-9737-32244bd70b24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1325301697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1325301697 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3273407472 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 447261017 ps |
| CPU time | 9.86 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:40:04 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-4f8b8a73-4cd0-43c4-9c56-e6ce48c4647e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3273407472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3273407472 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.123203397 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 78695024456 ps |
| CPU time | 239.34 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:43:52 PM PST 24 |
| Peak memory | 202372 kb |
| Host | smart-6acfed3f-d654-4f29-8da8-5de52691b013 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=123203397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo w_rsp.123203397 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3325477079 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 594349376 ps |
| CPU time | 7.13 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:39:55 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-cc5046c8-223f-4841-ade4-8ba5f86cd369 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3325477079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3325477079 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.3391418963 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 2134064831 ps |
| CPU time | 13.46 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:40:30 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-15beef6b-0b97-4397-b976-6bc26811e7c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3391418963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3391418963 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.2920337604 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2300619951 ps |
| CPU time | 9.63 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:40:05 PM PST 24 |
| Peak memory | 200596 kb |
| Host | smart-fb05b3b6-6986-4812-a051-daeb5330e43b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2920337604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2920337604 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3841513593 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 39443492477 ps |
| CPU time | 125.46 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:41:44 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-f81bdb1b-bb34-4969-9970-e5cf2eefdeb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841513593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3841513593 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1547634430 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 9404867000 ps |
| CPU time | 8.71 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:40:05 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-c183c36d-4f25-4e01-8c7c-55c9519d13e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1547634430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1547634430 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3951072475 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 50547412 ps |
| CPU time | 3.53 seconds |
| Started | Jan 07 01:39:14 PM PST 24 |
| Finished | Jan 07 01:39:20 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-fa9b8125-bd05-4943-afbf-5fc348f7143e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951072475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3951072475 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.1939077450 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1087678678 ps |
| CPU time | 11.62 seconds |
| Started | Jan 07 01:39:47 PM PST 24 |
| Finished | Jan 07 01:40:16 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-18f2ef01-dcaa-458e-bf5b-c2b890211c62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1939077450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1939077450 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.3463609683 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 42915988 ps |
| CPU time | 1.53 seconds |
| Started | Jan 07 01:39:17 PM PST 24 |
| Finished | Jan 07 01:39:21 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-bdcb604f-d7d0-4d94-a764-e8a28e1e552b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3463609683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3463609683 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.446906323 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 10790530699 ps |
| CPU time | 9.36 seconds |
| Started | Jan 07 01:39:23 PM PST 24 |
| Finished | Jan 07 01:39:38 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-92f29b83-9398-48ad-b2d8-4ac867a94b1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=446906323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.446906323 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.435638448 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1158048571 ps |
| CPU time | 7.99 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:39:02 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-8dce5945-71fd-4940-8fd8-dd81ef100a56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=435638448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.435638448 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2127575231 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 17789746 ps |
| CPU time | 1.31 seconds |
| Started | Jan 07 01:38:58 PM PST 24 |
| Finished | Jan 07 01:39:01 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-5f0796a6-848f-4cc6-8cd9-98b1ee0476aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127575231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2127575231 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.285487487 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 8690618193 ps |
| CPU time | 76.65 seconds |
| Started | Jan 07 01:39:21 PM PST 24 |
| Finished | Jan 07 01:40:44 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-17463b95-9635-4d3e-a918-4f0365cf4c56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=285487487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.285487487 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2950457005 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3846097151 ps |
| CPU time | 63.9 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:40:51 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-58795dbf-b2f9-4e1d-b2bd-d06f49c2395c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2950457005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2950457005 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1260849444 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 592330595 ps |
| CPU time | 52.61 seconds |
| Started | Jan 07 01:39:20 PM PST 24 |
| Finished | Jan 07 01:40:17 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-68a1c06b-c8d0-4540-8534-dfb8155ba1e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1260849444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.1260849444 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3610702010 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 5320700670 ps |
| CPU time | 74.43 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:40:57 PM PST 24 |
| Peak memory | 204988 kb |
| Host | smart-a3bf5994-d7fe-4ce8-aa80-18752d752f39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3610702010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.3610702010 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.1823623735 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 224072531 ps |
| CPU time | 4.88 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:40:01 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-d7329b9a-46f8-4037-97da-04654f570da1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1823623735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1823623735 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3171629190 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 87963204 ps |
| CPU time | 7.55 seconds |
| Started | Jan 07 01:39:34 PM PST 24 |
| Finished | Jan 07 01:39:58 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-0184f0bd-1d14-42d5-b92a-5ebbfa0d2c33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3171629190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3171629190 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.786530200 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 91054112 ps |
| CPU time | 2.4 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:41 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-c54baaff-5ae6-4c68-af11-fadda180c21f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=786530200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.786530200 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.2730873619 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 55822957 ps |
| CPU time | 7.19 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:39:45 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-510dc8c1-e683-4495-9c0f-1fe70ce78a52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2730873619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2730873619 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.1461634183 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 71015443 ps |
| CPU time | 5.4 seconds |
| Started | Jan 07 01:39:23 PM PST 24 |
| Finished | Jan 07 01:39:35 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-27488f99-fa07-49a9-a421-10c2984311c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1461634183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1461634183 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.2207149116 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 25010460834 ps |
| CPU time | 113.61 seconds |
| Started | Jan 07 01:40:02 PM PST 24 |
| Finished | Jan 07 01:42:24 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-64c3b5ca-8d28-41b6-95a5-3309d6a1b84c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207149116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2207149116 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2622349274 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 9046152012 ps |
| CPU time | 38.44 seconds |
| Started | Jan 07 01:39:02 PM PST 24 |
| Finished | Jan 07 01:39:41 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-c7bed00a-1f0b-4cbd-9bf9-6ce6f336beb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2622349274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2622349274 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3446464975 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 201365116 ps |
| CPU time | 6.96 seconds |
| Started | Jan 07 01:39:27 PM PST 24 |
| Finished | Jan 07 01:39:40 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-b56e761d-9460-4655-b95f-cfdb4a8bd3f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446464975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3446464975 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.4093278381 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 118585603 ps |
| CPU time | 5.98 seconds |
| Started | Jan 07 01:39:21 PM PST 24 |
| Finished | Jan 07 01:39:32 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-7e69bdc9-8360-4712-b19f-30dbcb7b41f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4093278381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.4093278381 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.3839836580 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 52803862 ps |
| CPU time | 1.51 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:39:39 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-54d14837-9986-49d2-adf0-c12a497b5836 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3839836580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3839836580 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.4214809967 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2541071027 ps |
| CPU time | 10.46 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-5c2d0e7d-422a-443f-af90-e4f738c2c418 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214809967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.4214809967 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1635407673 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1626623138 ps |
| CPU time | 10.28 seconds |
| Started | Jan 07 01:39:59 PM PST 24 |
| Finished | Jan 07 01:40:38 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-6f654b30-ecc1-4f31-836a-24f7c4b3a5ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1635407673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1635407673 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3324226134 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 10214368 ps |
| CPU time | 0.99 seconds |
| Started | Jan 07 01:38:45 PM PST 24 |
| Finished | Jan 07 01:38:47 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-cc3be776-74e4-432f-9ca8-e9b824f14b0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324226134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3324226134 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3203381369 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1907889255 ps |
| CPU time | 37.62 seconds |
| Started | Jan 07 01:39:28 PM PST 24 |
| Finished | Jan 07 01:40:12 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-07459e9e-f17f-45ec-800a-3f8fafceaa4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3203381369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3203381369 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.4100662722 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 847790142 ps |
| CPU time | 10.83 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:39:57 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-2745b0d5-e687-49c4-b4a8-ee4dba31ee99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4100662722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.4100662722 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2888055373 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 446701578 ps |
| CPU time | 52.22 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:41:00 PM PST 24 |
| Peak memory | 203548 kb |
| Host | smart-a68ec2fd-4bca-4e06-aee9-ec7e8a605dcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2888055373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.2888055373 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1887181280 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 793795724 ps |
| CPU time | 88.6 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:41:24 PM PST 24 |
| Peak memory | 205340 kb |
| Host | smart-4e01b71f-c7ee-40b9-a35f-5340dd29ae69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1887181280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.1887181280 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1471722905 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 24463956 ps |
| CPU time | 1.11 seconds |
| Started | Jan 07 01:39:48 PM PST 24 |
| Finished | Jan 07 01:40:08 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-fe1e01de-aa56-4865-837b-72d46340920d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1471722905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1471722905 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.2427057601 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 52773574 ps |
| CPU time | 6.07 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:16 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-9d4400ad-5872-4187-bde5-499b988dc6e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2427057601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2427057601 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2015991940 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1129264049 ps |
| CPU time | 8.15 seconds |
| Started | Jan 07 01:39:27 PM PST 24 |
| Finished | Jan 07 01:39:42 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-544e9da8-e26f-46a8-b7d6-7e305ecb1d99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2015991940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2015991940 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.2950167773 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 143943570 ps |
| CPU time | 2.63 seconds |
| Started | Jan 07 01:39:52 PM PST 24 |
| Finished | Jan 07 01:40:17 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-8ca990de-d2dd-44fd-b1fb-d3552a8d5194 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2950167773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2950167773 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.2229350114 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 21674949 ps |
| CPU time | 2.77 seconds |
| Started | Jan 07 01:39:34 PM PST 24 |
| Finished | Jan 07 01:39:47 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-6f3f94b6-c551-4ed0-8b87-6c36c8f66463 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2229350114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2229350114 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.45955793 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 26742774271 ps |
| CPU time | 98.51 seconds |
| Started | Jan 07 01:39:59 PM PST 24 |
| Finished | Jan 07 01:42:06 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-93cf9e2e-6296-4703-96c0-cf8196cce68b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=45955793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.45955793 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2014369808 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 21380390158 ps |
| CPU time | 110.93 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:41:46 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-cbd2dc5e-77bd-4974-a601-f4c72c0fa13f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2014369808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2014369808 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2395178673 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 195022653 ps |
| CPU time | 8.62 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:39:50 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-f046826b-5c0c-43df-a800-21e5100f83a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395178673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2395178673 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.1146357488 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 98003359 ps |
| CPU time | 4.25 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:39:53 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-0589a823-ed2a-455c-80d0-3de025f6f206 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1146357488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1146357488 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.4049630420 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 51057815 ps |
| CPU time | 1.53 seconds |
| Started | Jan 07 01:39:45 PM PST 24 |
| Finished | Jan 07 01:40:04 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-0a01e0c6-5f67-41d8-8027-3d55b6acb0ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4049630420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.4049630420 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3306453739 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 9736842608 ps |
| CPU time | 9.27 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:40:34 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-86160866-0f35-4442-9f78-811c634d2060 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306453739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3306453739 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3464632460 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 3972372232 ps |
| CPU time | 8.8 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-2963501f-4f37-44c7-b40f-e0a893540284 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3464632460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3464632460 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1169291072 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 18528419 ps |
| CPU time | 1.13 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:01 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-29ea413c-ab9e-4281-b345-8d031b944909 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169291072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1169291072 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.3368153706 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 6863761529 ps |
| CPU time | 75.52 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:41:08 PM PST 24 |
| Peak memory | 203288 kb |
| Host | smart-7e67b274-62b0-4e33-92d0-24465df9f68e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3368153706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3368153706 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2336091898 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3079742323 ps |
| CPU time | 48.81 seconds |
| Started | Jan 07 01:39:17 PM PST 24 |
| Finished | Jan 07 01:40:08 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-606684a3-a011-4107-8fb7-3de120e72632 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2336091898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2336091898 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1077541321 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 739428771 ps |
| CPU time | 112.06 seconds |
| Started | Jan 07 01:39:51 PM PST 24 |
| Finished | Jan 07 01:42:05 PM PST 24 |
| Peak memory | 203324 kb |
| Host | smart-dce6ad42-eeba-4ddc-ab98-b223158aced2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1077541321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.1077541321 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.739777663 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 17205952 ps |
| CPU time | 2.17 seconds |
| Started | Jan 07 01:39:54 PM PST 24 |
| Finished | Jan 07 01:40:21 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-82d7a11a-ee9f-4796-94d4-2ac481c117a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=739777663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.739777663 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3909427200 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 5505893789 ps |
| CPU time | 13.98 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:40:35 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-a869e613-87f5-420c-9745-30d1ab8371cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3909427200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3909427200 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2562840423 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 140702408 ps |
| CPU time | 4.36 seconds |
| Started | Jan 07 01:40:08 PM PST 24 |
| Finished | Jan 07 01:40:41 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-b1caa47f-5b8a-4063-8aa7-e48843af71f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2562840423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2562840423 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.3625697349 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 927344363 ps |
| CPU time | 5.08 seconds |
| Started | Jan 07 01:40:17 PM PST 24 |
| Finished | Jan 07 01:40:48 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-0efe37cd-616d-4a0d-9566-6ad14c2f4011 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3625697349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3625697349 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.3819207100 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 109429946 ps |
| CPU time | 5.77 seconds |
| Started | Jan 07 01:39:54 PM PST 24 |
| Finished | Jan 07 01:40:23 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-0fc74d28-1671-4f8e-a464-05d58f1552c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3819207100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3819207100 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.180948451 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 4008607663 ps |
| CPU time | 12.89 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:40:22 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-75f4e3a2-19a1-429b-8d91-4ab1face2098 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=180948451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.180948451 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.4060983075 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 27281107386 ps |
| CPU time | 191.88 seconds |
| Started | Jan 07 01:39:57 PM PST 24 |
| Finished | Jan 07 01:43:35 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-329afb37-386c-4db5-9825-29d96cb08a9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4060983075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4060983075 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2809233612 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 52530432 ps |
| CPU time | 6.63 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:47 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-cd55d3d2-d74a-4b36-9c49-9e5be67f8871 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809233612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2809233612 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.3996053969 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 648680727 ps |
| CPU time | 4.38 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:40:30 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-c3d4f020-c7ee-4af5-ac43-db912f34a892 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3996053969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3996053969 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.3250267166 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 14346412 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:39:57 PM PST 24 |
| Peak memory | 201336 kb |
| Host | smart-bd59cf1a-aff2-4e6d-8b57-8d9ea1163ea3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3250267166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3250267166 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1670012575 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 2752041783 ps |
| CPU time | 12.17 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:40:06 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-1235084b-473e-4014-b0da-55bf0420d7d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670012575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1670012575 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.4025649687 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1087642412 ps |
| CPU time | 8.67 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:40:30 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-cefa36dc-6839-4284-8e01-571d52d4ee7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4025649687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4025649687 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2930485246 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 10527362 ps |
| CPU time | 1.09 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:39:56 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-8a0b80e9-8adc-4356-9bd8-494117cd9cd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930485246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2930485246 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.509270425 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 175716797 ps |
| CPU time | 18.62 seconds |
| Started | Jan 07 01:40:17 PM PST 24 |
| Finished | Jan 07 01:41:01 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-611e5d14-d390-4a01-a6a6-3d87ef8e1006 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=509270425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.509270425 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2479398358 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1998987522 ps |
| CPU time | 26.72 seconds |
| Started | Jan 07 01:40:12 PM PST 24 |
| Finished | Jan 07 01:41:06 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-cb743c03-0c83-412c-909e-fdf13bf88f68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2479398358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2479398358 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1236593432 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3549283837 ps |
| CPU time | 55.69 seconds |
| Started | Jan 07 01:40:14 PM PST 24 |
| Finished | Jan 07 01:41:37 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-1edf2554-040b-425c-9f5e-8f14708c74a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1236593432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.1236593432 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.36726341 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2583379602 ps |
| CPU time | 11.23 seconds |
| Started | Jan 07 01:39:55 PM PST 24 |
| Finished | Jan 07 01:40:31 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-f28f9ea8-c781-40cd-8ab1-c936ce5a87fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=36726341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.36726341 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.3119490932 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 57999600 ps |
| CPU time | 9.78 seconds |
| Started | Jan 07 01:39:20 PM PST 24 |
| Finished | Jan 07 01:39:33 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-26066fdd-234c-49f6-b8a5-8e33191db7a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3119490932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3119490932 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3762275076 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 82186494403 ps |
| CPU time | 151.76 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:42:08 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-19268345-45a7-461d-8db4-96deeafcb798 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3762275076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.3762275076 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.301717054 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 940228040 ps |
| CPU time | 9.1 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-a907a004-12df-4c9f-b76c-21d74a51fb1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=301717054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.301717054 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.626199841 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4780437804 ps |
| CPU time | 11.75 seconds |
| Started | Jan 07 01:39:27 PM PST 24 |
| Finished | Jan 07 01:39:46 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-0176d6ba-efb0-4ab4-86d7-1c7665e33eb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=626199841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.626199841 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.697951474 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 347726839 ps |
| CPU time | 8.05 seconds |
| Started | Jan 07 01:40:24 PM PST 24 |
| Finished | Jan 07 01:40:56 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-b33c37bb-d2ca-4e01-88e8-55c619b057a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=697951474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.697951474 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.3039192752 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 48534324075 ps |
| CPU time | 48.81 seconds |
| Started | Jan 07 01:39:24 PM PST 24 |
| Finished | Jan 07 01:40:19 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-a6a2f568-a67e-483b-8e0b-c38892d99891 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039192752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3039192752 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3382229169 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 9443785363 ps |
| CPU time | 51.77 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:40:44 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-b79fa86c-0de4-4194-9b07-40489c8b7078 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3382229169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3382229169 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.1263642194 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 384274947 ps |
| CPU time | 8.05 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:40:34 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-ec15d845-fb3f-487e-8577-1d49b66de08b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263642194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1263642194 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.2261276129 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 303195710 ps |
| CPU time | 4.55 seconds |
| Started | Jan 07 01:39:34 PM PST 24 |
| Finished | Jan 07 01:39:49 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-fb19ebfd-5933-4bfa-b533-865d23db8fd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2261276129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2261276129 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.3347240437 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 54573530 ps |
| CPU time | 1.49 seconds |
| Started | Jan 07 01:40:15 PM PST 24 |
| Finished | Jan 07 01:40:43 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-bb8ba658-3413-48be-b349-c88da0b5cec6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3347240437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3347240437 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2073875358 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 4483667771 ps |
| CPU time | 8.27 seconds |
| Started | Jan 07 01:40:29 PM PST 24 |
| Finished | Jan 07 01:41:03 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-1b5912cb-ba1a-433a-acc1-a15db2462de1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073875358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2073875358 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2994031231 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1110127418 ps |
| CPU time | 7.03 seconds |
| Started | Jan 07 01:40:25 PM PST 24 |
| Finished | Jan 07 01:40:55 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-2114001b-942b-478b-bc50-32f51d2d027d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2994031231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2994031231 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3468294096 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 8529377 ps |
| CPU time | 1.18 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:42 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-02bb466c-c0ec-4b70-951c-0e835a96ec19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468294096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3468294096 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.3958513949 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1624215645 ps |
| CPU time | 28.99 seconds |
| Started | Jan 07 01:39:42 PM PST 24 |
| Finished | Jan 07 01:40:31 PM PST 24 |
| Peak memory | 201968 kb |
| Host | smart-811e41af-581d-4fff-9388-de4c29de7b88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3958513949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3958513949 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3985999404 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 116035628 ps |
| CPU time | 9.73 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:49 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-a9b72e21-557d-495a-b93e-c8653cfb221c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3985999404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3985999404 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.376724832 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 242030703 ps |
| CPU time | 26.81 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:40:07 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-c22c03b0-dc8c-4b7c-8fbb-9c2df8a36a89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=376724832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand _reset.376724832 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2925303801 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 960749246 ps |
| CPU time | 72.48 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:41:13 PM PST 24 |
| Peak memory | 204916 kb |
| Host | smart-0b0890e8-b843-4a01-8884-44e93f3dc4f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2925303801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.2925303801 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.868915029 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 740049961 ps |
| CPU time | 10.12 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:40:05 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-7841f4da-b240-4a48-8443-5897118896cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=868915029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.868915029 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.3431021650 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 226690720 ps |
| CPU time | 12.25 seconds |
| Started | Jan 07 01:38:52 PM PST 24 |
| Finished | Jan 07 01:39:06 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-660ed805-dc49-45b7-837a-b6c729d90249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3431021650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3431021650 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2680409248 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 18526215985 ps |
| CPU time | 86.56 seconds |
| Started | Jan 07 01:39:00 PM PST 24 |
| Finished | Jan 07 01:40:28 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-5697dbc4-2ea8-4c70-a064-5c38642456de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2680409248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.2680409248 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.2664694589 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 555364479 ps |
| CPU time | 8.65 seconds |
| Started | Jan 07 01:39:26 PM PST 24 |
| Finished | Jan 07 01:39:41 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-717d901a-182f-46d5-b9b0-0b64dead6e8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2664694589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2664694589 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.2501604161 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2473622010 ps |
| CPU time | 8.82 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:39:59 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-fbea800d-ba43-4237-a1a6-cdf6beb7b791 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2501604161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2501604161 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.3804890378 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 611303314 ps |
| CPU time | 10.05 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:10 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-4e68d832-1ce1-4fcf-bf72-95671c580db1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3804890378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3804890378 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.1224887510 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 32800140554 ps |
| CPU time | 83.59 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:41:02 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-a08ff66c-b5d1-443b-91e0-e65938b95ef4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224887510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1224887510 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.4163129563 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 14666393419 ps |
| CPU time | 98.03 seconds |
| Started | Jan 07 01:38:49 PM PST 24 |
| Finished | Jan 07 01:40:29 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-fac06e4f-69de-4a8c-84e4-b3dad6009ba0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4163129563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4163129563 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1421822262 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 74597120 ps |
| CPU time | 7.34 seconds |
| Started | Jan 07 01:38:57 PM PST 24 |
| Finished | Jan 07 01:39:06 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-b71647b9-f6b6-4618-a666-c1da6ea9ea00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421822262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1421822262 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3019233445 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 980407110 ps |
| CPU time | 13.04 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:40:07 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-d1e0674e-5c6e-4984-9d9b-e583213d8ea2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3019233445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3019233445 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.3739756453 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 44269115 ps |
| CPU time | 1.46 seconds |
| Started | Jan 07 01:38:56 PM PST 24 |
| Finished | Jan 07 01:38:59 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-cf9a9576-467c-436a-9e60-227f27b4f1b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3739756453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3739756453 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3830323117 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3894352861 ps |
| CPU time | 9.07 seconds |
| Started | Jan 07 01:39:24 PM PST 24 |
| Finished | Jan 07 01:39:40 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-6e5bfae6-bfbf-4c87-a520-ceb3289c8f92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830323117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3830323117 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2246032425 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1302170128 ps |
| CPU time | 9.22 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:40:03 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-1c9a3d3e-ccf8-4df2-a520-daf988465bbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2246032425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2246032425 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2164030022 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 9577605 ps |
| CPU time | 1.09 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:40 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-35cf8226-a873-440f-929b-e0b1d859ed75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164030022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2164030022 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3613920163 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 5230052899 ps |
| CPU time | 34.85 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:47 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-22d5aea2-4ba8-440c-a13f-1a6710008f9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3613920163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3613920163 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3748805439 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1291037972 ps |
| CPU time | 34.61 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:40:24 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-20e29807-b854-40ab-9b87-17a3720a08c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3748805439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3748805439 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3379282878 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 258168569 ps |
| CPU time | 27.61 seconds |
| Started | Jan 07 01:39:25 PM PST 24 |
| Finished | Jan 07 01:39:59 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-8682a8dd-2b4a-4905-801e-c42416b873b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3379282878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.3379282878 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.628091767 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 779501976 ps |
| CPU time | 92.34 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:41:27 PM PST 24 |
| Peak memory | 205760 kb |
| Host | smart-338bbc7d-bb24-4360-8be2-d0680d1aef8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=628091767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rese t_error.628091767 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3913362696 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 847230203 ps |
| CPU time | 10.26 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:39:59 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-45e9cf29-97b2-47e8-8306-ce7675f09bd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3913362696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3913362696 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.869543968 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 248345055 ps |
| CPU time | 3.56 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:04 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-4afdf864-b70a-4fa0-81f6-df444ed6429a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=869543968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.869543968 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3869913495 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 6234684360 ps |
| CPU time | 36.5 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:40:32 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-8e316fc8-e307-4a2a-9421-cca0c756a127 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3869913495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.3869913495 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.201337121 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 148924991 ps |
| CPU time | 2.61 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:39:58 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-e675a68d-c1b1-4126-8456-287dc354fb6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=201337121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.201337121 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.3222012493 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 63412458 ps |
| CPU time | 3.88 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:39:58 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-6fe9b74d-49df-444f-aa46-a555ac29444f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3222012493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3222012493 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.866255670 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 243344174 ps |
| CPU time | 4.45 seconds |
| Started | Jan 07 01:39:51 PM PST 24 |
| Finished | Jan 07 01:40:17 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-86f0c44e-4275-4f7b-9514-e2f6c1c8361d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=866255670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.866255670 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3773241472 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 15645948294 ps |
| CPU time | 55.5 seconds |
| Started | Jan 07 01:39:34 PM PST 24 |
| Finished | Jan 07 01:40:39 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-6ffbe593-8f27-44aa-9f9c-324d099d8688 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773241472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3773241472 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.2826275626 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 29197930575 ps |
| CPU time | 108.45 seconds |
| Started | Jan 07 01:39:45 PM PST 24 |
| Finished | Jan 07 01:41:51 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-43a63a6b-c7ba-483c-ad2f-a993da775c40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2826275626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2826275626 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.2863629397 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 235923414 ps |
| CPU time | 6.79 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:40:28 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-b1b9f079-ec9b-4fa0-af0a-a14db0677943 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863629397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2863629397 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.3184561219 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 294106556 ps |
| CPU time | 3.32 seconds |
| Started | Jan 07 01:40:01 PM PST 24 |
| Finished | Jan 07 01:40:32 PM PST 24 |
| Peak memory | 201332 kb |
| Host | smart-2b5ed4e2-5b13-497d-bd7b-8d179fffd63c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3184561219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3184561219 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.2815034201 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 113668780 ps |
| CPU time | 1.25 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:39:55 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-e4196aef-5af6-464c-a615-ebb65694e9ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2815034201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2815034201 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3141859791 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3868079413 ps |
| CPU time | 10.46 seconds |
| Started | Jan 07 01:39:52 PM PST 24 |
| Finished | Jan 07 01:40:25 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-4eae2654-56e1-4c6f-829d-68ffdffd6349 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141859791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3141859791 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.41125504 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 981522008 ps |
| CPU time | 7.99 seconds |
| Started | Jan 07 01:39:48 PM PST 24 |
| Finished | Jan 07 01:40:14 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-6f2121d1-8022-4ad7-8d10-2ca91e16d307 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=41125504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.41125504 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2006708033 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 9406008 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:39:58 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-33bf2bb7-3774-4f21-a894-2690c3eb26f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006708033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2006708033 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2816487871 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2679652992 ps |
| CPU time | 41.94 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:41:03 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-39d13a0d-0e66-481d-a2a3-5380cb5e6f73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2816487871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2816487871 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2496324644 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 813905856 ps |
| CPU time | 7.82 seconds |
| Started | Jan 07 01:40:11 PM PST 24 |
| Finished | Jan 07 01:40:47 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-23f44419-bee5-4046-9be3-5e698d1635de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2496324644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2496324644 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2144937519 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 39217580 ps |
| CPU time | 7.59 seconds |
| Started | Jan 07 01:39:51 PM PST 24 |
| Finished | Jan 07 01:40:21 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-6539d5cc-f7c4-4160-8272-7c9b9ed2505f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2144937519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2144937519 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2212753150 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 422118305 ps |
| CPU time | 24.15 seconds |
| Started | Jan 07 01:39:46 PM PST 24 |
| Finished | Jan 07 01:40:28 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-37b8e29d-3c88-47fc-973d-c832943ea25f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2212753150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.2212753150 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.481274008 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 11795504 ps |
| CPU time | 1.07 seconds |
| Started | Jan 07 01:39:51 PM PST 24 |
| Finished | Jan 07 01:40:14 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-afdcbaa6-7595-49b4-b04d-2dce45a509b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=481274008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.481274008 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.4085540628 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 39651554 ps |
| CPU time | 7.83 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-9dd2f47d-8c18-4b1a-886c-8ff21bb0f2eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4085540628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.4085540628 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.587079272 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 81205756791 ps |
| CPU time | 112.45 seconds |
| Started | Jan 07 01:39:30 PM PST 24 |
| Finished | Jan 07 01:41:29 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-4131891d-0991-4ebe-a6d8-eec4ee6b6909 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=587079272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo w_rsp.587079272 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.586785093 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 149081254 ps |
| CPU time | 4.9 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:39:41 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-3af04953-a502-4fed-a628-809026bc766c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=586785093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.586785093 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.3184988352 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2029483503 ps |
| CPU time | 5 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:39:43 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-340ef1d5-979d-410b-8c25-3e6fc279dc2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3184988352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3184988352 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.112553301 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 111533443 ps |
| CPU time | 6.43 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:17 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-70ce0add-f7fe-4b91-8901-c033b71d9912 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=112553301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.112553301 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.432013998 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 64483005290 ps |
| CPU time | 84.06 seconds |
| Started | Jan 07 01:39:18 PM PST 24 |
| Finished | Jan 07 01:40:45 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-4c96b087-ef49-44b9-8888-20046e300687 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=432013998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.432013998 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1070878722 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 18398515479 ps |
| CPU time | 28.62 seconds |
| Started | Jan 07 01:39:23 PM PST 24 |
| Finished | Jan 07 01:39:57 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-8bd8b250-ed75-46b8-a0d8-af73c0e87c56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1070878722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1070878722 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.2274781717 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 122879898 ps |
| CPU time | 7.18 seconds |
| Started | Jan 07 01:40:11 PM PST 24 |
| Finished | Jan 07 01:40:46 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-9dfa0354-36b5-4940-a746-d990c61f9e04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274781717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2274781717 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.2345994466 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 569771783 ps |
| CPU time | 4.42 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:45 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-ffc0bb6d-e617-4a56-8ad1-836d6f505537 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2345994466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2345994466 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.2651207937 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 181532010 ps |
| CPU time | 1.58 seconds |
| Started | Jan 07 01:40:01 PM PST 24 |
| Finished | Jan 07 01:40:31 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-3164a31f-64e1-44b5-af0a-16ceb8b288a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2651207937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2651207937 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.740454521 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 1623595330 ps |
| CPU time | 7.55 seconds |
| Started | Jan 07 01:39:54 PM PST 24 |
| Finished | Jan 07 01:40:25 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-a4015256-b73a-42e9-8df3-a59a2072249e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=740454521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.740454521 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.723376008 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3938325719 ps |
| CPU time | 10.75 seconds |
| Started | Jan 07 01:39:43 PM PST 24 |
| Finished | Jan 07 01:40:09 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-78d27303-e188-4cdf-a995-d36772813624 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=723376008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.723376008 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1502489830 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 9095888 ps |
| CPU time | 1.12 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:41 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-770b6fef-e717-4248-8c20-4ff23a135392 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502489830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1502489830 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.455092026 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 343602768 ps |
| CPU time | 15.89 seconds |
| Started | Jan 07 01:39:25 PM PST 24 |
| Finished | Jan 07 01:39:48 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-3839e805-dd67-4b73-b184-624690708bf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=455092026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.455092026 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1953739931 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 15454214090 ps |
| CPU time | 52.22 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:40:35 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-02fa318f-52b8-46af-adbf-9564a78c6776 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1953739931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1953739931 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1310493674 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 751071941 ps |
| CPU time | 82.62 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:41:22 PM PST 24 |
| Peak memory | 203608 kb |
| Host | smart-ea2ae170-1d7f-4da0-bae7-ac830f75808c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1310493674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1310493674 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1378411884 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1008693230 ps |
| CPU time | 45.79 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:40:43 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-6ef5a7af-bade-4af6-94a3-4a63a1f4f0be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1378411884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.1378411884 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.553662485 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 59132345 ps |
| CPU time | 6.41 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:40:03 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-ec73c4d2-20c0-4d1f-a94b-ba98a8a3f915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=553662485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.553662485 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3628357877 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 42660463 ps |
| CPU time | 1.55 seconds |
| Started | Jan 07 01:39:42 PM PST 24 |
| Finished | Jan 07 01:40:06 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-abf32b41-5a4c-4fcf-872a-2b2c380226e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3628357877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3628357877 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.950760064 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 18617129863 ps |
| CPU time | 144.25 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:42:19 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-1b3bd87e-c621-4e5a-a0cc-4cebb1098e70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=950760064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slo w_rsp.950760064 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3816822045 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 680513766 ps |
| CPU time | 8.77 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:39:56 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-39f078ba-fd49-4e01-8071-f0ec771a8880 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3816822045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3816822045 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.4242826607 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 1469662892 ps |
| CPU time | 4.67 seconds |
| Started | Jan 07 01:40:03 PM PST 24 |
| Finished | Jan 07 01:40:37 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-e30f0c0c-eeca-41a4-bb89-b77a89ba62ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4242826607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.4242826607 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.2828850065 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 32794847 ps |
| CPU time | 2.56 seconds |
| Started | Jan 07 01:40:07 PM PST 24 |
| Finished | Jan 07 01:40:38 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-8df1b8da-c700-4870-beb7-87f08d3123e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2828850065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2828850065 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1783432562 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 14872678097 ps |
| CPU time | 53.63 seconds |
| Started | Jan 07 01:39:45 PM PST 24 |
| Finished | Jan 07 01:40:56 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-66fd7d9b-10a8-4faf-96b3-2b02ff9fa3cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783432562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1783432562 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1930245339 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 8220035509 ps |
| CPU time | 32.75 seconds |
| Started | Jan 07 01:39:42 PM PST 24 |
| Finished | Jan 07 01:40:30 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-18e5c875-ba43-46f7-9497-5f26deab327d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1930245339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1930245339 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.4025698065 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 113744384 ps |
| CPU time | 4.06 seconds |
| Started | Jan 07 01:39:34 PM PST 24 |
| Finished | Jan 07 01:39:49 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-4d15249b-86b6-4d44-8387-8a19adf6462e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025698065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.4025698065 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.2068933203 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 394045870 ps |
| CPU time | 4.4 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:05 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-d7581537-46ce-479c-b4fd-29fb97090ae0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2068933203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2068933203 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.3650523980 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 9286247 ps |
| CPU time | 1.02 seconds |
| Started | Jan 07 01:39:47 PM PST 24 |
| Finished | Jan 07 01:40:06 PM PST 24 |
| Peak memory | 201308 kb |
| Host | smart-efb7d5dc-968d-4714-91f3-86a33fabb672 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3650523980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3650523980 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2644863738 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2011024985 ps |
| CPU time | 9.05 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:40:18 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-737ba7aa-bbd0-403c-a871-d54aa3766a7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644863738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2644863738 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3920501541 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2132041987 ps |
| CPU time | 8.34 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:39:59 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-d6c91932-78ca-4b37-bcbe-87fc2748fd16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3920501541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3920501541 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.410318924 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 9244139 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:39:48 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-9fc439bb-0c4d-4072-b100-390994a562bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410318924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.410318924 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.3109606909 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 424066262 ps |
| CPU time | 5.65 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:45 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-dfa8c0f3-4cc0-4a02-beea-193691aad737 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3109606909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3109606909 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2730889304 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3812041666 ps |
| CPU time | 38.82 seconds |
| Started | Jan 07 01:40:00 PM PST 24 |
| Finished | Jan 07 01:41:07 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-a3a0ac12-0bae-4c89-a7b8-fb2e26abf28a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2730889304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2730889304 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1640237828 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 710809820 ps |
| CPU time | 110.93 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:41:48 PM PST 24 |
| Peak memory | 204916 kb |
| Host | smart-7962cd37-0981-4ba1-8a3f-bc1665442451 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1640237828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.1640237828 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.399938654 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 9291678635 ps |
| CPU time | 85.52 seconds |
| Started | Jan 07 01:40:05 PM PST 24 |
| Finished | Jan 07 01:41:59 PM PST 24 |
| Peak memory | 204520 kb |
| Host | smart-e2d0594e-7c82-41a1-a7c2-8b66c3bc49b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=399938654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_res et_error.399938654 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3799137113 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1576710423 ps |
| CPU time | 11.52 seconds |
| Started | Jan 07 01:39:48 PM PST 24 |
| Finished | Jan 07 01:40:19 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-61ef4518-6543-446a-8362-272746e82c65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3799137113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3799137113 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.579574758 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 73558427 ps |
| CPU time | 1.68 seconds |
| Started | Jan 07 01:39:43 PM PST 24 |
| Finished | Jan 07 01:40:01 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-2acaf234-453e-4ee0-b8d6-930b0517b52a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=579574758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.579574758 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1615617066 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 54763823059 ps |
| CPU time | 249.03 seconds |
| Started | Jan 07 01:40:02 PM PST 24 |
| Finished | Jan 07 01:44:39 PM PST 24 |
| Peak memory | 203608 kb |
| Host | smart-14eea88b-c320-4628-a00c-cfef723a720e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1615617066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.1615617066 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2015709742 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 751264019 ps |
| CPU time | 10.08 seconds |
| Started | Jan 07 01:39:52 PM PST 24 |
| Finished | Jan 07 01:40:24 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-b8008efc-20fb-46ec-8046-bf96be3eeebf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2015709742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2015709742 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.821023091 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 1025540883 ps |
| CPU time | 11.09 seconds |
| Started | Jan 07 01:40:28 PM PST 24 |
| Finished | Jan 07 01:41:04 PM PST 24 |
| Peak memory | 201304 kb |
| Host | smart-e0f3b707-6fd3-4fec-973b-8038d6e62049 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=821023091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.821023091 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2493554865 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 92389135 ps |
| CPU time | 2.24 seconds |
| Started | Jan 07 01:40:11 PM PST 24 |
| Finished | Jan 07 01:40:42 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-aa9e1e62-94bf-4925-a6a2-51f5b8e754d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2493554865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2493554865 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2199788109 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 119636882354 ps |
| CPU time | 149.23 seconds |
| Started | Jan 07 01:40:06 PM PST 24 |
| Finished | Jan 07 01:43:04 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-0cf207b2-d012-4577-816d-d67e0df0df2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199788109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2199788109 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.674328833 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 6273910364 ps |
| CPU time | 48.64 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:41:01 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-259cc374-3c8c-4042-8910-e6d3b2ca4cbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=674328833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.674328833 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.844240271 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 107885758 ps |
| CPU time | 4.36 seconds |
| Started | Jan 07 01:40:14 PM PST 24 |
| Finished | Jan 07 01:40:46 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-a1f957f1-c98f-4b71-811e-785e060badee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844240271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.844240271 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.972030371 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 611450117 ps |
| CPU time | 4.77 seconds |
| Started | Jan 07 01:40:17 PM PST 24 |
| Finished | Jan 07 01:40:48 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-d5eb5a69-c8cf-4ee4-a2e0-3b00d980c14b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=972030371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.972030371 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.1839725687 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 8912782 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:40:26 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-1d33f7f2-c78a-406f-9128-eb11785b011b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1839725687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1839725687 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1558380460 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 3899184211 ps |
| CPU time | 6.8 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:07 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-43f29f9a-1e3a-49b6-b18d-6af1f87ab4b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558380460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1558380460 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1032903870 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 4789508048 ps |
| CPU time | 4.75 seconds |
| Started | Jan 07 01:40:07 PM PST 24 |
| Finished | Jan 07 01:40:41 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-abf94425-3fa5-4127-b33e-e087d1757bdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1032903870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1032903870 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2771602126 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 12919416 ps |
| CPU time | 1.24 seconds |
| Started | Jan 07 01:40:19 PM PST 24 |
| Finished | Jan 07 01:40:46 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-38506967-2700-49da-876e-d76c0e47e5f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771602126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2771602126 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.1077631427 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 162363083 ps |
| CPU time | 7.97 seconds |
| Started | Jan 07 01:40:39 PM PST 24 |
| Finished | Jan 07 01:41:14 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-733bcd89-d437-4f08-bb11-5c99f5b517e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1077631427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1077631427 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3515318729 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 683903601 ps |
| CPU time | 21.3 seconds |
| Started | Jan 07 01:40:12 PM PST 24 |
| Finished | Jan 07 01:41:01 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-891fa897-3265-44da-ab9c-99dad94a533f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3515318729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3515318729 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.340883265 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 6225407839 ps |
| CPU time | 102.08 seconds |
| Started | Jan 07 01:40:09 PM PST 24 |
| Finished | Jan 07 01:42:20 PM PST 24 |
| Peak memory | 205852 kb |
| Host | smart-2c9d0457-c6bf-4996-95f5-88cf0881ae3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=340883265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand _reset.340883265 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2547514304 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4466819521 ps |
| CPU time | 61.05 seconds |
| Started | Jan 07 01:40:14 PM PST 24 |
| Finished | Jan 07 01:41:42 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-6d2bcf4e-7555-44e7-b98c-368c86a1275f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2547514304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.2547514304 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1555126229 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2101430878 ps |
| CPU time | 9.29 seconds |
| Started | Jan 07 01:40:06 PM PST 24 |
| Finished | Jan 07 01:40:44 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-0efb0973-96a9-4693-a871-9ca83b825e1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1555126229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1555126229 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2322275452 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1510115498 ps |
| CPU time | 14.03 seconds |
| Started | Jan 07 01:39:46 PM PST 24 |
| Finished | Jan 07 01:40:18 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-7077d0e4-af2a-4a13-8568-1adb8ec88226 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2322275452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2322275452 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2462988622 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 15441644559 ps |
| CPU time | 67.39 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:40:46 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-0171ae4b-818c-4e24-a20b-16c15e0d87a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2462988622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.2462988622 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.89787784 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 138233682 ps |
| CPU time | 5.09 seconds |
| Started | Jan 07 01:39:42 PM PST 24 |
| Finished | Jan 07 01:40:03 PM PST 24 |
| Peak memory | 201348 kb |
| Host | smart-318d2e3d-59da-4ff3-a18c-a99f3ad1a1aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=89787784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.89787784 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.1301234839 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 196246391 ps |
| CPU time | 2.69 seconds |
| Started | Jan 07 01:39:43 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-d914e1b5-76c8-43b4-ae39-447c02a63a0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1301234839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1301234839 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.3843967880 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 520393585 ps |
| CPU time | 9.55 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:40:01 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-bac76c5a-b7f1-4857-9f7e-a3b776bf4247 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3843967880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3843967880 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.4143802125 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 10602440625 ps |
| CPU time | 37.54 seconds |
| Started | Jan 07 01:39:18 PM PST 24 |
| Finished | Jan 07 01:39:59 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-c6649ee2-9256-4fde-bcac-9bce421e7096 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143802125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4143802125 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1171641868 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 66433153968 ps |
| CPU time | 110.52 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:41:45 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-79e05572-e08e-4805-a67d-7183934b32a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1171641868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1171641868 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.932925951 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 39681187 ps |
| CPU time | 2.6 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:39:55 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-c4303e76-4617-4420-bd12-f91379dbedad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932925951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.932925951 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.2515246634 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1764992877 ps |
| CPU time | 5.63 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:23 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-a46e2bfc-0879-42e1-b8c3-3e56c5cb659c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2515246634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2515246634 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.2730599523 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 51089145 ps |
| CPU time | 1.54 seconds |
| Started | Jan 07 01:40:11 PM PST 24 |
| Finished | Jan 07 01:40:40 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-764670a6-ffc5-48ae-9e23-8b7c34923dd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2730599523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2730599523 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.193192459 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3234173380 ps |
| CPU time | 10.23 seconds |
| Started | Jan 07 01:40:18 PM PST 24 |
| Finished | Jan 07 01:40:54 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-d773fa69-d2c6-4b83-8bc3-f0f6ac20d257 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=193192459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.193192459 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.322395741 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1229074302 ps |
| CPU time | 7.86 seconds |
| Started | Jan 07 01:40:04 PM PST 24 |
| Finished | Jan 07 01:40:41 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-5e4028d9-5e49-44af-a5c5-0f6cc3483da8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=322395741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.322395741 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2202448272 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 9807636 ps |
| CPU time | 1.09 seconds |
| Started | Jan 07 01:40:34 PM PST 24 |
| Finished | Jan 07 01:41:01 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-06ffbb0a-38c7-4500-b5ff-1fe76981cc55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202448272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2202448272 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.4273666897 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 2095492922 ps |
| CPU time | 27.42 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:40:43 PM PST 24 |
| Peak memory | 201304 kb |
| Host | smart-427353c6-a8b0-4890-bd24-86c95460181f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4273666897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.4273666897 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1758378138 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 342602428 ps |
| CPU time | 34.82 seconds |
| Started | Jan 07 01:39:45 PM PST 24 |
| Finished | Jan 07 01:40:38 PM PST 24 |
| Peak memory | 203028 kb |
| Host | smart-88d69024-8d14-48ec-a93b-8232676be9be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1758378138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.1758378138 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.119664232 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 966969027 ps |
| CPU time | 47.85 seconds |
| Started | Jan 07 01:39:43 PM PST 24 |
| Finished | Jan 07 01:40:47 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-b686d0cb-6a70-49c1-a859-d0a24fd63ed8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=119664232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res et_error.119664232 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.2273805011 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 293889859 ps |
| CPU time | 5.53 seconds |
| Started | Jan 07 01:39:42 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-6c37b790-2636-431b-b6c9-0cb18db0c0da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2273805011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2273805011 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2914122190 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1047136693 ps |
| CPU time | 21.8 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:40:17 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-ce1cbbf6-16a9-4517-8315-010ceed8d34e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2914122190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2914122190 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2769950899 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 199934827804 ps |
| CPU time | 302.55 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:45:11 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-6d8a7a7b-9a76-4e63-94d1-da69a7e1a2e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2769950899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.2769950899 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1100045321 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 8529199 ps |
| CPU time | 1.04 seconds |
| Started | Jan 07 01:39:42 PM PST 24 |
| Finished | Jan 07 01:39:58 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-fef3cb94-0175-4a41-8915-d17fc31a56ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1100045321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1100045321 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.2583164226 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1766495897 ps |
| CPU time | 4.76 seconds |
| Started | Jan 07 01:39:52 PM PST 24 |
| Finished | Jan 07 01:40:20 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-8fece52b-da6d-48c5-b229-a0be0f439ab0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2583164226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2583164226 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.2703454196 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 826201932 ps |
| CPU time | 5.22 seconds |
| Started | Jan 07 01:40:11 PM PST 24 |
| Finished | Jan 07 01:40:44 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-aa9f7c5a-a12f-423e-abe4-b3606ea900fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2703454196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2703454196 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2876884251 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 45570301876 ps |
| CPU time | 40.52 seconds |
| Started | Jan 07 01:39:52 PM PST 24 |
| Finished | Jan 07 01:40:55 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-4bb7de78-06cd-4cb2-a00c-d250292e3a65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876884251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2876884251 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3563025345 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 21906269697 ps |
| CPU time | 145.58 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:42:25 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-4271e166-9ac7-40b1-b0c1-c824c7b76dfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3563025345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3563025345 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3286840035 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 350116572 ps |
| CPU time | 5.76 seconds |
| Started | Jan 07 01:40:04 PM PST 24 |
| Finished | Jan 07 01:40:39 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-06de21f0-42f8-4440-bc13-6008ed9be2cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286840035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3286840035 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.1869433583 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 534220066 ps |
| CPU time | 2.65 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:39:57 PM PST 24 |
| Peak memory | 201328 kb |
| Host | smart-c7941167-ee04-47c6-8756-fcfaa3eae29e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1869433583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1869433583 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.1484317921 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 62804738 ps |
| CPU time | 1.64 seconds |
| Started | Jan 07 01:39:25 PM PST 24 |
| Finished | Jan 07 01:39:33 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-d47f390a-f59b-42ce-b931-3f1723daeb12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1484317921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1484317921 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.2473810904 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2653868018 ps |
| CPU time | 9.36 seconds |
| Started | Jan 07 01:39:46 PM PST 24 |
| Finished | Jan 07 01:40:13 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-eaceac92-fc57-40ff-b932-8ac87fbb0cfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473810904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2473810904 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1385165851 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 2210529498 ps |
| CPU time | 7.33 seconds |
| Started | Jan 07 01:40:01 PM PST 24 |
| Finished | Jan 07 01:40:36 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-99580cc8-82bf-4b31-8d3e-a7315aede758 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1385165851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1385165851 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2796637275 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 10216347 ps |
| CPU time | 1.23 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:40:23 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-115dc124-989e-4979-9a11-3a2a0d784e8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796637275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2796637275 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.2979817497 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1509062956 ps |
| CPU time | 53.12 seconds |
| Started | Jan 07 01:39:52 PM PST 24 |
| Finished | Jan 07 01:41:07 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-2bcb6366-22f1-46a6-8a74-993bc6b787df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2979817497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2979817497 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1666256787 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 126797553 ps |
| CPU time | 11.61 seconds |
| Started | Jan 07 01:40:27 PM PST 24 |
| Finished | Jan 07 01:41:01 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-9b38e0f9-1cbe-495a-ad66-11c22445df49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1666256787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1666256787 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3397477562 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 142657309 ps |
| CPU time | 29.21 seconds |
| Started | Jan 07 01:40:12 PM PST 24 |
| Finished | Jan 07 01:41:08 PM PST 24 |
| Peak memory | 202608 kb |
| Host | smart-d9893da3-a605-4ad9-b64c-22a8bc922e7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3397477562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.3397477562 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3813246680 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 136182702 ps |
| CPU time | 2.2 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:39:59 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-a76c2d10-e828-4345-9c35-dd85cd057da1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3813246680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3813246680 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3097417585 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 70750325 ps |
| CPU time | 9.72 seconds |
| Started | Jan 07 01:40:21 PM PST 24 |
| Finished | Jan 07 01:40:55 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-269b8e1f-d8dc-4944-988a-0edafdf06130 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3097417585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3097417585 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1445343026 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 20266019038 ps |
| CPU time | 102.6 seconds |
| Started | Jan 07 01:40:32 PM PST 24 |
| Finished | Jan 07 01:42:41 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-866989e0-e880-45f2-a622-8aa428c0e2d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1445343026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.1445343026 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1011248459 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 66458445 ps |
| CPU time | 2.6 seconds |
| Started | Jan 07 01:40:42 PM PST 24 |
| Finished | Jan 07 01:41:11 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-9b404dd1-a9ec-4e51-815e-742a89945e03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1011248459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1011248459 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.4271192865 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 713469945 ps |
| CPU time | 8.19 seconds |
| Started | Jan 07 01:40:17 PM PST 24 |
| Finished | Jan 07 01:40:52 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-92a4cefc-6bfa-436a-98e0-64a02185dd0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4271192865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.4271192865 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.3242772954 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 709599747 ps |
| CPU time | 9.94 seconds |
| Started | Jan 07 01:39:43 PM PST 24 |
| Finished | Jan 07 01:40:09 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-c49d3703-e3e2-4411-a6d8-c514320d9c07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3242772954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3242772954 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2599854941 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 192300408611 ps |
| CPU time | 179.18 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:42:53 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-52fae186-0d27-470a-b0d3-db1c8a86d1ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599854941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2599854941 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1416571089 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 141371938765 ps |
| CPU time | 188.84 seconds |
| Started | Jan 07 01:40:15 PM PST 24 |
| Finished | Jan 07 01:43:51 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-f3018327-2649-4cbe-b12a-8417c0102cd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1416571089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1416571089 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2378938931 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 109953458 ps |
| CPU time | 4.43 seconds |
| Started | Jan 07 01:40:00 PM PST 24 |
| Finished | Jan 07 01:40:33 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-1075a591-06ef-4f1b-8f11-fd2c132e2202 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378938931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2378938931 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.3484732146 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1092364204 ps |
| CPU time | 6.68 seconds |
| Started | Jan 07 01:40:23 PM PST 24 |
| Finished | Jan 07 01:40:53 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-c7fd555b-58d8-4564-82ef-eceac9895d95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3484732146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3484732146 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.2830168111 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 43225312 ps |
| CPU time | 1.53 seconds |
| Started | Jan 07 01:40:07 PM PST 24 |
| Finished | Jan 07 01:40:38 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-0fe8f249-914d-44e5-9ec2-14c77b5a2365 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2830168111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2830168111 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1446377978 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 3595983546 ps |
| CPU time | 10.16 seconds |
| Started | Jan 07 01:40:05 PM PST 24 |
| Finished | Jan 07 01:40:45 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-00f5f386-010e-49fc-a3f7-94ddef006ac2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446377978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1446377978 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.212014419 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1088956970 ps |
| CPU time | 6.39 seconds |
| Started | Jan 07 01:40:06 PM PST 24 |
| Finished | Jan 07 01:40:41 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-a3e8a624-4ac2-48ea-ad7d-a4bb2f53c63b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=212014419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.212014419 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.738681333 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 10589589 ps |
| CPU time | 1.28 seconds |
| Started | Jan 07 01:40:21 PM PST 24 |
| Finished | Jan 07 01:40:47 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-f7263249-6707-412f-9e02-f5e03683acb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738681333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.738681333 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2096969745 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 7060456718 ps |
| CPU time | 103.65 seconds |
| Started | Jan 07 01:40:35 PM PST 24 |
| Finished | Jan 07 01:42:45 PM PST 24 |
| Peak memory | 203572 kb |
| Host | smart-51a69db1-8fe0-41f3-aae1-49ee3c38227f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2096969745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2096969745 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.186991354 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 1808516750 ps |
| CPU time | 8.79 seconds |
| Started | Jan 07 01:40:42 PM PST 24 |
| Finished | Jan 07 01:41:18 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-9690c18b-a9e7-418b-a25f-15d8759b7306 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=186991354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.186991354 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2459421441 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 990114449 ps |
| CPU time | 48.02 seconds |
| Started | Jan 07 01:40:34 PM PST 24 |
| Finished | Jan 07 01:41:48 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-6233c36d-280f-4619-a6d6-46552cf31bfd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2459421441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.2459421441 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.460629658 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 329007249 ps |
| CPU time | 61.06 seconds |
| Started | Jan 07 01:40:36 PM PST 24 |
| Finished | Jan 07 01:42:04 PM PST 24 |
| Peak memory | 203220 kb |
| Host | smart-5dc4a8b4-edbd-4d9e-8d8d-800b8310b38e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=460629658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_res et_error.460629658 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.61399017 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 53495349 ps |
| CPU time | 4.54 seconds |
| Started | Jan 07 01:40:26 PM PST 24 |
| Finished | Jan 07 01:40:54 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-70876886-6fd7-4c9f-88cc-21c8bc4bad2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=61399017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.61399017 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.2090150252 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 733101864 ps |
| CPU time | 14.48 seconds |
| Started | Jan 07 01:39:21 PM PST 24 |
| Finished | Jan 07 01:39:41 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-6099ee17-8586-4947-bc80-4cb60928c2f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2090150252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2090150252 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3001880881 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 15565824312 ps |
| CPU time | 55.88 seconds |
| Started | Jan 07 01:39:24 PM PST 24 |
| Finished | Jan 07 01:40:25 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-c27a1b6f-c84e-40f0-9c14-5ebb84ea23d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3001880881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.3001880881 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.4252369602 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 70823522 ps |
| CPU time | 4.32 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:39:57 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-3ac4a1c1-72d9-4e99-a2e1-ba4b4edbee9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4252369602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.4252369602 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.11626506 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 56092740 ps |
| CPU time | 4.49 seconds |
| Started | Jan 07 01:39:19 PM PST 24 |
| Finished | Jan 07 01:39:33 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-67eff84e-ff78-4799-b65d-25ad0aece8c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=11626506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.11626506 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.1476915950 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 26581022 ps |
| CPU time | 2.3 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:39:38 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-14052b7f-661a-48c9-b230-9ce0792ceccb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1476915950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1476915950 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.947377627 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 6754316753 ps |
| CPU time | 26.43 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:40:21 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-eb424b6e-843e-4b02-80db-21d0758cefc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=947377627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.947377627 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.671853183 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 16015830012 ps |
| CPU time | 23.36 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:40:16 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-5f8b34a6-80d7-4e09-9bf6-358def21237a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=671853183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.671853183 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.796428929 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 35040376 ps |
| CPU time | 5.09 seconds |
| Started | Jan 07 01:39:22 PM PST 24 |
| Finished | Jan 07 01:39:33 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-21ee7c6a-c12c-484d-a57f-89084ef6013d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796428929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.796428929 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.95361526 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 876646714 ps |
| CPU time | 11.67 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:39:53 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-7a48941b-b9b6-4cde-8597-8d90b4f61fa1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=95361526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.95361526 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.2295649158 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 31331382 ps |
| CPU time | 1.01 seconds |
| Started | Jan 07 01:39:25 PM PST 24 |
| Finished | Jan 07 01:39:32 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-a302b487-f25e-49c3-a03b-381701a5b75e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2295649158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2295649158 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2914846449 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1901976367 ps |
| CPU time | 9.1 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:21 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-72f2b43c-e11f-469d-85a9-8576509383e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914846449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2914846449 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.785760809 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 2017555209 ps |
| CPU time | 8.49 seconds |
| Started | Jan 07 01:40:08 PM PST 24 |
| Finished | Jan 07 01:40:45 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-ce9b7356-1afe-4676-90e3-a4cfb721d315 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=785760809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.785760809 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.244363983 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9330424 ps |
| CPU time | 1.2 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:39:38 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-cfcdf42b-7886-484b-a2e1-dfb07287fd62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244363983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.244363983 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3154738674 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 511414494 ps |
| CPU time | 7.07 seconds |
| Started | Jan 07 01:39:54 PM PST 24 |
| Finished | Jan 07 01:40:25 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-9dccd6ec-2511-44b6-adc4-4bba31da54df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3154738674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3154738674 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.671743761 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 4668986840 ps |
| CPU time | 40.99 seconds |
| Started | Jan 07 01:39:55 PM PST 24 |
| Finished | Jan 07 01:41:00 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-99ac7a86-3b6a-4423-bd9d-c5ebc7a7f70c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=671743761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.671743761 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.734774954 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 3923537928 ps |
| CPU time | 61.12 seconds |
| Started | Jan 07 01:39:55 PM PST 24 |
| Finished | Jan 07 01:41:22 PM PST 24 |
| Peak memory | 205284 kb |
| Host | smart-757a5e24-9dd8-49fe-848f-0c15e492dbed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=734774954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand _reset.734774954 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.4096965647 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4017558130 ps |
| CPU time | 92.61 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:41:13 PM PST 24 |
| Peak memory | 203560 kb |
| Host | smart-73b85202-d94f-41c6-9675-dce088b26f08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4096965647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.4096965647 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3313653880 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 974787903 ps |
| CPU time | 9.64 seconds |
| Started | Jan 07 01:39:15 PM PST 24 |
| Finished | Jan 07 01:39:27 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-2903d37e-6f24-462e-bff1-01ca4e3a8c4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3313653880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3313653880 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1479609705 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 872377743 ps |
| CPU time | 9.02 seconds |
| Started | Jan 07 01:39:54 PM PST 24 |
| Finished | Jan 07 01:40:27 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-dce57651-3eea-42a3-8ac8-e3dfdd7d32b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1479609705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1479609705 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3240593675 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 119787616204 ps |
| CPU time | 333.21 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:45:21 PM PST 24 |
| Peak memory | 203560 kb |
| Host | smart-ad0b2556-2d6e-48b1-9919-c0e5eb00739a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3240593675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.3240593675 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.35335864 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 28888994 ps |
| CPU time | 1.14 seconds |
| Started | Jan 07 01:40:02 PM PST 24 |
| Finished | Jan 07 01:40:32 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-9f5ef831-15c7-42e8-82b6-444ac830c175 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=35335864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.35335864 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.678540657 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 1781573764 ps |
| CPU time | 14.5 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:40:40 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-9575942d-336c-4b99-b719-b86936f47d11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=678540657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.678540657 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.2224292396 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 839133131 ps |
| CPU time | 10.92 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:40:05 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-d3f914b9-c215-4bfa-b093-6344c6b9be8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2224292396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2224292396 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.4262249375 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 50795352239 ps |
| CPU time | 100.73 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:41:50 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-f9dd2663-6b2a-405a-8fc0-1d35ed4e5dcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262249375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.4262249375 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1929160033 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 9813792973 ps |
| CPU time | 41.58 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:41:02 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-9fcba194-00a0-4988-92b4-c69af3750e06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1929160033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1929160033 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1963822522 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 61169271 ps |
| CPU time | 2.85 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:39:58 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-d8864b99-062f-4537-80a9-f3a3a7df9221 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963822522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1963822522 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.2404306437 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 148055897 ps |
| CPU time | 2.68 seconds |
| Started | Jan 07 01:39:34 PM PST 24 |
| Finished | Jan 07 01:39:47 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-385149b6-93da-4e4b-a35b-914fcc648fdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2404306437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2404306437 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.2513724207 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 145839411 ps |
| CPU time | 1.4 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:40:17 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-8e11d3f7-a297-4722-a8ac-2066c265151d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2513724207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2513724207 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.4078034680 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 7914948618 ps |
| CPU time | 9.53 seconds |
| Started | Jan 07 01:39:43 PM PST 24 |
| Finished | Jan 07 01:40:08 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-7ea64477-6c32-404b-818b-6409f51ebdb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078034680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.4078034680 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2469409241 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 878156240 ps |
| CPU time | 6.09 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-2c87bc97-b5b2-4f3d-8281-6892a82e0f3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2469409241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2469409241 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2974712272 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 13769349 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:40 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-a7cb999a-6fe1-4f89-ba40-fad4995b3361 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974712272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2974712272 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.4132534016 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 9654529738 ps |
| CPU time | 91.96 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:41:31 PM PST 24 |
| Peak memory | 202892 kb |
| Host | smart-603b0c2f-6bca-453e-a42b-3be60f7f6bea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4132534016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.4132534016 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.254709155 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 180241654 ps |
| CPU time | 15.03 seconds |
| Started | Jan 07 01:39:55 PM PST 24 |
| Finished | Jan 07 01:40:36 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-dae14fd4-2a93-4878-8106-8af2edc4bae0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=254709155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.254709155 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3983641719 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 635149802 ps |
| CPU time | 101.38 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:41:29 PM PST 24 |
| Peak memory | 206772 kb |
| Host | smart-fb41c278-69c0-44a9-a144-38ac8cfcb3e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3983641719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.3983641719 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2800341189 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 8250929106 ps |
| CPU time | 98.65 seconds |
| Started | Jan 07 01:40:09 PM PST 24 |
| Finished | Jan 07 01:42:15 PM PST 24 |
| Peak memory | 204268 kb |
| Host | smart-ea6d44fa-42e1-42a2-b61d-44242a813ec0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2800341189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.2800341189 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3293299646 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 542675158 ps |
| CPU time | 9.78 seconds |
| Started | Jan 07 01:39:59 PM PST 24 |
| Finished | Jan 07 01:40:37 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-ff14198a-61fc-48e8-bdfc-b114d463ce46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3293299646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3293299646 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3854803028 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 19022571 ps |
| CPU time | 1.58 seconds |
| Started | Jan 07 01:40:23 PM PST 24 |
| Finished | Jan 07 01:40:49 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-47ed9131-2d5b-483c-911c-732747d86cbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3854803028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3854803028 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.52281083 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 100351180 ps |
| CPU time | 6.99 seconds |
| Started | Jan 07 01:40:41 PM PST 24 |
| Finished | Jan 07 01:41:15 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-c39ef2c0-575f-4a6d-9cf1-33dd37b32296 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=52281083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.52281083 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.1853330658 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 279426062 ps |
| CPU time | 4.22 seconds |
| Started | Jan 07 01:40:19 PM PST 24 |
| Finished | Jan 07 01:40:49 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-b1b22e91-7cdd-4a80-b431-1eaa02bc80f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1853330658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1853330658 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.4111002429 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3216939942 ps |
| CPU time | 14.51 seconds |
| Started | Jan 07 01:40:17 PM PST 24 |
| Finished | Jan 07 01:40:58 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-4cbcc9a5-50b8-418e-91c6-84c96767e00f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4111002429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.4111002429 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.1227846733 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 23961684839 ps |
| CPU time | 101.08 seconds |
| Started | Jan 07 01:40:05 PM PST 24 |
| Finished | Jan 07 01:42:15 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-977c2bf8-56cc-42b3-89e7-dc307180e4ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227846733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1227846733 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2774164601 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 26028838505 ps |
| CPU time | 156.42 seconds |
| Started | Jan 07 01:40:26 PM PST 24 |
| Finished | Jan 07 01:43:25 PM PST 24 |
| Peak memory | 201532 kb |
| Host | smart-86e9ce77-09c2-4bdb-9209-9f197b1a70aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2774164601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2774164601 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3987723169 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 111613561 ps |
| CPU time | 6.54 seconds |
| Started | Jan 07 01:40:06 PM PST 24 |
| Finished | Jan 07 01:40:42 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-4018dce8-b761-4431-a1f4-7add8f2ee4d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987723169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3987723169 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.2187780377 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 44962957 ps |
| CPU time | 3.32 seconds |
| Started | Jan 07 01:40:11 PM PST 24 |
| Finished | Jan 07 01:40:42 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-fa892dda-4f80-42c5-a3db-9f20584aba53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2187780377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2187780377 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.3653495508 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 13142014 ps |
| CPU time | 1.19 seconds |
| Started | Jan 07 01:40:28 PM PST 24 |
| Finished | Jan 07 01:40:55 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-1ef49a46-5a26-4563-b98c-a255815990c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3653495508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3653495508 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2172169739 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1695193369 ps |
| CPU time | 6.48 seconds |
| Started | Jan 07 01:39:55 PM PST 24 |
| Finished | Jan 07 01:40:26 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-ab6dc111-ad74-4fda-8eb9-7f8a9ea852f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172169739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2172169739 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1473704887 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 7603884699 ps |
| CPU time | 12.36 seconds |
| Started | Jan 07 01:40:10 PM PST 24 |
| Finished | Jan 07 01:40:50 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-3318a021-91be-4ac4-ae47-cecefdaddb7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1473704887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1473704887 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2491526860 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 9464639 ps |
| CPU time | 1.01 seconds |
| Started | Jan 07 01:40:19 PM PST 24 |
| Finished | Jan 07 01:40:45 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-290483a4-2447-4f65-95be-9a171e96d6ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491526860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2491526860 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3965216830 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 659360615 ps |
| CPU time | 23.44 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:40:32 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-63ed339f-3fb4-4dae-bbd3-1a648f5b165a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3965216830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3965216830 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2850981976 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1857819475 ps |
| CPU time | 27.62 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:40:22 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-a876dce8-f402-4c25-80e7-afffe78490e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2850981976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2850981976 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.357708425 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 632489258 ps |
| CPU time | 95.65 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:41:12 PM PST 24 |
| Peak memory | 203904 kb |
| Host | smart-fa469d59-4f4f-49ab-b95c-511cd371b0de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=357708425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand _reset.357708425 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.92770132 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1096172770 ps |
| CPU time | 101.32 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:41:17 PM PST 24 |
| Peak memory | 205768 kb |
| Host | smart-86015cf2-dd6a-4722-90fc-03b2f7888ae7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=92770132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rese t_error.92770132 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3020599102 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 46026499 ps |
| CPU time | 4.03 seconds |
| Started | Jan 07 01:40:17 PM PST 24 |
| Finished | Jan 07 01:40:47 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-8cfc53a5-57dc-4b27-84cc-300a3cc14a02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3020599102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3020599102 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.572129774 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2570406382 ps |
| CPU time | 11.19 seconds |
| Started | Jan 07 01:37:58 PM PST 24 |
| Finished | Jan 07 01:38:11 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-f20c433e-d859-45d3-aaea-f81a1b0c09a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=572129774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.572129774 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2545935835 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 35861673846 ps |
| CPU time | 106.56 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:41:39 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-0cddb7bc-6154-4eed-9f99-7250fc6fe2e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2545935835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.2545935835 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2410237141 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 37406675 ps |
| CPU time | 1.2 seconds |
| Started | Jan 07 01:37:53 PM PST 24 |
| Finished | Jan 07 01:37:56 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-7f4f60a7-de40-451c-8448-ad43bab90252 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2410237141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2410237141 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.902961304 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 727914229 ps |
| CPU time | 10.59 seconds |
| Started | Jan 07 01:37:49 PM PST 24 |
| Finished | Jan 07 01:38:02 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-01206f3d-d954-46be-bcd7-5204b4f05da1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=902961304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.902961304 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.1302935940 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 442336139 ps |
| CPU time | 2.3 seconds |
| Started | Jan 07 01:38:25 PM PST 24 |
| Finished | Jan 07 01:38:28 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-4e8fc9fd-6ee6-4ac3-8aef-ddfbe389676f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1302935940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1302935940 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1632587271 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 49346526827 ps |
| CPU time | 113.53 seconds |
| Started | Jan 07 01:37:49 PM PST 24 |
| Finished | Jan 07 01:39:45 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-60b1e224-1f59-4053-866f-4cf4641ff305 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632587271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1632587271 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2473136401 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 11849768003 ps |
| CPU time | 85.68 seconds |
| Started | Jan 07 01:38:57 PM PST 24 |
| Finished | Jan 07 01:40:24 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-77dae16a-dab2-4f2d-ab62-7a561102ef01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2473136401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2473136401 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1820995215 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 18790409 ps |
| CPU time | 2.02 seconds |
| Started | Jan 07 01:38:08 PM PST 24 |
| Finished | Jan 07 01:38:11 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-36848e13-3f7c-48f1-ad3f-136f27e6697b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820995215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1820995215 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.1127970062 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 36143477 ps |
| CPU time | 4.22 seconds |
| Started | Jan 07 01:37:53 PM PST 24 |
| Finished | Jan 07 01:38:00 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-4cd86e7c-846b-45e4-9ec3-740319ae649e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1127970062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1127970062 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.3284343660 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 60582972 ps |
| CPU time | 1.41 seconds |
| Started | Jan 07 01:40:02 PM PST 24 |
| Finished | Jan 07 01:40:32 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-077d9eac-9c53-457c-ada3-3968895a674b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3284343660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3284343660 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2708988612 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 3313329180 ps |
| CPU time | 7.38 seconds |
| Started | Jan 07 01:39:45 PM PST 24 |
| Finished | Jan 07 01:40:10 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-e578ff16-5742-4c4d-b193-b2a15b6552db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708988612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2708988612 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3249161761 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 2260786612 ps |
| CPU time | 8.91 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:39:58 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-4c16b979-74a2-4d32-b9fd-590bfd066289 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3249161761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3249161761 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2829622467 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 12833311 ps |
| CPU time | 1.14 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:39:55 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-90a820f4-dfe2-4872-a43a-b4a7c68ffe50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829622467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2829622467 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.2177808249 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 867721730 ps |
| CPU time | 34.89 seconds |
| Started | Jan 07 01:37:45 PM PST 24 |
| Finished | Jan 07 01:38:21 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-d5d385ee-4150-4393-a514-e359d8eabec5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2177808249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2177808249 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2957408021 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 382438144 ps |
| CPU time | 28.75 seconds |
| Started | Jan 07 01:37:59 PM PST 24 |
| Finished | Jan 07 01:38:30 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-192a6311-76ba-4754-9f00-689669078af1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2957408021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2957408021 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.190092025 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 277675333 ps |
| CPU time | 50.91 seconds |
| Started | Jan 07 01:37:48 PM PST 24 |
| Finished | Jan 07 01:38:41 PM PST 24 |
| Peak memory | 203896 kb |
| Host | smart-186723ba-10ef-4901-9ade-83a0aa4244bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=190092025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_ reset.190092025 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.634540253 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 524683470 ps |
| CPU time | 89.19 seconds |
| Started | Jan 07 01:38:01 PM PST 24 |
| Finished | Jan 07 01:39:33 PM PST 24 |
| Peak memory | 205404 kb |
| Host | smart-b6646c6c-29cb-4e70-a47d-cf0a83ece209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=634540253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese t_error.634540253 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.4279813966 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 528879215 ps |
| CPU time | 11.52 seconds |
| Started | Jan 07 01:37:59 PM PST 24 |
| Finished | Jan 07 01:38:13 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-3df5fb0b-3016-4bf0-9368-e9b1338068d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4279813966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.4279813966 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3903622606 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 14751628 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 01:39:55 PM PST 24 |
| Finished | Jan 07 01:40:22 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-e2e36341-8769-4400-a370-5d349b53fc5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3903622606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3903622606 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.1712957114 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 77801219882 ps |
| CPU time | 320.33 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:45:08 PM PST 24 |
| Peak memory | 201664 kb |
| Host | smart-1c8ecf64-c609-4db7-8e4f-dc46be72c9e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1712957114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.1712957114 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1786986856 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 162329820 ps |
| CPU time | 3.33 seconds |
| Started | Jan 07 01:39:47 PM PST 24 |
| Finished | Jan 07 01:40:09 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-1b00e68b-7d1d-480f-8b49-1e47b543e264 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1786986856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1786986856 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.3776238559 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 497863815 ps |
| CPU time | 7.64 seconds |
| Started | Jan 07 01:39:52 PM PST 24 |
| Finished | Jan 07 01:40:22 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-1c1a45c7-66a9-49e7-9b90-9bbd8e852654 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3776238559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3776238559 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.2011522392 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 3098433288 ps |
| CPU time | 9.02 seconds |
| Started | Jan 07 01:39:28 PM PST 24 |
| Finished | Jan 07 01:39:44 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-32bf5d9d-a791-4ac2-8a10-b59405a581ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2011522392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2011522392 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.2022787986 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 14523146079 ps |
| CPU time | 45.73 seconds |
| Started | Jan 07 01:39:48 PM PST 24 |
| Finished | Jan 07 01:40:53 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-a11b16a0-c08c-43d5-822c-9a0e349ec026 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022787986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2022787986 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3523244001 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 23207602744 ps |
| CPU time | 162.7 seconds |
| Started | Jan 07 01:39:34 PM PST 24 |
| Finished | Jan 07 01:42:27 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-75b10421-838f-4933-a8f8-fba1d9643cac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3523244001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3523244001 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1404333437 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 110348608 ps |
| CPU time | 6.37 seconds |
| Started | Jan 07 01:39:45 PM PST 24 |
| Finished | Jan 07 01:40:09 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-3cba220f-52a0-4fb6-af46-a611fc6f17db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404333437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1404333437 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.2003895440 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 697195516 ps |
| CPU time | 7.64 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:39:53 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-387a4d55-47c5-4dbe-8ede-7ce320c7fbe3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2003895440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2003895440 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.329852929 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 80986986 ps |
| CPU time | 1.63 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:39:57 PM PST 24 |
| Peak memory | 201520 kb |
| Host | smart-5c43fcb5-a9d6-488b-b695-bd8b27b4259d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=329852929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.329852929 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.298833216 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 8302872232 ps |
| CPU time | 7.38 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-01895f69-de6b-4553-b26e-e5a8d0af0143 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=298833216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.298833216 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1742147995 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 1016262985 ps |
| CPU time | 7.13 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:39:55 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-2a639963-da73-4d9a-9062-93e5dcab53d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1742147995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1742147995 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3090772738 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 16556201 ps |
| CPU time | 1.09 seconds |
| Started | Jan 07 01:40:03 PM PST 24 |
| Finished | Jan 07 01:40:33 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-6ff2666a-ebae-4252-9a85-3799344ba1fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090772738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3090772738 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.686935210 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1484633195 ps |
| CPU time | 21.81 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:40:39 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-586d871f-c9a8-4be6-9bea-8cbb296ee631 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=686935210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.686935210 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.144335046 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4845265982 ps |
| CPU time | 55.96 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:40:50 PM PST 24 |
| Peak memory | 201528 kb |
| Host | smart-085ce26d-1a46-4ce7-9e5e-5529a9e0dc0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=144335046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.144335046 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.339426579 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2080809646 ps |
| CPU time | 223.2 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:44:00 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-df9b15a0-c69b-4346-89d0-3243f9f28418 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=339426579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand _reset.339426579 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3604037251 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 867682013 ps |
| CPU time | 78.73 seconds |
| Started | Jan 07 01:40:01 PM PST 24 |
| Finished | Jan 07 01:41:48 PM PST 24 |
| Peak memory | 204136 kb |
| Host | smart-a88f1aff-1e13-464c-99cc-657fc3dadd8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3604037251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.3604037251 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2740920163 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 66008894 ps |
| CPU time | 9.94 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:09 PM PST 24 |
| Peak memory | 200716 kb |
| Host | smart-c36840fc-9bba-4595-91ed-4665339a88d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2740920163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2740920163 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2292141818 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 52744142 ps |
| CPU time | 3.47 seconds |
| Started | Jan 07 01:40:25 PM PST 24 |
| Finished | Jan 07 01:40:52 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-411ef6db-099c-4aff-bb7f-9b6f529eea8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2292141818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2292141818 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.173346527 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 39210059 ps |
| CPU time | 4.4 seconds |
| Started | Jan 07 01:40:10 PM PST 24 |
| Finished | Jan 07 01:40:43 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-53c88cae-6cf8-41c5-a51b-903a615db82c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=173346527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.173346527 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.2986393421 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 79071981 ps |
| CPU time | 4.47 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:40:26 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-492b8ece-fa15-495a-a215-6beaa9f8bd4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2986393421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2986393421 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.830514176 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2561645202 ps |
| CPU time | 12.56 seconds |
| Started | Jan 07 01:39:51 PM PST 24 |
| Finished | Jan 07 01:40:26 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-1359d08c-6926-4a2a-8599-b672c0f71cd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=830514176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.830514176 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1042748148 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 60655773735 ps |
| CPU time | 124.64 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:42:20 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-97b5598b-2221-4b54-948d-f67e9e76acf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1042748148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1042748148 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1970489739 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 53368447 ps |
| CPU time | 3.74 seconds |
| Started | Jan 07 01:39:55 PM PST 24 |
| Finished | Jan 07 01:40:24 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-86b6e736-bfd1-4c15-8240-aca424b1a789 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970489739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1970489739 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.2974172507 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 398362736 ps |
| CPU time | 4.35 seconds |
| Started | Jan 07 01:40:20 PM PST 24 |
| Finished | Jan 07 01:40:49 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-d3efa5fd-f651-4830-a069-91e892c530ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2974172507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2974172507 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.3342260715 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 89313274 ps |
| CPU time | 1.23 seconds |
| Started | Jan 07 01:39:46 PM PST 24 |
| Finished | Jan 07 01:40:05 PM PST 24 |
| Peak memory | 201380 kb |
| Host | smart-6271b068-74a7-4997-979c-5c827ae2c6ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3342260715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3342260715 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2214574359 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2185492940 ps |
| CPU time | 8.6 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:40:30 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-9d3eed58-95b6-48ee-b331-b9194d8490bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214574359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2214574359 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3549800000 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 719145383 ps |
| CPU time | 4.9 seconds |
| Started | Jan 07 01:40:17 PM PST 24 |
| Finished | Jan 07 01:40:48 PM PST 24 |
| Peak memory | 201328 kb |
| Host | smart-8578eaac-9609-40b7-82a3-659965bdd4dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3549800000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3549800000 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2767927795 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 9680585 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 01:39:39 PM PST 24 |
| Finished | Jan 07 01:39:56 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-ba11c796-ebde-4c40-9c58-f6a992712b9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767927795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2767927795 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.2216190454 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 5288629137 ps |
| CPU time | 69.23 seconds |
| Started | Jan 07 01:40:17 PM PST 24 |
| Finished | Jan 07 01:41:52 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-beaa7d80-0db2-47fa-afba-201215c25cea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2216190454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2216190454 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3967050717 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 6168111674 ps |
| CPU time | 100.59 seconds |
| Started | Jan 07 01:40:20 PM PST 24 |
| Finished | Jan 07 01:42:25 PM PST 24 |
| Peak memory | 203508 kb |
| Host | smart-cc9c7877-a8a9-4057-81b5-5096a2f175e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3967050717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3967050717 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.4248165289 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 504820152 ps |
| CPU time | 47.59 seconds |
| Started | Jan 07 01:40:03 PM PST 24 |
| Finished | Jan 07 01:41:19 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-28a85a9d-712f-49f1-98f9-179cf4e1c3a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4248165289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.4248165289 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.541432765 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2415175891 ps |
| CPU time | 124.65 seconds |
| Started | Jan 07 01:39:45 PM PST 24 |
| Finished | Jan 07 01:42:07 PM PST 24 |
| Peak memory | 206744 kb |
| Host | smart-9a9e6007-86b5-4e19-a214-a2417f48f700 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=541432765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_res et_error.541432765 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2573031051 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 49530990 ps |
| CPU time | 3.65 seconds |
| Started | Jan 07 01:40:16 PM PST 24 |
| Finished | Jan 07 01:40:46 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-fb72195d-3b03-4bfe-9f99-d6a024b46c6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2573031051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2573031051 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3501705703 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1443246178 ps |
| CPU time | 18.77 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:40:44 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-5dadf514-9773-427f-afaa-4e3eb8f7e190 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3501705703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3501705703 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.4197072541 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 264041696697 ps |
| CPU time | 221.55 seconds |
| Started | Jan 07 01:39:52 PM PST 24 |
| Finished | Jan 07 01:43:56 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-4e1d4b59-f2a2-4827-bfa5-6a4255431c15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4197072541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.4197072541 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2860715855 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 191143142 ps |
| CPU time | 3.59 seconds |
| Started | Jan 07 01:39:57 PM PST 24 |
| Finished | Jan 07 01:40:27 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-46be32be-f675-4553-844a-36a52a19c193 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2860715855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2860715855 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.4078131940 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 91436502 ps |
| CPU time | 8.22 seconds |
| Started | Jan 07 01:39:28 PM PST 24 |
| Finished | Jan 07 01:39:43 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-2c88cc03-e7f5-43a5-816f-952c78cd3cf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4078131940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.4078131940 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.3893754917 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 3243153049 ps |
| CPU time | 9.98 seconds |
| Started | Jan 07 01:40:29 PM PST 24 |
| Finished | Jan 07 01:41:04 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-425cf1e4-13e9-4202-ba93-3fa43e3b98ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3893754917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3893754917 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.2622555314 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 194582016323 ps |
| CPU time | 130.3 seconds |
| Started | Jan 07 01:39:48 PM PST 24 |
| Finished | Jan 07 01:42:18 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-c7a50d2d-5221-4067-a815-438f0fa04515 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622555314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2622555314 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3440380504 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 47246193016 ps |
| CPU time | 114.16 seconds |
| Started | Jan 07 01:40:00 PM PST 24 |
| Finished | Jan 07 01:42:22 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-c79c4528-d815-4eee-9cb1-9cd614976a44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3440380504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3440380504 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.2615531643 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 18507401 ps |
| CPU time | 1.89 seconds |
| Started | Jan 07 01:39:51 PM PST 24 |
| Finished | Jan 07 01:40:15 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-78ee877f-6c03-4379-9aa9-094f8a010f9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615531643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2615531643 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.387047741 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 895890488 ps |
| CPU time | 3.21 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:39:56 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-c69cdaa7-d757-472a-aaaf-8573d7929bf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=387047741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.387047741 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.59399543 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 8358202 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 01:40:26 PM PST 24 |
| Finished | Jan 07 01:40:50 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-5f1e8437-0146-4cda-b9f4-edf412420151 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=59399543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.59399543 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2246925043 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1869200437 ps |
| CPU time | 7.37 seconds |
| Started | Jan 07 01:40:22 PM PST 24 |
| Finished | Jan 07 01:40:54 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-e4dd66bd-661d-42ea-8070-ed4e74badd30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246925043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2246925043 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3790134649 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1057089287 ps |
| CPU time | 7.48 seconds |
| Started | Jan 07 01:40:28 PM PST 24 |
| Finished | Jan 07 01:40:57 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-56a570fa-c9e9-49f6-88b1-2f41b65e2e7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3790134649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3790134649 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1951882368 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 23737833 ps |
| CPU time | 1.03 seconds |
| Started | Jan 07 01:40:19 PM PST 24 |
| Finished | Jan 07 01:40:46 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-3351a024-397d-4d3b-9b4d-21cd56023dda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951882368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1951882368 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.2324555196 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2330700140 ps |
| CPU time | 37.72 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:40:24 PM PST 24 |
| Peak memory | 202592 kb |
| Host | smart-10ec7e1e-1f61-42fe-9229-56850f2d9ecc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2324555196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2324555196 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.303346541 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 635905848 ps |
| CPU time | 22.09 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:40:11 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-344f350e-c906-47de-9e0e-66349cfe3e40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=303346541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.303346541 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.755422506 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 454419846 ps |
| CPU time | 70.65 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:40:53 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-be42a352-b72c-4225-9550-368951b8e19a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=755422506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand _reset.755422506 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1528425940 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 440061423 ps |
| CPU time | 54.32 seconds |
| Started | Jan 07 01:39:47 PM PST 24 |
| Finished | Jan 07 01:41:00 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-5f53140f-5a5c-45c8-b1d6-30b7dce1d714 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1528425940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.1528425940 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.3740180647 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 732538696 ps |
| CPU time | 11.58 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:39:49 PM PST 24 |
| Peak memory | 201304 kb |
| Host | smart-827bc771-6f3d-4ed0-ba06-c988682aa0dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3740180647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3740180647 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2369305814 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1385559076 ps |
| CPU time | 7.76 seconds |
| Started | Jan 07 01:39:34 PM PST 24 |
| Finished | Jan 07 01:39:52 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-b74f55b4-6e3a-46c5-a2cf-313ca54fcf26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2369305814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2369305814 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.4252443733 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 19015079567 ps |
| CPU time | 149.45 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:42:33 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-c61478d3-ecee-49aa-b144-c447b8876210 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4252443733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.4252443733 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.4000096457 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 47293870 ps |
| CPU time | 1.24 seconds |
| Started | Jan 07 01:39:59 PM PST 24 |
| Finished | Jan 07 01:40:29 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-883f3489-ddcd-43d7-a8ac-41d9aecbdfd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4000096457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.4000096457 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.3683035247 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 44758224 ps |
| CPU time | 4.01 seconds |
| Started | Jan 07 01:39:47 PM PST 24 |
| Finished | Jan 07 01:40:09 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-5b3c9d59-8dba-49ff-9fbd-0a96713a9f35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3683035247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3683035247 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.1695115654 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 889047599 ps |
| CPU time | 14.64 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:40:05 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-001fa74a-1392-44c4-b40b-953636bd8940 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1695115654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1695115654 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.3836736929 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 40085503559 ps |
| CPU time | 160.04 seconds |
| Started | Jan 07 01:39:49 PM PST 24 |
| Finished | Jan 07 01:42:49 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-84131cf9-b449-4b48-ac80-5c4d36b3022b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836736929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3836736929 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.1529721130 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 78709556479 ps |
| CPU time | 77.73 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:41:44 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-c2db6040-d9e3-40bc-b9c8-44d972dc4715 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1529721130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1529721130 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1771056383 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 20377128 ps |
| CPU time | 2.6 seconds |
| Started | Jan 07 01:39:51 PM PST 24 |
| Finished | Jan 07 01:40:17 PM PST 24 |
| Peak memory | 201308 kb |
| Host | smart-59417962-1add-4e43-b1a5-981836668c9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771056383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1771056383 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.890434413 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1282309299 ps |
| CPU time | 9.38 seconds |
| Started | Jan 07 01:39:55 PM PST 24 |
| Finished | Jan 07 01:40:29 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-f74bef3f-5705-441f-a408-db4966c6acb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=890434413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.890434413 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.3031148176 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 73970461 ps |
| CPU time | 1.78 seconds |
| Started | Jan 07 01:39:31 PM PST 24 |
| Finished | Jan 07 01:39:39 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-95b990c1-5f64-4c42-890c-589de948d380 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3031148176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3031148176 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3804717843 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 5526565493 ps |
| CPU time | 12.72 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:40:35 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-5ba662f0-a8f3-4581-9a18-5ca6e45315ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804717843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3804717843 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2513237513 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1050380599 ps |
| CPU time | 4.99 seconds |
| Started | Jan 07 01:40:01 PM PST 24 |
| Finished | Jan 07 01:40:34 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-ab8bd98c-73cd-4997-a0d5-88ad4497ecfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2513237513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2513237513 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.684847280 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 23100796 ps |
| CPU time | 1.29 seconds |
| Started | Jan 07 01:39:43 PM PST 24 |
| Finished | Jan 07 01:40:00 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-6211524f-6d5f-43f9-93e1-d93c6252b65c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684847280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.684847280 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.2105737002 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 5581259989 ps |
| CPU time | 74.46 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:41:08 PM PST 24 |
| Peak memory | 204612 kb |
| Host | smart-5369ceed-43a2-4989-9d13-e3b72c5225b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2105737002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2105737002 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.561157518 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 21251047946 ps |
| CPU time | 75.41 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:41:04 PM PST 24 |
| Peak memory | 202652 kb |
| Host | smart-8dc38181-4174-470d-83cb-7b491d1682f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=561157518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.561157518 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2903868855 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2123093366 ps |
| CPU time | 73.49 seconds |
| Started | Jan 07 01:39:53 PM PST 24 |
| Finished | Jan 07 01:41:30 PM PST 24 |
| Peak memory | 205424 kb |
| Host | smart-25d37220-f1dc-4c2a-9c44-972313f0c1f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2903868855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.2903868855 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3850408344 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 10253585034 ps |
| CPU time | 94.53 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:41:45 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-297529ac-df40-4afc-b070-37d80f80c6a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3850408344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3850408344 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3906887737 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 49802939 ps |
| CPU time | 4.52 seconds |
| Started | Jan 07 01:39:50 PM PST 24 |
| Finished | Jan 07 01:40:17 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-5f967611-f6ad-49f8-8e70-4d01b0ce4d60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3906887737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3906887737 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1797766268 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 52256445 ps |
| CPU time | 11.75 seconds |
| Started | Jan 07 01:39:35 PM PST 24 |
| Finished | Jan 07 01:39:59 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-51dfddad-566a-403c-8e02-3625ab349aa6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1797766268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1797766268 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3858869945 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 18140750317 ps |
| CPU time | 37.35 seconds |
| Started | Jan 07 01:39:57 PM PST 24 |
| Finished | Jan 07 01:41:01 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-e3092553-6d89-4f1b-99f2-f7c56615b7cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3858869945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.3858869945 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2662425687 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1072036894 ps |
| CPU time | 10.25 seconds |
| Started | Jan 07 01:40:03 PM PST 24 |
| Finished | Jan 07 01:40:42 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-1799c1e2-2c6a-40e0-af1b-04f051a5bb13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2662425687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2662425687 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.2855913636 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 706400791 ps |
| CPU time | 7.41 seconds |
| Started | Jan 07 01:40:03 PM PST 24 |
| Finished | Jan 07 01:40:39 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-ef1246db-0d75-4652-ac27-07c2ef0b4aaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2855913636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2855913636 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.1648546933 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 171254526 ps |
| CPU time | 5.67 seconds |
| Started | Jan 07 01:39:30 PM PST 24 |
| Finished | Jan 07 01:39:43 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-58a15b3b-7819-4b6e-a8f0-2f4218f3861f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1648546933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1648546933 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2145073893 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5734790171 ps |
| CPU time | 27.71 seconds |
| Started | Jan 07 01:40:06 PM PST 24 |
| Finished | Jan 07 01:41:02 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-a094f226-05de-4e10-ad7a-7df23a648c44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145073893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2145073893 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1519430253 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 5820929796 ps |
| CPU time | 27.08 seconds |
| Started | Jan 07 01:39:40 PM PST 24 |
| Finished | Jan 07 01:40:23 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-e1637bd0-0bb4-411d-8035-b4c0d928ef6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1519430253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1519430253 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1733361496 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 78652498 ps |
| CPU time | 6.18 seconds |
| Started | Jan 07 01:40:00 PM PST 24 |
| Finished | Jan 07 01:40:34 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-40846401-669d-4fe7-b807-5578794bbfe3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733361496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1733361496 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.931879751 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 287795102 ps |
| CPU time | 3.51 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:40:25 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-b9e4189c-b057-48a2-b84e-ae52748cc5a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=931879751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.931879751 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.2829930217 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 41832789 ps |
| CPU time | 1.4 seconds |
| Started | Jan 07 01:40:05 PM PST 24 |
| Finished | Jan 07 01:40:34 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-4bf99743-ff9f-4a26-82c6-75038f68931c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2829930217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2829930217 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.548490177 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 17533095031 ps |
| CPU time | 11.96 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:40:38 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-6f2f1def-e62d-44a3-9506-2b00d3a8b222 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=548490177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.548490177 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1635923182 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2342232987 ps |
| CPU time | 8.1 seconds |
| Started | Jan 07 01:39:43 PM PST 24 |
| Finished | Jan 07 01:40:07 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-496f7d19-d571-42e9-8156-26e51572d261 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1635923182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1635923182 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2152660326 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 9734063 ps |
| CPU time | 1.23 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:39:54 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-b2393314-4476-4764-b2bb-38ffa64c102f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152660326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2152660326 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.3729621376 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 394004838 ps |
| CPU time | 21.58 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:40:12 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-e22d76fe-319d-4603-8dd1-98de729e0cf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3729621376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3729621376 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.58313115 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 14352032621 ps |
| CPU time | 123.87 seconds |
| Started | Jan 07 01:39:54 PM PST 24 |
| Finished | Jan 07 01:42:22 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-90269e6a-868c-4cb5-b379-cf309706f98b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=58313115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.58313115 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1041844953 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1202479523 ps |
| CPU time | 90.1 seconds |
| Started | Jan 07 01:39:43 PM PST 24 |
| Finished | Jan 07 01:41:29 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-44e2fe0d-73e0-4a19-bf35-de21840812a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1041844953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.1041844953 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.786365627 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1635534235 ps |
| CPU time | 4.18 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:40:29 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-0f6f0132-a335-4bb7-bed6-323401e3088c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=786365627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.786365627 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.1087211886 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 58741745 ps |
| CPU time | 2.08 seconds |
| Started | Jan 07 01:40:16 PM PST 24 |
| Finished | Jan 07 01:40:47 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-bf74198c-a844-491f-8038-8b98e296043d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1087211886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1087211886 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2056148026 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 43295882256 ps |
| CPU time | 215.16 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:44:01 PM PST 24 |
| Peak memory | 203552 kb |
| Host | smart-cec471a4-ce1e-4c32-9348-cf63f8c0e6da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2056148026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.2056148026 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3673673023 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 227063775 ps |
| CPU time | 2.9 seconds |
| Started | Jan 07 01:40:27 PM PST 24 |
| Finished | Jan 07 01:40:53 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-6842a4ae-6c28-446a-ae50-c947dd565fbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3673673023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3673673023 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.1233383418 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 380364908 ps |
| CPU time | 5.17 seconds |
| Started | Jan 07 01:39:59 PM PST 24 |
| Finished | Jan 07 01:40:32 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-af6a2f30-c60d-43c6-983b-07ac204893fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1233383418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1233383418 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.3379401650 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 3543664154 ps |
| CPU time | 13.37 seconds |
| Started | Jan 07 01:40:17 PM PST 24 |
| Finished | Jan 07 01:40:56 PM PST 24 |
| Peak memory | 201620 kb |
| Host | smart-fdaf65c3-6595-4126-a436-5cddd547a647 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3379401650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3379401650 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3874880295 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1470008058 ps |
| CPU time | 9.1 seconds |
| Started | Jan 07 01:40:20 PM PST 24 |
| Finished | Jan 07 01:40:54 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-08403c0a-b736-4fcd-b775-956ef3b81aea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3874880295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3874880295 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3544276295 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 30396472 ps |
| CPU time | 3.36 seconds |
| Started | Jan 07 01:40:15 PM PST 24 |
| Finished | Jan 07 01:40:45 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-cef4e5aa-1a10-4487-bbec-0596d5d933b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544276295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3544276295 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.2863355435 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 2267133749 ps |
| CPU time | 10.24 seconds |
| Started | Jan 07 01:40:09 PM PST 24 |
| Finished | Jan 07 01:40:48 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-8b95b32f-fdbd-4343-90bf-78f1c54e4a81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2863355435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2863355435 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.4169913991 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 11827430 ps |
| CPU time | 1.06 seconds |
| Started | Jan 07 01:40:20 PM PST 24 |
| Finished | Jan 07 01:40:46 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-746b91d9-e13e-4feb-89fd-51cbf038c839 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4169913991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4169913991 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2450370082 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3893048306 ps |
| CPU time | 8.96 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:40:31 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-5e0e17cc-2c06-4183-b7de-c920d2469201 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450370082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2450370082 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.686588454 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1545501813 ps |
| CPU time | 9.41 seconds |
| Started | Jan 07 01:40:01 PM PST 24 |
| Finished | Jan 07 01:40:39 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-0d4dfe78-5a42-48d3-8cb4-c63528be536b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=686588454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.686588454 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1688281093 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 12499322 ps |
| CPU time | 1.04 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:39:49 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-ffe63154-bfc8-4c21-8c02-c7aac477a562 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688281093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1688281093 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2320438555 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 30692162550 ps |
| CPU time | 66.42 seconds |
| Started | Jan 07 01:40:22 PM PST 24 |
| Finished | Jan 07 01:41:53 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-bf3a641c-2f25-4b0f-bb5e-62a6f134f0b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2320438555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2320438555 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1244177576 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 370693000 ps |
| CPU time | 34.85 seconds |
| Started | Jan 07 01:40:35 PM PST 24 |
| Finished | Jan 07 01:41:36 PM PST 24 |
| Peak memory | 203536 kb |
| Host | smart-baf67ae5-085e-4fc7-bf44-cef4c64e2a19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1244177576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.1244177576 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.381050748 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 233061093 ps |
| CPU time | 30.46 seconds |
| Started | Jan 07 01:39:42 PM PST 24 |
| Finished | Jan 07 01:40:33 PM PST 24 |
| Peak memory | 202880 kb |
| Host | smart-037aa1a1-c2dd-4bad-823d-92a471358bd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=381050748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_res et_error.381050748 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.858595137 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 653669552 ps |
| CPU time | 9.93 seconds |
| Started | Jan 07 01:40:09 PM PST 24 |
| Finished | Jan 07 01:40:47 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-bf1ba6b3-81ef-4554-8187-262198637388 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=858595137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.858595137 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.133019407 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 46890673 ps |
| CPU time | 5.14 seconds |
| Started | Jan 07 01:40:20 PM PST 24 |
| Finished | Jan 07 01:40:50 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-9b944853-4005-4456-914f-5b6d387a0394 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=133019407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.133019407 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3533848268 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 7840365781 ps |
| CPU time | 41.62 seconds |
| Started | Jan 07 01:39:46 PM PST 24 |
| Finished | Jan 07 01:40:46 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-665c6333-ec00-4419-849b-b8ca9caa619b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3533848268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.3533848268 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2385989699 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 54819973 ps |
| CPU time | 4.49 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:40:26 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-791b05a8-329e-46ce-98a2-373e2d567cda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2385989699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2385989699 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.2567594544 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1374578166 ps |
| CPU time | 15.12 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:15 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-accd9d2b-6d38-4592-9846-0fe32a5378b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2567594544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2567594544 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.2430383644 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 52737962 ps |
| CPU time | 3.62 seconds |
| Started | Jan 07 01:40:12 PM PST 24 |
| Finished | Jan 07 01:40:43 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-a1f69968-f7ee-42c0-ab83-88b6c4c68ff1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2430383644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2430383644 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1146046834 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 77654645281 ps |
| CPU time | 115.77 seconds |
| Started | Jan 07 01:40:22 PM PST 24 |
| Finished | Jan 07 01:42:42 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-582f9030-1add-44f1-9fc2-a147ffca946f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146046834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1146046834 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3850669310 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 24511214058 ps |
| CPU time | 162.9 seconds |
| Started | Jan 07 01:39:59 PM PST 24 |
| Finished | Jan 07 01:43:11 PM PST 24 |
| Peak memory | 201556 kb |
| Host | smart-e917451e-bd40-4e46-b1e1-ba91af2ab236 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3850669310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3850669310 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1816402355 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 58298361 ps |
| CPU time | 3.68 seconds |
| Started | Jan 07 01:40:18 PM PST 24 |
| Finished | Jan 07 01:40:47 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-8b500c9a-dcb6-4a74-9fc0-2a27ac119e22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816402355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1816402355 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.1226750403 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 65908428 ps |
| CPU time | 2.42 seconds |
| Started | Jan 07 01:40:11 PM PST 24 |
| Finished | Jan 07 01:40:41 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-db4c94a9-a83f-4b7c-8355-9abfe7fbf347 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1226750403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1226750403 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.1292904507 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 14952331 ps |
| CPU time | 1.13 seconds |
| Started | Jan 07 01:40:16 PM PST 24 |
| Finished | Jan 07 01:40:44 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-c66dd537-ceb1-46a7-a123-1aa49a7735a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1292904507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1292904507 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2698248383 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1741907459 ps |
| CPU time | 7.64 seconds |
| Started | Jan 07 01:40:13 PM PST 24 |
| Finished | Jan 07 01:40:47 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-8c2cc70b-92d0-488b-a797-06188063f09f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698248383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2698248383 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1592843056 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1611228774 ps |
| CPU time | 11.96 seconds |
| Started | Jan 07 01:40:17 PM PST 24 |
| Finished | Jan 07 01:40:55 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-b2d32e09-1f94-432f-b416-a62860396cdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1592843056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1592843056 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2953524324 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 20189798 ps |
| CPU time | 1.05 seconds |
| Started | Jan 07 01:40:04 PM PST 24 |
| Finished | Jan 07 01:40:34 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-46afdb68-cc72-4c78-824f-ab3619cf0d00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953524324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2953524324 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2482168570 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 10450369162 ps |
| CPU time | 77.52 seconds |
| Started | Jan 07 01:40:10 PM PST 24 |
| Finished | Jan 07 01:41:56 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-f357166d-0c3a-40fb-88d9-65e34d152878 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2482168570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2482168570 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.297627913 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 37870360438 ps |
| CPU time | 73.52 seconds |
| Started | Jan 07 01:40:06 PM PST 24 |
| Finished | Jan 07 01:41:48 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-ceb78bda-08f9-4cb6-8367-81bf1076a313 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=297627913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.297627913 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3639273606 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 87445961 ps |
| CPU time | 9.37 seconds |
| Started | Jan 07 01:39:41 PM PST 24 |
| Finished | Jan 07 01:40:05 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-2d40a527-5983-44a4-a81a-c9de8e8d8dd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3639273606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.3639273606 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.3206905842 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 922585829 ps |
| CPU time | 9.56 seconds |
| Started | Jan 07 01:40:07 PM PST 24 |
| Finished | Jan 07 01:40:46 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-88222acc-41c6-4fe2-9701-3994b18d5fb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3206905842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3206905842 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3507782346 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 3124651195 ps |
| CPU time | 13.11 seconds |
| Started | Jan 07 01:39:57 PM PST 24 |
| Finished | Jan 07 01:40:36 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-ef8b9e06-9680-4aea-9d43-9494d85dae11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3507782346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3507782346 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.825426104 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 56144292533 ps |
| CPU time | 81.03 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:41:42 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-89ce7096-61e1-4793-ae64-26a867a50c18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=825426104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slo w_rsp.825426104 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1676668214 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 283667645 ps |
| CPU time | 6.02 seconds |
| Started | Jan 07 01:39:51 PM PST 24 |
| Finished | Jan 07 01:40:19 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-358815df-934c-4ffd-ae60-46d0c7dffb60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1676668214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.1676668214 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.827923092 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 61523665 ps |
| CPU time | 5.05 seconds |
| Started | Jan 07 01:39:56 PM PST 24 |
| Finished | Jan 07 01:40:26 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-4268a5ac-25e8-4252-8a38-e75f59ceb72b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=827923092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.827923092 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.3951578421 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 6098235680 ps |
| CPU time | 13.75 seconds |
| Started | Jan 07 01:40:35 PM PST 24 |
| Finished | Jan 07 01:41:15 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-2f7c16e0-bed3-4ec1-a24a-932f9a946db0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3951578421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3951578421 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1740744617 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 14861378840 ps |
| CPU time | 35.11 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:41:05 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-7c0f120f-2854-429f-a617-05e1f0e08c07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740744617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1740744617 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.703490196 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 16166843176 ps |
| CPU time | 51.13 seconds |
| Started | Jan 07 01:40:04 PM PST 24 |
| Finished | Jan 07 01:41:23 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-ce8fe5cf-dc6f-44df-b387-64aa23992de0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=703490196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.703490196 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2775721727 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 9154243 ps |
| CPU time | 1.31 seconds |
| Started | Jan 07 01:40:16 PM PST 24 |
| Finished | Jan 07 01:40:43 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-430d56c3-74e6-4044-a664-8090e1eea6e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775721727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2775721727 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.1607628366 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 22888567 ps |
| CPU time | 2.08 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:40:27 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-8072cad3-2c0d-493e-b352-8c7d9a5a0992 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1607628366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1607628366 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.1209262725 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 124141713 ps |
| CPU time | 1.5 seconds |
| Started | Jan 07 01:39:54 PM PST 24 |
| Finished | Jan 07 01:40:20 PM PST 24 |
| Peak memory | 201388 kb |
| Host | smart-4ff8c162-c92c-4e13-ad55-96f4b2b8d4d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1209262725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1209262725 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1752684667 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 14120454641 ps |
| CPU time | 11.78 seconds |
| Started | Jan 07 01:39:58 PM PST 24 |
| Finished | Jan 07 01:40:36 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-f01c1ec0-b6a5-407a-accd-8628666c5dac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752684667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1752684667 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1951498204 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 798657926 ps |
| CPU time | 6.38 seconds |
| Started | Jan 07 01:40:11 PM PST 24 |
| Finished | Jan 07 01:40:46 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-0258ff9f-6850-4f7a-97bc-3debde557a00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1951498204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1951498204 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2522194546 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 9641756 ps |
| CPU time | 1.05 seconds |
| Started | Jan 07 01:40:16 PM PST 24 |
| Finished | Jan 07 01:40:43 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-77168a6c-8218-4580-bea5-79a439d60e87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522194546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2522194546 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1850812824 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 5007662845 ps |
| CPU time | 42.18 seconds |
| Started | Jan 07 01:40:00 PM PST 24 |
| Finished | Jan 07 01:41:10 PM PST 24 |
| Peak memory | 201584 kb |
| Host | smart-9adf5b3a-ee43-4c81-95d9-af083d9969cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1850812824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1850812824 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2476323243 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 8801160302 ps |
| CPU time | 108.39 seconds |
| Started | Jan 07 01:40:21 PM PST 24 |
| Finished | Jan 07 01:42:34 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-1f8b46fb-0a6c-4310-984d-a3d0630c2333 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2476323243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2476323243 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3771119434 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 3702182256 ps |
| CPU time | 63.6 seconds |
| Started | Jan 07 01:40:08 PM PST 24 |
| Finished | Jan 07 01:41:40 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-668272d4-7d1a-4469-9feb-dde6167aa588 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3771119434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.3771119434 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3381296078 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 4850012847 ps |
| CPU time | 227.6 seconds |
| Started | Jan 07 01:40:18 PM PST 24 |
| Finished | Jan 07 01:44:31 PM PST 24 |
| Peak memory | 206464 kb |
| Host | smart-1f8bb387-ed37-4f2f-8d66-273b500326df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3381296078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.3381296078 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2973490789 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 312694524 ps |
| CPU time | 4.25 seconds |
| Started | Jan 07 01:39:57 PM PST 24 |
| Finished | Jan 07 01:40:27 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-98d867c5-2958-4013-9efc-6cd72264d058 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2973490789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2973490789 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3557861383 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1358781573 ps |
| CPU time | 25.35 seconds |
| Started | Jan 07 01:40:38 PM PST 24 |
| Finished | Jan 07 01:41:31 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-703e5dbc-0850-408d-9d8b-409dc7fd0a39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3557861383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3557861383 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1489474342 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 48907152899 ps |
| CPU time | 345.85 seconds |
| Started | Jan 07 01:40:28 PM PST 24 |
| Finished | Jan 07 01:46:36 PM PST 24 |
| Peak memory | 203584 kb |
| Host | smart-21e70e90-a98f-4888-b3e8-c812add8bf62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1489474342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.1489474342 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3117714258 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1979852690 ps |
| CPU time | 4.39 seconds |
| Started | Jan 07 01:40:22 PM PST 24 |
| Finished | Jan 07 01:40:51 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-ccfccbf6-a825-42d8-99f3-eeae691cc4d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3117714258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3117714258 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.1550951568 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 193500225 ps |
| CPU time | 6.41 seconds |
| Started | Jan 07 01:40:40 PM PST 24 |
| Finished | Jan 07 01:41:13 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-a1992605-89fe-4100-bcd3-570c2688ca82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1550951568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1550951568 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.1310680617 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1099298888 ps |
| CPU time | 12.66 seconds |
| Started | Jan 07 01:40:20 PM PST 24 |
| Finished | Jan 07 01:40:58 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-6439d014-01fa-4a01-8b4c-eb5332caec5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1310680617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1310680617 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.1292515835 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 28824756862 ps |
| CPU time | 23.7 seconds |
| Started | Jan 07 01:40:32 PM PST 24 |
| Finished | Jan 07 01:41:22 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-986fa106-a098-4b1a-9eed-df5dccea1322 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292515835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1292515835 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3104604046 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 67268460491 ps |
| CPU time | 103.79 seconds |
| Started | Jan 07 01:40:15 PM PST 24 |
| Finished | Jan 07 01:42:26 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-37f1e24f-5572-4fab-954c-d131f6982f0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3104604046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3104604046 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.4110723120 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 72736646 ps |
| CPU time | 7.85 seconds |
| Started | Jan 07 01:40:32 PM PST 24 |
| Finished | Jan 07 01:41:06 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-f5120c63-cc22-4413-8bc0-5b3734d9b043 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110723120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.4110723120 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.3663275930 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 681144955 ps |
| CPU time | 5.53 seconds |
| Started | Jan 07 01:40:25 PM PST 24 |
| Finished | Jan 07 01:40:54 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-59940d57-00a6-48dd-8449-1cb1149a1326 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3663275930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3663275930 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.3830941433 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 17201582 ps |
| CPU time | 1.38 seconds |
| Started | Jan 07 01:40:37 PM PST 24 |
| Finished | Jan 07 01:41:05 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-e63e4f09-9fd8-4fed-a434-f3b5f0c0a774 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3830941433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3830941433 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1538815905 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3658820941 ps |
| CPU time | 9.26 seconds |
| Started | Jan 07 01:40:21 PM PST 24 |
| Finished | Jan 07 01:40:55 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-7f0235b5-fa08-4a26-80d9-886ce6afcd3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538815905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1538815905 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.42051853 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1673082068 ps |
| CPU time | 9.56 seconds |
| Started | Jan 07 01:40:27 PM PST 24 |
| Finished | Jan 07 01:40:59 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-d139f220-95c5-462d-8ee6-f79ee2ca0ddf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=42051853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.42051853 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.555226749 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 12289749 ps |
| CPU time | 0.97 seconds |
| Started | Jan 07 01:40:31 PM PST 24 |
| Finished | Jan 07 01:40:58 PM PST 24 |
| Peak memory | 201524 kb |
| Host | smart-005fb5a2-922b-4a34-837c-e99ded373cc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555226749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.555226749 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.3640691008 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3087197497 ps |
| CPU time | 13.46 seconds |
| Started | Jan 07 01:40:23 PM PST 24 |
| Finished | Jan 07 01:41:00 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-a6284cf8-d264-4fdf-812a-88a1d452dad1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3640691008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3640691008 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2426183497 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3595789056 ps |
| CPU time | 28.62 seconds |
| Started | Jan 07 01:40:31 PM PST 24 |
| Finished | Jan 07 01:41:25 PM PST 24 |
| Peak memory | 201580 kb |
| Host | smart-061adca9-daf3-494f-86d7-7f5ea9341dea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2426183497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2426183497 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1123953903 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2439944078 ps |
| CPU time | 120.05 seconds |
| Started | Jan 07 01:40:25 PM PST 24 |
| Finished | Jan 07 01:42:49 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-4485608f-d101-4a0c-a643-b23e580ee485 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1123953903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.1123953903 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2185255868 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 134937851 ps |
| CPU time | 6.88 seconds |
| Started | Jan 07 01:40:39 PM PST 24 |
| Finished | Jan 07 01:41:14 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-1e56658d-0f57-4365-81eb-a159d7d67a72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2185255868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.2185255868 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.1586134975 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 371120619 ps |
| CPU time | 7.57 seconds |
| Started | Jan 07 01:40:34 PM PST 24 |
| Finished | Jan 07 01:41:07 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-b4eff952-e4ce-43e5-b716-e34616f03c1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1586134975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1586134975 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.629510380 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 121844178 ps |
| CPU time | 5.36 seconds |
| Started | Jan 07 01:40:36 PM PST 24 |
| Finished | Jan 07 01:41:08 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-042f18ba-40c3-45b1-934e-25ab87d2dd32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=629510380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.629510380 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1621976223 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 132728951210 ps |
| CPU time | 207.65 seconds |
| Started | Jan 07 01:40:33 PM PST 24 |
| Finished | Jan 07 01:44:27 PM PST 24 |
| Peak memory | 202504 kb |
| Host | smart-10adc636-8193-4ff8-9c7c-c026e2a5a47d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1621976223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.1621976223 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2902176477 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 196268950 ps |
| CPU time | 3.35 seconds |
| Started | Jan 07 01:40:21 PM PST 24 |
| Finished | Jan 07 01:40:49 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-b5694e3c-160d-4cad-84d4-f41d380e45bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2902176477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2902176477 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.2556937059 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 205146401 ps |
| CPU time | 5.18 seconds |
| Started | Jan 07 01:40:21 PM PST 24 |
| Finished | Jan 07 01:40:51 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-9a00d691-12ce-4f2f-9cf3-fad9bbc1b473 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2556937059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2556937059 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.1112903770 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 47916818 ps |
| CPU time | 4.63 seconds |
| Started | Jan 07 01:40:13 PM PST 24 |
| Finished | Jan 07 01:40:45 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-439695c9-9188-48f4-90ab-8db30d4888b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1112903770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1112903770 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3463869584 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 17763942969 ps |
| CPU time | 72.13 seconds |
| Started | Jan 07 01:40:21 PM PST 24 |
| Finished | Jan 07 01:41:59 PM PST 24 |
| Peak memory | 201576 kb |
| Host | smart-e559da49-44a4-462d-948d-166b5aabf9a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463869584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3463869584 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.4239106478 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 20258013469 ps |
| CPU time | 106.94 seconds |
| Started | Jan 07 01:40:45 PM PST 24 |
| Finished | Jan 07 01:42:58 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-bb6d1bb2-1d91-42d8-bf82-f67798c001c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4239106478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4239106478 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1078500234 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 16029120 ps |
| CPU time | 1.21 seconds |
| Started | Jan 07 01:40:25 PM PST 24 |
| Finished | Jan 07 01:40:50 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-6242ceb6-f92f-4e8f-b954-d2c7c268d3c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078500234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1078500234 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.2242504007 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 187935174 ps |
| CPU time | 4.99 seconds |
| Started | Jan 07 01:40:34 PM PST 24 |
| Finished | Jan 07 01:41:05 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-6a84c2a1-85a2-46f0-9853-52a8e1c64779 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2242504007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2242504007 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.3201594146 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 49364420 ps |
| CPU time | 1.37 seconds |
| Started | Jan 07 01:40:20 PM PST 24 |
| Finished | Jan 07 01:40:51 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-9f1e09dd-7833-4552-b323-cb008282cc4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3201594146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3201594146 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3766646452 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2060490456 ps |
| CPU time | 10.26 seconds |
| Started | Jan 07 01:40:21 PM PST 24 |
| Finished | Jan 07 01:40:56 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-60bd1283-14b8-4330-8ca4-1f4c18e45316 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766646452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3766646452 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2814492808 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1244818017 ps |
| CPU time | 8.95 seconds |
| Started | Jan 07 01:40:24 PM PST 24 |
| Finished | Jan 07 01:40:57 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-20c0cf0b-4a10-4593-925e-d28e710a7e55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2814492808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2814492808 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3473247339 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 10073791 ps |
| CPU time | 1.26 seconds |
| Started | Jan 07 01:40:23 PM PST 24 |
| Finished | Jan 07 01:40:48 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-d2a58088-2d4f-4778-a667-b2fa9ff326b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473247339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3473247339 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.4248813415 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1756383930 ps |
| CPU time | 12.22 seconds |
| Started | Jan 07 01:40:38 PM PST 24 |
| Finished | Jan 07 01:41:18 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-7b717361-142c-409a-803b-0e2f5bcf36ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4248813415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.4248813415 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1536901802 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 145085761 ps |
| CPU time | 9.18 seconds |
| Started | Jan 07 01:40:25 PM PST 24 |
| Finished | Jan 07 01:40:58 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-d4c417c6-44cf-4e2a-b7ef-73a5c1ddaad8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1536901802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1536901802 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2736780320 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 586441686 ps |
| CPU time | 67.7 seconds |
| Started | Jan 07 01:40:41 PM PST 24 |
| Finished | Jan 07 01:42:16 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-3658271d-205e-4569-a6ad-cad330076e32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2736780320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.2736780320 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.4129583366 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 97765994 ps |
| CPU time | 2.65 seconds |
| Started | Jan 07 01:40:25 PM PST 24 |
| Finished | Jan 07 01:40:51 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-c6d66b6f-7262-45e7-a944-da2bc76c6b3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4129583366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.4129583366 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1608970805 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 31024224 ps |
| CPU time | 3.95 seconds |
| Started | Jan 07 01:40:25 PM PST 24 |
| Finished | Jan 07 01:40:52 PM PST 24 |
| Peak memory | 201360 kb |
| Host | smart-c1f7692d-887b-473b-96bb-79c0fd586287 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1608970805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1608970805 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3569434023 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 115486342 ps |
| CPU time | 3.85 seconds |
| Started | Jan 07 01:38:48 PM PST 24 |
| Finished | Jan 07 01:38:54 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-b36eea6e-8ddd-483f-b2c2-8972123b9e84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3569434023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3569434023 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2005542306 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 27206608340 ps |
| CPU time | 96 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:41:26 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-dc43e8b8-a1db-4d38-a88d-e59e3e5bf697 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2005542306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.2005542306 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.512646486 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 34974585 ps |
| CPU time | 1.48 seconds |
| Started | Jan 07 01:39:05 PM PST 24 |
| Finished | Jan 07 01:39:09 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-13122593-61fe-4b43-989a-e44ae391c565 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=512646486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.512646486 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.59611923 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 62035948 ps |
| CPU time | 2.53 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:39:39 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-90b2e956-0cc3-4c53-94a2-4b79eccc06c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=59611923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.59611923 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.1781866435 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 557934229 ps |
| CPU time | 7.46 seconds |
| Started | Jan 07 01:38:32 PM PST 24 |
| Finished | Jan 07 01:38:41 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-1948352d-489e-4978-b783-a82f9bbc2d75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1781866435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1781866435 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.976586117 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 28552471734 ps |
| CPU time | 75.88 seconds |
| Started | Jan 07 01:38:33 PM PST 24 |
| Finished | Jan 07 01:39:51 PM PST 24 |
| Peak memory | 201516 kb |
| Host | smart-83937051-b812-42d0-a9be-aef62f9d5c11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=976586117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.976586117 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3980938905 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 13635805566 ps |
| CPU time | 45.61 seconds |
| Started | Jan 07 01:38:43 PM PST 24 |
| Finished | Jan 07 01:39:31 PM PST 24 |
| Peak memory | 201428 kb |
| Host | smart-8c199977-c275-46b5-8014-5428ccac0c80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3980938905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3980938905 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3696765329 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 58030816 ps |
| CPU time | 3 seconds |
| Started | Jan 07 01:39:16 PM PST 24 |
| Finished | Jan 07 01:39:22 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-82c93dcf-6042-462b-b3d8-64595e05f790 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696765329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3696765329 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.4006191155 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 20724682 ps |
| CPU time | 2.24 seconds |
| Started | Jan 07 01:38:38 PM PST 24 |
| Finished | Jan 07 01:38:42 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-d2dc6aa8-9bb0-4900-8821-dea0d27d8b8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4006191155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.4006191155 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.2134444530 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 12342864 ps |
| CPU time | 1.31 seconds |
| Started | Jan 07 01:38:29 PM PST 24 |
| Finished | Jan 07 01:38:32 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-299966fa-47c8-441c-902d-4d417fc7f0aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2134444530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2134444530 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1335215341 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1810117523 ps |
| CPU time | 9.41 seconds |
| Started | Jan 07 01:39:01 PM PST 24 |
| Finished | Jan 07 01:39:11 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-56b4ef8a-a38e-4725-87d4-d3a5fe49f114 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335215341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1335215341 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1601456922 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1462742738 ps |
| CPU time | 5.48 seconds |
| Started | Jan 07 01:38:33 PM PST 24 |
| Finished | Jan 07 01:38:41 PM PST 24 |
| Peak memory | 201444 kb |
| Host | smart-299c9c48-72d7-43f2-a3ea-6537cc2133e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1601456922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1601456922 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.890477849 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 15768201 ps |
| CPU time | 1.18 seconds |
| Started | Jan 07 01:39:05 PM PST 24 |
| Finished | Jan 07 01:39:08 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-fe684a11-71f2-4f76-989d-54a7dd59a77b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890477849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.890477849 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3070598896 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1523057909 ps |
| CPU time | 12.71 seconds |
| Started | Jan 07 01:39:02 PM PST 24 |
| Finished | Jan 07 01:39:15 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-684ae841-6351-4601-a8c1-90bc24593ca8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3070598896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3070598896 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2389338461 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 403450378 ps |
| CPU time | 32.13 seconds |
| Started | Jan 07 01:38:48 PM PST 24 |
| Finished | Jan 07 01:39:22 PM PST 24 |
| Peak memory | 202368 kb |
| Host | smart-88f0cf9a-7ec4-4b24-b07f-128ee2d5954f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2389338461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2389338461 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1636776649 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2233222932 ps |
| CPU time | 72.81 seconds |
| Started | Jan 07 01:38:48 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-518f3d63-ca59-419b-9755-301b92262a82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1636776649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.1636776649 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.328966258 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1792050874 ps |
| CPU time | 57.13 seconds |
| Started | Jan 07 01:38:49 PM PST 24 |
| Finished | Jan 07 01:39:48 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-e8cdc1b3-6450-4043-a084-62699ba050ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=328966258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese t_error.328966258 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3020029464 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 61914391 ps |
| CPU time | 5.85 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:39:48 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-c2411d42-eb0c-494b-9d53-96b3b4c4f9fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3020029464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3020029464 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.742532430 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1611142153 ps |
| CPU time | 7.7 seconds |
| Started | Jan 07 01:39:27 PM PST 24 |
| Finished | Jan 07 01:39:41 PM PST 24 |
| Peak memory | 201500 kb |
| Host | smart-50a9fc03-6ad5-4fbb-880c-dc625c112480 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=742532430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.742532430 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1721424552 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 67948254101 ps |
| CPU time | 336.25 seconds |
| Started | Jan 07 01:38:49 PM PST 24 |
| Finished | Jan 07 01:44:27 PM PST 24 |
| Peak memory | 202776 kb |
| Host | smart-ff3a14e1-e3c6-4e24-98d5-ca6d932f93af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1721424552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.1721424552 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3733866403 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 306414122 ps |
| CPU time | 6.59 seconds |
| Started | Jan 07 01:39:19 PM PST 24 |
| Finished | Jan 07 01:39:30 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-6aaabc09-059f-4766-8355-f4b01ebaba27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3733866403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3733866403 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.141554033 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 14107460 ps |
| CPU time | 1.53 seconds |
| Started | Jan 07 01:38:45 PM PST 24 |
| Finished | Jan 07 01:38:48 PM PST 24 |
| Peak memory | 201432 kb |
| Host | smart-a40cc5e8-014e-4e2f-b588-f2a0d7cb63af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=141554033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.141554033 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.785160939 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 46161227 ps |
| CPU time | 2.56 seconds |
| Started | Jan 07 01:38:38 PM PST 24 |
| Finished | Jan 07 01:38:44 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-dbecef36-2a43-496f-bc03-91d430982aa8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=785160939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.785160939 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1396062114 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2607891425 ps |
| CPU time | 9.03 seconds |
| Started | Jan 07 01:38:44 PM PST 24 |
| Finished | Jan 07 01:38:54 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-ea26ed3a-2d2d-4132-94ff-d4ee5c4db050 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396062114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1396062114 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2961797981 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 1606752825 ps |
| CPU time | 11.52 seconds |
| Started | Jan 07 01:38:39 PM PST 24 |
| Finished | Jan 07 01:38:55 PM PST 24 |
| Peak memory | 201408 kb |
| Host | smart-79084611-7814-41a1-9399-e8690955f6ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2961797981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2961797981 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.2214962902 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 53948857 ps |
| CPU time | 6.9 seconds |
| Started | Jan 07 01:38:41 PM PST 24 |
| Finished | Jan 07 01:38:50 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-7b247928-70f0-4d20-86fe-84d54c07edc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214962902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2214962902 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.1149488313 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 467609445 ps |
| CPU time | 4.24 seconds |
| Started | Jan 07 01:38:54 PM PST 24 |
| Finished | Jan 07 01:39:00 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-122b0319-6f0f-47d8-a5d9-0f184b48d60c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1149488313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1149488313 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.1863186003 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 17125968 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:38:59 PM PST 24 |
| Finished | Jan 07 01:39:02 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-44a1f3a3-b4ab-4d68-901e-a775f670592a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1863186003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1863186003 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.4102455068 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2285971747 ps |
| CPU time | 9.7 seconds |
| Started | Jan 07 01:38:01 PM PST 24 |
| Finished | Jan 07 01:38:13 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-d90da22f-d502-4252-a8d0-97aef99249a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102455068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4102455068 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.160991485 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1657221964 ps |
| CPU time | 7.84 seconds |
| Started | Jan 07 01:38:54 PM PST 24 |
| Finished | Jan 07 01:39:04 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-2a98ff5b-4e8b-4426-954a-8e1da6830a77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=160991485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.160991485 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1033045095 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 13678576 ps |
| CPU time | 1.31 seconds |
| Started | Jan 07 01:38:37 PM PST 24 |
| Finished | Jan 07 01:38:41 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-f5cb09f7-c5c2-4215-b5b5-a286b8919dcd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033045095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1033045095 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.3813164664 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 12989763734 ps |
| CPU time | 53.41 seconds |
| Started | Jan 07 01:38:54 PM PST 24 |
| Finished | Jan 07 01:39:49 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-2bf728ee-2eae-4852-b4e4-81399fe4e025 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3813164664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3813164664 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3345210633 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 12101283507 ps |
| CPU time | 99.9 seconds |
| Started | Jan 07 01:38:48 PM PST 24 |
| Finished | Jan 07 01:40:29 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-a671e0b6-0169-4864-b49c-5bf20e9d1191 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3345210633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3345210633 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1855710082 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4063078096 ps |
| CPU time | 46.15 seconds |
| Started | Jan 07 01:39:22 PM PST 24 |
| Finished | Jan 07 01:40:13 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-f347e672-0223-4c96-af31-2d6c2ca46c38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1855710082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.1855710082 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.3435148942 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 34131531 ps |
| CPU time | 2.82 seconds |
| Started | Jan 07 01:39:02 PM PST 24 |
| Finished | Jan 07 01:39:06 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-04eeab9f-669b-4287-95ae-250afa6e8e8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3435148942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3435148942 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3705343573 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 159329429 ps |
| CPU time | 2.77 seconds |
| Started | Jan 07 01:38:42 PM PST 24 |
| Finished | Jan 07 01:38:46 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-b1996a6e-44a9-4a51-8f04-5bec308ec1f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3705343573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3705343573 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.932118858 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 211143094 ps |
| CPU time | 4.11 seconds |
| Started | Jan 07 01:39:27 PM PST 24 |
| Finished | Jan 07 01:39:37 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-62f8e3b1-840b-4843-b9dd-9859ee19f3b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=932118858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.932118858 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.1402140288 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 62787232 ps |
| CPU time | 6.15 seconds |
| Started | Jan 07 01:39:09 PM PST 24 |
| Finished | Jan 07 01:39:18 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-ac9b1c3f-ce46-4d26-95b3-b8aaa469f6eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1402140288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1402140288 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.594847581 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 255870475 ps |
| CPU time | 6.58 seconds |
| Started | Jan 07 01:39:33 PM PST 24 |
| Finished | Jan 07 01:39:47 PM PST 24 |
| Peak memory | 201480 kb |
| Host | smart-8d8da1f5-43de-45ac-aa91-472abf05cff3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=594847581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.594847581 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2188598903 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 63846582482 ps |
| CPU time | 167.71 seconds |
| Started | Jan 07 01:38:44 PM PST 24 |
| Finished | Jan 07 01:41:33 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-6e0b065a-9eb0-4be0-9aff-e56ce9ee5c26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188598903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2188598903 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.44742398 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 30498427864 ps |
| CPU time | 156.9 seconds |
| Started | Jan 07 01:38:49 PM PST 24 |
| Finished | Jan 07 01:41:27 PM PST 24 |
| Peak memory | 201572 kb |
| Host | smart-d8177a4f-9b9c-4c86-889c-fbc53e12375c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=44742398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.44742398 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.617296543 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 46641163 ps |
| CPU time | 4.12 seconds |
| Started | Jan 07 01:38:41 PM PST 24 |
| Finished | Jan 07 01:38:47 PM PST 24 |
| Peak memory | 201504 kb |
| Host | smart-e57d6c82-f484-40a5-97dc-078f21e8bd98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617296543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.617296543 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.1834030513 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 39086282 ps |
| CPU time | 2.57 seconds |
| Started | Jan 07 01:38:46 PM PST 24 |
| Finished | Jan 07 01:38:49 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-ba5cf869-e9ca-4f0e-be1e-683baed38a52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1834030513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1834030513 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.3091587596 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12614378 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:39:36 PM PST 24 |
| Finished | Jan 07 01:39:49 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-144b480e-7ee8-4491-9068-f931dcbe96e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3091587596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3091587596 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1969824235 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2650125160 ps |
| CPU time | 7.3 seconds |
| Started | Jan 07 01:38:43 PM PST 24 |
| Finished | Jan 07 01:38:52 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-4d4717ab-5c4d-47e5-a061-429f2b663688 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969824235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1969824235 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1132488463 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 707607244 ps |
| CPU time | 5.5 seconds |
| Started | Jan 07 01:38:37 PM PST 24 |
| Finished | Jan 07 01:38:45 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-bdd7fef9-a2e3-4c3c-b0cd-572876319d56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1132488463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1132488463 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.943201289 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 10208368 ps |
| CPU time | 1.1 seconds |
| Started | Jan 07 01:39:32 PM PST 24 |
| Finished | Jan 07 01:39:41 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-a8204dc9-4b71-4193-aec1-e11f51b76d2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943201289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.943201289 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.880863863 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 2236704359 ps |
| CPU time | 27.26 seconds |
| Started | Jan 07 01:38:44 PM PST 24 |
| Finished | Jan 07 01:39:13 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-e3145506-843d-412b-90b5-ff66e6f4794f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=880863863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.880863863 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.497280763 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 6036631481 ps |
| CPU time | 60.22 seconds |
| Started | Jan 07 01:38:57 PM PST 24 |
| Finished | Jan 07 01:39:59 PM PST 24 |
| Peak memory | 202572 kb |
| Host | smart-c5e6c830-67ff-4bda-b485-1bc79b05605d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=497280763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.497280763 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1659492469 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 11118568972 ps |
| CPU time | 131.49 seconds |
| Started | Jan 07 01:39:37 PM PST 24 |
| Finished | Jan 07 01:42:04 PM PST 24 |
| Peak memory | 204084 kb |
| Host | smart-15b0ed11-2322-496e-83a1-d85032988893 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1659492469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.1659492469 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.4082705370 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2749100153 ps |
| CPU time | 50.46 seconds |
| Started | Jan 07 01:38:46 PM PST 24 |
| Finished | Jan 07 01:39:37 PM PST 24 |
| Peak memory | 202876 kb |
| Host | smart-7786d7e0-a933-413b-84ff-95338fa3156e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4082705370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.4082705370 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.1104092940 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 66031668 ps |
| CPU time | 5.97 seconds |
| Started | Jan 07 01:38:45 PM PST 24 |
| Finished | Jan 07 01:38:52 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-5861d23d-7235-4b30-b771-a14cea15e945 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1104092940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1104092940 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.2078621469 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1025383194 ps |
| CPU time | 9.91 seconds |
| Started | Jan 07 01:37:50 PM PST 24 |
| Finished | Jan 07 01:38:02 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-45c62b57-24e4-48cd-9256-35e62bc0812e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2078621469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2078621469 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1546403054 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 218092929897 ps |
| CPU time | 334 seconds |
| Started | Jan 07 01:37:45 PM PST 24 |
| Finished | Jan 07 01:43:21 PM PST 24 |
| Peak memory | 203992 kb |
| Host | smart-f8d9ae8e-1f75-4bfd-8fa2-1c1734045e43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1546403054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.1546403054 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1375902839 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 374070996 ps |
| CPU time | 4.9 seconds |
| Started | Jan 07 01:38:14 PM PST 24 |
| Finished | Jan 07 01:38:20 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-4e09bac4-70b2-4d45-b639-16bd38b8b0e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1375902839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1375902839 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.245893735 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 46669427 ps |
| CPU time | 4.53 seconds |
| Started | Jan 07 01:37:49 PM PST 24 |
| Finished | Jan 07 01:37:56 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-99a49525-5b07-4368-9ee6-9a6817113c41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=245893735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.245893735 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.2828661013 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 15029314 ps |
| CPU time | 1.92 seconds |
| Started | Jan 07 01:37:49 PM PST 24 |
| Finished | Jan 07 01:37:53 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-f39e76e4-a17e-4c38-ac8a-ca4fa8a7b196 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2828661013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2828661013 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2077590777 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 129396392230 ps |
| CPU time | 179.81 seconds |
| Started | Jan 07 01:38:07 PM PST 24 |
| Finished | Jan 07 01:41:08 PM PST 24 |
| Peak memory | 201588 kb |
| Host | smart-97bc317e-8f66-49eb-9974-1d6bb474431c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077590777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2077590777 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3544560920 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 9536195222 ps |
| CPU time | 73.86 seconds |
| Started | Jan 07 01:38:38 PM PST 24 |
| Finished | Jan 07 01:39:55 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-ff498c3e-59b6-4301-ab44-b7f8c1fa5911 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3544560920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3544560920 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.2333671085 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 117032452 ps |
| CPU time | 9.3 seconds |
| Started | Jan 07 01:37:50 PM PST 24 |
| Finished | Jan 07 01:38:02 PM PST 24 |
| Peak memory | 201476 kb |
| Host | smart-969c9ef2-1fd2-45ee-ae26-402dee40a325 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333671085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2333671085 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.3707747117 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 613313166 ps |
| CPU time | 8.7 seconds |
| Started | Jan 07 01:37:58 PM PST 24 |
| Finished | Jan 07 01:38:09 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-a47c4eca-883c-4038-b6ee-a7d9a258cb40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3707747117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3707747117 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.1976507778 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 47958183 ps |
| CPU time | 1.43 seconds |
| Started | Jan 07 01:39:44 PM PST 24 |
| Finished | Jan 07 01:40:02 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-952e9c3a-9517-40be-a4ff-80fd77979514 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1976507778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1976507778 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1532055567 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 7999420886 ps |
| CPU time | 10 seconds |
| Started | Jan 07 01:38:33 PM PST 24 |
| Finished | Jan 07 01:38:45 PM PST 24 |
| Peak memory | 201392 kb |
| Host | smart-7b70e8a8-b22a-465d-a855-2a589e6c8ca2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532055567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1532055567 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.4018953465 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3505615516 ps |
| CPU time | 10.92 seconds |
| Started | Jan 07 01:38:36 PM PST 24 |
| Finished | Jan 07 01:38:49 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-41773b41-ec13-45b1-a5ed-17523c6fd33b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4018953465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.4018953465 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1088874955 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 9028575 ps |
| CPU time | 1.2 seconds |
| Started | Jan 07 01:38:31 PM PST 24 |
| Finished | Jan 07 01:38:34 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-318b2a18-520b-4711-9ece-c594a15f80a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088874955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1088874955 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1801287069 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4217953795 ps |
| CPU time | 58.42 seconds |
| Started | Jan 07 01:38:27 PM PST 24 |
| Finished | Jan 07 01:39:26 PM PST 24 |
| Peak memory | 201536 kb |
| Host | smart-047933a0-566b-46ee-831a-2c393aba316f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1801287069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1801287069 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.597215079 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 10129032987 ps |
| CPU time | 71.34 seconds |
| Started | Jan 07 01:38:32 PM PST 24 |
| Finished | Jan 07 01:39:45 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-40ef58f4-c686-442a-8cd1-54858748e8d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=597215079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.597215079 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1227781168 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2918877287 ps |
| CPU time | 54.95 seconds |
| Started | Jan 07 01:38:45 PM PST 24 |
| Finished | Jan 07 01:39:41 PM PST 24 |
| Peak memory | 202772 kb |
| Host | smart-cde04c02-8e35-4e4f-9835-2ef26ca4b693 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1227781168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.1227781168 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1456247872 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 330950765 ps |
| CPU time | 5.52 seconds |
| Started | Jan 07 01:37:59 PM PST 24 |
| Finished | Jan 07 01:38:07 PM PST 24 |
| Peak memory | 201496 kb |
| Host | smart-beec21f3-f4ad-42ed-8eac-e293bb146d27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1456247872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1456247872 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.465660167 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1668924967 ps |
| CPU time | 5.57 seconds |
| Started | Jan 07 01:39:23 PM PST 24 |
| Finished | Jan 07 01:39:34 PM PST 24 |
| Peak memory | 201364 kb |
| Host | smart-ec7c5fc4-70ff-49b5-a093-4ac328d9aa69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=465660167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.465660167 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3020451371 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 83996901781 ps |
| CPU time | 256.37 seconds |
| Started | Jan 07 01:39:30 PM PST 24 |
| Finished | Jan 07 01:43:53 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-0ea0cf75-574c-479c-a11c-d4e3ce02bcd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3020451371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.3020451371 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3934497212 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 52039331 ps |
| CPU time | 1.64 seconds |
| Started | Jan 07 01:39:38 PM PST 24 |
| Finished | Jan 07 01:39:54 PM PST 24 |
| Peak memory | 201400 kb |
| Host | smart-ff8f95db-84ca-483a-bb75-618f5947a397 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3934497212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3934497212 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.1593546851 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 138597248 ps |
| CPU time | 5.76 seconds |
| Started | Jan 07 01:38:56 PM PST 24 |
| Finished | Jan 07 01:39:04 PM PST 24 |
| Peak memory | 201488 kb |
| Host | smart-6c5bde32-cfbf-4893-a81c-9f41196746fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1593546851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1593546851 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.420984170 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 657974583 ps |
| CPU time | 8.87 seconds |
| Started | Jan 07 01:39:28 PM PST 24 |
| Finished | Jan 07 01:39:44 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-16f294ed-ac40-406e-8bc2-677ade8cec3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=420984170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.420984170 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.2686546068 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 21290463942 ps |
| CPU time | 87.98 seconds |
| Started | Jan 07 01:38:55 PM PST 24 |
| Finished | Jan 07 01:40:24 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-8edd1522-f21c-44db-bcc9-3b07acebdb3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686546068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2686546068 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3855393209 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 15871046462 ps |
| CPU time | 50.21 seconds |
| Started | Jan 07 01:38:59 PM PST 24 |
| Finished | Jan 07 01:39:51 PM PST 24 |
| Peak memory | 201468 kb |
| Host | smart-9cb11e89-d205-44cb-8619-b8cf72cb969d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3855393209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3855393209 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2053483426 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 40697518 ps |
| CPU time | 4.03 seconds |
| Started | Jan 07 01:38:40 PM PST 24 |
| Finished | Jan 07 01:38:47 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-2a54a4a9-d9ce-4957-a3d5-798940befdf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053483426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2053483426 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.423002029 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 703620470 ps |
| CPU time | 7.73 seconds |
| Started | Jan 07 01:39:25 PM PST 24 |
| Finished | Jan 07 01:39:39 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-bc1c8f85-9586-4322-bfc3-781a59b81909 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=423002029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.423002029 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.1258446739 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 10593460 ps |
| CPU time | 1.16 seconds |
| Started | Jan 07 01:38:51 PM PST 24 |
| Finished | Jan 07 01:38:54 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-cbb6d3fc-a158-405c-b1e4-44971f2aad06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1258446739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1258446739 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3913866564 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1975645449 ps |
| CPU time | 9.7 seconds |
| Started | Jan 07 01:39:04 PM PST 24 |
| Finished | Jan 07 01:39:15 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-467f25fc-0162-4e48-8af8-4cfc6cce40e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913866564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3913866564 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.942191184 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1754366188 ps |
| CPU time | 11.05 seconds |
| Started | Jan 07 01:39:17 PM PST 24 |
| Finished | Jan 07 01:39:31 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-b2a0482c-e8f5-402f-b5e2-952323adf21d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=942191184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.942191184 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.4115720057 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 8242130 ps |
| CPU time | 1.05 seconds |
| Started | Jan 07 01:38:59 PM PST 24 |
| Finished | Jan 07 01:39:01 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-ee778946-e5aa-43f3-a746-be438145fea4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115720057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.4115720057 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.1264972203 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 4078804506 ps |
| CPU time | 38.92 seconds |
| Started | Jan 07 01:38:49 PM PST 24 |
| Finished | Jan 07 01:39:30 PM PST 24 |
| Peak memory | 201544 kb |
| Host | smart-01192edf-6a2f-4170-8b82-f11964f48491 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1264972203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1264972203 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.3215850202 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 9597730689 ps |
| CPU time | 51.38 seconds |
| Started | Jan 07 01:39:27 PM PST 24 |
| Finished | Jan 07 01:40:25 PM PST 24 |
| Peak memory | 201564 kb |
| Host | smart-41d74b9e-fadd-4b17-8b8d-7f839e0d50f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3215850202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3215850202 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1713621374 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 637600033 ps |
| CPU time | 32.49 seconds |
| Started | Jan 07 01:39:29 PM PST 24 |
| Finished | Jan 07 01:40:09 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-6bce84c7-636e-47d0-825a-5bdca5bd5f14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1713621374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.1713621374 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2335523206 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3983775975 ps |
| CPU time | 66.84 seconds |
| Started | Jan 07 01:38:44 PM PST 24 |
| Finished | Jan 07 01:39:53 PM PST 24 |
| Peak memory | 204256 kb |
| Host | smart-beb0d56f-500d-4eed-bb69-3cdce2b77970 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2335523206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2335523206 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.2766249669 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 123576852 ps |
| CPU time | 6.5 seconds |
| Started | Jan 07 01:39:10 PM PST 24 |
| Finished | Jan 07 01:39:19 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-c6ea6922-164d-4e80-a828-0b47dfbd90f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2766249669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2766249669 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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