Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.38	100.00	96.27	100.00		100.00	100.00	100.00

Total test records in report: 900

T760	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1233705055	Jan 10 12:44:00 PM PST 24	Jan 10 12:47:06 PM PST 24	16670222731 ps
T173	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1378952307	Jan 10 12:42:32 PM PST 24	Jan 10 12:43:55 PM PST 24	1939689420 ps
T761	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2456896753	Jan 10 12:43:17 PM PST 24	Jan 10 12:44:32 PM PST 24	16582959 ps
T762	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.351232077	Jan 10 12:44:19 PM PST 24	Jan 10 12:45:36 PM PST 24	11688609 ps
T763	/workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.1271984593	Jan 10 12:43:02 PM PST 24	Jan 10 12:47:05 PM PST 24	38150938998 ps
T764	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.289102953	Jan 10 12:42:13 PM PST 24	Jan 10 12:43:35 PM PST 24	1025932253 ps
T765	/workspace/coverage/xbar_build_mode/13.xbar_stress_all.7016034	Jan 10 12:42:39 PM PST 24	Jan 10 12:45:52 PM PST 24	57363857957 ps
T229	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.565803217	Jan 10 12:43:26 PM PST 24	Jan 10 12:48:01 PM PST 24	30952753348 ps
T233	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2842519822	Jan 10 12:43:06 PM PST 24	Jan 10 12:47:19 PM PST 24	35561561019 ps
T766	/workspace/coverage/xbar_build_mode/15.xbar_same_source.686226507	Jan 10 12:42:43 PM PST 24	Jan 10 12:44:02 PM PST 24	312879765 ps
T767	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.8953932	Jan 10 12:42:06 PM PST 24	Jan 10 12:43:26 PM PST 24	7834054449 ps
T768	/workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1846076660	Jan 10 12:43:14 PM PST 24	Jan 10 12:44:28 PM PST 24	137849034 ps
T174	/workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.625750563	Jan 10 12:43:12 PM PST 24	Jan 10 12:45:32 PM PST 24	12756173871 ps
T769	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2663391042	Jan 10 12:43:55 PM PST 24	Jan 10 12:46:13 PM PST 24	8517353192 ps
T770	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3025501141	Jan 10 12:43:06 PM PST 24	Jan 10 12:44:20 PM PST 24	13608077 ps
T771	/workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3094379680	Jan 10 12:42:12 PM PST 24	Jan 10 12:43:31 PM PST 24	205010900 ps
T772	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2722020402	Jan 10 12:43:53 PM PST 24	Jan 10 12:45:12 PM PST 24	197341963 ps
T773	/workspace/coverage/xbar_build_mode/16.xbar_error_random.1811848898	Jan 10 12:42:54 PM PST 24	Jan 10 12:44:09 PM PST 24	202997272 ps
T774	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2630967336	Jan 10 12:43:01 PM PST 24	Jan 10 12:44:15 PM PST 24	11668257 ps
T775	/workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.490432177	Jan 10 12:43:25 PM PST 24	Jan 10 12:44:47 PM PST 24	76557776 ps
T776	/workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.866377807	Jan 10 12:42:19 PM PST 24	Jan 10 12:43:39 PM PST 24	896172936 ps
T777	/workspace/coverage/xbar_build_mode/5.xbar_stress_all.1176894119	Jan 10 12:42:21 PM PST 24	Jan 10 12:44:48 PM PST 24	634055348 ps
T778	/workspace/coverage/xbar_build_mode/15.xbar_smoke.1510886689	Jan 10 12:42:50 PM PST 24	Jan 10 12:44:05 PM PST 24	23810610 ps
T779	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1258773716	Jan 10 12:44:11 PM PST 24	Jan 10 12:45:30 PM PST 24	103456168 ps
T780	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3191250271	Jan 10 12:42:40 PM PST 24	Jan 10 12:44:08 PM PST 24	2030386084 ps
T781	/workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3670376751	Jan 10 12:43:14 PM PST 24	Jan 10 12:44:38 PM PST 24	2926220698 ps
T782	/workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1436062584	Jan 10 12:42:10 PM PST 24	Jan 10 12:43:35 PM PST 24	4318652688 ps
T783	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3895087258	Jan 10 12:42:11 PM PST 24	Jan 10 12:44:47 PM PST 24	48332555786 ps
T784	/workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1906528573	Jan 10 12:42:36 PM PST 24	Jan 10 12:43:59 PM PST 24	882359780 ps
T785	/workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1057388200	Jan 10 12:42:43 PM PST 24	Jan 10 12:45:41 PM PST 24	27445184205 ps
T786	/workspace/coverage/xbar_build_mode/35.xbar_same_source.1022384492	Jan 10 12:43:54 PM PST 24	Jan 10 12:45:13 PM PST 24	152760372 ps
T787	/workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3566927039	Jan 10 12:43:57 PM PST 24	Jan 10 12:45:16 PM PST 24	49319922 ps
T788	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.1101843409	Jan 10 12:44:01 PM PST 24	Jan 10 12:45:53 PM PST 24	8503413552 ps
T789	/workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1059379776	Jan 10 12:43:40 PM PST 24	Jan 10 12:45:08 PM PST 24	1890125439 ps
T790	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2537804533	Jan 10 12:43:38 PM PST 24	Jan 10 12:46:59 PM PST 24	6714001974 ps
T791	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1589625595	Jan 10 12:44:12 PM PST 24	Jan 10 12:45:47 PM PST 24	1747677518 ps
T792	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1261867843	Jan 10 12:43:06 PM PST 24	Jan 10 12:45:04 PM PST 24	302565980 ps
T793	/workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3263415181	Jan 10 12:44:10 PM PST 24	Jan 10 12:45:29 PM PST 24	44166917 ps
T794	/workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2757436617	Jan 10 12:42:33 PM PST 24	Jan 10 12:43:58 PM PST 24	1746832980 ps
T795	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1165004500	Jan 10 12:43:55 PM PST 24	Jan 10 12:45:21 PM PST 24	3145430044 ps
T796	/workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1064798653	Jan 10 12:43:16 PM PST 24	Jan 10 12:46:50 PM PST 24	29075145789 ps
T797	/workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3459827675	Jan 10 12:42:59 PM PST 24	Jan 10 12:44:22 PM PST 24	2681129692 ps
T798	/workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2001713414	Jan 10 12:43:06 PM PST 24	Jan 10 12:44:27 PM PST 24	1068047651 ps
T799	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1768963726	Jan 10 12:44:06 PM PST 24	Jan 10 12:47:19 PM PST 24	555188155 ps
T800	/workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.2077107828	Jan 10 12:44:03 PM PST 24	Jan 10 12:45:22 PM PST 24	27003152 ps
T801	/workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3759991869	Jan 10 12:42:19 PM PST 24	Jan 10 12:43:36 PM PST 24	446677608 ps
T802	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.917347565	Jan 10 12:43:20 PM PST 24	Jan 10 12:44:38 PM PST 24	44232269 ps
T13	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1232058706	Jan 10 12:42:45 PM PST 24	Jan 10 12:44:19 PM PST 24	152162177 ps
T803	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device.2828218602	Jan 10 12:42:36 PM PST 24	Jan 10 12:43:55 PM PST 24	164377552 ps
T804	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3560829512	Jan 10 12:43:59 PM PST 24	Jan 10 12:45:40 PM PST 24	1235622747 ps
T805	/workspace/coverage/xbar_build_mode/5.xbar_random.1670835693	Jan 10 12:42:27 PM PST 24	Jan 10 12:43:41 PM PST 24	43004969 ps
T806	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2804983536	Jan 10 12:43:03 PM PST 24	Jan 10 12:46:09 PM PST 24	33539116337 ps
T223	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.804386738	Jan 10 12:43:44 PM PST 24	Jan 10 12:47:48 PM PST 24	41820585211 ps
T807	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3926605574	Jan 10 12:42:05 PM PST 24	Jan 10 12:44:37 PM PST 24	552496775 ps
T808	/workspace/coverage/xbar_build_mode/25.xbar_random.3297618814	Jan 10 12:43:22 PM PST 24	Jan 10 12:44:40 PM PST 24	25983417 ps
T809	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3705009412	Jan 10 12:43:57 PM PST 24	Jan 10 12:47:06 PM PST 24	3327701635 ps
T810	/workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1002305314	Jan 10 12:43:45 PM PST 24	Jan 10 12:46:15 PM PST 24	15641385451 ps
T811	/workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2633525293	Jan 10 12:43:12 PM PST 24	Jan 10 12:44:29 PM PST 24	354672102 ps
T812	/workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.630594121	Jan 10 12:42:16 PM PST 24	Jan 10 12:43:30 PM PST 24	11858151 ps
T813	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.4073804248	Jan 10 12:43:49 PM PST 24	Jan 10 12:46:27 PM PST 24	13404930522 ps
T814	/workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2470499289	Jan 10 12:44:21 PM PST 24	Jan 10 12:45:44 PM PST 24	2228636804 ps
T815	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2208808044	Jan 10 12:43:45 PM PST 24	Jan 10 12:45:25 PM PST 24	15812964222 ps
T816	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.981153751	Jan 10 12:43:59 PM PST 24	Jan 10 12:46:03 PM PST 24	1716311287 ps
T817	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.402403898	Jan 10 12:43:04 PM PST 24	Jan 10 12:45:27 PM PST 24	4526285069 ps
T818	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1504704247	Jan 10 12:42:53 PM PST 24	Jan 10 12:44:07 PM PST 24	11042569 ps
T819	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.196380153	Jan 10 12:43:55 PM PST 24	Jan 10 12:45:22 PM PST 24	193165315 ps
T820	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1998210411	Jan 10 12:42:05 PM PST 24	Jan 10 12:43:21 PM PST 24	18476913 ps
T160	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.636374806	Jan 10 12:42:09 PM PST 24	Jan 10 12:43:30 PM PST 24	1310335599 ps
T821	/workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3609532483	Jan 10 12:44:26 PM PST 24	Jan 10 12:45:44 PM PST 24	9724686 ps
T822	/workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1697517457	Jan 10 12:43:24 PM PST 24	Jan 10 12:46:45 PM PST 24	49881978436 ps
T823	/workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1493470671	Jan 10 12:42:53 PM PST 24	Jan 10 12:44:17 PM PST 24	732998595 ps
T824	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2664009265	Jan 10 12:42:34 PM PST 24	Jan 10 12:43:53 PM PST 24	906176077 ps
T825	/workspace/coverage/xbar_build_mode/21.xbar_stress_all.1514828015	Jan 10 12:43:24 PM PST 24	Jan 10 12:46:29 PM PST 24	8225816492 ps
T826	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3039707575	Jan 10 12:43:34 PM PST 24	Jan 10 12:45:53 PM PST 24	597522965 ps
T827	/workspace/coverage/xbar_build_mode/42.xbar_same_source.2828371003	Jan 10 12:44:04 PM PST 24	Jan 10 12:45:32 PM PST 24	56703539 ps
T828	/workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.4222300872	Jan 10 12:42:52 PM PST 24	Jan 10 12:44:08 PM PST 24	33507126 ps
T829	/workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3664911616	Jan 10 12:44:07 PM PST 24	Jan 10 12:45:27 PM PST 24	83523819 ps
T830	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.44674525	Jan 10 12:43:19 PM PST 24	Jan 10 12:46:33 PM PST 24	112618430888 ps
T831	/workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3218409520	Jan 10 12:43:10 PM PST 24	Jan 10 12:46:15 PM PST 24	15897190010 ps
T832	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.600224415	Jan 10 12:44:18 PM PST 24	Jan 10 12:46:07 PM PST 24	375194070 ps
T833	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1010308070	Jan 10 12:43:58 PM PST 24	Jan 10 12:45:13 PM PST 24	22879011 ps
T834	/workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.671153842	Jan 10 12:43:30 PM PST 24	Jan 10 12:44:58 PM PST 24	3254346757 ps
T835	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.157783517	Jan 10 12:44:29 PM PST 24	Jan 10 12:46:55 PM PST 24	7678866587 ps
T836	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3277557607	Jan 10 12:43:08 PM PST 24	Jan 10 12:45:02 PM PST 24	2769461863 ps
T837	/workspace/coverage/xbar_build_mode/31.xbar_error_random.592798796	Jan 10 12:43:40 PM PST 24	Jan 10 12:44:56 PM PST 24	19102002 ps
T838	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2666199218	Jan 10 12:42:08 PM PST 24	Jan 10 12:43:33 PM PST 24	513895371 ps
T839	/workspace/coverage/xbar_build_mode/37.xbar_stress_all.1803284989	Jan 10 12:44:05 PM PST 24	Jan 10 12:45:27 PM PST 24	787101538 ps
T840	/workspace/coverage/xbar_build_mode/19.xbar_smoke.294189597	Jan 10 12:43:09 PM PST 24	Jan 10 12:44:26 PM PST 24	13046465 ps
T841	/workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.244661737	Jan 10 12:43:54 PM PST 24	Jan 10 12:45:20 PM PST 24	4483885823 ps
T842	/workspace/coverage/xbar_build_mode/33.xbar_random.3025482419	Jan 10 12:43:40 PM PST 24	Jan 10 12:45:11 PM PST 24	1742383850 ps
T843	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3251429659	Jan 10 12:44:21 PM PST 24	Jan 10 12:45:43 PM PST 24	352045712 ps
T844	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.783909473	Jan 10 12:43:25 PM PST 24	Jan 10 12:44:49 PM PST 24	47961771 ps
T845	/workspace/coverage/xbar_build_mode/49.xbar_error_random.3410525967	Jan 10 12:44:35 PM PST 24	Jan 10 12:45:54 PM PST 24	83050144 ps
T846	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1315146092	Jan 10 12:42:05 PM PST 24	Jan 10 12:43:38 PM PST 24	4473401338 ps
T847	/workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2776469974	Jan 10 12:44:18 PM PST 24	Jan 10 12:45:42 PM PST 24	1215188126 ps
T848	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.795197803	Jan 10 12:43:57 PM PST 24	Jan 10 12:45:32 PM PST 24	3825221184 ps
T849	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1061430313	Jan 10 12:42:03 PM PST 24	Jan 10 12:44:57 PM PST 24	1229392949 ps
T850	/workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1819399983	Jan 10 12:44:03 PM PST 24	Jan 10 12:45:21 PM PST 24	25516917 ps
T851	/workspace/coverage/xbar_build_mode/8.xbar_same_source.628126646	Jan 10 12:42:21 PM PST 24	Jan 10 12:43:38 PM PST 24	100796308 ps
T852	/workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.39865128	Jan 10 12:42:44 PM PST 24	Jan 10 12:44:07 PM PST 24	2753921393 ps
T853	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.535864343	Jan 10 12:43:31 PM PST 24	Jan 10 12:45:06 PM PST 24	3540345463 ps
T854	/workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2388449702	Jan 10 12:43:49 PM PST 24	Jan 10 12:45:11 PM PST 24	526345206 ps
T855	/workspace/coverage/xbar_build_mode/5.xbar_same_source.1727616176	Jan 10 12:42:16 PM PST 24	Jan 10 12:43:37 PM PST 24	896479636 ps
T856	/workspace/coverage/xbar_build_mode/17.xbar_random.1951444933	Jan 10 12:43:22 PM PST 24	Jan 10 12:44:40 PM PST 24	92688528 ps
T112	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device.3869144867	Jan 10 12:42:11 PM PST 24	Jan 10 12:43:44 PM PST 24	3901482209 ps
T857	/workspace/coverage/xbar_build_mode/30.xbar_random.1602628720	Jan 10 12:43:46 PM PST 24	Jan 10 12:45:04 PM PST 24	604362602 ps
T858	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3594062537	Jan 10 12:42:33 PM PST 24	Jan 10 12:45:08 PM PST 24	23774796990 ps
T859	/workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3824357530	Jan 10 12:42:41 PM PST 24	Jan 10 12:44:07 PM PST 24	5780266587 ps
T860	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.572477659	Jan 10 12:42:08 PM PST 24	Jan 10 12:44:16 PM PST 24	4443508496 ps
T861	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.117492980	Jan 10 12:43:28 PM PST 24	Jan 10 12:44:55 PM PST 24	11026674340 ps
T862	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3416445920	Jan 10 12:42:59 PM PST 24	Jan 10 12:49:41 PM PST 24	123362238110 ps
T863	/workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2856737625	Jan 10 12:42:10 PM PST 24	Jan 10 12:43:46 PM PST 24	4588779553 ps
T864	/workspace/coverage/xbar_build_mode/27.xbar_stress_all.327546731	Jan 10 12:43:23 PM PST 24	Jan 10 12:45:01 PM PST 24	287260846 ps
T865	/workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3549657414	Jan 10 12:42:21 PM PST 24	Jan 10 12:43:58 PM PST 24	3620691140 ps
T866	/workspace/coverage/xbar_build_mode/48.xbar_random.1277083557	Jan 10 12:44:24 PM PST 24	Jan 10 12:45:43 PM PST 24	28258422 ps
T867	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.119380201	Jan 10 12:43:07 PM PST 24	Jan 10 12:44:26 PM PST 24	592678955 ps
T868	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3888941796	Jan 10 12:44:07 PM PST 24	Jan 10 12:46:31 PM PST 24	423568611 ps
T869	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3570643027	Jan 10 12:44:25 PM PST 24	Jan 10 12:46:17 PM PST 24	6643228460 ps
T870	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3378810948	Jan 10 12:42:41 PM PST 24	Jan 10 12:44:30 PM PST 24	1878939984 ps
T871	/workspace/coverage/xbar_build_mode/43.xbar_same_source.1337151778	Jan 10 12:44:11 PM PST 24	Jan 10 12:45:33 PM PST 24	766287780 ps
T872	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2773799899	Jan 10 12:44:17 PM PST 24	Jan 10 12:45:37 PM PST 24	58673164 ps
T873	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3341133370	Jan 10 12:43:37 PM PST 24	Jan 10 12:46:00 PM PST 24	1711654225 ps
T874	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.192393716	Jan 10 12:42:25 PM PST 24	Jan 10 12:43:42 PM PST 24	9971778 ps
T875	/workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3037004091	Jan 10 12:43:59 PM PST 24	Jan 10 12:45:46 PM PST 24	8839879415 ps
T876	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2823518614	Jan 10 12:43:33 PM PST 24	Jan 10 12:48:57 PM PST 24	43554515850 ps
T129	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2610181101	Jan 10 12:43:48 PM PST 24	Jan 10 12:47:07 PM PST 24	71929834473 ps
T877	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3064912901	Jan 10 12:43:41 PM PST 24	Jan 10 12:45:09 PM PST 24	2671264732 ps
T878	/workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1325824955	Jan 10 12:44:06 PM PST 24	Jan 10 12:45:28 PM PST 24	3167287883 ps
T879	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3663034059	Jan 10 12:43:40 PM PST 24	Jan 10 12:45:07 PM PST 24	68037154 ps
T880	/workspace/coverage/xbar_build_mode/19.xbar_same_source.325943832	Jan 10 12:43:02 PM PST 24	Jan 10 12:44:18 PM PST 24	130921520 ps
T881	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.131403660	Jan 10 12:44:21 PM PST 24	Jan 10 12:48:24 PM PST 24	27448640098 ps
T882	/workspace/coverage/xbar_build_mode/30.xbar_error_random.3939591946	Jan 10 12:43:45 PM PST 24	Jan 10 12:45:04 PM PST 24	112410418 ps
T883	/workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.536286227	Jan 10 12:42:09 PM PST 24	Jan 10 12:45:12 PM PST 24	18370937080 ps
T884	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.199772038	Jan 10 12:43:36 PM PST 24	Jan 10 12:45:05 PM PST 24	97217863 ps
T885	/workspace/coverage/xbar_build_mode/30.xbar_stress_all.1773010333	Jan 10 12:43:43 PM PST 24	Jan 10 12:44:59 PM PST 24	5999549 ps
T886	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.4094129578	Jan 10 12:42:17 PM PST 24	Jan 10 12:48:37 PM PST 24	53348509735 ps
T887	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.305163088	Jan 10 12:43:09 PM PST 24	Jan 10 12:44:59 PM PST 24	3192303710 ps
T888	/workspace/coverage/xbar_build_mode/2.xbar_error_random.2066369718	Jan 10 12:42:06 PM PST 24	Jan 10 12:43:26 PM PST 24	97586627 ps
T889	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2748767501	Jan 10 12:43:35 PM PST 24	Jan 10 12:44:51 PM PST 24	10178757 ps
T890	/workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1531202772	Jan 10 12:44:29 PM PST 24	Jan 10 12:45:54 PM PST 24	6781176115 ps
T891	/workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.155606069	Jan 10 12:42:18 PM PST 24	Jan 10 12:45:09 PM PST 24	29417868637 ps
T892	/workspace/coverage/xbar_build_mode/15.xbar_error_random.2403839701	Jan 10 12:42:39 PM PST 24	Jan 10 12:44:02 PM PST 24	386783945 ps
T893	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2012892337	Jan 10 12:43:58 PM PST 24	Jan 10 12:45:19 PM PST 24	1153080393 ps
T894	/workspace/coverage/xbar_build_mode/38.xbar_random.3743749220	Jan 10 12:43:58 PM PST 24	Jan 10 12:45:17 PM PST 24	151939029 ps
T895	/workspace/coverage/xbar_build_mode/7.xbar_smoke.2014556441	Jan 10 12:42:17 PM PST 24	Jan 10 12:43:32 PM PST 24	45473731 ps
T896	/workspace/coverage/xbar_build_mode/17.xbar_smoke.3603091040	Jan 10 12:42:55 PM PST 24	Jan 10 12:44:10 PM PST 24	13682990 ps
T897	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2720237670	Jan 10 12:42:25 PM PST 24	Jan 10 12:43:42 PM PST 24	13015988 ps
T898	/workspace/coverage/xbar_build_mode/35.xbar_error_random.4038762638	Jan 10 12:43:58 PM PST 24	Jan 10 12:45:13 PM PST 24	34566476 ps
T899	/workspace/coverage/xbar_build_mode/44.xbar_same_source.3263052338	Jan 10 12:44:06 PM PST 24	Jan 10 12:45:34 PM PST 24	688012947 ps
T900	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1391418605	Jan 10 12:42:35 PM PST 24	Jan 10 12:43:55 PM PST 24	1679046263 ps

Test location	/workspace/coverage/xbar_build_mode/49.xbar_same_source.2492575126
Short name	T1
Test name
Test status
Simulation time	2799844261 ps
CPU time	9.7 seconds
Started	Jan 10 12:44:48 PM PST 24
Finished	Jan 10 12:46:16 PM PST 24
Peak memory	201592 kb
Host	smart-642748d2-a580-46e3-9235-224d2534d1ef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2492575126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2492575126
Directory	/workspace/49.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1416327675
Short name	T167
Test name
Test status
Simulation time	82802905757 ps
CPU time	297.16 seconds
Started	Jan 10 12:43:53 PM PST 24
Finished	Jan 10 12:50:05 PM PST 24
Peak memory	203712 kb
Host	smart-3a59bf5c-c0e8-43e4-988c-ec8711e97649
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1416327675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.1416327675
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.131684868
Short name	T181
Test name
Test status
Simulation time	48053909674 ps
CPU time	290.54 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:48:13 PM PST 24
Peak memory	202960 kb
Host	smart-edb1e7e1-81ca-4c67-8410-065c0f1a0ce6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=131684868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow _rsp.131684868
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.604210099
Short name	T213
Test name
Test status
Simulation time	106600080810 ps
CPU time	368.3 seconds
Started	Jan 10 12:42:08 PM PST 24
Finished	Jan 10 12:49:30 PM PST 24
Peak memory	202712 kb
Host	smart-79635c08-d971-4a0e-9a8b-0ca861e312eb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=604210099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow _rsp.604210099
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1226802645
Short name	T16
Test name
Test status
Simulation time	458019490 ps
CPU time	34.1 seconds
Started	Jan 10 12:42:23 PM PST 24
Finished	Jan 10 12:44:17 PM PST 24
Peak memory	201624 kb
Host	smart-dabaf428-40e7-464f-914f-82074d49080c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1226802645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1226802645
Directory	/workspace/9.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1015398885
Short name	T222
Test name
Test status
Simulation time	71770913339 ps
CPU time	217.76 seconds
Started	Jan 10 12:43:06 PM PST 24
Finished	Jan 10 12:47:57 PM PST 24
Peak memory	202828 kb
Host	smart-a7ef6191-d2e4-4a04-8b2b-7139e300e65a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1015398885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.1015398885
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.578212317
Short name	T53
Test name
Test status
Simulation time	7581630305 ps
CPU time	181.89 seconds
Started	Jan 10 12:43:11 PM PST 24
Finished	Jan 10 12:47:25 PM PST 24
Peak memory	206380 kb
Host	smart-72342358-20f4-4a62-b0e8-3d8ee57c8d63
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=578212317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand _reset.578212317
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.4080027646
Short name	T105
Test name
Test status
Simulation time	290306008522 ps
CPU time	300.55 seconds
Started	Jan 10 12:42:39 PM PST 24
Finished	Jan 10 12:48:54 PM PST 24
Peak memory	202956 kb
Host	smart-644f9b1f-922b-43ea-9a10-fcaf78d362d8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4080027646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.4080027646
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3802128406
Short name	T15
Test name
Test status
Simulation time	36966801193 ps
CPU time	194.65 seconds
Started	Jan 10 12:44:10 PM PST 24
Finished	Jan 10 12:48:41 PM PST 24
Peak memory	202740 kb
Host	smart-5bba826d-8ada-4501-8f1f-1676fbd7fbf8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3802128406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.3802128406
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.723107316
Short name	T14
Test name
Test status
Simulation time	7810162763 ps
CPU time	143.36 seconds
Started	Jan 10 12:42:41 PM PST 24
Finished	Jan 10 12:46:18 PM PST 24
Peak memory	204500 kb
Host	smart-54cb02a8-3fda-4186-b536-adbbaa80a632
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=723107316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res et_error.723107316
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.317530394
Short name	T39
Test name
Test status
Simulation time	29869862001 ps
CPU time	191.29 seconds
Started	Jan 10 12:43:54 PM PST 24
Finished	Jan 10 12:48:21 PM PST 24
Peak memory	203832 kb
Host	smart-5902710b-65d2-4fbb-b3de-3e0304531fab
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=317530394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slo w_rsp.317530394
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1290648945
Short name	T7
Test name
Test status
Simulation time	1083709194 ps
CPU time	84.65 seconds
Started	Jan 10 12:43:55 PM PST 24
Finished	Jan 10 12:46:34 PM PST 24
Peak memory	206192 kb
Host	smart-157f3f58-b88a-4a8a-bbe8-6949779dc006
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1290648945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.1290648945
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.54895491
Short name	T22
Test name
Test status
Simulation time	11271873224 ps
CPU time	13.37 seconds
Started	Jan 10 12:44:20 PM PST 24
Finished	Jan 10 12:45:50 PM PST 24
Peak memory	201620 kb
Host	smart-f4012447-4163-4c1a-9630-9e16882e47df
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=54895491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.54895491
Directory	/workspace/45.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2853275688
Short name	T109
Test name
Test status
Simulation time	63671360168 ps
CPU time	349.28 seconds
Started	Jan 10 12:42:49 PM PST 24
Finished	Jan 10 12:49:53 PM PST 24
Peak memory	204320 kb
Host	smart-26a93f65-21c3-4f76-ae94-ee0d82ff621e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2853275688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.2853275688
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3488830354
Short name	T217
Test name
Test status
Simulation time	30531674657 ps
CPU time	134.29 seconds
Started	Jan 10 12:43:17 PM PST 24
Finished	Jan 10 12:46:45 PM PST 24
Peak memory	201820 kb
Host	smart-ad718a9a-0aff-4e81-8385-4c442241691d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3488830354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.3488830354
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random.3550244383
Short name	T20
Test name
Test status
Simulation time	53532539 ps
CPU time	4.49 seconds
Started	Jan 10 12:42:24 PM PST 24
Finished	Jan 10 12:43:41 PM PST 24
Peak memory	201584 kb
Host	smart-e94294c1-8025-4fb5-a2fb-bd435234638c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3550244383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3550244383
Directory	/workspace/10.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.4221878706
Short name	T10
Test name
Test status
Simulation time	232977294 ps
CPU time	22.59 seconds
Started	Jan 10 12:42:08 PM PST 24
Finished	Jan 10 12:43:45 PM PST 24
Peak memory	202752 kb
Host	smart-6d61a1da-29a1-4b34-bade-cc3ad28502af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4221878706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.4221878706
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1143299716
Short name	T8
Test name
Test status
Simulation time	669697867 ps
CPU time	76.73 seconds
Started	Jan 10 12:42:20 PM PST 24
Finished	Jan 10 12:44:50 PM PST 24
Peak memory	205296 kb
Host	smart-40b11363-af8d-4688-b82e-50ba668c71df
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1143299716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.1143299716
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.4271753890
Short name	T6
Test name
Test status
Simulation time	2489237944 ps
CPU time	90.54 seconds
Started	Jan 10 12:44:00 PM PST 24
Finished	Jan 10 12:46:45 PM PST 24
Peak memory	204172 kb
Host	smart-74868a5d-f3fd-4132-969e-68c9b74561bf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4271753890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.4271753890
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2454861153
Short name	T9
Test name
Test status
Simulation time	545458323 ps
CPU time	95.81 seconds
Started	Jan 10 12:42:30 PM PST 24
Finished	Jan 10 12:45:19 PM PST 24
Peak memory	205060 kb
Host	smart-0be78887-33f7-43c8-b930-ed67ad4c1fde
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2454861153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.2454861153
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1232058706
Short name	T13
Test name
Test status
Simulation time	152162177 ps
CPU time	20.31 seconds
Started	Jan 10 12:42:45 PM PST 24
Finished	Jan 10 12:44:19 PM PST 24
Peak memory	201748 kb
Host	smart-a3936416-6e1c-4df6-b4e6-948b07f45423
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1232058706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.1232058706
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device.649422361
Short name	T61
Test name
Test status
Simulation time	1058777986 ps
CPU time	13.06 seconds
Started	Jan 10 12:42:27 PM PST 24
Finished	Jan 10 12:43:53 PM PST 24
Peak memory	201628 kb
Host	smart-dd2664d2-6cb8-4e29-8961-6a1ed98cbe8a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=649422361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.649422361
Directory	/workspace/5.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3680528739
Short name	T219
Test name
Test status
Simulation time	6629737947 ps
CPU time	73.01 seconds
Started	Jan 10 12:42:07 PM PST 24
Finished	Jan 10 12:44:33 PM PST 24
Peak memory	204640 kb
Host	smart-16807be9-24ac-405f-ba12-47fb1bec0bc5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3680528739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.3680528739
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.4049776972
Short name	T80
Test name
Test status
Simulation time	8107451757 ps
CPU time	192.92 seconds
Started	Jan 10 12:42:22 PM PST 24
Finished	Jan 10 12:46:52 PM PST 24
Peak memory	204424 kb
Host	smart-a5c126ee-2ed3-452c-bf3c-2d4b82c70eff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4049776972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.4049776972
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.4015000355
Short name	T36
Test name
Test status
Simulation time	289763608629 ps
CPU time	301.11 seconds
Started	Jan 10 12:41:55 PM PST 24
Finished	Jan 10 12:48:07 PM PST 24
Peak memory	203148 kb
Host	smart-41da518e-e078-4cbf-8699-8356e3d42643
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4015000355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.4015000355
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.3070688634
Short name	T81
Test name
Test status
Simulation time	9748165622 ps
CPU time	51.18 seconds
Started	Jan 10 12:43:10 PM PST 24
Finished	Jan 10 12:45:14 PM PST 24
Peak memory	202568 kb
Host	smart-fa3c1289-3ce7-453f-9225-10a25cf0e661
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3070688634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3070688634
Directory	/workspace/16.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.930516196
Short name	T244
Test name
Test status
Simulation time	2648554129 ps
CPU time	115.92 seconds
Started	Jan 10 12:43:33 PM PST 24
Finished	Jan 10 12:46:47 PM PST 24
Peak memory	205696 kb
Host	smart-3ab158f7-890d-459e-9cff-a116222e7ec2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=930516196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res et_error.930516196
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1742229969
Short name	T111
Test name
Test status
Simulation time	2468581337 ps
CPU time	23.21 seconds
Started	Jan 10 12:41:59 PM PST 24
Finished	Jan 10 12:43:36 PM PST 24
Peak memory	201708 kb
Host	smart-ab6286bc-91be-45e1-a8eb-e7fe1952a74a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1742229969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1742229969
Directory	/workspace/0.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2751564498
Short name	T134
Test name
Test status
Simulation time	692303558 ps
CPU time	9.88 seconds
Started	Jan 10 12:42:07 PM PST 24
Finished	Jan 10 12:43:30 PM PST 24
Peak memory	201712 kb
Host	smart-ea3b21df-4e69-42e8-9c2a-e7b530b1ecf3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2751564498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2751564498
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_random.444331089
Short name	T594
Test name
Test status
Simulation time	718380932 ps
CPU time	10.88 seconds
Started	Jan 10 12:41:59 PM PST 24
Finished	Jan 10 12:43:23 PM PST 24
Peak memory	201640 kb
Host	smart-dd50a4ff-f629-4b6e-a13c-ae6529f5cd1d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=444331089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.444331089
Directory	/workspace/0.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random.3051236928
Short name	T680
Test name
Test status
Simulation time	219052557 ps
CPU time	8.43 seconds
Started	Jan 10 12:41:58 PM PST 24
Finished	Jan 10 12:43:19 PM PST 24
Peak memory	201696 kb
Host	smart-03723302-dd9c-48d0-a467-fa7c2ec1e688
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3051236928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3051236928
Directory	/workspace/0.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3281530104
Short name	T647
Test name
Test status
Simulation time	65075877631 ps
CPU time	106.5 seconds
Started	Jan 10 12:41:55 PM PST 24
Finished	Jan 10 12:44:53 PM PST 24
Peak memory	201664 kb
Host	smart-3622318e-d847-4f6f-882a-1a5a54f64197
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281530104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3281530104
Directory	/workspace/0.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3466846264
Short name	T274
Test name
Test status
Simulation time	25671183323 ps
CPU time	118.03 seconds
Started	Jan 10 12:41:59 PM PST 24
Finished	Jan 10 12:45:10 PM PST 24
Peak memory	201800 kb
Host	smart-3e203a3d-1369-4a2c-9a15-a6c239a5b360
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3466846264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3466846264
Directory	/workspace/0.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1594763895
Short name	T503
Test name
Test status
Simulation time	101250664 ps
CPU time	9.52 seconds
Started	Jan 10 12:42:00 PM PST 24
Finished	Jan 10 12:43:23 PM PST 24
Peak memory	201576 kb
Host	smart-3dc8b9c6-ac44-473f-8f64-21445bc81265
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594763895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1594763895
Directory	/workspace/0.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_same_source.4209331816
Short name	T94
Test name
Test status
Simulation time	16248904 ps
CPU time	1.71 seconds
Started	Jan 10 12:41:55 PM PST 24
Finished	Jan 10 12:43:07 PM PST 24
Peak memory	201732 kb
Host	smart-d2e5bc95-217d-48a6-ae32-298cc458d29a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4209331816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.4209331816
Directory	/workspace/0.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke.834581982
Short name	T612
Test name
Test status
Simulation time	37980719 ps
CPU time	1.19 seconds
Started	Jan 10 12:41:59 PM PST 24
Finished	Jan 10 12:43:14 PM PST 24
Peak memory	201672 kb
Host	smart-16b21da3-939d-4f9e-9d54-3e0f873dafd2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=834581982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.834581982
Directory	/workspace/0.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1266110067
Short name	T72
Test name
Test status
Simulation time	7635173500 ps
CPU time	11.87 seconds
Started	Jan 10 12:41:55 PM PST 24
Finished	Jan 10 12:43:18 PM PST 24
Peak memory	201776 kb
Host	smart-fa405f18-7658-49bb-ae62-259fbcfa3356
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266110067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1266110067
Directory	/workspace/0.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2100480994
Short name	T458
Test name
Test status
Simulation time	940589162 ps
CPU time	6.67 seconds
Started	Jan 10 12:42:01 PM PST 24
Finished	Jan 10 12:43:21 PM PST 24
Peak memory	201640 kb
Host	smart-b5c4c301-6d93-447e-aa11-899c0e7fca59
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2100480994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2100480994
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3064553957
Short name	T667
Test name
Test status
Simulation time	10560584 ps
CPU time	1.31 seconds
Started	Jan 10 12:42:00 PM PST 24
Finished	Jan 10 12:43:15 PM PST 24
Peak memory	201748 kb
Host	smart-1e04ea58-473b-4488-a627-e783cd9098ce
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064553957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3064553957
Directory	/workspace/0.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all.2903320987
Short name	T613
Test name
Test status
Simulation time	5421206279 ps
CPU time	81.35 seconds
Started	Jan 10 12:42:10 PM PST 24
Finished	Jan 10 12:44:44 PM PST 24
Peak memory	202880 kb
Host	smart-4981b0df-0e87-43d4-9d41-1954b6d52ea2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2903320987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2903320987
Directory	/workspace/0.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.572477659
Short name	T860
Test name
Test status
Simulation time	4443508496 ps
CPU time	54.37 seconds
Started	Jan 10 12:42:08 PM PST 24
Finished	Jan 10 12:44:16 PM PST 24
Peak memory	201808 kb
Host	smart-71040c7c-77eb-4d69-8f57-38a22dc5be32
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=572477659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.572477659
Directory	/workspace/0.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1061430313
Short name	T849
Test name
Test status
Simulation time	1229392949 ps
CPU time	100.73 seconds
Started	Jan 10 12:42:03 PM PST 24
Finished	Jan 10 12:44:57 PM PST 24
Peak memory	204632 kb
Host	smart-c0f0d74d-0ef1-4b15-b0dd-42af1090823e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1061430313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.1061430313
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.1422902534
Short name	T192
Test name
Test status
Simulation time	195160113 ps
CPU time	4.17 seconds
Started	Jan 10 12:42:07 PM PST 24
Finished	Jan 10 12:43:24 PM PST 24
Peak memory	201696 kb
Host	smart-d29cb4f7-c14b-4944-992c-c37981bfe4a6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1422902534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1422902534
Directory	/workspace/0.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device.428873902
Short name	T65
Test name
Test status
Simulation time	69792646 ps
CPU time	15.06 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:43:37 PM PST 24
Peak memory	201724 kb
Host	smart-a07ddd40-ad35-4b3b-85f4-b0672011aa7e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=428873902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.428873902
Directory	/workspace/1.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.851173660
Short name	T252
Test name
Test status
Simulation time	998014952 ps
CPU time	9.31 seconds
Started	Jan 10 12:42:10 PM PST 24
Finished	Jan 10 12:43:32 PM PST 24
Peak memory	201752 kb
Host	smart-b49fbec6-43d6-4e94-8e79-7765384877cb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=851173660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.851173660
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_random.3817556081
Short name	T157
Test name
Test status
Simulation time	1228311038 ps
CPU time	10.02 seconds
Started	Jan 10 12:42:06 PM PST 24
Finished	Jan 10 12:43:29 PM PST 24
Peak memory	201744 kb
Host	smart-bcd23fcc-e7ef-41d8-b80c-f40b04e81315
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3817556081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3817556081
Directory	/workspace/1.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random.4070112547
Short name	T643
Test name
Test status
Simulation time	131138287 ps
CPU time	2.28 seconds
Started	Jan 10 12:42:12 PM PST 24
Finished	Jan 10 12:43:27 PM PST 24
Peak memory	201620 kb
Host	smart-89b54cfb-8b3d-450d-8f3a-a15f66e964e2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4070112547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.4070112547
Directory	/workspace/1.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2098972720
Short name	T131
Test name
Test status
Simulation time	9938460867 ps
CPU time	47.63 seconds
Started	Jan 10 12:42:06 PM PST 24
Finished	Jan 10 12:44:07 PM PST 24
Peak memory	201696 kb
Host	smart-8e6487ad-4c7e-4e1c-ba19-150023ca561c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098972720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2098972720
Directory	/workspace/1.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1144077850
Short name	T26
Test name
Test status
Simulation time	31241933046 ps
CPU time	101.54 seconds
Started	Jan 10 12:42:13 PM PST 24
Finished	Jan 10 12:45:07 PM PST 24
Peak memory	201668 kb
Host	smart-913afd99-6100-4fdf-8c8a-c35a77b9b84e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1144077850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1144077850
Directory	/workspace/1.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3798281190
Short name	T702
Test name
Test status
Simulation time	60701442 ps
CPU time	6.72 seconds
Started	Jan 10 12:42:06 PM PST 24
Finished	Jan 10 12:43:26 PM PST 24
Peak memory	201636 kb
Host	smart-0a3835d6-6e7a-45b3-8bb2-8178f0ab2c1e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798281190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3798281190
Directory	/workspace/1.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_same_source.4185781330
Short name	T23
Test name
Test status
Simulation time	974230842 ps
CPU time	8.79 seconds
Started	Jan 10 12:42:06 PM PST 24
Finished	Jan 10 12:43:29 PM PST 24
Peak memory	201672 kb
Host	smart-608e14d6-eda0-46ef-b865-ece51ad874b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4185781330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4185781330
Directory	/workspace/1.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke.330723915
Short name	T146
Test name
Test status
Simulation time	36077703 ps
CPU time	1.32 seconds
Started	Jan 10 12:42:06 PM PST 24
Finished	Jan 10 12:43:20 PM PST 24
Peak memory	201584 kb
Host	smart-35be0deb-0d30-428d-b3ad-44d3b59a9c52
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=330723915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.330723915
Directory	/workspace/1.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.8953932
Short name	T767
Test name
Test status
Simulation time	7834054449 ps
CPU time	7.25 seconds
Started	Jan 10 12:42:06 PM PST 24
Finished	Jan 10 12:43:26 PM PST 24
Peak memory	201820 kb
Host	smart-7de91a47-fee7-4de2-87df-23421100988a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=8953932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.8953932
Directory	/workspace/1.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3861823292
Short name	T635
Test name
Test status
Simulation time	2123769863 ps
CPU time	5.73 seconds
Started	Jan 10 12:42:06 PM PST 24
Finished	Jan 10 12:43:25 PM PST 24
Peak memory	201676 kb
Host	smart-511fdf0d-1476-47e2-bb49-b40db4f5470a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3861823292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3861823292
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2851772303
Short name	T412
Test name
Test status
Simulation time	13116247 ps
CPU time	1.1 seconds
Started	Jan 10 12:42:15 PM PST 24
Finished	Jan 10 12:43:28 PM PST 24
Peak memory	201712 kb
Host	smart-c2aab9e8-b21a-44ae-9703-9393bf323070
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851772303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2851772303
Directory	/workspace/1.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all.2570310368
Short name	T388
Test name
Test status
Simulation time	2665952759 ps
CPU time	62.61 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:44:25 PM PST 24
Peak memory	202808 kb
Host	smart-e271e6e8-96f5-4540-8294-6af0a3ce7f38
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2570310368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2570310368
Directory	/workspace/1.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2135718796
Short name	T509
Test name
Test status
Simulation time	15189808910 ps
CPU time	96.43 seconds
Started	Jan 10 12:42:07 PM PST 24
Finished	Jan 10 12:44:57 PM PST 24
Peak memory	203456 kb
Host	smart-4573c82c-c650-4016-bafe-2090e3b9dd6c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2135718796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2135718796
Directory	/workspace/1.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.4275522096
Short name	T118
Test name
Test status
Simulation time	756067454 ps
CPU time	66.51 seconds
Started	Jan 10 12:42:06 PM PST 24
Finished	Jan 10 12:44:26 PM PST 24
Peak memory	204408 kb
Host	smart-76f35a27-8022-4e51-acdf-c343fdc3eb80
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4275522096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.4275522096
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.233541868
Short name	T393
Test name
Test status
Simulation time	300931056 ps
CPU time	21.03 seconds
Started	Jan 10 12:42:08 PM PST 24
Finished	Jan 10 12:43:43 PM PST 24
Peak memory	201736 kb
Host	smart-6191163f-5a71-4b9e-89c9-399613c98dad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=233541868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese t_error.233541868
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2666199218
Short name	T838
Test name
Test status
Simulation time	513895371 ps
CPU time	11.71 seconds
Started	Jan 10 12:42:08 PM PST 24
Finished	Jan 10 12:43:33 PM PST 24
Peak memory	201716 kb
Host	smart-51c4599e-71a7-457e-a268-919454355757
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2666199218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2666199218
Directory	/workspace/1.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3172554409
Short name	T552
Test name
Test status
Simulation time	12955920 ps
CPU time	1.93 seconds
Started	Jan 10 12:42:23 PM PST 24
Finished	Jan 10 12:43:41 PM PST 24
Peak memory	201732 kb
Host	smart-4ea25660-a073-4439-8f26-422e469c5edc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3172554409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3172554409
Directory	/workspace/10.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1991677501
Short name	T132
Test name
Test status
Simulation time	58121153481 ps
CPU time	51.37 seconds
Started	Jan 10 12:42:28 PM PST 24
Finished	Jan 10 12:44:32 PM PST 24
Peak memory	201756 kb
Host	smart-69895831-43a3-4083-a22d-82cb8b8072ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1991677501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.1991677501
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2115517652
Short name	T467
Test name
Test status
Simulation time	459236290 ps
CPU time	7.68 seconds
Started	Jan 10 12:42:24 PM PST 24
Finished	Jan 10 12:43:45 PM PST 24
Peak memory	201584 kb
Host	smart-0bd126a4-4f76-4aeb-adfa-4e202247e347
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2115517652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2115517652
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_random.1307899743
Short name	T746
Test name
Test status
Simulation time	1638837825 ps
CPU time	6.94 seconds
Started	Jan 10 12:42:27 PM PST 24
Finished	Jan 10 12:43:47 PM PST 24
Peak memory	201632 kb
Host	smart-96439d58-5afd-4d01-bedd-60d7e5a63aa7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1307899743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1307899743
Directory	/workspace/10.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3395710763
Short name	T576
Test name
Test status
Simulation time	45357563917 ps
CPU time	141.31 seconds
Started	Jan 10 12:42:33 PM PST 24
Finished	Jan 10 12:46:08 PM PST 24
Peak memory	201680 kb
Host	smart-b9e7b551-5830-4764-a5f3-6b9ed341d8f8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395710763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3395710763
Directory	/workspace/10.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.848542466
Short name	T296
Test name
Test status
Simulation time	11969253081 ps
CPU time	84.38 seconds
Started	Jan 10 12:42:20 PM PST 24
Finished	Jan 10 12:44:58 PM PST 24
Peak memory	201572 kb
Host	smart-e24df5f2-9a89-47e4-926e-aac1c19a2e1e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=848542466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.848542466
Directory	/workspace/10.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3122383515
Short name	T367
Test name
Test status
Simulation time	34716574 ps
CPU time	2.7 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:43:52 PM PST 24
Peak memory	201544 kb
Host	smart-5c652b75-7319-41ee-ab18-a7d9b59e484f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122383515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3122383515
Directory	/workspace/10.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_same_source.2292249493
Short name	T561
Test name
Test status
Simulation time	1380181141 ps
CPU time	13.54 seconds
Started	Jan 10 12:42:20 PM PST 24
Finished	Jan 10 12:43:50 PM PST 24
Peak memory	201632 kb
Host	smart-215e6e15-ca0a-4bbb-9d45-ffb463ff9a6b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2292249493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2292249493
Directory	/workspace/10.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke.3929980106
Short name	T207
Test name
Test status
Simulation time	8417917 ps
CPU time	1.11 seconds
Started	Jan 10 12:42:33 PM PST 24
Finished	Jan 10 12:43:47 PM PST 24
Peak memory	201568 kb
Host	smart-fbc51ff5-b785-4272-8a89-42bea963e850
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3929980106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3929980106
Directory	/workspace/10.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2654929313
Short name	T669
Test name
Test status
Simulation time	1917593958 ps
CPU time	8.69 seconds
Started	Jan 10 12:42:28 PM PST 24
Finished	Jan 10 12:43:49 PM PST 24
Peak memory	201680 kb
Host	smart-35fe2725-aa28-48f3-88d5-217aea9221a1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654929313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2654929313
Directory	/workspace/10.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.263182195
Short name	T338
Test name
Test status
Simulation time	3977801830 ps
CPU time	7.23 seconds
Started	Jan 10 12:42:20 PM PST 24
Finished	Jan 10 12:43:41 PM PST 24
Peak memory	201824 kb
Host	smart-41a4c30a-566b-4bc2-b2e1-fad33777e259
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=263182195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.263182195
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1638768400
Short name	T544
Test name
Test status
Simulation time	9139250 ps
CPU time	1.15 seconds
Started	Jan 10 12:42:28 PM PST 24
Finished	Jan 10 12:43:45 PM PST 24
Peak memory	201672 kb
Host	smart-39a6b2e6-b460-4297-adc3-1671047c4aae
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638768400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1638768400
Directory	/workspace/10.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all.1606514378
Short name	T717
Test name
Test status
Simulation time	3580170428 ps
CPU time	75.79 seconds
Started	Jan 10 12:42:35 PM PST 24
Finished	Jan 10 12:45:05 PM PST 24
Peak memory	204404 kb
Host	smart-ba57fe04-4ef9-495d-a41a-ff1b34012052
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1606514378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1606514378
Directory	/workspace/10.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3491538886
Short name	T293
Test name
Test status
Simulation time	283102843 ps
CPU time	15.12 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:44:05 PM PST 24
Peak memory	201552 kb
Host	smart-d8fcc1d5-c8a8-4963-9ef2-13500ff20b77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3491538886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3491538886
Directory	/workspace/10.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3262896000
Short name	T500
Test name
Test status
Simulation time	30299766 ps
CPU time	11.51 seconds
Started	Jan 10 12:42:24 PM PST 24
Finished	Jan 10 12:43:49 PM PST 24
Peak memory	201604 kb
Host	smart-34c55ae6-4f90-4569-b4c0-d01492a99f47
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3262896000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.3262896000
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.595547958
Short name	T12
Test name
Test status
Simulation time	9295386483 ps
CPU time	141.67 seconds
Started	Jan 10 12:42:33 PM PST 24
Finished	Jan 10 12:46:08 PM PST 24
Peak memory	205764 kb
Host	smart-476d90a5-aab8-43e8-99ea-876c5e563e44
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=595547958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_res et_error.595547958
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.456197526
Short name	T290
Test name
Test status
Simulation time	214687663 ps
CPU time	6.89 seconds
Started	Jan 10 12:42:24 PM PST 24
Finished	Jan 10 12:43:53 PM PST 24
Peak memory	201592 kb
Host	smart-60cdb851-6c05-45a8-9990-47e7ee1df948
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=456197526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.456197526
Directory	/workspace/10.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device.2828218602
Short name	T803
Test name
Test status
Simulation time	164377552 ps
CPU time	5.23 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:43:55 PM PST 24
Peak memory	200748 kb
Host	smart-164ce915-e88f-4bdf-a96e-af52a9f67780
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2828218602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2828218602
Directory	/workspace/11.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.303947954
Short name	T76
Test name
Test status
Simulation time	80027919409 ps
CPU time	300.72 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:48:50 PM PST 24
Peak memory	202956 kb
Host	smart-ee439ff2-946a-4f4d-a657-9fe50faba11d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=303947954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo w_rsp.303947954
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1906528573
Short name	T784
Test name
Test status
Simulation time	882359780 ps
CPU time	9.05 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:43:59 PM PST 24
Peak memory	201608 kb
Host	smart-40e22bfe-b9b6-4604-85ff-54f8c522de7d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1906528573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1906528573
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_random.1518946040
Short name	T514
Test name
Test status
Simulation time	372380342 ps
CPU time	4.16 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:43:36 PM PST 24
Peak memory	201708 kb
Host	smart-875620e4-4d9e-47ab-99c9-65b2bff473bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1518946040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1518946040
Directory	/workspace/11.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random.1034530478
Short name	T300
Test name
Test status
Simulation time	2254252303 ps
CPU time	10.88 seconds
Started	Jan 10 12:42:22 PM PST 24
Finished	Jan 10 12:43:49 PM PST 24
Peak memory	201644 kb
Host	smart-1e15c6e8-191b-49f6-b2ad-f2a46e41e254
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1034530478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1034530478
Directory	/workspace/11.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.4275210933
Short name	T524
Test name
Test status
Simulation time	43509991303 ps
CPU time	142.18 seconds
Started	Jan 10 12:42:37 PM PST 24
Finished	Jan 10 12:46:16 PM PST 24
Peak memory	201688 kb
Host	smart-0cb14569-84da-4413-a3af-bfeef7cb4583
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275210933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.4275210933
Directory	/workspace/11.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1391418605
Short name	T900
Test name
Test status
Simulation time	1679046263 ps
CPU time	6.07 seconds
Started	Jan 10 12:42:35 PM PST 24
Finished	Jan 10 12:43:55 PM PST 24
Peak memory	201568 kb
Host	smart-848889c5-91a0-4a4d-b1af-8b7fd9f87ad6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1391418605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1391418605
Directory	/workspace/11.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.12048143
Short name	T91
Test name
Test status
Simulation time	11204598 ps
CPU time	1.39 seconds
Started	Jan 10 12:42:33 PM PST 24
Finished	Jan 10 12:43:48 PM PST 24
Peak memory	201736 kb
Host	smart-26b27f1a-a95f-461c-9e27-e4cdf2066035
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12048143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.12048143
Directory	/workspace/11.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_same_source.1718756001
Short name	T263
Test name
Test status
Simulation time	15359714 ps
CPU time	1.58 seconds
Started	Jan 10 12:42:37 PM PST 24
Finished	Jan 10 12:43:53 PM PST 24
Peak memory	201720 kb
Host	smart-dc8a6d8f-f94e-431e-8d09-8d780e9860cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1718756001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1718756001
Directory	/workspace/11.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke.2030757904
Short name	T654
Test name
Test status
Simulation time	48613533 ps
CPU time	1.39 seconds
Started	Jan 10 12:42:24 PM PST 24
Finished	Jan 10 12:43:38 PM PST 24
Peak memory	201576 kb
Host	smart-a3eb4c04-7679-4985-93d8-fbfae93f232d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2030757904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2030757904
Directory	/workspace/11.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3896455411
Short name	T57
Test name
Test status
Simulation time	13935409106 ps
CPU time	8.27 seconds
Started	Jan 10 12:42:32 PM PST 24
Finished	Jan 10 12:43:54 PM PST 24
Peak memory	201680 kb
Host	smart-01df17e6-e7cb-4517-a06b-0dc0156bdfba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896455411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3896455411
Directory	/workspace/11.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2757436617
Short name	T794
Test name
Test status
Simulation time	1746832980 ps
CPU time	12.01 seconds
Started	Jan 10 12:42:33 PM PST 24
Finished	Jan 10 12:43:58 PM PST 24
Peak memory	201736 kb
Host	smart-dc443397-b4f6-458f-9d39-de2eb1b2ed54
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2757436617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2757436617
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.652751441
Short name	T352
Test name
Test status
Simulation time	11111274 ps
CPU time	0.98 seconds
Started	Jan 10 12:42:33 PM PST 24
Finished	Jan 10 12:43:48 PM PST 24
Peak memory	201728 kb
Host	smart-940c6994-ab82-4610-8dc3-8c7b90e676a7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652751441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.652751441
Directory	/workspace/11.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all.4068032571
Short name	T260
Test name
Test status
Simulation time	2934121276 ps
CPU time	23.64 seconds
Started	Jan 10 12:42:33 PM PST 24
Finished	Jan 10 12:44:10 PM PST 24
Peak memory	201812 kb
Host	smart-36914109-56bf-4bea-bfeb-ad1a202fd95c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4068032571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.4068032571
Directory	/workspace/11.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1110196829
Short name	T313
Test name
Test status
Simulation time	16175439 ps
CPU time	0.95 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:43:55 PM PST 24
Peak memory	201672 kb
Host	smart-4230adca-d37e-4aa4-8ff2-19be7be4912a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1110196829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1110196829
Directory	/workspace/11.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.928336208
Short name	T401
Test name
Test status
Simulation time	160914598 ps
CPU time	33.88 seconds
Started	Jan 10 12:42:39 PM PST 24
Finished	Jan 10 12:44:27 PM PST 24
Peak memory	202664 kb
Host	smart-c6ddc5ce-6032-41ea-b8de-2a283a441bb4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=928336208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_res et_error.928336208
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1334492148
Short name	T373
Test name
Test status
Simulation time	36287427 ps
CPU time	2.04 seconds
Started	Jan 10 12:42:37 PM PST 24
Finished	Jan 10 12:43:56 PM PST 24
Peak memory	201720 kb
Host	smart-7497bf35-99e0-4286-9bbe-e916764b7a5d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1334492148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1334492148
Directory	/workspace/11.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device.693762733
Short name	T297
Test name
Test status
Simulation time	1355717138 ps
CPU time	14.48 seconds
Started	Jan 10 12:42:46 PM PST 24
Finished	Jan 10 12:44:14 PM PST 24
Peak memory	201508 kb
Host	smart-3f7b8de8-5e90-4375-a0a8-78a286a40a29
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=693762733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.693762733
Directory	/workspace/12.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.4166286702
Short name	T329
Test name
Test status
Simulation time	325820074 ps
CPU time	3.88 seconds
Started	Jan 10 12:42:35 PM PST 24
Finished	Jan 10 12:43:53 PM PST 24
Peak memory	201716 kb
Host	smart-293bb0a0-1239-4dc9-9253-f6a226cefab9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4166286702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.4166286702
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_random.2546435157
Short name	T327
Test name
Test status
Simulation time	435174902 ps
CPU time	6.35 seconds
Started	Jan 10 12:42:31 PM PST 24
Finished	Jan 10 12:44:00 PM PST 24
Peak memory	201708 kb
Host	smart-67b46736-22fc-40f4-89dc-a0fe0eb71fa8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2546435157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2546435157
Directory	/workspace/12.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random.3030321498
Short name	T287
Test name
Test status
Simulation time	2602477050 ps
CPU time	15.21 seconds
Started	Jan 10 12:42:45 PM PST 24
Finished	Jan 10 12:44:14 PM PST 24
Peak memory	201584 kb
Host	smart-3b53e1d4-36db-4d94-8f23-ee36bbf2bd71
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3030321498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3030321498
Directory	/workspace/12.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3296420556
Short name	T441
Test name
Test status
Simulation time	140641582757 ps
CPU time	147.94 seconds
Started	Jan 10 12:42:30 PM PST 24
Finished	Jan 10 12:46:11 PM PST 24
Peak memory	201560 kb
Host	smart-7788dbd0-ee4d-47df-a534-8217347f55d7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296420556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3296420556
Directory	/workspace/12.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3090289304
Short name	T714
Test name
Test status
Simulation time	9685833386 ps
CPU time	64.4 seconds
Started	Jan 10 12:42:39 PM PST 24
Finished	Jan 10 12:44:58 PM PST 24
Peak memory	201648 kb
Host	smart-42d61cf5-6d8d-402c-bb8f-6cf6d1726e28
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3090289304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3090289304
Directory	/workspace/12.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.700631467
Short name	T718
Test name
Test status
Simulation time	60423868 ps
CPU time	6.17 seconds
Started	Jan 10 12:42:31 PM PST 24
Finished	Jan 10 12:44:00 PM PST 24
Peak memory	201660 kb
Host	smart-4e50cdb0-0a3e-4eb0-9238-3eeb00ce4469
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700631467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.700631467
Directory	/workspace/12.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_same_source.1734668545
Short name	T475
Test name
Test status
Simulation time	1097259002 ps
CPU time	9.53 seconds
Started	Jan 10 12:42:30 PM PST 24
Finished	Jan 10 12:43:52 PM PST 24
Peak memory	201732 kb
Host	smart-e9b285b3-df6c-4f4a-a975-2cad84823bbd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1734668545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1734668545
Directory	/workspace/12.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke.1688147780
Short name	T689
Test name
Test status
Simulation time	11183521 ps
CPU time	1.07 seconds
Started	Jan 10 12:42:39 PM PST 24
Finished	Jan 10 12:43:54 PM PST 24
Peak memory	201568 kb
Host	smart-3ae4e704-9974-4230-9d1f-3bcd5e665b64
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1688147780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1688147780
Directory	/workspace/12.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2045952613
Short name	T621
Test name
Test status
Simulation time	5312508346 ps
CPU time	9.74 seconds
Started	Jan 10 12:42:29 PM PST 24
Finished	Jan 10 12:43:52 PM PST 24
Peak memory	201708 kb
Host	smart-a88ae0d6-f7a5-4e36-8543-d37a0cbcd6fc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045952613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2045952613
Directory	/workspace/12.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2664009265
Short name	T824
Test name
Test status
Simulation time	906176077 ps
CPU time	5.79 seconds
Started	Jan 10 12:42:34 PM PST 24
Finished	Jan 10 12:43:53 PM PST 24
Peak memory	201676 kb
Host	smart-3f706e59-1b81-4056-b0ab-058c7126f0e3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2664009265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2664009265
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.914754111
Short name	T315
Test name
Test status
Simulation time	8223395 ps
CPU time	1.02 seconds
Started	Jan 10 12:42:39 PM PST 24
Finished	Jan 10 12:43:54 PM PST 24
Peak memory	201724 kb
Host	smart-8de20567-2395-417b-be6a-9096e42ec395
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914754111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.914754111
Directory	/workspace/12.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all.2966950363
Short name	T684
Test name
Test status
Simulation time	1156834319 ps
CPU time	13.79 seconds
Started	Jan 10 12:42:40 PM PST 24
Finished	Jan 10 12:44:08 PM PST 24
Peak memory	201744 kb
Host	smart-542885d4-f63a-4c50-99c7-cb4e66430684
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2966950363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2966950363
Directory	/workspace/12.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2684068186
Short name	T693
Test name
Test status
Simulation time	6491022081 ps
CPU time	56.52 seconds
Started	Jan 10 12:42:39 PM PST 24
Finished	Jan 10 12:44:50 PM PST 24
Peak memory	203700 kb
Host	smart-23ebdc8b-811f-4064-82ad-e24a300459c9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2684068186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2684068186
Directory	/workspace/12.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.923636946
Short name	T82
Test name
Test status
Simulation time	3889820809 ps
CPU time	108.59 seconds
Started	Jan 10 12:42:32 PM PST 24
Finished	Jan 10 12:45:34 PM PST 24
Peak memory	204140 kb
Host	smart-f8402d3e-442f-413d-ad14-dc3aa3b3a733
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=923636946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand _reset.923636946
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.566055462
Short name	T710
Test name
Test status
Simulation time	2784003823 ps
CPU time	90.47 seconds
Started	Jan 10 12:42:30 PM PST 24
Finished	Jan 10 12:45:14 PM PST 24
Peak memory	204760 kb
Host	smart-8b7fdc65-6a02-4ceb-a2db-6ebdc7efb472
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=566055462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_res et_error.566055462
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.39865128
Short name	T852
Test name
Test status
Simulation time	2753921393 ps
CPU time	9.41 seconds
Started	Jan 10 12:42:44 PM PST 24
Finished	Jan 10 12:44:07 PM PST 24
Peak memory	201604 kb
Host	smart-3daf3c0d-47fb-47f2-8171-d32ac7810f7e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=39865128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.39865128
Directory	/workspace/12.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device.4175642507
Short name	T267
Test name
Test status
Simulation time	50022276 ps
CPU time	5.28 seconds
Started	Jan 10 12:42:44 PM PST 24
Finished	Jan 10 12:44:04 PM PST 24
Peak memory	201724 kb
Host	smart-4eb26c45-3c0a-4145-8e4e-0a802d3e95f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4175642507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.4175642507
Directory	/workspace/13.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1837287177
Short name	T235
Test name
Test status
Simulation time	18204968403 ps
CPU time	114.94 seconds
Started	Jan 10 12:42:40 PM PST 24
Finished	Jan 10 12:45:50 PM PST 24
Peak memory	201820 kb
Host	smart-bfa186a4-f82a-43fa-a651-245baa930cda
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1837287177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.1837287177
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1917297509
Short name	T486
Test name
Test status
Simulation time	99597386 ps
CPU time	1.24 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:43:51 PM PST 24
Peak memory	201716 kb
Host	smart-bc79aa2c-b019-408f-afc5-901b764ccaeb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1917297509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1917297509
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_random.3641483066
Short name	T250
Test name
Test status
Simulation time	31530395 ps
CPU time	1.9 seconds
Started	Jan 10 12:42:31 PM PST 24
Finished	Jan 10 12:43:55 PM PST 24
Peak memory	201644 kb
Host	smart-571acd94-b2dc-4799-bb6c-d1d8388a7a5a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3641483066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3641483066
Directory	/workspace/13.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random.3539761526
Short name	T636
Test name
Test status
Simulation time	147098312 ps
CPU time	5.5 seconds
Started	Jan 10 12:42:31 PM PST 24
Finished	Jan 10 12:43:59 PM PST 24
Peak memory	201712 kb
Host	smart-3a4ea7b1-afe0-4891-abd9-bf30a114049d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3539761526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3539761526
Directory	/workspace/13.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3442761786
Short name	T461
Test name
Test status
Simulation time	15386083252 ps
CPU time	14.88 seconds
Started	Jan 10 12:42:33 PM PST 24
Finished	Jan 10 12:44:01 PM PST 24
Peak memory	201624 kb
Host	smart-e2ba1fe9-67b4-4e47-ac8d-678346483913
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442761786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3442761786
Directory	/workspace/13.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2968209087
Short name	T606
Test name
Test status
Simulation time	10160004080 ps
CPU time	22.85 seconds
Started	Jan 10 12:42:44 PM PST 24
Finished	Jan 10 12:44:21 PM PST 24
Peak memory	201592 kb
Host	smart-f4d7f7f8-3a66-44cf-bc4a-c506f7c0e968
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2968209087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2968209087
Directory	/workspace/13.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.2447279314
Short name	T677
Test name
Test status
Simulation time	141469259 ps
CPU time	8.39 seconds
Started	Jan 10 12:42:35 PM PST 24
Finished	Jan 10 12:43:57 PM PST 24
Peak memory	201720 kb
Host	smart-7c113630-ad49-4e5d-8a3c-1a70205fe9ea
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447279314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2447279314
Directory	/workspace/13.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_same_source.2970086584
Short name	T579
Test name
Test status
Simulation time	1085136168 ps
CPU time	7.8 seconds
Started	Jan 10 12:42:41 PM PST 24
Finished	Jan 10 12:44:03 PM PST 24
Peak memory	201720 kb
Host	smart-af9c12f8-1112-40be-ad23-1ec614600730
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2970086584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2970086584
Directory	/workspace/13.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke.1115350666
Short name	T672
Test name
Test status
Simulation time	148054987 ps
CPU time	1.6 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:43:55 PM PST 24
Peak memory	201712 kb
Host	smart-35ccc58a-f7d6-4f58-a3e7-7e179befd56b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1115350666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1115350666
Directory	/workspace/13.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2894154960
Short name	T85
Test name
Test status
Simulation time	2153012114 ps
CPU time	6.83 seconds
Started	Jan 10 12:42:35 PM PST 24
Finished	Jan 10 12:43:56 PM PST 24
Peak memory	201704 kb
Host	smart-afc5fa25-c175-46a9-bf67-5546a8c4a19d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894154960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2894154960
Directory	/workspace/13.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.4249874495
Short name	T512
Test name
Test status
Simulation time	1225598983 ps
CPU time	8.44 seconds
Started	Jan 10 12:42:45 PM PST 24
Finished	Jan 10 12:44:07 PM PST 24
Peak memory	201532 kb
Host	smart-5e69f790-f909-4f5b-98fc-44e89130177f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4249874495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.4249874495
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.339161857
Short name	T481
Test name
Test status
Simulation time	9019135 ps
CPU time	1.2 seconds
Started	Jan 10 12:42:45 PM PST 24
Finished	Jan 10 12:44:00 PM PST 24
Peak memory	201524 kb
Host	smart-b27245d2-ffc5-47e9-b0f6-64852fc80c44
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339161857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.339161857
Directory	/workspace/13.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all.7016034
Short name	T765
Test name
Test status
Simulation time	57363857957 ps
CPU time	119.32 seconds
Started	Jan 10 12:42:39 PM PST 24
Finished	Jan 10 12:45:52 PM PST 24
Peak memory	204144 kb
Host	smart-cc43db15-1312-4e3d-a3d5-79637b9e596c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=7016034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.7016034
Directory	/workspace/13.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3594062537
Short name	T858
Test name
Test status
Simulation time	23774796990 ps
CPU time	81.28 seconds
Started	Jan 10 12:42:33 PM PST 24
Finished	Jan 10 12:45:08 PM PST 24
Peak memory	204104 kb
Host	smart-ba708839-1d67-4ddc-a343-1832d57959b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3594062537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3594062537
Directory	/workspace/13.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3084797936
Short name	T589
Test name
Test status
Simulation time	153557479 ps
CPU time	20.2 seconds
Started	Jan 10 12:42:30 PM PST 24
Finished	Jan 10 12:44:04 PM PST 24
Peak memory	202660 kb
Host	smart-4ee36080-dbaf-4145-89aa-abbd77cdcda3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3084797936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.3084797936
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3922966774
Short name	T246
Test name
Test status
Simulation time	174544249 ps
CPU time	36.15 seconds
Started	Jan 10 12:42:37 PM PST 24
Finished	Jan 10 12:44:28 PM PST 24
Peak memory	202872 kb
Host	smart-e4fd88e2-e506-473e-8059-d3c52fabe5d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3922966774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.3922966774
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3736870867
Short name	T302
Test name
Test status
Simulation time	71708553 ps
CPU time	1.61 seconds
Started	Jan 10 12:42:37 PM PST 24
Finished	Jan 10 12:43:55 PM PST 24
Peak memory	201580 kb
Host	smart-a8146c3e-e9ab-4960-8bfd-923f451bf372
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3736870867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3736870867
Directory	/workspace/13.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device.703041158
Short name	T724
Test name
Test status
Simulation time	821051972 ps
CPU time	3.85 seconds
Started	Jan 10 12:42:30 PM PST 24
Finished	Jan 10 12:43:47 PM PST 24
Peak memory	201732 kb
Host	smart-092c4e13-e52b-435b-8fef-8028e686b143
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=703041158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.703041158
Directory	/workspace/14.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1492717369
Short name	T215
Test name
Test status
Simulation time	61594757583 ps
CPU time	261.08 seconds
Started	Jan 10 12:42:45 PM PST 24
Finished	Jan 10 12:48:20 PM PST 24
Peak memory	202616 kb
Host	smart-b8ce9a18-b7db-472e-95d8-a53d5ef6f4cf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1492717369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1492717369
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1828027972
Short name	T372
Test name
Test status
Simulation time	439537550 ps
CPU time	7.1 seconds
Started	Jan 10 12:42:35 PM PST 24
Finished	Jan 10 12:43:56 PM PST 24
Peak memory	201628 kb
Host	smart-2ed7c4c0-e398-4f54-a116-e42c60d9d897
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1828027972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1828027972
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_random.951464217
Short name	T658
Test name
Test status
Simulation time	77694334 ps
CPU time	6.68 seconds
Started	Jan 10 12:42:38 PM PST 24
Finished	Jan 10 12:43:59 PM PST 24
Peak memory	201704 kb
Host	smart-141d6e9a-d399-401d-9864-0a207e7731d0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=951464217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.951464217
Directory	/workspace/14.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random.910522191
Short name	T532
Test name
Test status
Simulation time	25610399 ps
CPU time	2.64 seconds
Started	Jan 10 12:42:35 PM PST 24
Finished	Jan 10 12:43:51 PM PST 24
Peak memory	201612 kb
Host	smart-0656ae9f-138d-4392-bf56-1eca02d8cd7d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=910522191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.910522191
Directory	/workspace/14.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.1552496409
Short name	T32
Test name
Test status
Simulation time	30023912791 ps
CPU time	94 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:45:24 PM PST 24
Peak memory	202012 kb
Host	smart-9a924204-8f35-4734-b724-2b3d67639d7f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552496409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1552496409
Directory	/workspace/14.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.987843577
Short name	T138
Test name
Test status
Simulation time	7807078255 ps
CPU time	49.4 seconds
Started	Jan 10 12:42:31 PM PST 24
Finished	Jan 10 12:44:43 PM PST 24
Peak memory	201792 kb
Host	smart-e5d58cbb-3cee-43b3-b165-102b3c1a555c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=987843577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.987843577
Directory	/workspace/14.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.3161672824
Short name	T659
Test name
Test status
Simulation time	159720938 ps
CPU time	7.66 seconds
Started	Jan 10 12:42:31 PM PST 24
Finished	Jan 10 12:43:55 PM PST 24
Peak memory	201600 kb
Host	smart-b770a6a3-9d3a-4964-97c3-d2b1c86c90f5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161672824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3161672824
Directory	/workspace/14.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_same_source.3074851647
Short name	T462
Test name
Test status
Simulation time	57041849 ps
CPU time	4.28 seconds
Started	Jan 10 12:42:34 PM PST 24
Finished	Jan 10 12:43:52 PM PST 24
Peak memory	201632 kb
Host	smart-ca662856-4672-45a0-8372-943979cb3a48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3074851647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3074851647
Directory	/workspace/14.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke.3319859247
Short name	T288
Test name
Test status
Simulation time	288781963 ps
CPU time	1.61 seconds
Started	Jan 10 12:42:46 PM PST 24
Finished	Jan 10 12:44:00 PM PST 24
Peak memory	201508 kb
Host	smart-1cec2765-186e-41ff-87a4-37e1f95de89e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3319859247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3319859247
Directory	/workspace/14.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2560609899
Short name	T487
Test name
Test status
Simulation time	3619793977 ps
CPU time	9.6 seconds
Started	Jan 10 12:42:30 PM PST 24
Finished	Jan 10 12:43:53 PM PST 24
Peak memory	201748 kb
Host	smart-c521c49e-85ff-45c9-86bc-2557efd2e8e3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560609899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2560609899
Directory	/workspace/14.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.1003734821
Short name	T690
Test name
Test status
Simulation time	2521862295 ps
CPU time	4.85 seconds
Started	Jan 10 12:42:44 PM PST 24
Finished	Jan 10 12:44:03 PM PST 24
Peak memory	201592 kb
Host	smart-de3237b1-c3d6-4ece-91e0-ad418d4c1e59
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1003734821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1003734821
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.684511135
Short name	T314
Test name
Test status
Simulation time	11622777 ps
CPU time	1.25 seconds
Started	Jan 10 12:42:32 PM PST 24
Finished	Jan 10 12:43:47 PM PST 24
Peak memory	201560 kb
Host	smart-83e9d688-8d90-4383-8a50-cb848b21cf70
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684511135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.684511135
Directory	/workspace/14.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all.332290245
Short name	T731
Test name
Test status
Simulation time	3699817862 ps
CPU time	35.12 seconds
Started	Jan 10 12:42:46 PM PST 24
Finished	Jan 10 12:44:34 PM PST 24
Peak memory	201664 kb
Host	smart-0127a21a-248d-48b9-90d4-e59ab2ffe994
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=332290245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.332290245
Directory	/workspace/14.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.681730888
Short name	T491
Test name
Test status
Simulation time	1532441133 ps
CPU time	33.11 seconds
Started	Jan 10 12:42:49 PM PST 24
Finished	Jan 10 12:44:36 PM PST 24
Peak memory	201672 kb
Host	smart-607639c9-7cbe-4672-b698-35271a246f7b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=681730888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.681730888
Directory	/workspace/14.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.81993031
Short name	T683
Test name
Test status
Simulation time	5821465197 ps
CPU time	116.34 seconds
Started	Jan 10 12:42:41 PM PST 24
Finished	Jan 10 12:45:52 PM PST 24
Peak memory	204516 kb
Host	smart-1b67b45f-237b-49bd-8259-6dc46cba568c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=81993031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_ reset.81993031
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.196555923
Short name	T4
Test name
Test status
Simulation time	238078911 ps
CPU time	3.19 seconds
Started	Jan 10 12:42:41 PM PST 24
Finished	Jan 10 12:43:58 PM PST 24
Peak memory	201476 kb
Host	smart-b5d2903b-a0fb-4c18-8fef-382f4b34edd7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=196555923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.196555923
Directory	/workspace/14.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3300813511
Short name	T46
Test name
Test status
Simulation time	97852256 ps
CPU time	7.5 seconds
Started	Jan 10 12:42:40 PM PST 24
Finished	Jan 10 12:44:02 PM PST 24
Peak memory	201692 kb
Host	smart-16946030-4ebe-44fe-bad4-f496a325db4f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3300813511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3300813511
Directory	/workspace/15.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1211749087
Short name	T225
Test name
Test status
Simulation time	6200081108 ps
CPU time	46.44 seconds
Started	Jan 10 12:42:41 PM PST 24
Finished	Jan 10 12:44:42 PM PST 24
Peak memory	201664 kb
Host	smart-54e66fb2-ff31-475c-9527-c2424d5b0197
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1211749087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.1211749087
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.140062872
Short name	T711
Test name
Test status
Simulation time	817079605 ps
CPU time	8.66 seconds
Started	Jan 10 12:42:44 PM PST 24
Finished	Jan 10 12:44:07 PM PST 24
Peak memory	201740 kb
Host	smart-684ea437-7b97-4d57-a43c-885061cbb14d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=140062872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.140062872
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_random.2403839701
Short name	T892
Test name
Test status
Simulation time	386783945 ps
CPU time	4.91 seconds
Started	Jan 10 12:42:39 PM PST 24
Finished	Jan 10 12:44:02 PM PST 24
Peak memory	201592 kb
Host	smart-d98dd2d3-314c-46aa-bb62-9aa7c8c4b115
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2403839701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2403839701
Directory	/workspace/15.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random.1939191248
Short name	T478
Test name
Test status
Simulation time	48991995 ps
CPU time	5.49 seconds
Started	Jan 10 12:42:45 PM PST 24
Finished	Jan 10 12:44:11 PM PST 24
Peak memory	201748 kb
Host	smart-5a0d580f-a961-40e1-aac8-82be86708f39
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1939191248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.1939191248
Directory	/workspace/15.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1057388200
Short name	T785
Test name
Test status
Simulation time	27445184205 ps
CPU time	103.91 seconds
Started	Jan 10 12:42:43 PM PST 24
Finished	Jan 10 12:45:41 PM PST 24
Peak memory	201676 kb
Host	smart-40244cde-bc49-46c6-a436-725f735efff7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057388200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1057388200
Directory	/workspace/15.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3191250271
Short name	T780
Test name
Test status
Simulation time	2030386084 ps
CPU time	13.8 seconds
Started	Jan 10 12:42:40 PM PST 24
Finished	Jan 10 12:44:08 PM PST 24
Peak memory	201712 kb
Host	smart-886a50cb-5761-4029-bf0e-aeda01fb8f1d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3191250271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3191250271
Directory	/workspace/15.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.386261595
Short name	T145
Test name
Test status
Simulation time	58636626 ps
CPU time	8.41 seconds
Started	Jan 10 12:42:40 PM PST 24
Finished	Jan 10 12:44:03 PM PST 24
Peak memory	201944 kb
Host	smart-734f8e7a-7b68-4fc8-b9eb-011ac78c6a16
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386261595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.386261595
Directory	/workspace/15.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_same_source.686226507
Short name	T766
Test name
Test status
Simulation time	312879765 ps
CPU time	4.03 seconds
Started	Jan 10 12:42:43 PM PST 24
Finished	Jan 10 12:44:02 PM PST 24
Peak memory	201736 kb
Host	smart-a2131cb2-f28b-45c0-82d1-2ef6d0d46676
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=686226507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.686226507
Directory	/workspace/15.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke.1510886689
Short name	T778
Test name
Test status
Simulation time	23810610 ps
CPU time	1.29 seconds
Started	Jan 10 12:42:50 PM PST 24
Finished	Jan 10 12:44:05 PM PST 24
Peak memory	201676 kb
Host	smart-7ff628d9-5019-4957-9bac-d2f344e245b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1510886689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1510886689
Directory	/workspace/15.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3824357530
Short name	T859
Test name
Test status
Simulation time	5780266587 ps
CPU time	11.2 seconds
Started	Jan 10 12:42:41 PM PST 24
Finished	Jan 10 12:44:07 PM PST 24
Peak memory	201624 kb
Host	smart-19664057-bc59-4472-bde1-8bbb722c9df8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824357530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3824357530
Directory	/workspace/15.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.1880211509
Short name	T271
Test name
Test status
Simulation time	1716549809 ps
CPU time	7.26 seconds
Started	Jan 10 12:42:39 PM PST 24
Finished	Jan 10 12:44:00 PM PST 24
Peak memory	201684 kb
Host	smart-81d3733a-5db2-4641-b8e1-5d4a89fc8c7a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1880211509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1880211509
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2714770429
Short name	T285
Test name
Test status
Simulation time	9313574 ps
CPU time	1.21 seconds
Started	Jan 10 12:42:47 PM PST 24
Finished	Jan 10 12:44:03 PM PST 24
Peak memory	201632 kb
Host	smart-904b5c92-6bbd-4673-95a2-090c17f446b3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714770429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2714770429
Directory	/workspace/15.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all.3804757866
Short name	T493
Test name
Test status
Simulation time	15340629 ps
CPU time	1.29 seconds
Started	Jan 10 12:42:42 PM PST 24
Finished	Jan 10 12:43:58 PM PST 24
Peak memory	201732 kb
Host	smart-063ff821-965b-4428-a9bc-de7878c69913
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3804757866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3804757866
Directory	/workspace/15.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.107225772
Short name	T563
Test name
Test status
Simulation time	1130631798 ps
CPU time	48.58 seconds
Started	Jan 10 12:42:41 PM PST 24
Finished	Jan 10 12:44:43 PM PST 24
Peak memory	203880 kb
Host	smart-8cd1bab9-57d3-4f73-bb28-8d86022e9e48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=107225772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.107225772
Directory	/workspace/15.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3378810948
Short name	T870
Test name
Test status
Simulation time	1878939984 ps
CPU time	35.09 seconds
Started	Jan 10 12:42:41 PM PST 24
Finished	Jan 10 12:44:30 PM PST 24
Peak memory	203704 kb
Host	smart-047c9fdf-e6d6-4ec0-b208-f21b30d7e882
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3378810948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3378810948
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.785197998
Short name	T748
Test name
Test status
Simulation time	907260653 ps
CPU time	11.56 seconds
Started	Jan 10 12:42:47 PM PST 24
Finished	Jan 10 12:44:13 PM PST 24
Peak memory	201680 kb
Host	smart-42771e68-6920-46e0-b536-8e9cbf507a9b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=785197998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.785197998
Directory	/workspace/15.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.4201447111
Short name	T480
Test name
Test status
Simulation time	17971277 ps
CPU time	2.36 seconds
Started	Jan 10 12:43:06 PM PST 24
Finished	Jan 10 12:44:21 PM PST 24
Peak memory	201700 kb
Host	smart-03129838-f361-4de5-a94d-5011ff676fdb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4201447111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.4201447111
Directory	/workspace/16.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1493470671
Short name	T823
Test name
Test status
Simulation time	732998595 ps
CPU time	10.57 seconds
Started	Jan 10 12:42:53 PM PST 24
Finished	Jan 10 12:44:17 PM PST 24
Peak memory	201696 kb
Host	smart-be1e9e45-fa04-42cd-b536-24d60345f122
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1493470671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1493470671
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_random.1811848898
Short name	T773
Test name
Test status
Simulation time	202997272 ps
CPU time	1.7 seconds
Started	Jan 10 12:42:54 PM PST 24
Finished	Jan 10 12:44:09 PM PST 24
Peak memory	201580 kb
Host	smart-3095bd4f-3ccc-46b1-b7b0-fd3c6e92b98c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1811848898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1811848898
Directory	/workspace/16.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random.1968062085
Short name	T28
Test name
Test status
Simulation time	756106938 ps
CPU time	2.91 seconds
Started	Jan 10 12:42:51 PM PST 24
Finished	Jan 10 12:44:07 PM PST 24
Peak memory	201724 kb
Host	smart-e29dc36a-2c90-4533-9933-e6aec2e4ef64
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1968062085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1968062085
Directory	/workspace/16.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.1197255878
Short name	T738
Test name
Test status
Simulation time	16128139645 ps
CPU time	32.99 seconds
Started	Jan 10 12:42:58 PM PST 24
Finished	Jan 10 12:44:45 PM PST 24
Peak memory	201788 kb
Host	smart-b232bb34-5eb6-45d6-a8dd-6f2bb4e48834
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197255878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1197255878
Directory	/workspace/16.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.4276671925
Short name	T95
Test name
Test status
Simulation time	14873783512 ps
CPU time	64.08 seconds
Started	Jan 10 12:42:58 PM PST 24
Finished	Jan 10 12:45:15 PM PST 24
Peak memory	201684 kb
Host	smart-986f1fd2-053e-48c1-b4dc-337e3f64a78d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4276671925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.4276671925
Directory	/workspace/16.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.4222300872
Short name	T828
Test name
Test status
Simulation time	33507126 ps
CPU time	2.02 seconds
Started	Jan 10 12:42:52 PM PST 24
Finished	Jan 10 12:44:08 PM PST 24
Peak memory	201652 kb
Host	smart-e3333867-20fd-4675-9d7e-36f6e215217b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222300872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4222300872
Directory	/workspace/16.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_same_source.1578584863
Short name	T25
Test name
Test status
Simulation time	222728353 ps
CPU time	3.77 seconds
Started	Jan 10 12:42:56 PM PST 24
Finished	Jan 10 12:44:13 PM PST 24
Peak memory	201636 kb
Host	smart-b201fa03-6e50-4fc6-a84d-4590276802b8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1578584863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1578584863
Directory	/workspace/16.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke.1103280075
Short name	T355
Test name
Test status
Simulation time	14595707 ps
CPU time	1.05 seconds
Started	Jan 10 12:42:55 PM PST 24
Finished	Jan 10 12:44:09 PM PST 24
Peak memory	201560 kb
Host	smart-cda0ee07-db75-4401-b28b-ea22f3cd32fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1103280075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1103280075
Directory	/workspace/16.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.188303121
Short name	T674
Test name
Test status
Simulation time	1981392819 ps
CPU time	9.38 seconds
Started	Jan 10 12:43:07 PM PST 24
Finished	Jan 10 12:44:30 PM PST 24
Peak memory	201716 kb
Host	smart-b30ed403-4832-49bc-9b07-7126eb21a7e0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=188303121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.188303121
Directory	/workspace/16.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.254344272
Short name	T165
Test name
Test status
Simulation time	2345291615 ps
CPU time	10.47 seconds
Started	Jan 10 12:43:06 PM PST 24
Finished	Jan 10 12:44:29 PM PST 24
Peak memory	201784 kb
Host	smart-d228b3a6-7df6-4eb2-8653-f5c55f9b0398
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=254344272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.254344272
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1504704247
Short name	T818
Test name
Test status
Simulation time	11042569 ps
CPU time	1.17 seconds
Started	Jan 10 12:42:53 PM PST 24
Finished	Jan 10 12:44:07 PM PST 24
Peak memory	201708 kb
Host	smart-1e258f07-f2cc-4517-b303-bdbd3f4afe73
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504704247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1504704247
Directory	/workspace/16.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.664745483
Short name	T413
Test name
Test status
Simulation time	121505522 ps
CPU time	9.32 seconds
Started	Jan 10 12:42:53 PM PST 24
Finished	Jan 10 12:44:15 PM PST 24
Peak memory	201628 kb
Host	smart-38ffacb8-5d77-4d32-a269-f19b3f046a6a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=664745483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.664745483
Directory	/workspace/16.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3314561293
Short name	T499
Test name
Test status
Simulation time	6363492861 ps
CPU time	172.48 seconds
Started	Jan 10 12:43:13 PM PST 24
Finished	Jan 10 12:47:19 PM PST 24
Peak memory	206120 kb
Host	smart-531ed930-56ce-404d-a8f8-6893a7578643
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3314561293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.3314561293
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.4252593090
Short name	T653
Test name
Test status
Simulation time	474356864 ps
CPU time	42.08 seconds
Started	Jan 10 12:42:55 PM PST 24
Finished	Jan 10 12:44:51 PM PST 24
Peak memory	202792 kb
Host	smart-217afef0-3a75-46da-ab2e-06ca32a3a3c9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4252593090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.4252593090
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2001713414
Short name	T798
Test name
Test status
Simulation time	1068047651 ps
CPU time	7.48 seconds
Started	Jan 10 12:43:06 PM PST 24
Finished	Jan 10 12:44:27 PM PST 24
Peak memory	201700 kb
Host	smart-e1dc9dde-186c-4bc6-8b30-070fbce89658
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2001713414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2001713414
Directory	/workspace/16.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2713474975
Short name	T416
Test name
Test status
Simulation time	183045684 ps
CPU time	4.4 seconds
Started	Jan 10 12:42:55 PM PST 24
Finished	Jan 10 12:44:13 PM PST 24
Peak memory	201676 kb
Host	smart-80089d6e-49a6-473c-a109-fef5e3ce9ac7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2713474975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2713474975
Directory	/workspace/17.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3416445920
Short name	T862
Test name
Test status
Simulation time	123362238110 ps
CPU time	327.84 seconds
Started	Jan 10 12:42:59 PM PST 24
Finished	Jan 10 12:49:41 PM PST 24
Peak memory	202684 kb
Host	smart-fa400ed7-d4d0-454d-a904-25aac00219aa
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3416445920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.3416445920
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.430812202
Short name	T623
Test name
Test status
Simulation time	892116428 ps
CPU time	9.46 seconds
Started	Jan 10 12:43:10 PM PST 24
Finished	Jan 10 12:44:32 PM PST 24
Peak memory	201472 kb
Host	smart-54edcb03-a272-4598-b9af-29faa9e9f761
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=430812202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.430812202
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_random.349442814
Short name	T752
Test name
Test status
Simulation time	84588171 ps
CPU time	2.64 seconds
Started	Jan 10 12:43:14 PM PST 24
Finished	Jan 10 12:44:29 PM PST 24
Peak memory	201480 kb
Host	smart-d185861a-4c7f-4576-8cda-497188efa81f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=349442814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.349442814
Directory	/workspace/17.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random.1951444933
Short name	T856
Test name
Test status
Simulation time	92688528 ps
CPU time	4.67 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:44:40 PM PST 24
Peak memory	201620 kb
Host	smart-bbc3c5f4-42ef-4b2d-83fa-4f27709ffb5c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1951444933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1951444933
Directory	/workspace/17.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.4283439055
Short name	T437
Test name
Test status
Simulation time	21280521806 ps
CPU time	96.71 seconds
Started	Jan 10 12:42:53 PM PST 24
Finished	Jan 10 12:45:43 PM PST 24
Peak memory	201828 kb
Host	smart-ba7fb819-89a1-42ff-a49b-fb15b89c9210
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283439055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4283439055
Directory	/workspace/17.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.1642080358
Short name	T482
Test name
Test status
Simulation time	7170584437 ps
CPU time	44.08 seconds
Started	Jan 10 12:43:23 PM PST 24
Finished	Jan 10 12:45:21 PM PST 24
Peak memory	201704 kb
Host	smart-e1743388-1435-403c-a817-7778b33ae9b1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1642080358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1642080358
Directory	/workspace/17.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3408177375
Short name	T309
Test name
Test status
Simulation time	118008396 ps
CPU time	6.43 seconds
Started	Jan 10 12:43:11 PM PST 24
Finished	Jan 10 12:44:30 PM PST 24
Peak memory	201468 kb
Host	smart-de238115-f57d-4e0b-8548-b8efea512814
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408177375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3408177375
Directory	/workspace/17.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_same_source.4218714898
Short name	T629
Test name
Test status
Simulation time	1589715202 ps
CPU time	10.63 seconds
Started	Jan 10 12:42:53 PM PST 24
Finished	Jan 10 12:44:17 PM PST 24
Peak memory	201700 kb
Host	smart-70003636-5259-4a78-b7fa-eae7dad6aa76
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4218714898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.4218714898
Directory	/workspace/17.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke.3603091040
Short name	T896
Test name
Test status
Simulation time	13682990 ps
CPU time	1.18 seconds
Started	Jan 10 12:42:55 PM PST 24
Finished	Jan 10 12:44:10 PM PST 24
Peak memory	201728 kb
Host	smart-3bfe345a-6aef-470a-9aef-44f85fca287a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3603091040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3603091040
Directory	/workspace/17.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1460623664
Short name	T450
Test name
Test status
Simulation time	2509484173 ps
CPU time	11.66 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:36 PM PST 24
Peak memory	201548 kb
Host	smart-76d23890-ff68-4d96-b396-f75561df845c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460623664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1460623664
Directory	/workspace/17.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2108022464
Short name	T625
Test name
Test status
Simulation time	1457921041 ps
CPU time	5.28 seconds
Started	Jan 10 12:43:13 PM PST 24
Finished	Jan 10 12:44:32 PM PST 24
Peak memory	201492 kb
Host	smart-62716fd7-e58a-461d-98e2-690de4ae8335
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2108022464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2108022464
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3547316345
Short name	T723
Test name
Test status
Simulation time	9780038 ps
CPU time	1.03 seconds
Started	Jan 10 12:42:51 PM PST 24
Finished	Jan 10 12:44:06 PM PST 24
Peak memory	201644 kb
Host	smart-718912ed-5e8a-44c3-9bc6-1a2be35c71c2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547316345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3547316345
Directory	/workspace/17.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all.3554495025
Short name	T392
Test name
Test status
Simulation time	180805911 ps
CPU time	18.68 seconds
Started	Jan 10 12:43:21 PM PST 24
Finished	Jan 10 12:44:53 PM PST 24
Peak memory	201636 kb
Host	smart-14806380-1cb0-4078-90a2-3b07769f9137
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3554495025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3554495025
Directory	/workspace/17.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3146721234
Short name	T440
Test name
Test status
Simulation time	213247088 ps
CPU time	16.97 seconds
Started	Jan 10 12:42:52 PM PST 24
Finished	Jan 10 12:44:23 PM PST 24
Peak memory	201612 kb
Host	smart-f8c25669-c6ba-4c11-acbb-66e97b2b0a90
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3146721234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3146721234
Directory	/workspace/17.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.271928296
Short name	T74
Test name
Test status
Simulation time	4690941328 ps
CPU time	134.6 seconds
Started	Jan 10 12:43:31 PM PST 24
Finished	Jan 10 12:47:03 PM PST 24
Peak memory	206368 kb
Host	smart-7ce9809a-b476-4fa0-8521-f4e3f9ca52f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=271928296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand _reset.271928296
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1320472457
Short name	T407
Test name
Test status
Simulation time	1334900645 ps
CPU time	122.29 seconds
Started	Jan 10 12:43:13 PM PST 24
Finished	Jan 10 12:46:29 PM PST 24
Peak memory	203548 kb
Host	smart-ece1d6e9-381c-4c43-b27e-bc173409a725
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1320472457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.1320472457
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2168903218
Short name	T292
Test name
Test status
Simulation time	645006288 ps
CPU time	3.28 seconds
Started	Jan 10 12:42:58 PM PST 24
Finished	Jan 10 12:44:15 PM PST 24
Peak memory	201700 kb
Host	smart-66745bf0-9ebd-4ae3-b510-81ee45f43ba5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2168903218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2168903218
Directory	/workspace/17.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device.3206688893
Short name	T663
Test name
Test status
Simulation time	99671596 ps
CPU time	2.8 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:26 PM PST 24
Peak memory	201728 kb
Host	smart-e4f857d0-2d26-4c1b-a8ef-4f272306267e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3206688893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3206688893
Directory	/workspace/18.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2804983536
Short name	T806
Test name
Test status
Simulation time	33539116337 ps
CPU time	112.47 seconds
Started	Jan 10 12:43:03 PM PST 24
Finished	Jan 10 12:46:09 PM PST 24
Peak memory	201824 kb
Host	smart-62c3e5b5-70ab-4dec-b770-87086f6da927
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2804983536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.2804983536
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3026646166
Short name	T664
Test name
Test status
Simulation time	143065691 ps
CPU time	5.04 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:28 PM PST 24
Peak memory	201496 kb
Host	smart-adfbe5f9-e8d0-4031-85c8-de8658459cd8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3026646166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3026646166
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_random.831870680
Short name	T581
Test name
Test status
Simulation time	3884539996 ps
CPU time	11.36 seconds
Started	Jan 10 12:43:00 PM PST 24
Finished	Jan 10 12:44:25 PM PST 24
Peak memory	201684 kb
Host	smart-1637f180-088b-4dc8-ae57-ceebd91df5cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=831870680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.831870680
Directory	/workspace/18.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random.1174754567
Short name	T727
Test name
Test status
Simulation time	1181222980 ps
CPU time	9.61 seconds
Started	Jan 10 12:43:03 PM PST 24
Finished	Jan 10 12:44:36 PM PST 24
Peak memory	201688 kb
Host	smart-7f0571de-fde7-4bf8-bd06-74ec7b97e7e5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1174754567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1174754567
Directory	/workspace/18.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.3599375164
Short name	T479
Test name
Test status
Simulation time	11398569553 ps
CPU time	49.93 seconds
Started	Jan 10 12:43:07 PM PST 24
Finished	Jan 10 12:45:16 PM PST 24
Peak memory	201792 kb
Host	smart-6d188665-1953-4a7b-9568-025357d6674c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599375164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3599375164
Directory	/workspace/18.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1445754939
Short name	T729
Test name
Test status
Simulation time	14786391533 ps
CPU time	20.73 seconds
Started	Jan 10 12:43:11 PM PST 24
Finished	Jan 10 12:44:45 PM PST 24
Peak memory	201736 kb
Host	smart-578c33d9-92fa-4564-8ca2-854647ed6dc7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1445754939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1445754939
Directory	/workspace/18.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3426216541
Short name	T251
Test name
Test status
Simulation time	91964474 ps
CPU time	3.35 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:27 PM PST 24
Peak memory	201496 kb
Host	smart-c00fd4f4-c997-4bf1-b2c4-ff33da0897ac
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426216541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3426216541
Directory	/workspace/18.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_same_source.685560749
Short name	T273
Test name
Test status
Simulation time	155073456 ps
CPU time	4.98 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:28 PM PST 24
Peak memory	201512 kb
Host	smart-89c6c150-55e7-4c78-a378-ba3000ae3043
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=685560749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.685560749
Directory	/workspace/18.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke.2887563048
Short name	T34
Test name
Test status
Simulation time	77450861 ps
CPU time	1.3 seconds
Started	Jan 10 12:43:02 PM PST 24
Finished	Jan 10 12:44:16 PM PST 24
Peak memory	201624 kb
Host	smart-f4460d74-28c5-41a3-97a9-61e6b20ea892
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2887563048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2887563048
Directory	/workspace/18.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1193003362
Short name	T281
Test name
Test status
Simulation time	1959399050 ps
CPU time	9.82 seconds
Started	Jan 10 12:43:04 PM PST 24
Finished	Jan 10 12:44:32 PM PST 24
Peak memory	201688 kb
Host	smart-387defa9-5062-4ceb-842b-5d881ca7bb71
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193003362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1193003362
Directory	/workspace/18.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1571624568
Short name	T639
Test name
Test status
Simulation time	1876627975 ps
CPU time	13.36 seconds
Started	Jan 10 12:43:13 PM PST 24
Finished	Jan 10 12:44:40 PM PST 24
Peak memory	201680 kb
Host	smart-4097350c-361b-43ec-be84-d567e5eca91f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1571624568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1571624568
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1491612682
Short name	T518
Test name
Test status
Simulation time	8721051 ps
CPU time	1.02 seconds
Started	Jan 10 12:43:01 PM PST 24
Finished	Jan 10 12:44:17 PM PST 24
Peak memory	201736 kb
Host	smart-9cff0428-98c3-4dd4-8a03-60f7f3a63df7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491612682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1491612682
Directory	/workspace/18.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all.2869468315
Short name	T722
Test name
Test status
Simulation time	5063008695 ps
CPU time	65.43 seconds
Started	Jan 10 12:43:15 PM PST 24
Finished	Jan 10 12:45:34 PM PST 24
Peak memory	202724 kb
Host	smart-f03395b3-9133-4e29-930d-c5431faaf060
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2869468315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2869468315
Directory	/workspace/18.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.163230350
Short name	T298
Test name
Test status
Simulation time	3698299880 ps
CPU time	49.13 seconds
Started	Jan 10 12:43:11 PM PST 24
Finished	Jan 10 12:45:12 PM PST 24
Peak memory	201572 kb
Host	smart-ebaec9ec-41a3-4603-b9b2-b995a2f58c69
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=163230350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.163230350
Directory	/workspace/18.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2896302488
Short name	T239
Test name
Test status
Simulation time	912407907 ps
CPU time	126.56 seconds
Started	Jan 10 12:43:07 PM PST 24
Finished	Jan 10 12:46:33 PM PST 24
Peak memory	203800 kb
Host	smart-c875a36b-9dcc-4216-a2f8-12181a205183
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2896302488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.2896302488
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1966470757
Short name	T473
Test name
Test status
Simulation time	2015638065 ps
CPU time	65.69 seconds
Started	Jan 10 12:43:10 PM PST 24
Finished	Jan 10 12:45:28 PM PST 24
Peak memory	203712 kb
Host	smart-7b40443a-e6f5-43a6-9d9b-1acfd01808c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1966470757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.1966470757
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3847370648
Short name	T692
Test name
Test status
Simulation time	9604089 ps
CPU time	1.06 seconds
Started	Jan 10 12:43:05 PM PST 24
Finished	Jan 10 12:44:20 PM PST 24
Peak memory	201708 kb
Host	smart-7c757cbb-844b-4dbb-838c-c567e39cf37b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3847370648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3847370648
Directory	/workspace/18.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device.437675859
Short name	T379
Test name
Test status
Simulation time	126974333 ps
CPU time	2.97 seconds
Started	Jan 10 12:43:13 PM PST 24
Finished	Jan 10 12:44:29 PM PST 24
Peak memory	201664 kb
Host	smart-ee06eae9-d37b-4601-8dd5-052776eebd4d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=437675859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.437675859
Directory	/workspace/19.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.3056122086
Short name	T586
Test name
Test status
Simulation time	325095384 ps
CPU time	2.49 seconds
Started	Jan 10 12:43:07 PM PST 24
Finished	Jan 10 12:44:23 PM PST 24
Peak memory	201592 kb
Host	smart-cd97c9d7-4b5d-42e6-b8bd-0fa56b99926e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3056122086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3056122086
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_random.1307254711
Short name	T704
Test name
Test status
Simulation time	1632196650 ps
CPU time	10.63 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:44:53 PM PST 24
Peak memory	201632 kb
Host	smart-9772a1e4-1f9e-4547-a63c-975b69b80570
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1307254711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1307254711
Directory	/workspace/19.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random.796731874
Short name	T357
Test name
Test status
Simulation time	1933817482 ps
CPU time	11.27 seconds
Started	Jan 10 12:43:00 PM PST 24
Finished	Jan 10 12:44:25 PM PST 24
Peak memory	201596 kb
Host	smart-7d8e43e1-38ce-43cb-8274-5cf4005ff57a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=796731874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.796731874
Directory	/workspace/19.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.1544567737
Short name	T348
Test name
Test status
Simulation time	26316951777 ps
CPU time	106.32 seconds
Started	Jan 10 12:43:11 PM PST 24
Finished	Jan 10 12:46:09 PM PST 24
Peak memory	201800 kb
Host	smart-92c247c4-6c57-4e52-ab4d-a83ef392fe31
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544567737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1544567737
Directory	/workspace/19.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.777160828
Short name	T575
Test name
Test status
Simulation time	47824886002 ps
CPU time	90.65 seconds
Started	Jan 10 12:43:03 PM PST 24
Finished	Jan 10 12:45:47 PM PST 24
Peak memory	201796 kb
Host	smart-b5fb8708-97db-4b5d-90f8-04cd3ffba03f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=777160828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.777160828
Directory	/workspace/19.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.917347565
Short name	T802
Test name
Test status
Simulation time	44232269 ps
CPU time	4.59 seconds
Started	Jan 10 12:43:20 PM PST 24
Finished	Jan 10 12:44:38 PM PST 24
Peak memory	201632 kb
Host	smart-40cc19d6-4537-4ac0-803c-f9ea34fed873
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917347565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.917347565
Directory	/workspace/19.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_same_source.325943832
Short name	T880
Test name
Test status
Simulation time	130921520 ps
CPU time	2.14 seconds
Started	Jan 10 12:43:02 PM PST 24
Finished	Jan 10 12:44:18 PM PST 24
Peak memory	201680 kb
Host	smart-8b4c04cf-56d2-449a-a500-4b9c186da474
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=325943832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.325943832
Directory	/workspace/19.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke.294189597
Short name	T840
Test name
Test status
Simulation time	13046465 ps
CPU time	1.14 seconds
Started	Jan 10 12:43:09 PM PST 24
Finished	Jan 10 12:44:26 PM PST 24
Peak memory	201720 kb
Host	smart-38cd5bcc-2fe7-41cc-9a2e-a1f34134523d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=294189597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.294189597
Directory	/workspace/19.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3670376751
Short name	T781
Test name
Test status
Simulation time	2926220698 ps
CPU time	11.28 seconds
Started	Jan 10 12:43:14 PM PST 24
Finished	Jan 10 12:44:38 PM PST 24
Peak memory	201932 kb
Host	smart-aead220c-3332-47f4-a948-4fd2248a9e43
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670376751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3670376751
Directory	/workspace/19.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3756954994
Short name	T197
Test name
Test status
Simulation time	1187944485 ps
CPU time	8.31 seconds
Started	Jan 10 12:43:01 PM PST 24
Finished	Jan 10 12:44:23 PM PST 24
Peak memory	201640 kb
Host	smart-39b25e78-563c-4a21-8a71-27c8091e68de
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3756954994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3756954994
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2630967336
Short name	T774
Test name
Test status
Simulation time	11668257 ps
CPU time	1 seconds
Started	Jan 10 12:43:01 PM PST 24
Finished	Jan 10 12:44:15 PM PST 24
Peak memory	201744 kb
Host	smart-4786d17b-8600-4792-a204-a9dbde2a2226
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630967336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2630967336
Directory	/workspace/19.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.3399105877
Short name	T465
Test name
Test status
Simulation time	150991868 ps
CPU time	16.25 seconds
Started	Jan 10 12:43:11 PM PST 24
Finished	Jan 10 12:44:39 PM PST 24
Peak memory	201508 kb
Host	smart-b39dfa60-ab91-426f-a2c6-b3d10323fc1d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3399105877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3399105877
Directory	/workspace/19.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.402403898
Short name	T817
Test name
Test status
Simulation time	4526285069 ps
CPU time	60.71 seconds
Started	Jan 10 12:43:04 PM PST 24
Finished	Jan 10 12:45:27 PM PST 24
Peak memory	204448 kb
Host	smart-6931d20d-308b-4c69-8320-c7f00e94fbdf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=402403898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.402403898
Directory	/workspace/19.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3426882206
Short name	T44
Test name
Test status
Simulation time	495675053 ps
CPU time	60.39 seconds
Started	Jan 10 12:43:02 PM PST 24
Finished	Jan 10 12:45:15 PM PST 24
Peak memory	203736 kb
Host	smart-d3cf0add-6be5-4833-9aa5-64ac2b2dfabf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3426882206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.3426882206
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1651402604
Short name	T676
Test name
Test status
Simulation time	13503830552 ps
CPU time	94.9 seconds
Started	Jan 10 12:43:08 PM PST 24
Finished	Jan 10 12:45:56 PM PST 24
Peak memory	204136 kb
Host	smart-85664858-871f-45d9-a058-52f502d8f92b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1651402604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.1651402604
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2633525293
Short name	T811
Test name
Test status
Simulation time	354672102 ps
CPU time	5.15 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:29 PM PST 24
Peak memory	201548 kb
Host	smart-3be18f26-f57b-42ad-b862-67a2267473f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2633525293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2633525293
Directory	/workspace/19.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1315146092
Short name	T846
Test name
Test status
Simulation time	4473401338 ps
CPU time	20 seconds
Started	Jan 10 12:42:05 PM PST 24
Finished	Jan 10 12:43:38 PM PST 24
Peak memory	201728 kb
Host	smart-f80fe1a2-62bf-44e3-b2d1-19c869ebfe0d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1315146092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1315146092
Directory	/workspace/2.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3599143678
Short name	T148
Test name
Test status
Simulation time	10521917060 ps
CPU time	65.48 seconds
Started	Jan 10 12:42:07 PM PST 24
Finished	Jan 10 12:44:25 PM PST 24
Peak memory	201800 kb
Host	smart-587b13b7-770c-465d-998c-f3106aada803
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3599143678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.3599143678
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2790325400
Short name	T336
Test name
Test status
Simulation time	588970182 ps
CPU time	10.24 seconds
Started	Jan 10 12:42:07 PM PST 24
Finished	Jan 10 12:43:31 PM PST 24
Peak memory	201624 kb
Host	smart-7dc238a1-936b-4b26-be2d-adab1d2036cb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2790325400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2790325400
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_random.2066369718
Short name	T888
Test name
Test status
Simulation time	97586627 ps
CPU time	6.27 seconds
Started	Jan 10 12:42:06 PM PST 24
Finished	Jan 10 12:43:26 PM PST 24
Peak memory	201672 kb
Host	smart-6d4f5a26-1e84-4c4b-9b47-7a965d073dde
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2066369718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2066369718
Directory	/workspace/2.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random.231066426
Short name	T133
Test name
Test status
Simulation time	250645693 ps
CPU time	4.31 seconds
Started	Jan 10 12:42:07 PM PST 24
Finished	Jan 10 12:43:25 PM PST 24
Peak memory	201608 kb
Host	smart-cfb66261-e08c-4510-87e1-97e897956878
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=231066426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.231066426
Directory	/workspace/2.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1125828539
Short name	T463
Test name
Test status
Simulation time	21103219595 ps
CPU time	94.5 seconds
Started	Jan 10 12:42:16 PM PST 24
Finished	Jan 10 12:45:03 PM PST 24
Peak memory	201560 kb
Host	smart-b3e2eddd-3dda-40c5-9886-df157c7defd2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125828539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1125828539
Directory	/workspace/2.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2856737625
Short name	T863
Test name
Test status
Simulation time	4588779553 ps
CPU time	23.25 seconds
Started	Jan 10 12:42:10 PM PST 24
Finished	Jan 10 12:43:46 PM PST 24
Peak memory	201616 kb
Host	smart-a13c656d-879d-4480-907b-c9678be34ac8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2856737625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2856737625
Directory	/workspace/2.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2992775881
Short name	T310
Test name
Test status
Simulation time	67677635 ps
CPU time	3.42 seconds
Started	Jan 10 12:42:05 PM PST 24
Finished	Jan 10 12:43:22 PM PST 24
Peak memory	201584 kb
Host	smart-51915fee-e4da-4007-b466-95a6535d74a4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992775881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2992775881
Directory	/workspace/2.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_same_source.987109562
Short name	T189
Test name
Test status
Simulation time	257435755 ps
CPU time	4.86 seconds
Started	Jan 10 12:42:03 PM PST 24
Finished	Jan 10 12:43:21 PM PST 24
Peak memory	201744 kb
Host	smart-3c815dc9-1edc-42c7-950e-3aaf51cccd15
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=987109562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.987109562
Directory	/workspace/2.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke.2582349807
Short name	T35
Test name
Test status
Simulation time	132209102 ps
CPU time	1.59 seconds
Started	Jan 10 12:42:06 PM PST 24
Finished	Jan 10 12:43:21 PM PST 24
Peak memory	201592 kb
Host	smart-dbd77263-e549-4afe-ac62-168a8f813269
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2582349807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2582349807
Directory	/workspace/2.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1208408311
Short name	T474
Test name
Test status
Simulation time	1468934539 ps
CPU time	7.6 seconds
Started	Jan 10 12:42:07 PM PST 24
Finished	Jan 10 12:43:27 PM PST 24
Peak memory	201712 kb
Host	smart-a7aa3375-fd1f-48af-bcce-bcdd8746b282
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208408311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1208408311
Directory	/workspace/2.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2111607451
Short name	T707
Test name
Test status
Simulation time	4733563628 ps
CPU time	6.25 seconds
Started	Jan 10 12:42:10 PM PST 24
Finished	Jan 10 12:43:29 PM PST 24
Peak memory	201628 kb
Host	smart-1554e892-1461-4b82-a294-19ea0ae3c10c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2111607451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2111607451
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.4272158652
Short name	T531
Test name
Test status
Simulation time	15487777 ps
CPU time	1.22 seconds
Started	Jan 10 12:42:07 PM PST 24
Finished	Jan 10 12:43:21 PM PST 24
Peak memory	201608 kb
Host	smart-d7f4e7d4-6192-49ad-850c-51fab1aa6adf
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272158652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.4272158652
Directory	/workspace/2.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all.3665117392
Short name	T97
Test name
Test status
Simulation time	215714680 ps
CPU time	15.05 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:43:37 PM PST 24
Peak memory	201692 kb
Host	smart-10b2cf82-a0fa-473f-88d1-88199f479f76
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3665117392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3665117392
Directory	/workspace/2.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.682401777
Short name	T577
Test name
Test status
Simulation time	4566489281 ps
CPU time	34.06 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:43:56 PM PST 24
Peak memory	201796 kb
Host	smart-06aaff61-eb6e-46aa-9fff-f80520a1cb99
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=682401777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.682401777
Directory	/workspace/2.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3843345649
Short name	T127
Test name
Test status
Simulation time	471632708 ps
CPU time	42.45 seconds
Started	Jan 10 12:42:03 PM PST 24
Finished	Jan 10 12:43:59 PM PST 24
Peak memory	204188 kb
Host	smart-02fc2417-786e-49ae-bc8c-006c302f50c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3843345649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3843345649
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3926605574
Short name	T807
Test name
Test status
Simulation time	552496775 ps
CPU time	79.56 seconds
Started	Jan 10 12:42:05 PM PST 24
Finished	Jan 10 12:44:37 PM PST 24
Peak memory	203804 kb
Host	smart-274e7861-4ee4-4f1a-b239-8d0840cfcbda
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3926605574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.3926605574
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.503700451
Short name	T670
Test name
Test status
Simulation time	438721456 ps
CPU time	7.49 seconds
Started	Jan 10 12:42:08 PM PST 24
Finished	Jan 10 12:43:29 PM PST 24
Peak memory	201736 kb
Host	smart-063e1297-0c53-4d8d-b997-5f078efd6027
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=503700451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.503700451
Directory	/workspace/2.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device.588484232
Short name	T445
Test name
Test status
Simulation time	37002117 ps
CPU time	6.04 seconds
Started	Jan 10 12:43:14 PM PST 24
Finished	Jan 10 12:44:33 PM PST 24
Peak memory	201848 kb
Host	smart-c4f651e4-24f3-4db7-a23e-183922807833
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=588484232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.588484232
Directory	/workspace/20.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2842519822
Short name	T233
Test name
Test status
Simulation time	35561561019 ps
CPU time	180.04 seconds
Started	Jan 10 12:43:06 PM PST 24
Finished	Jan 10 12:47:19 PM PST 24
Peak memory	202652 kb
Host	smart-9510e3aa-9945-4712-b799-40988e4631b4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2842519822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.2842519822
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1582797466
Short name	T642
Test name
Test status
Simulation time	43987732 ps
CPU time	3.95 seconds
Started	Jan 10 12:43:07 PM PST 24
Finished	Jan 10 12:44:25 PM PST 24
Peak memory	201708 kb
Host	smart-a16df812-dc13-4440-9870-cfc8459a7f2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1582797466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1582797466
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_random.50862997
Short name	T557
Test name
Test status
Simulation time	188451735 ps
CPU time	2.26 seconds
Started	Jan 10 12:43:11 PM PST 24
Finished	Jan 10 12:44:26 PM PST 24
Peak memory	201548 kb
Host	smart-a3ccf64b-5575-444d-8bdc-19b3fe99beb4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=50862997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.50862997
Directory	/workspace/20.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random.1681920066
Short name	T730
Test name
Test status
Simulation time	730552244 ps
CPU time	14.19 seconds
Started	Jan 10 12:43:08 PM PST 24
Finished	Jan 10 12:44:34 PM PST 24
Peak memory	201660 kb
Host	smart-a398daf2-27e5-43e8-9877-daafb4202df0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1681920066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1681920066
Directory	/workspace/20.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.1271984593
Short name	T763
Test name
Test status
Simulation time	38150938998 ps
CPU time	169.48 seconds
Started	Jan 10 12:43:02 PM PST 24
Finished	Jan 10 12:47:05 PM PST 24
Peak memory	201804 kb
Host	smart-075d6149-24f4-4c57-a5d4-81f3e9db6138
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271984593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1271984593
Directory	/workspace/20.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.332256968
Short name	T578
Test name
Test status
Simulation time	57063155719 ps
CPU time	155.13 seconds
Started	Jan 10 12:43:01 PM PST 24
Finished	Jan 10 12:46:50 PM PST 24
Peak memory	201672 kb
Host	smart-aa591aab-f8ef-4afc-b7ed-198edfe36002
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=332256968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.332256968
Directory	/workspace/20.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3741080766
Short name	T154
Test name
Test status
Simulation time	116339667 ps
CPU time	5.75 seconds
Started	Jan 10 12:43:01 PM PST 24
Finished	Jan 10 12:44:20 PM PST 24
Peak memory	201720 kb
Host	smart-482d63c3-2104-4cfa-964c-3deb3e0023bc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741080766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3741080766
Directory	/workspace/20.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_same_source.1097765638
Short name	T686
Test name
Test status
Simulation time	36772834 ps
CPU time	2.95 seconds
Started	Jan 10 12:43:07 PM PST 24
Finished	Jan 10 12:44:23 PM PST 24
Peak memory	201548 kb
Host	smart-ec748aca-d2f1-4eed-9e8a-70a77b10bfa5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1097765638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1097765638
Directory	/workspace/20.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke.1935706562
Short name	T135
Test name
Test status
Simulation time	52980843 ps
CPU time	1.43 seconds
Started	Jan 10 12:43:03 PM PST 24
Finished	Jan 10 12:44:18 PM PST 24
Peak memory	201716 kb
Host	smart-96243b8b-d33f-40ca-aa1f-4208cd33b3c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1935706562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1935706562
Directory	/workspace/20.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3459827675
Short name	T797
Test name
Test status
Simulation time	2681129692 ps
CPU time	8.57 seconds
Started	Jan 10 12:42:59 PM PST 24
Finished	Jan 10 12:44:22 PM PST 24
Peak memory	201656 kb
Host	smart-5bac6743-68f2-4ae1-88fa-5dbdc2b12b83
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459827675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3459827675
Directory	/workspace/20.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.740414246
Short name	T513
Test name
Test status
Simulation time	2361743981 ps
CPU time	11.72 seconds
Started	Jan 10 12:43:01 PM PST 24
Finished	Jan 10 12:44:27 PM PST 24
Peak memory	201676 kb
Host	smart-60fff899-74c8-4421-9b54-4bca76fab561
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=740414246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.740414246
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3963437003
Short name	T184
Test name
Test status
Simulation time	10023711 ps
CPU time	1.33 seconds
Started	Jan 10 12:43:00 PM PST 24
Finished	Jan 10 12:44:15 PM PST 24
Peak memory	201748 kb
Host	smart-4b50ad84-c545-4bfc-8256-d6ff00183524
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963437003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3963437003
Directory	/workspace/20.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all.648166306
Short name	T190
Test name
Test status
Simulation time	2266658799 ps
CPU time	43.86 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:45:27 PM PST 24
Peak memory	202724 kb
Host	smart-34156af7-7a8f-4b4e-b4ff-74774ef49a0f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=648166306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.648166306
Directory	/workspace/20.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.55585489
Short name	T555
Test name
Test status
Simulation time	322516080 ps
CPU time	13.96 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:44:58 PM PST 24
Peak memory	201632 kb
Host	smart-7a8bc078-817d-4e15-a9e9-73f573423f73
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=55585489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.55585489
Directory	/workspace/20.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1946633524
Short name	T237
Test name
Test status
Simulation time	1522513043 ps
CPU time	128.43 seconds
Started	Jan 10 12:43:24 PM PST 24
Finished	Jan 10 12:46:52 PM PST 24
Peak memory	203764 kb
Host	smart-776ebb1b-f29e-49bc-99c8-ad9709571c6c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1946633524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.1946633524
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.2618320555
Short name	T242
Test name
Test status
Simulation time	5662672977 ps
CPU time	125.81 seconds
Started	Jan 10 12:43:03 PM PST 24
Finished	Jan 10 12:46:22 PM PST 24
Peak memory	205784 kb
Host	smart-bcb5522a-eeaf-4675-98cf-9cdd900cc1e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2618320555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.2618320555
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.119380201
Short name	T867
Test name
Test status
Simulation time	592678955 ps
CPU time	5.53 seconds
Started	Jan 10 12:43:07 PM PST 24
Finished	Jan 10 12:44:26 PM PST 24
Peak memory	201704 kb
Host	smart-60ba3049-3487-4f01-a492-e7ca51435539
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=119380201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.119380201
Directory	/workspace/20.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2317576428
Short name	T645
Test name
Test status
Simulation time	5388937358 ps
CPU time	17.54 seconds
Started	Jan 10 12:43:07 PM PST 24
Finished	Jan 10 12:44:38 PM PST 24
Peak memory	201780 kb
Host	smart-ec2e6b32-161a-469b-b11a-eebff1ef88f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2317576428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2317576428
Directory	/workspace/21.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3042458203
Short name	T234
Test name
Test status
Simulation time	40949226704 ps
CPU time	251.33 seconds
Started	Jan 10 12:43:05 PM PST 24
Finished	Jan 10 12:48:29 PM PST 24
Peak memory	202656 kb
Host	smart-a3ec3bf0-ae75-451a-beed-ddba3868f859
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3042458203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.3042458203
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1905337230
Short name	T687
Test name
Test status
Simulation time	85229166 ps
CPU time	3.05 seconds
Started	Jan 10 12:43:08 PM PST 24
Finished	Jan 10 12:44:24 PM PST 24
Peak memory	201600 kb
Host	smart-7f91f810-7bf6-4be0-a8d3-e6070188bf6e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1905337230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1905337230
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_random.2675029352
Short name	T201
Test name
Test status
Simulation time	3528078374 ps
CPU time	8.56 seconds
Started	Jan 10 12:43:15 PM PST 24
Finished	Jan 10 12:44:38 PM PST 24
Peak memory	201756 kb
Host	smart-f9886726-2866-4648-a016-af7e6da8da33
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2675029352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2675029352
Directory	/workspace/21.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random.3261866321
Short name	T402
Test name
Test status
Simulation time	50022899 ps
CPU time	6.26 seconds
Started	Jan 10 12:43:13 PM PST 24
Finished	Jan 10 12:44:31 PM PST 24
Peak memory	201724 kb
Host	smart-021650e1-a00a-43cf-853f-5afc52709a8d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3261866321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3261866321
Directory	/workspace/21.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2831660673
Short name	T617
Test name
Test status
Simulation time	8092256972 ps
CPU time	35.13 seconds
Started	Jan 10 12:43:09 PM PST 24
Finished	Jan 10 12:44:56 PM PST 24
Peak memory	201704 kb
Host	smart-143078dd-873f-4d86-a50e-598088edc65b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831660673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2831660673
Directory	/workspace/21.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.625750563
Short name	T174
Test name
Test status
Simulation time	12756173871 ps
CPU time	69.02 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:45:32 PM PST 24
Peak memory	201716 kb
Host	smart-8847b391-b354-45ec-9006-d1fb2566bab0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=625750563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.625750563
Directory	/workspace/21.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.2822207020
Short name	T301
Test name
Test status
Simulation time	31845511 ps
CPU time	2.43 seconds
Started	Jan 10 12:43:19 PM PST 24
Finished	Jan 10 12:44:35 PM PST 24
Peak memory	201700 kb
Host	smart-5ff6026a-aa0a-49d5-bdd5-af2dae789e82
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822207020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2822207020
Directory	/workspace/21.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_same_source.4209985782
Short name	T247
Test name
Test status
Simulation time	26664122 ps
CPU time	2.44 seconds
Started	Jan 10 12:43:15 PM PST 24
Finished	Jan 10 12:44:32 PM PST 24
Peak memory	201744 kb
Host	smart-f130f723-fc06-4ece-b9dc-748ce0eb5588
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4209985782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.4209985782
Directory	/workspace/21.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke.4015106011
Short name	T646
Test name
Test status
Simulation time	168427778 ps
CPU time	1.52 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:25 PM PST 24
Peak memory	201496 kb
Host	smart-46278033-b77c-4ff3-9839-27ee2dbce8fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4015106011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.4015106011
Directory	/workspace/21.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3270838767
Short name	T439
Test name
Test status
Simulation time	5792510119 ps
CPU time	12.2 seconds
Started	Jan 10 12:43:08 PM PST 24
Finished	Jan 10 12:44:34 PM PST 24
Peak memory	201776 kb
Host	smart-7975fd8f-e526-478d-a1c7-766c15783283
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270838767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3270838767
Directory	/workspace/21.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.595093299
Short name	T62
Test name
Test status
Simulation time	3986063600 ps
CPU time	9.03 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:33 PM PST 24
Peak memory	201796 kb
Host	smart-7272c0a5-01da-4f5e-9096-77ac410c4537
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=595093299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.595093299
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3025501141
Short name	T770
Test name
Test status
Simulation time	13608077 ps
CPU time	1.22 seconds
Started	Jan 10 12:43:06 PM PST 24
Finished	Jan 10 12:44:20 PM PST 24
Peak memory	201672 kb
Host	smart-ccb43c8d-9f5f-4e1f-ae50-8d0c4f0384c9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025501141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3025501141
Directory	/workspace/21.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all.1514828015
Short name	T825
Test name
Test status
Simulation time	8225816492 ps
CPU time	110.15 seconds
Started	Jan 10 12:43:24 PM PST 24
Finished	Jan 10 12:46:29 PM PST 24
Peak memory	204732 kb
Host	smart-06f46202-e4b9-4591-8308-3a5417b9316d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1514828015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1514828015
Directory	/workspace/21.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.305163088
Short name	T887
Test name
Test status
Simulation time	3192303710 ps
CPU time	37.24 seconds
Started	Jan 10 12:43:09 PM PST 24
Finished	Jan 10 12:44:59 PM PST 24
Peak memory	201700 kb
Host	smart-7bc968bd-d6c8-47e5-a53e-2e42b45cec83
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=305163088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.305163088
Directory	/workspace/21.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1161633516
Short name	T203
Test name
Test status
Simulation time	2103254655 ps
CPU time	72.08 seconds
Started	Jan 10 12:43:14 PM PST 24
Finished	Jan 10 12:45:38 PM PST 24
Peak memory	203664 kb
Host	smart-d2afc079-139e-436d-b0c4-9f9aa1f21e68
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1161633516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.1161633516
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3070465040
Short name	T11
Test name
Test status
Simulation time	8073216288 ps
CPU time	152.93 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:47:11 PM PST 24
Peak memory	206440 kb
Host	smart-4214edb7-f5f0-41a3-8720-be7a7c1f2626
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3070465040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.3070465040
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1846076660
Short name	T768
Test name
Test status
Simulation time	137849034 ps
CPU time	1.89 seconds
Started	Jan 10 12:43:14 PM PST 24
Finished	Jan 10 12:44:28 PM PST 24
Peak memory	201552 kb
Host	smart-4a528f3e-841e-4ad1-8aee-5188edbd2a35
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1846076660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1846076660
Directory	/workspace/21.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3635069247
Short name	T489
Test name
Test status
Simulation time	182079716 ps
CPU time	11.43 seconds
Started	Jan 10 12:43:10 PM PST 24
Finished	Jan 10 12:44:34 PM PST 24
Peak memory	201708 kb
Host	smart-2089fdab-78b0-4963-b1bb-0cbea85921d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3635069247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3635069247
Directory	/workspace/22.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2632322592
Short name	T108
Test name
Test status
Simulation time	72749289533 ps
CPU time	58.58 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:45:42 PM PST 24
Peak memory	201792 kb
Host	smart-4641127a-32c7-45ca-aa00-538ddfac2709
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2632322592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.2632322592
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.959854559
Short name	T520
Test name
Test status
Simulation time	768197041 ps
CPU time	8.97 seconds
Started	Jan 10 12:43:08 PM PST 24
Finished	Jan 10 12:44:31 PM PST 24
Peak memory	201628 kb
Host	smart-d924ce1d-6339-4cc3-bf54-269aa1a90350
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=959854559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.959854559
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_random.3181215900
Short name	T249
Test name
Test status
Simulation time	644662288 ps
CPU time	8.57 seconds
Started	Jan 10 12:43:14 PM PST 24
Finished	Jan 10 12:44:36 PM PST 24
Peak memory	201556 kb
Host	smart-45e09705-c3a3-4176-aad7-2f92681411d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3181215900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3181215900
Directory	/workspace/22.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random.322099815
Short name	T411
Test name
Test status
Simulation time	25844206 ps
CPU time	2.66 seconds
Started	Jan 10 12:43:07 PM PST 24
Finished	Jan 10 12:44:23 PM PST 24
Peak memory	201624 kb
Host	smart-1e27eca5-cf3c-42e4-a0f5-9d98f6361999
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=322099815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.322099815
Directory	/workspace/22.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3753974230
Short name	T671
Test name
Test status
Simulation time	30759649867 ps
CPU time	18.68 seconds
Started	Jan 10 12:43:14 PM PST 24
Finished	Jan 10 12:44:45 PM PST 24
Peak memory	201708 kb
Host	smart-b7925cbf-22f1-4b57-8067-adc0f54928cb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753974230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3753974230
Directory	/workspace/22.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3218409520
Short name	T831
Test name
Test status
Simulation time	15897190010 ps
CPU time	104.57 seconds
Started	Jan 10 12:43:10 PM PST 24
Finished	Jan 10 12:46:15 PM PST 24
Peak memory	201760 kb
Host	smart-79b04a07-0d15-4773-8ecf-87f0e0b02541
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3218409520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3218409520
Directory	/workspace/22.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.404007880
Short name	T679
Test name
Test status
Simulation time	72722823 ps
CPU time	6.85 seconds
Started	Jan 10 12:43:14 PM PST 24
Finished	Jan 10 12:44:33 PM PST 24
Peak memory	201680 kb
Host	smart-0dd727bd-10bd-4a1e-bc79-5b2d0b0a170a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404007880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.404007880
Directory	/workspace/22.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_same_source.3008921067
Short name	T205
Test name
Test status
Simulation time	167965858 ps
CPU time	3.85 seconds
Started	Jan 10 12:43:13 PM PST 24
Finished	Jan 10 12:44:28 PM PST 24
Peak memory	201608 kb
Host	smart-0cc6012a-08c9-4690-b5b6-9735a8b216e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3008921067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3008921067
Directory	/workspace/22.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke.2321886539
Short name	T549
Test name
Test status
Simulation time	90991946 ps
CPU time	1.35 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:26 PM PST 24
Peak memory	201728 kb
Host	smart-9a4a6bb1-2318-4070-bef9-d9c50eb30385
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2321886539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2321886539
Directory	/workspace/22.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2733468721
Short name	T334
Test name
Test status
Simulation time	3506699426 ps
CPU time	9.77 seconds
Started	Jan 10 12:43:15 PM PST 24
Finished	Jan 10 12:44:39 PM PST 24
Peak memory	201780 kb
Host	smart-d487443f-40da-41b1-a0a6-e75f8b17a806
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733468721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2733468721
Directory	/workspace/22.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.30163155
Short name	T419
Test name
Test status
Simulation time	695202954 ps
CPU time	5.13 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:29 PM PST 24
Peak memory	201580 kb
Host	smart-760c90d5-0376-48f5-8ca3-b08117e88188
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=30163155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.30163155
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1894037925
Short name	T42
Test name
Test status
Simulation time	10805521 ps
CPU time	1.08 seconds
Started	Jan 10 12:43:08 PM PST 24
Finished	Jan 10 12:44:22 PM PST 24
Peak memory	201736 kb
Host	smart-3720eb23-71cc-4bf5-b89e-744a7dbde7b9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894037925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1894037925
Directory	/workspace/22.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all.2011146135
Short name	T559
Test name
Test status
Simulation time	699852089 ps
CPU time	12.38 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:36 PM PST 24
Peak memory	201708 kb
Host	smart-622c8df3-90ad-475e-9e5d-dc7c52ce0ed1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2011146135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2011146135
Directory	/workspace/22.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3277557607
Short name	T836
Test name
Test status
Simulation time	2769461863 ps
CPU time	42.02 seconds
Started	Jan 10 12:43:08 PM PST 24
Finished	Jan 10 12:45:02 PM PST 24
Peak memory	201692 kb
Host	smart-b8a1a9cc-48ec-4cd8-b81c-68f0d448f9e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3277557607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3277557607
Directory	/workspace/22.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1261867843
Short name	T792
Test name
Test status
Simulation time	302565980 ps
CPU time	45.18 seconds
Started	Jan 10 12:43:06 PM PST 24
Finished	Jan 10 12:45:04 PM PST 24
Peak memory	203652 kb
Host	smart-271c227f-7a96-4a32-a896-880602724001
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1261867843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.1261867843
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1380007667
Short name	T651
Test name
Test status
Simulation time	10954497 ps
CPU time	1.12 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:44:45 PM PST 24
Peak memory	201704 kb
Host	smart-5e2dd598-6d94-41e7-882e-07207ed9cfc7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1380007667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1380007667
Directory	/workspace/22.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device.672576584
Short name	T21
Test name
Test status
Simulation time	1103069784 ps
CPU time	4.96 seconds
Started	Jan 10 12:43:21 PM PST 24
Finished	Jan 10 12:44:40 PM PST 24
Peak memory	201604 kb
Host	smart-0f3dfc58-e156-4458-92cf-bacd9c58196e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=672576584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.672576584
Directory	/workspace/23.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.44674525
Short name	T830
Test name
Test status
Simulation time	112618430888 ps
CPU time	119.27 seconds
Started	Jan 10 12:43:19 PM PST 24
Finished	Jan 10 12:46:33 PM PST 24
Peak memory	202692 kb
Host	smart-9835ef83-0412-4497-8830-2824e71f5b0a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=44674525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow _rsp.44674525
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1029994110
Short name	T641
Test name
Test status
Simulation time	967309436 ps
CPU time	10.74 seconds
Started	Jan 10 12:43:23 PM PST 24
Finished	Jan 10 12:44:48 PM PST 24
Peak memory	201708 kb
Host	smart-93e306bb-806f-4b05-aaaa-04df0f302ff2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1029994110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1029994110
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_random.2146891275
Short name	T339
Test name
Test status
Simulation time	940956022 ps
CPU time	10.52 seconds
Started	Jan 10 12:43:19 PM PST 24
Finished	Jan 10 12:44:44 PM PST 24
Peak memory	201736 kb
Host	smart-95e9ed91-41c8-4ef1-b0a3-e2de8945ed3a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2146891275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2146891275
Directory	/workspace/23.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random.2133219662
Short name	T182
Test name
Test status
Simulation time	911531197 ps
CPU time	13.68 seconds
Started	Jan 10 12:43:14 PM PST 24
Finished	Jan 10 12:44:40 PM PST 24
Peak memory	201624 kb
Host	smart-c8bcf3e9-e42a-45ba-937a-f31945a7ef15
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2133219662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2133219662
Directory	/workspace/23.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3078533035
Short name	T660
Test name
Test status
Simulation time	2025826941 ps
CPU time	10.28 seconds
Started	Jan 10 12:43:10 PM PST 24
Finished	Jan 10 12:44:35 PM PST 24
Peak memory	201596 kb
Host	smart-e1f0dca7-48f3-4a7b-9298-f600db9581e6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078533035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3078533035
Directory	/workspace/23.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1697517457
Short name	T822
Test name
Test status
Simulation time	49881978436 ps
CPU time	123.85 seconds
Started	Jan 10 12:43:24 PM PST 24
Finished	Jan 10 12:46:45 PM PST 24
Peak memory	201788 kb
Host	smart-d06de190-4f1e-4284-9068-56b509d280ac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1697517457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1697517457
Directory	/workspace/23.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.783909473
Short name	T844
Test name
Test status
Simulation time	47961771 ps
CPU time	4.97 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:44:49 PM PST 24
Peak memory	201712 kb
Host	smart-6c50b72a-7110-4b07-9ce6-993ff75e365d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783909473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.783909473
Directory	/workspace/23.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_same_source.3755962545
Short name	T187
Test name
Test status
Simulation time	56138741 ps
CPU time	5.89 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:44:49 PM PST 24
Peak memory	201728 kb
Host	smart-654eaacc-1396-4000-8da9-bc55d64352c7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3755962545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3755962545
Directory	/workspace/23.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke.3147690329
Short name	T446
Test name
Test status
Simulation time	9534573 ps
CPU time	1.08 seconds
Started	Jan 10 12:43:12 PM PST 24
Finished	Jan 10 12:44:25 PM PST 24
Peak memory	201624 kb
Host	smart-02835de9-121a-49dd-9adb-beb812b2e4c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3147690329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3147690329
Directory	/workspace/23.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4194827416
Short name	T605
Test name
Test status
Simulation time	2692470991 ps
CPU time	8.55 seconds
Started	Jan 10 12:43:08 PM PST 24
Finished	Jan 10 12:44:30 PM PST 24
Peak memory	201672 kb
Host	smart-df6f3d02-de6c-43b5-a596-1d692126dff1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194827416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.4194827416
Directory	/workspace/23.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.329545535
Short name	T121
Test name
Test status
Simulation time	4724171699 ps
CPU time	6.82 seconds
Started	Jan 10 12:43:09 PM PST 24
Finished	Jan 10 12:44:28 PM PST 24
Peak memory	201664 kb
Host	smart-b7c1e220-3cc8-4aae-9146-c2e503c47863
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=329545535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.329545535
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3336048445
Short name	T691
Test name
Test status
Simulation time	15585026 ps
CPU time	1.1 seconds
Started	Jan 10 12:43:30 PM PST 24
Finished	Jan 10 12:44:49 PM PST 24
Peak memory	201648 kb
Host	smart-9a99d411-4bbe-4635-8f98-a9fca250c81a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336048445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3336048445
Directory	/workspace/23.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all.2882731750
Short name	T150
Test name
Test status
Simulation time	2824319923 ps
CPU time	31.81 seconds
Started	Jan 10 12:43:26 PM PST 24
Finished	Jan 10 12:45:16 PM PST 24
Peak memory	201804 kb
Host	smart-691b45a2-1d83-41fa-96d1-155c74098351
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2882731750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2882731750
Directory	/workspace/23.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.4292726256
Short name	T755
Test name
Test status
Simulation time	12492570615 ps
CPU time	32.01 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:45:12 PM PST 24
Peak memory	201764 kb
Host	smart-8d489dce-e50a-4c1e-ad47-48cb0d90fae3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4292726256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.4292726256
Directory	/workspace/23.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1115271364
Short name	T38
Test name
Test status
Simulation time	386091229 ps
CPU time	38.55 seconds
Started	Jan 10 12:43:30 PM PST 24
Finished	Jan 10 12:45:26 PM PST 24
Peak memory	203772 kb
Host	smart-8fa50844-fae0-43c1-8bdd-9d5a9ffa85ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1115271364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.1115271364
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.575016058
Short name	T668
Test name
Test status
Simulation time	5516668218 ps
CPU time	141.56 seconds
Started	Jan 10 12:43:20 PM PST 24
Finished	Jan 10 12:46:55 PM PST 24
Peak memory	206476 kb
Host	smart-6226eee6-6403-4590-b938-43f8f6ea1681
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=575016058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_res et_error.575016058
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2362606798
Short name	T48
Test name
Test status
Simulation time	65809254 ps
CPU time	3.86 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:44:40 PM PST 24
Peak memory	201716 kb
Host	smart-5171754d-50aa-428a-bc61-5040221221cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2362606798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2362606798
Directory	/workspace/23.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device.226836242
Short name	T709
Test name
Test status
Simulation time	71563273 ps
CPU time	8.55 seconds
Started	Jan 10 12:43:19 PM PST 24
Finished	Jan 10 12:44:42 PM PST 24
Peak memory	201540 kb
Host	smart-2aff61df-f859-4264-921b-7cb5d8f60f90
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=226836242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.226836242
Directory	/workspace/24.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1803830967
Short name	T424
Test name
Test status
Simulation time	20671816 ps
CPU time	2.09 seconds
Started	Jan 10 12:43:23 PM PST 24
Finished	Jan 10 12:44:39 PM PST 24
Peak memory	201724 kb
Host	smart-d268d596-f124-4fd7-83ad-8c0a840f35a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1803830967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1803830967
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_random.3616235558
Short name	T529
Test name
Test status
Simulation time	780387769 ps
CPU time	5.51 seconds
Started	Jan 10 12:43:20 PM PST 24
Finished	Jan 10 12:44:39 PM PST 24
Peak memory	201716 kb
Host	smart-d5ace9b3-d075-49f1-aa4f-0d560ccd11b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3616235558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3616235558
Directory	/workspace/24.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random.4175975024
Short name	T743
Test name
Test status
Simulation time	77302539 ps
CPU time	5.71 seconds
Started	Jan 10 12:43:24 PM PST 24
Finished	Jan 10 12:44:45 PM PST 24
Peak memory	201596 kb
Host	smart-3e3cc56b-bb93-47cb-8b7e-9173036cdb16
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4175975024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.4175975024
Directory	/workspace/24.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3880998332
Short name	T454
Test name
Test status
Simulation time	4328439238 ps
CPU time	16.94 seconds
Started	Jan 10 12:43:19 PM PST 24
Finished	Jan 10 12:44:50 PM PST 24
Peak memory	201660 kb
Host	smart-4e3e4155-a89b-410a-a9f0-03df8a19e89a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880998332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3880998332
Directory	/workspace/24.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.753258837
Short name	T261
Test name
Test status
Simulation time	2554756700 ps
CPU time	12.69 seconds
Started	Jan 10 12:43:28 PM PST 24
Finished	Jan 10 12:44:59 PM PST 24
Peak memory	201700 kb
Host	smart-33b35c4a-2259-4348-b257-03c0f0b209e5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=753258837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.753258837
Directory	/workspace/24.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1706471744
Short name	T694
Test name
Test status
Simulation time	23962671 ps
CPU time	1.3 seconds
Started	Jan 10 12:43:19 PM PST 24
Finished	Jan 10 12:44:34 PM PST 24
Peak memory	201720 kb
Host	smart-b02f25b0-3146-4f49-9023-f95c31ddea21
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706471744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1706471744
Directory	/workspace/24.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_same_source.2324201707
Short name	T560
Test name
Test status
Simulation time	72259734 ps
CPU time	4.57 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:44:40 PM PST 24
Peak memory	201740 kb
Host	smart-cc0989c8-0fac-4268-bc3c-323ebd82a668
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2324201707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2324201707
Directory	/workspace/24.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke.959105029
Short name	T136
Test name
Test status
Simulation time	78432455 ps
CPU time	1.66 seconds
Started	Jan 10 12:43:15 PM PST 24
Finished	Jan 10 12:44:32 PM PST 24
Peak memory	201744 kb
Host	smart-a4ac7051-3264-4c14-ae11-db6704f766ce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=959105029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.959105029
Directory	/workspace/24.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2172436858
Short name	T395
Test name
Test status
Simulation time	2194060791 ps
CPU time	8.81 seconds
Started	Jan 10 12:43:29 PM PST 24
Finished	Jan 10 12:44:53 PM PST 24
Peak memory	201732 kb
Host	smart-5e95c591-3d0c-4cb7-836d-96efbaa1e969
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172436858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2172436858
Directory	/workspace/24.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.405596942
Short name	T196
Test name
Test status
Simulation time	1138375740 ps
CPU time	5.53 seconds
Started	Jan 10 12:43:18 PM PST 24
Finished	Jan 10 12:44:37 PM PST 24
Peak memory	201720 kb
Host	smart-a38b2239-c505-4586-a10c-4a240196f665
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=405596942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.405596942
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1374330611
Short name	T753
Test name
Test status
Simulation time	9164832 ps
CPU time	1.3 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:44:37 PM PST 24
Peak memory	201648 kb
Host	smart-395ca747-ad91-4893-b088-f8f470115e54
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374330611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1374330611
Directory	/workspace/24.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all.434278908
Short name	T231
Test name
Test status
Simulation time	2517851041 ps
CPU time	32.46 seconds
Started	Jan 10 12:43:19 PM PST 24
Finished	Jan 10 12:45:05 PM PST 24
Peak memory	201700 kb
Host	smart-26124872-a682-47ed-a349-9f79a12d6e4c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=434278908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.434278908
Directory	/workspace/24.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.4189714960
Short name	T644
Test name
Test status
Simulation time	3771548629 ps
CPU time	53.21 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:45:31 PM PST 24
Peak memory	201772 kb
Host	smart-04f0f49a-38da-4cf8-ad3f-62c80a51d1bd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4189714960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.4189714960
Directory	/workspace/24.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3200145240
Short name	T550
Test name
Test status
Simulation time	7663912938 ps
CPU time	156.44 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:47:20 PM PST 24
Peak memory	207096 kb
Host	smart-7923dc0b-f985-488f-8c18-c03f7b6e1b2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3200145240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.3200145240
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2109162023
Short name	T356
Test name
Test status
Simulation time	148477310 ps
CPU time	20.52 seconds
Started	Jan 10 12:43:19 PM PST 24
Finished	Jan 10 12:44:54 PM PST 24
Peak memory	201572 kb
Host	smart-6db14f1d-34be-4b2a-a57c-49eb4a2861aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2109162023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.2109162023
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.95647789
Short name	T185
Test name
Test status
Simulation time	75973628 ps
CPU time	2.44 seconds
Started	Jan 10 12:43:20 PM PST 24
Finished	Jan 10 12:44:36 PM PST 24
Peak memory	201772 kb
Host	smart-d0e6c458-1f15-464b-868d-dbd13e04445b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=95647789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.95647789
Directory	/workspace/24.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device.1980052219
Short name	T171
Test name
Test status
Simulation time	982623116 ps
CPU time	4.15 seconds
Started	Jan 10 12:43:26 PM PST 24
Finished	Jan 10 12:44:48 PM PST 24
Peak memory	201640 kb
Host	smart-498f0e89-2754-47d0-b050-0e3bb979f0c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1980052219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1980052219
Directory	/workspace/25.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2823518614
Short name	T876
Test name
Test status
Simulation time	43554515850 ps
CPU time	248.82 seconds
Started	Jan 10 12:43:33 PM PST 24
Finished	Jan 10 12:48:57 PM PST 24
Peak memory	204068 kb
Host	smart-5de2e375-00e4-416b-b904-844d1ad9c44e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2823518614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.2823518614
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.362871946
Short name	T257
Test name
Test status
Simulation time	288061083 ps
CPU time	4.72 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:44:41 PM PST 24
Peak memory	201628 kb
Host	smart-33fa5bda-c867-49b9-a764-1b3bab1553d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=362871946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.362871946
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_random.3033965830
Short name	T452
Test name
Test status
Simulation time	141388036 ps
CPU time	4.4 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:44:50 PM PST 24
Peak memory	201636 kb
Host	smart-286babaf-9fd3-4725-a03a-9dcc01cc3b5d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3033965830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3033965830
Directory	/workspace/25.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random.3297618814
Short name	T808
Test name
Test status
Simulation time	25983417 ps
CPU time	2.15 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:44:40 PM PST 24
Peak memory	201724 kb
Host	smart-6a7ffdf7-6f64-4b59-a069-bfd846303229
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3297618814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3297618814
Directory	/workspace/25.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1983854559
Short name	T265
Test name
Test status
Simulation time	11508172632 ps
CPU time	51.91 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:45:28 PM PST 24
Peak memory	201820 kb
Host	smart-35755c9f-8d2d-45c4-992d-96c088e37dcf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983854559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1983854559
Directory	/workspace/25.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1064798653
Short name	T796
Test name
Test status
Simulation time	29075145789 ps
CPU time	140.71 seconds
Started	Jan 10 12:43:16 PM PST 24
Finished	Jan 10 12:46:50 PM PST 24
Peak memory	201688 kb
Host	smart-ffb11733-ce15-4dc9-ae1c-84c462ea7a51
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1064798653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1064798653
Directory	/workspace/25.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.55787524
Short name	T719
Test name
Test status
Simulation time	148943297 ps
CPU time	7.08 seconds
Started	Jan 10 12:43:23 PM PST 24
Finished	Jan 10 12:44:44 PM PST 24
Peak memory	201756 kb
Host	smart-bb513de3-7da7-4338-a638-af3965334a61
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55787524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.55787524
Directory	/workspace/25.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_same_source.3550917706
Short name	T396
Test name
Test status
Simulation time	1618389267 ps
CPU time	11.42 seconds
Started	Jan 10 12:43:18 PM PST 24
Finished	Jan 10 12:44:43 PM PST 24
Peak memory	201600 kb
Host	smart-9efc6e08-6ceb-4735-b1ed-7554248364da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3550917706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3550917706
Directory	/workspace/25.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke.550042476
Short name	T496
Test name
Test status
Simulation time	10159585 ps
CPU time	1.11 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:44:37 PM PST 24
Peak memory	201760 kb
Host	smart-9714479c-acc6-4942-9fc8-8fba5b40ac7d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=550042476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.550042476
Directory	/workspace/25.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2752716282
Short name	T697
Test name
Test status
Simulation time	5850048637 ps
CPU time	8.2 seconds
Started	Jan 10 12:43:17 PM PST 24
Finished	Jan 10 12:44:39 PM PST 24
Peak memory	201764 kb
Host	smart-7ab9aa0d-66c6-435c-9bc5-68c1b3ffd2e9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752716282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2752716282
Directory	/workspace/25.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1053562130
Short name	T583
Test name
Test status
Simulation time	759067452 ps
CPU time	5.63 seconds
Started	Jan 10 12:43:21 PM PST 24
Finished	Jan 10 12:44:40 PM PST 24
Peak memory	201736 kb
Host	smart-063d30b8-981f-434d-b04f-4f8711fda3c0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1053562130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1053562130
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2456896753
Short name	T761
Test name
Test status
Simulation time	16582959 ps
CPU time	1.29 seconds
Started	Jan 10 12:43:17 PM PST 24
Finished	Jan 10 12:44:32 PM PST 24
Peak memory	201644 kb
Host	smart-8eee8d6e-d9d4-4b74-b56f-46c14664b5cc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456896753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2456896753
Directory	/workspace/25.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all.493502728
Short name	T289
Test name
Test status
Simulation time	416799680 ps
CPU time	34.31 seconds
Started	Jan 10 12:43:20 PM PST 24
Finished	Jan 10 12:45:10 PM PST 24
Peak memory	201740 kb
Host	smart-ced496de-5551-457c-9e12-cdc4b278ac43
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=493502728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.493502728
Directory	/workspace/25.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.513181194
Short name	T728
Test name
Test status
Simulation time	486930077 ps
CPU time	3.54 seconds
Started	Jan 10 12:43:26 PM PST 24
Finished	Jan 10 12:44:47 PM PST 24
Peak memory	201632 kb
Host	smart-b3551ad3-51e0-406c-8b20-559f65be0590
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=513181194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.513181194
Directory	/workspace/25.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.2743816401
Short name	T243
Test name
Test status
Simulation time	437314947 ps
CPU time	68.64 seconds
Started	Jan 10 12:43:23 PM PST 24
Finished	Jan 10 12:45:46 PM PST 24
Peak memory	205624 kb
Host	smart-f6191042-3e9b-488b-a256-a23d88dd98da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2743816401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.2743816401
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.146037569
Short name	T741
Test name
Test status
Simulation time	213908691 ps
CPU time	39.46 seconds
Started	Jan 10 12:43:26 PM PST 24
Finished	Jan 10 12:45:23 PM PST 24
Peak memory	203112 kb
Host	smart-1883f142-d221-4f80-a15f-3f0cabdcea58
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=146037569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res et_error.146037569
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.490432177
Short name	T775
Test name
Test status
Simulation time	76557776 ps
CPU time	3.47 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:44:47 PM PST 24
Peak memory	201544 kb
Host	smart-024db6cb-5d5e-45aa-8ae4-e497e01c0ef6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=490432177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.490432177
Directory	/workspace/25.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3016963795
Short name	T627
Test name
Test status
Simulation time	89527556 ps
CPU time	9.63 seconds
Started	Jan 10 12:43:19 PM PST 24
Finished	Jan 10 12:44:43 PM PST 24
Peak memory	201636 kb
Host	smart-04577139-d617-40a9-bdcd-e813b78607a5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3016963795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3016963795
Directory	/workspace/26.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2164753263
Short name	T175
Test name
Test status
Simulation time	2317053451 ps
CPU time	17.44 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:45:00 PM PST 24
Peak memory	201700 kb
Host	smart-11f3d7de-66c2-4e5c-b899-ef0d5f92d33a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2164753263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.2164753263
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.214196481
Short name	T739
Test name
Test status
Simulation time	694142134 ps
CPU time	8.2 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:44:54 PM PST 24
Peak memory	201708 kb
Host	smart-8b0d6114-1bf0-48df-87a6-b84fa1d90f1a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=214196481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.214196481
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_random.1563512016
Short name	T662
Test name
Test status
Simulation time	172144632 ps
CPU time	6.97 seconds
Started	Jan 10 12:43:19 PM PST 24
Finished	Jan 10 12:44:40 PM PST 24
Peak memory	201708 kb
Host	smart-04d18a31-d1d4-4669-944d-05c1980baba0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1563512016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1563512016
Directory	/workspace/26.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random.26629309
Short name	T51
Test name
Test status
Simulation time	42233262 ps
CPU time	3.3 seconds
Started	Jan 10 12:43:24 PM PST 24
Finished	Jan 10 12:44:44 PM PST 24
Peak memory	201600 kb
Host	smart-93103f69-1fe3-4483-b409-7638bdc01cd5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=26629309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.26629309
Directory	/workspace/26.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1363191042
Short name	T542
Test name
Test status
Simulation time	25116014725 ps
CPU time	84.71 seconds
Started	Jan 10 12:43:28 PM PST 24
Finished	Jan 10 12:46:11 PM PST 24
Peak memory	201640 kb
Host	smart-61f87ec6-9e21-4bdb-92da-d84afa288b04
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363191042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1363191042
Directory	/workspace/26.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3589229596
Short name	T408
Test name
Test status
Simulation time	10215682051 ps
CPU time	48.11 seconds
Started	Jan 10 12:43:23 PM PST 24
Finished	Jan 10 12:45:26 PM PST 24
Peak memory	201696 kb
Host	smart-2092a822-3aaa-4a0b-8d89-1b252575049a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3589229596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3589229596
Directory	/workspace/26.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3298511151
Short name	T492
Test name
Test status
Simulation time	9284474 ps
CPU time	1.09 seconds
Started	Jan 10 12:43:24 PM PST 24
Finished	Jan 10 12:44:40 PM PST 24
Peak memory	201688 kb
Host	smart-6606e1c6-f2d0-4932-b2b6-cf896fd7f5f7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298511151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3298511151
Directory	/workspace/26.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_same_source.443803729
Short name	T178
Test name
Test status
Simulation time	2391045046 ps
CPU time	8.58 seconds
Started	Jan 10 12:43:24 PM PST 24
Finished	Jan 10 12:44:49 PM PST 24
Peak memory	201684 kb
Host	smart-2f9e9ba1-3512-410b-90bf-040e7bec504d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=443803729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.443803729
Directory	/workspace/26.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke.1762990109
Short name	T545
Test name
Test status
Simulation time	10547370 ps
CPU time	1.02 seconds
Started	Jan 10 12:43:22 PM PST 24
Finished	Jan 10 12:44:37 PM PST 24
Peak memory	201748 kb
Host	smart-64d692af-0204-4e44-8c2b-f8c32c833f2b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1762990109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1762990109
Directory	/workspace/26.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3993273947
Short name	T673
Test name
Test status
Simulation time	2935663484 ps
CPU time	11.78 seconds
Started	Jan 10 12:43:23 PM PST 24
Finished	Jan 10 12:44:48 PM PST 24
Peak memory	201828 kb
Host	smart-455a1f98-7815-4607-8bef-aa11fc587cb7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993273947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3993273947
Directory	/workspace/26.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.117492980
Short name	T861
Test name
Test status
Simulation time	11026674340 ps
CPU time	8.83 seconds
Started	Jan 10 12:43:28 PM PST 24
Finished	Jan 10 12:44:55 PM PST 24
Peak memory	201640 kb
Host	smart-e36d693b-1ec4-4ea6-beef-c050689e46a6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=117492980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.117492980
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3723393553
Short name	T333
Test name
Test status
Simulation time	8648095 ps
CPU time	1.04 seconds
Started	Jan 10 12:43:23 PM PST 24
Finished	Jan 10 12:44:38 PM PST 24
Peak memory	201752 kb
Host	smart-05c0f609-27b8-431d-b0ea-81fe8f5c0db7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723393553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3723393553
Directory	/workspace/26.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.3353301065
Short name	T587
Test name
Test status
Simulation time	3426518021 ps
CPU time	32.05 seconds
Started	Jan 10 12:43:30 PM PST 24
Finished	Jan 10 12:45:28 PM PST 24
Peak memory	201704 kb
Host	smart-de69dba9-eb9d-4636-a884-7454578a288d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3353301065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3353301065
Directory	/workspace/26.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3215993806
Short name	T385
Test name
Test status
Simulation time	11988646435 ps
CPU time	67.08 seconds
Started	Jan 10 12:43:24 PM PST 24
Finished	Jan 10 12:45:48 PM PST 24
Peak memory	201700 kb
Host	smart-ec776cb0-e854-4727-9a45-c37390c37aa3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3215993806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3215993806
Directory	/workspace/26.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.634475673
Short name	T548
Test name
Test status
Simulation time	1940842491 ps
CPU time	86.76 seconds
Started	Jan 10 12:43:28 PM PST 24
Finished	Jan 10 12:46:13 PM PST 24
Peak memory	203724 kb
Host	smart-0d4e186a-57d8-4104-b010-423cfe246809
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=634475673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand _reset.634475673
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1364123286
Short name	T572
Test name
Test status
Simulation time	48865145 ps
CPU time	1.13 seconds
Started	Jan 10 12:43:45 PM PST 24
Finished	Jan 10 12:45:04 PM PST 24
Peak memory	201612 kb
Host	smart-ffc4a000-f0ad-49c6-9563-b5af27daa853
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1364123286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1364123286
Directory	/workspace/26.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1225878541
Short name	T218
Test name
Test status
Simulation time	3821246880 ps
CPU time	10.66 seconds
Started	Jan 10 12:43:26 PM PST 24
Finished	Jan 10 12:44:54 PM PST 24
Peak memory	201788 kb
Host	smart-fd11bce5-4fca-4fae-8b12-8f9fadc84f30
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1225878541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1225878541
Directory	/workspace/27.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.565803217
Short name	T229
Test name
Test status
Simulation time	30952753348 ps
CPU time	197.33 seconds
Started	Jan 10 12:43:26 PM PST 24
Finished	Jan 10 12:48:01 PM PST 24
Peak memory	203056 kb
Host	smart-75d9f15f-17e9-4b37-9d4f-b658c1b82afc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=565803217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo w_rsp.565803217
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.745010012
Short name	T609
Test name
Test status
Simulation time	46592352 ps
CPU time	4.14 seconds
Started	Jan 10 12:43:23 PM PST 24
Finished	Jan 10 12:44:42 PM PST 24
Peak memory	201712 kb
Host	smart-6a372ba9-40dc-4711-ad16-2c9cb08778da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=745010012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.745010012
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_random.156562791
Short name	T498
Test name
Test status
Simulation time	917758300 ps
CPU time	10.23 seconds
Started	Jan 10 12:43:42 PM PST 24
Finished	Jan 10 12:45:08 PM PST 24
Peak memory	201560 kb
Host	smart-e7fb2be2-13d3-40f7-93d6-5b86be3e5d45
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=156562791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.156562791
Directory	/workspace/27.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random.2058150468
Short name	T666
Test name
Test status
Simulation time	44949229 ps
CPU time	5.06 seconds
Started	Jan 10 12:43:29 PM PST 24
Finished	Jan 10 12:44:50 PM PST 24
Peak memory	201720 kb
Host	smart-0e122b52-8c3a-4de9-9de6-9bc256ed1dc5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2058150468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2058150468
Directory	/workspace/27.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3078611419
Short name	T172
Test name
Test status
Simulation time	20937225495 ps
CPU time	94.02 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:46:17 PM PST 24
Peak memory	201800 kb
Host	smart-a9ea830e-d1c1-4310-bfb1-e981974d2c81
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078611419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3078611419
Directory	/workspace/27.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2441674236
Short name	T17
Test name
Test status
Simulation time	27322697476 ps
CPU time	119.03 seconds
Started	Jan 10 12:43:24 PM PST 24
Finished	Jan 10 12:46:38 PM PST 24
Peak memory	201672 kb
Host	smart-673f10e7-34d6-4ba1-baac-a16f3cb92c6f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2441674236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2441674236
Directory	/workspace/27.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.3189635173
Short name	T448
Test name
Test status
Simulation time	55717600 ps
CPU time	2.95 seconds
Started	Jan 10 12:43:28 PM PST 24
Finished	Jan 10 12:44:49 PM PST 24
Peak memory	201580 kb
Host	smart-202025ad-acd9-405d-8460-639eb133c8bc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189635173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3189635173
Directory	/workspace/27.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_same_source.3247088168
Short name	T54
Test name
Test status
Simulation time	872244024 ps
CPU time	1.9 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:44:48 PM PST 24
Peak memory	201752 kb
Host	smart-a87aa74e-acf2-47d0-876a-c1781ef6e84e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3247088168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3247088168
Directory	/workspace/27.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke.804677365
Short name	T434
Test name
Test status
Simulation time	9160075 ps
CPU time	1.12 seconds
Started	Jan 10 12:43:31 PM PST 24
Finished	Jan 10 12:44:50 PM PST 24
Peak memory	201668 kb
Host	smart-3412b948-2098-4a47-a0f3-f9a09cc5a255
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=804677365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.804677365
Directory	/workspace/27.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.4052706377
Short name	T359
Test name
Test status
Simulation time	2862620113 ps
CPU time	8.93 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:44:48 PM PST 24
Peak memory	201712 kb
Host	smart-23d9a4e4-5b51-4b8d-9c6b-2c39765cdfbf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052706377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4052706377
Directory	/workspace/27.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.613172515
Short name	T180
Test name
Test status
Simulation time	1375932189 ps
CPU time	8.18 seconds
Started	Jan 10 12:43:24 PM PST 24
Finished	Jan 10 12:44:49 PM PST 24
Peak memory	201612 kb
Host	smart-e332a6fa-4b88-44ee-b064-4dbec0087ab5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=613172515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.613172515
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2716192287
Short name	T346
Test name
Test status
Simulation time	10071410 ps
CPU time	1.24 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:44:47 PM PST 24
Peak memory	201728 kb
Host	smart-6baecb59-ca95-4e64-b356-0624506fbf31
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716192287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2716192287
Directory	/workspace/27.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all.327546731
Short name	T864
Test name
Test status
Simulation time	287260846 ps
CPU time	20.82 seconds
Started	Jan 10 12:43:23 PM PST 24
Finished	Jan 10 12:45:01 PM PST 24
Peak memory	201744 kb
Host	smart-c210d087-6c6b-40cd-bae1-b4466a0ae80e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=327546731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.327546731
Directory	/workspace/27.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3223812792
Short name	T456
Test name
Test status
Simulation time	14124671785 ps
CPU time	46.45 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:45:29 PM PST 24
Peak memory	201660 kb
Host	smart-e7d6a083-cf6f-4211-beeb-ba60b516e3a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3223812792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3223812792
Directory	/workspace/27.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1552519432
Short name	T98
Test name
Test status
Simulation time	1030529490 ps
CPU time	142.17 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:47:06 PM PST 24
Peak memory	205320 kb
Host	smart-8fe1aada-a862-49b9-8f70-542e10e73ba9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1552519432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.1552519432
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3542073920
Short name	T140
Test name
Test status
Simulation time	10751452308 ps
CPU time	84.52 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:46:07 PM PST 24
Peak memory	204168 kb
Host	smart-e787156e-18c8-48a8-988a-93af74a839b3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3542073920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.3542073920
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2304713691
Short name	T598
Test name
Test status
Simulation time	69175017 ps
CPU time	1.8 seconds
Started	Jan 10 12:43:26 PM PST 24
Finished	Jan 10 12:44:43 PM PST 24
Peak memory	201736 kb
Host	smart-b63c788d-bb44-4d45-ad85-e5083d3e254a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2304713691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2304713691
Directory	/workspace/27.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1132431301
Short name	T75
Test name
Test status
Simulation time	1162925439 ps
CPU time	10.68 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:44:54 PM PST 24
Peak memory	201624 kb
Host	smart-01306d2b-0e08-444a-83bd-604fc1f832c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1132431301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1132431301
Directory	/workspace/28.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1407252931
Short name	T212
Test name
Test status
Simulation time	20911958775 ps
CPU time	100.61 seconds
Started	Jan 10 12:43:28 PM PST 24
Finished	Jan 10 12:46:27 PM PST 24
Peak memory	201824 kb
Host	smart-1b000259-68aa-4085-9272-a95e4e4d6350
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1407252931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.1407252931
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.4158777904
Short name	T168
Test name
Test status
Simulation time	2367759719 ps
CPU time	9.09 seconds
Started	Jan 10 12:43:26 PM PST 24
Finished	Jan 10 12:44:53 PM PST 24
Peak memory	201688 kb
Host	smart-0d4bbfba-63b0-47d7-9acc-97b6aa2d85c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4158777904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.4158777904
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_random.1933110322
Short name	T331
Test name
Test status
Simulation time	1625840528 ps
CPU time	10.33 seconds
Started	Jan 10 12:43:29 PM PST 24
Finished	Jan 10 12:44:55 PM PST 24
Peak memory	201792 kb
Host	smart-647260d7-f025-4625-a983-32512cca71f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1933110322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1933110322
Directory	/workspace/28.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random.2880911145
Short name	T634
Test name
Test status
Simulation time	41436330 ps
CPU time	5.95 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:44:50 PM PST 24
Peak memory	201612 kb
Host	smart-28005487-8db7-411a-8571-0d53a42fd402
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2880911145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2880911145
Directory	/workspace/28.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3968320372
Short name	T256
Test name
Test status
Simulation time	3576172098 ps
CPU time	16.31 seconds
Started	Jan 10 12:43:34 PM PST 24
Finished	Jan 10 12:45:08 PM PST 24
Peak memory	201520 kb
Host	smart-8236b571-a47d-4bfc-a370-347ad38b2842
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968320372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3968320372
Directory	/workspace/28.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.464394906
Short name	T502
Test name
Test status
Simulation time	9728770958 ps
CPU time	56.55 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:45:37 PM PST 24
Peak memory	201684 kb
Host	smart-a6b1d152-2912-4cda-8808-5c3e894cefd9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=464394906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.464394906
Directory	/workspace/28.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.390166727
Short name	T126
Test name
Test status
Simulation time	39850586 ps
CPU time	3.2 seconds
Started	Jan 10 12:43:24 PM PST 24
Finished	Jan 10 12:44:42 PM PST 24
Peak memory	201736 kb
Host	smart-68d131f0-a0a9-4985-8471-477128ae0dba
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390166727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.390166727
Directory	/workspace/28.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_same_source.2796241341
Short name	T70
Test name
Test status
Simulation time	209234424 ps
CPU time	4.29 seconds
Started	Jan 10 12:43:36 PM PST 24
Finished	Jan 10 12:44:58 PM PST 24
Peak memory	201560 kb
Host	smart-bf5f186b-20f6-47db-8a12-59f154606ac8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2796241341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2796241341
Directory	/workspace/28.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke.2509337395
Short name	T616
Test name
Test status
Simulation time	8240587 ps
CPU time	0.97 seconds
Started	Jan 10 12:43:34 PM PST 24
Finished	Jan 10 12:44:52 PM PST 24
Peak memory	201548 kb
Host	smart-76964093-23af-4871-98b7-3096b0b6c81c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2509337395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2509337395
Directory	/workspace/28.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.671153842
Short name	T834
Test name
Test status
Simulation time	3254346757 ps
CPU time	9.22 seconds
Started	Jan 10 12:43:30 PM PST 24
Finished	Jan 10 12:44:58 PM PST 24
Peak memory	201808 kb
Host	smart-4ef76b71-042e-4f50-98ac-d91e78d04be4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=671153842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.671153842
Directory	/workspace/28.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2742210152
Short name	T593
Test name
Test status
Simulation time	2258843898 ps
CPU time	5.35 seconds
Started	Jan 10 12:43:31 PM PST 24
Finished	Jan 10 12:44:54 PM PST 24
Peak memory	201676 kb
Host	smart-0bab468a-e3c2-403c-870f-b4c2e58c9eda
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2742210152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2742210152
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3209663879
Short name	T2
Test name
Test status
Simulation time	21120402 ps
CPU time	0.95 seconds
Started	Jan 10 12:43:32 PM PST 24
Finished	Jan 10 12:44:48 PM PST 24
Peak memory	201588 kb
Host	smart-66b183ef-b0c1-4608-bf82-d3a60fbcebfc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209663879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3209663879
Directory	/workspace/28.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all.3285688466
Short name	T418
Test name
Test status
Simulation time	195865260 ps
CPU time	20.66 seconds
Started	Jan 10 12:43:28 PM PST 24
Finished	Jan 10 12:45:07 PM PST 24
Peak memory	201608 kb
Host	smart-286ee381-071e-41f5-83ef-67f6c79e3ac5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3285688466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3285688466
Directory	/workspace/28.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.535864343
Short name	T853
Test name
Test status
Simulation time	3540345463 ps
CPU time	19.35 seconds
Started	Jan 10 12:43:31 PM PST 24
Finished	Jan 10 12:45:06 PM PST 24
Peak memory	201644 kb
Host	smart-6a763f14-d84a-425b-9dda-0f5ed0a2fa7c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=535864343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.535864343
Directory	/workspace/28.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1173089399
Short name	T553
Test name
Test status
Simulation time	237855221 ps
CPU time	16.34 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:44:59 PM PST 24
Peak memory	203856 kb
Host	smart-adfe20b6-491b-4d9f-867c-62b43b709a82
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1173089399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.1173089399
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3342625419
Short name	T245
Test name
Test status
Simulation time	529441117 ps
CPU time	62.73 seconds
Started	Jan 10 12:43:27 PM PST 24
Finished	Jan 10 12:45:45 PM PST 24
Peak memory	203828 kb
Host	smart-24365cfc-6cbd-4d12-ba9a-c342d7a50de1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3342625419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.3342625419
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.1359560832
Short name	T571
Test name
Test status
Simulation time	158555932 ps
CPU time	3.23 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:44:47 PM PST 24
Peak memory	201612 kb
Host	smart-60261604-19f1-4cd9-93c7-2efaa0f857be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1359560832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1359560832
Directory	/workspace/28.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device.3250061439
Short name	T404
Test name
Test status
Simulation time	1167096406 ps
CPU time	20.59 seconds
Started	Jan 10 12:43:32 PM PST 24
Finished	Jan 10 12:45:08 PM PST 24
Peak memory	201580 kb
Host	smart-848a9e14-6553-4906-9e60-4e02d4c18dbb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3250061439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3250061439
Directory	/workspace/29.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.2940517671
Short name	T179
Test name
Test status
Simulation time	24286248836 ps
CPU time	23.79 seconds
Started	Jan 10 12:43:35 PM PST 24
Finished	Jan 10 12:45:14 PM PST 24
Peak memory	201640 kb
Host	smart-98221cbd-0a16-4d14-a999-72c68bf586c5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2940517671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.2940517671
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1855025814
Short name	T262
Test name
Test status
Simulation time	68768763 ps
CPU time	1.9 seconds
Started	Jan 10 12:43:38 PM PST 24
Finished	Jan 10 12:44:55 PM PST 24
Peak memory	201636 kb
Host	smart-137b54b2-91a3-4c47-97eb-a0799b4bf0dd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1855025814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1855025814
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_random.3961697128
Short name	T426
Test name
Test status
Simulation time	137623007 ps
CPU time	2.44 seconds
Started	Jan 10 12:43:40 PM PST 24
Finished	Jan 10 12:44:57 PM PST 24
Peak memory	201564 kb
Host	smart-fde75f52-b3db-46d4-a8d3-a4997fe3673a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3961697128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3961697128
Directory	/workspace/29.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random.1055889974
Short name	T429
Test name
Test status
Simulation time	869059184 ps
CPU time	6.89 seconds
Started	Jan 10 12:43:25 PM PST 24
Finished	Jan 10 12:44:51 PM PST 24
Peak memory	201700 kb
Host	smart-f1fd73d9-3183-4839-a1ba-7315a8374ee3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1055889974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1055889974
Directory	/workspace/29.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.240658188
Short name	T703
Test name
Test status
Simulation time	11318076110 ps
CPU time	45.27 seconds
Started	Jan 10 12:43:30 PM PST 24
Finished	Jan 10 12:45:33 PM PST 24
Peak memory	201688 kb
Host	smart-aed5048b-bf6d-4e36-9b87-604428b12a26
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=240658188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.240658188
Directory	/workspace/29.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2208808044
Short name	T815
Test name
Test status
Simulation time	15812964222 ps
CPU time	24.98 seconds
Started	Jan 10 12:43:45 PM PST 24
Finished	Jan 10 12:45:25 PM PST 24
Peak memory	201692 kb
Host	smart-83b35b3a-4973-4954-8330-4952ef2b9b2e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2208808044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2208808044
Directory	/workspace/29.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.1772278859
Short name	T269
Test name
Test status
Simulation time	110994842 ps
CPU time	9.44 seconds
Started	Jan 10 12:43:28 PM PST 24
Finished	Jan 10 12:44:56 PM PST 24
Peak memory	201616 kb
Host	smart-2c91269c-6627-4aff-97da-d401402112e3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772278859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1772278859
Directory	/workspace/29.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_same_source.1437019542
Short name	T700
Test name
Test status
Simulation time	218454890 ps
CPU time	1.53 seconds
Started	Jan 10 12:43:35 PM PST 24
Finished	Jan 10 12:44:51 PM PST 24
Peak memory	201560 kb
Host	smart-1175ed62-7560-45d6-aa96-461c1cfa37de
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1437019542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1437019542
Directory	/workspace/29.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke.4160675892
Short name	T383
Test name
Test status
Simulation time	8634568 ps
CPU time	1.11 seconds
Started	Jan 10 12:43:28 PM PST 24
Finished	Jan 10 12:44:48 PM PST 24
Peak memory	201596 kb
Host	smart-986f6f85-3aaf-40d1-8bcb-bd25c8f498d1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4160675892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4160675892
Directory	/workspace/29.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2974186013
Short name	T345
Test name
Test status
Simulation time	3549113733 ps
CPU time	5.93 seconds
Started	Jan 10 12:43:23 PM PST 24
Finished	Jan 10 12:44:43 PM PST 24
Peak memory	201680 kb
Host	smart-9891544c-8832-42a1-9931-0858620162fb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974186013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2974186013
Directory	/workspace/29.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1987211253
Short name	T649
Test name
Test status
Simulation time	2089450950 ps
CPU time	9.51 seconds
Started	Jan 10 12:43:34 PM PST 24
Finished	Jan 10 12:45:01 PM PST 24
Peak memory	201488 kb
Host	smart-cfbed1db-c692-4c04-8dee-833726516789
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1987211253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1987211253
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2748767501
Short name	T889
Test name
Test status
Simulation time	10178757 ps
CPU time	1.18 seconds
Started	Jan 10 12:43:35 PM PST 24
Finished	Jan 10 12:44:51 PM PST 24
Peak memory	201724 kb
Host	smart-31b86e6b-ab6d-4b81-b4ec-80781e3185e4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748767501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2748767501
Directory	/workspace/29.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all.711815227
Short name	T330
Test name
Test status
Simulation time	12897430783 ps
CPU time	65.17 seconds
Started	Jan 10 12:44:05 PM PST 24
Finished	Jan 10 12:46:26 PM PST 24
Peak memory	203820 kb
Host	smart-321fc8a9-25d4-4264-9929-4afe6a8e83a4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=711815227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.711815227
Directory	/workspace/29.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.819703665
Short name	T633
Test name
Test status
Simulation time	521816079 ps
CPU time	9.91 seconds
Started	Jan 10 12:43:39 PM PST 24
Finished	Jan 10 12:45:03 PM PST 24
Peak memory	201728 kb
Host	smart-2c374c43-2752-4fab-83fd-9b2d6ab5597d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=819703665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.819703665
Directory	/workspace/29.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3039707575
Short name	T826
Test name
Test status
Simulation time	597522965 ps
CPU time	63.5 seconds
Started	Jan 10 12:43:34 PM PST 24
Finished	Jan 10 12:45:53 PM PST 24
Peak memory	203960 kb
Host	smart-301c34c7-52c0-4474-8114-225c47d99a77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3039707575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.3039707575
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2703126123
Short name	T238
Test name
Test status
Simulation time	2921811093 ps
CPU time	43.99 seconds
Started	Jan 10 12:43:40 PM PST 24
Finished	Jan 10 12:45:39 PM PST 24
Peak memory	203752 kb
Host	smart-72f881f8-d01a-41fa-b17f-4a9f59cff473
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2703126123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.2703126123
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2167152330
Short name	T477
Test name
Test status
Simulation time	442538179 ps
CPU time	5.63 seconds
Started	Jan 10 12:43:42 PM PST 24
Finished	Jan 10 12:45:03 PM PST 24
Peak memory	201556 kb
Host	smart-94eaec34-486e-4395-96f1-350a076f03d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2167152330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2167152330
Directory	/workspace/29.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device.3869144867
Short name	T112
Test name
Test status
Simulation time	3901482209 ps
CPU time	20.94 seconds
Started	Jan 10 12:42:11 PM PST 24
Finished	Jan 10 12:43:44 PM PST 24
Peak memory	201796 kb
Host	smart-869498c6-ff7c-4cba-8638-e979e3fa57b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3869144867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3869144867
Directory	/workspace/3.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3379867566
Short name	T227
Test name
Test status
Simulation time	339665258115 ps
CPU time	302 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:48:24 PM PST 24
Peak memory	204172 kb
Host	smart-968336c7-5030-4991-9070-916d8b52ddf8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3379867566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.3379867566
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.854629694
Short name	T354
Test name
Test status
Simulation time	59452668 ps
CPU time	6.12 seconds
Started	Jan 10 12:42:14 PM PST 24
Finished	Jan 10 12:43:32 PM PST 24
Peak memory	201712 kb
Host	smart-dc1e47d4-71bc-4905-b592-660db2acf9c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=854629694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.854629694
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_random.358265709
Short name	T142
Test name
Test status
Simulation time	43897083 ps
CPU time	5.11 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:43:27 PM PST 24
Peak memory	201620 kb
Host	smart-81033fe0-bae0-4f74-adf4-39d6aa863a9e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=358265709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.358265709
Directory	/workspace/3.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random.3425277861
Short name	T341
Test name
Test status
Simulation time	703488485 ps
CPU time	6.06 seconds
Started	Jan 10 12:42:10 PM PST 24
Finished	Jan 10 12:43:29 PM PST 24
Peak memory	201676 kb
Host	smart-ee59c5a4-69b7-4210-a1e5-8742e078d8c1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3425277861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3425277861
Directory	/workspace/3.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3895087258
Short name	T783
Test name
Test status
Simulation time	48332555786 ps
CPU time	83.39 seconds
Started	Jan 10 12:42:11 PM PST 24
Finished	Jan 10 12:44:47 PM PST 24
Peak memory	201760 kb
Host	smart-d70a69ed-5952-45ae-b148-ccfa7a2cf0d5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895087258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3895087258
Directory	/workspace/3.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2756466695
Short name	T618
Test name
Test status
Simulation time	3463413404 ps
CPU time	23.74 seconds
Started	Jan 10 12:42:11 PM PST 24
Finished	Jan 10 12:43:48 PM PST 24
Peak memory	201752 kb
Host	smart-b1fd4171-d105-475c-b5aa-29ea5c32fe9b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2756466695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2756466695
Directory	/workspace/3.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1998210411
Short name	T820
Test name
Test status
Simulation time	18476913 ps
CPU time	2.1 seconds
Started	Jan 10 12:42:05 PM PST 24
Finished	Jan 10 12:43:21 PM PST 24
Peak memory	201716 kb
Host	smart-764cae9e-8143-4583-bd7c-451611b6a6f9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998210411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1998210411
Directory	/workspace/3.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_same_source.2418175806
Short name	T84
Test name
Test status
Simulation time	130139127 ps
CPU time	2.15 seconds
Started	Jan 10 12:42:10 PM PST 24
Finished	Jan 10 12:43:25 PM PST 24
Peak memory	201720 kb
Host	smart-d871328c-1b24-4f31-96d6-a070dfe1bdf2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2418175806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2418175806
Directory	/workspace/3.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke.2771172579
Short name	T466
Test name
Test status
Simulation time	11857394 ps
CPU time	1.29 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:43:23 PM PST 24
Peak memory	201716 kb
Host	smart-f90c5df1-e688-4ff7-a0c7-eacb98599813
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2771172579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2771172579
Directory	/workspace/3.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3404336423
Short name	T363
Test name
Test status
Simulation time	1466977166 ps
CPU time	6.82 seconds
Started	Jan 10 12:42:12 PM PST 24
Finished	Jan 10 12:43:31 PM PST 24
Peak memory	201696 kb
Host	smart-829b0238-0ee3-491a-ad5b-7e9cf16900e5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404336423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3404336423
Directory	/workspace/3.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1436062584
Short name	T782
Test name
Test status
Simulation time	4318652688 ps
CPU time	12.48 seconds
Started	Jan 10 12:42:10 PM PST 24
Finished	Jan 10 12:43:35 PM PST 24
Peak memory	201756 kb
Host	smart-63dde1c6-90d3-4aa3-839f-b430faa3f5c6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1436062584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1436062584
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3507298018
Short name	T526
Test name
Test status
Simulation time	8165218 ps
CPU time	1.04 seconds
Started	Jan 10 12:42:08 PM PST 24
Finished	Jan 10 12:43:23 PM PST 24
Peak memory	201740 kb
Host	smart-b09b9ea9-ec2f-40a8-be17-3ed919fbff7d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507298018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3507298018
Directory	/workspace/3.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all.2148877499
Short name	T425
Test name
Test status
Simulation time	5382484429 ps
CPU time	62.66 seconds
Started	Jan 10 12:42:08 PM PST 24
Finished	Jan 10 12:44:25 PM PST 24
Peak memory	201676 kb
Host	smart-895a1a56-ad04-4d98-beb4-dd566e43227c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2148877499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2148877499
Directory	/workspace/3.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3272399866
Short name	T444
Test name
Test status
Simulation time	199272480 ps
CPU time	10.09 seconds
Started	Jan 10 12:42:08 PM PST 24
Finished	Jan 10 12:43:31 PM PST 24
Peak memory	201720 kb
Host	smart-30a816ab-5466-4b73-8b2b-7016cce440fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3272399866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3272399866
Directory	/workspace/3.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2191508113
Short name	T708
Test name
Test status
Simulation time	2394476002 ps
CPU time	83.19 seconds
Started	Jan 10 12:42:11 PM PST 24
Finished	Jan 10 12:44:47 PM PST 24
Peak memory	205672 kb
Host	smart-87d54c5f-6887-45d3-98de-a895130d933a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2191508113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.2191508113
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.636374806
Short name	T160
Test name
Test status
Simulation time	1310335599 ps
CPU time	7.77 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:43:30 PM PST 24
Peak memory	201716 kb
Host	smart-49432633-053a-46f0-9a65-5ed8f74655e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=636374806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.636374806
Directory	/workspace/3.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3087155770
Short name	T632
Test name
Test status
Simulation time	45753773 ps
CPU time	7.3 seconds
Started	Jan 10 12:43:35 PM PST 24
Finished	Jan 10 12:44:57 PM PST 24
Peak memory	201732 kb
Host	smart-5de65198-275b-4d3f-b5ed-debf20bf4e92
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3087155770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3087155770
Directory	/workspace/30.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.804386738
Short name	T223
Test name
Test status
Simulation time	41820585211 ps
CPU time	169.02 seconds
Started	Jan 10 12:43:44 PM PST 24
Finished	Jan 10 12:47:48 PM PST 24
Peak memory	202816 kb
Host	smart-0e8cb73e-2d70-40c7-a87b-05961bb6f691
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=804386738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slo w_rsp.804386738
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1650362451
Short name	T93
Test name
Test status
Simulation time	441552967 ps
CPU time	2.43 seconds
Started	Jan 10 12:43:43 PM PST 24
Finished	Jan 10 12:45:01 PM PST 24
Peak memory	201736 kb
Host	smart-35cbeb6a-dca4-410a-898d-0c185add95c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1650362451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.1650362451
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_random.3939591946
Short name	T882
Test name
Test status
Simulation time	112410418 ps
CPU time	4.36 seconds
Started	Jan 10 12:43:45 PM PST 24
Finished	Jan 10 12:45:04 PM PST 24
Peak memory	201668 kb
Host	smart-cf962e7a-c515-4018-b933-7dd9defae75e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3939591946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3939591946
Directory	/workspace/30.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random.1602628720
Short name	T857
Test name
Test status
Simulation time	604362602 ps
CPU time	2.57 seconds
Started	Jan 10 12:43:46 PM PST 24
Finished	Jan 10 12:45:04 PM PST 24
Peak memory	201708 kb
Host	smart-4680e0e0-8f25-48c1-9b60-6877ff59522c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1602628720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1602628720
Directory	/workspace/30.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1032702473
Short name	T389
Test name
Test status
Simulation time	46202473799 ps
CPU time	113.99 seconds
Started	Jan 10 12:43:49 PM PST 24
Finished	Jan 10 12:46:57 PM PST 24
Peak memory	201576 kb
Host	smart-abe4d12c-5917-4fe2-9d98-da03931b2de6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032702473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1032702473
Directory	/workspace/30.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3109810722
Short name	T159
Test name
Test status
Simulation time	13207283225 ps
CPU time	85.39 seconds
Started	Jan 10 12:43:37 PM PST 24
Finished	Jan 10 12:46:18 PM PST 24
Peak memory	201828 kb
Host	smart-d06b398e-19a1-4a92-901b-b993627e5ca8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3109810722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3109810722
Directory	/workspace/30.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.200361492
Short name	T736
Test name
Test status
Simulation time	54663982 ps
CPU time	1.86 seconds
Started	Jan 10 12:43:35 PM PST 24
Finished	Jan 10 12:44:52 PM PST 24
Peak memory	201756 kb
Host	smart-2b366a9e-a9c3-49b4-8676-fdb797c04425
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200361492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.200361492
Directory	/workspace/30.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_same_source.4011676633
Short name	T534
Test name
Test status
Simulation time	1664173930 ps
CPU time	5.5 seconds
Started	Jan 10 12:43:31 PM PST 24
Finished	Jan 10 12:44:54 PM PST 24
Peak memory	201584 kb
Host	smart-b369dcd8-dcd8-473d-8ac4-d7dfcf70db36
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4011676633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.4011676633
Directory	/workspace/30.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke.654177275
Short name	T624
Test name
Test status
Simulation time	98043971 ps
CPU time	1.36 seconds
Started	Jan 10 12:43:35 PM PST 24
Finished	Jan 10 12:44:51 PM PST 24
Peak memory	201588 kb
Host	smart-1b31e5db-6a9d-4b75-890a-35950711f2b4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=654177275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.654177275
Directory	/workspace/30.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1193152645
Short name	T364
Test name
Test status
Simulation time	1926386660 ps
CPU time	8.02 seconds
Started	Jan 10 12:43:46 PM PST 24
Finished	Jan 10 12:45:09 PM PST 24
Peak memory	201628 kb
Host	smart-dcc6cf7a-681a-4eaf-b253-9ccc25debeed
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193152645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1193152645
Directory	/workspace/30.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1059379776
Short name	T789
Test name
Test status
Simulation time	1890125439 ps
CPU time	12.69 seconds
Started	Jan 10 12:43:40 PM PST 24
Finished	Jan 10 12:45:08 PM PST 24
Peak memory	201736 kb
Host	smart-85867c22-3b07-4e73-ba2d-44422e3e2e02
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1059379776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1059379776
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2755352276
Short name	T517
Test name
Test status
Simulation time	13112090 ps
CPU time	1.18 seconds
Started	Jan 10 12:43:45 PM PST 24
Finished	Jan 10 12:45:01 PM PST 24
Peak memory	201756 kb
Host	smart-029dcc74-7919-4a96-abd7-ba7ca7ab9684
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755352276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2755352276
Directory	/workspace/30.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all.1773010333
Short name	T885
Test name
Test status
Simulation time	5999549 ps
CPU time	0.72 seconds
Started	Jan 10 12:43:43 PM PST 24
Finished	Jan 10 12:44:59 PM PST 24
Peak memory	193360 kb
Host	smart-83ded9f4-fa3e-4254-a799-f066a49c355b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1773010333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1773010333
Directory	/workspace/30.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2885956312
Short name	T326
Test name
Test status
Simulation time	17836211938 ps
CPU time	62.36 seconds
Started	Jan 10 12:43:45 PM PST 24
Finished	Jan 10 12:46:03 PM PST 24
Peak memory	201560 kb
Host	smart-3637da0c-c078-44cb-a3d6-68352102f73a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2885956312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2885956312
Directory	/workspace/30.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.485753259
Short name	T176
Test name
Test status
Simulation time	7262716130 ps
CPU time	125.46 seconds
Started	Jan 10 12:43:48 PM PST 24
Finished	Jan 10 12:47:08 PM PST 24
Peak memory	204248 kb
Host	smart-77ef59b2-0a57-424e-a74f-ea6421f9619b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=485753259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand _reset.485753259
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2537804533
Short name	T790
Test name
Test status
Simulation time	6714001974 ps
CPU time	125.29 seconds
Started	Jan 10 12:43:38 PM PST 24
Finished	Jan 10 12:46:59 PM PST 24
Peak memory	204712 kb
Host	smart-e1f1be8f-cf13-44ed-9b27-708107fbe2e4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2537804533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.2537804533
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.2077107828
Short name	T800
Test name
Test status
Simulation time	27003152 ps
CPU time	3.05 seconds
Started	Jan 10 12:44:03 PM PST 24
Finished	Jan 10 12:45:22 PM PST 24
Peak memory	201488 kb
Host	smart-5d6d5d5b-d89e-4f8f-8f76-9f6776538a08
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2077107828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2077107828
Directory	/workspace/30.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3281229490
Short name	T735
Test name
Test status
Simulation time	56189164 ps
CPU time	1.7 seconds
Started	Jan 10 12:43:38 PM PST 24
Finished	Jan 10 12:44:55 PM PST 24
Peak memory	201608 kb
Host	smart-a43a6871-c403-4537-b625-153bbde1df5e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3281229490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3281229490
Directory	/workspace/31.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.286279174
Short name	T143
Test name
Test status
Simulation time	7041408980 ps
CPU time	48.79 seconds
Started	Jan 10 12:43:35 PM PST 24
Finished	Jan 10 12:45:39 PM PST 24
Peak memory	201684 kb
Host	smart-bd0ec8b6-bd03-4014-b7b6-7f2dcea731db
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=286279174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo w_rsp.286279174
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.963351054
Short name	T546
Test name
Test status
Simulation time	299316902 ps
CPU time	1.48 seconds
Started	Jan 10 12:43:32 PM PST 24
Finished	Jan 10 12:44:48 PM PST 24
Peak memory	201724 kb
Host	smart-23d58e41-4451-4587-bc1d-6aae1da34a3d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=963351054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.963351054
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_random.592798796
Short name	T837
Test name
Test status
Simulation time	19102002 ps
CPU time	1.32 seconds
Started	Jan 10 12:43:40 PM PST 24
Finished	Jan 10 12:44:56 PM PST 24
Peak memory	201672 kb
Host	smart-60455093-ef36-4ec6-8a82-46e3f2adc81e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=592798796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.592798796
Directory	/workspace/31.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random.1603455591
Short name	T695
Test name
Test status
Simulation time	274031238 ps
CPU time	6.34 seconds
Started	Jan 10 12:43:57 PM PST 24
Finished	Jan 10 12:45:18 PM PST 24
Peak memory	201608 kb
Host	smart-b6d262ad-42b6-4c29-98c5-e2326eadd486
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1603455591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1603455591
Directory	/workspace/31.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.2248105712
Short name	T610
Test name
Test status
Simulation time	98665764826 ps
CPU time	86.9 seconds
Started	Jan 10 12:43:45 PM PST 24
Finished	Jan 10 12:46:27 PM PST 24
Peak memory	201764 kb
Host	smart-566431a7-835d-40d8-a58c-44bedcc1459c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248105712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2248105712
Directory	/workspace/31.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.48891622
Short name	T122
Test name
Test status
Simulation time	29993635818 ps
CPU time	183.31 seconds
Started	Jan 10 12:43:46 PM PST 24
Finished	Jan 10 12:48:04 PM PST 24
Peak memory	201796 kb
Host	smart-696331c4-eef2-4922-8285-a29036f72896
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=48891622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.48891622
Directory	/workspace/31.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3589459974
Short name	T320
Test name
Test status
Simulation time	68046847 ps
CPU time	1.66 seconds
Started	Jan 10 12:43:43 PM PST 24
Finished	Jan 10 12:45:00 PM PST 24
Peak memory	201732 kb
Host	smart-e276087b-e154-4114-98e3-5c8487bb7318
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589459974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3589459974
Directory	/workspace/31.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_same_source.3734535725
Short name	T279
Test name
Test status
Simulation time	111276197 ps
CPU time	4.87 seconds
Started	Jan 10 12:43:44 PM PST 24
Finished	Jan 10 12:45:05 PM PST 24
Peak memory	201740 kb
Host	smart-6b086180-103a-4ea2-be79-07ceabad6721
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3734535725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3734535725
Directory	/workspace/31.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke.2459071968
Short name	T361
Test name
Test status
Simulation time	45803951 ps
CPU time	1.43 seconds
Started	Jan 10 12:43:35 PM PST 24
Finished	Jan 10 12:44:51 PM PST 24
Peak memory	201724 kb
Host	smart-31ecbb44-604b-458b-82f5-62b74a5af4d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2459071968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2459071968
Directory	/workspace/31.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2087990336
Short name	T405
Test name
Test status
Simulation time	1245090271 ps
CPU time	6.01 seconds
Started	Jan 10 12:43:40 PM PST 24
Finished	Jan 10 12:45:01 PM PST 24
Peak memory	201608 kb
Host	smart-0bf1e8cc-f5d6-4f4b-a1ca-aa926cf2d632
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087990336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2087990336
Directory	/workspace/31.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2826224344
Short name	T324
Test name
Test status
Simulation time	2175360506 ps
CPU time	5.99 seconds
Started	Jan 10 12:43:37 PM PST 24
Finished	Jan 10 12:44:58 PM PST 24
Peak memory	201708 kb
Host	smart-85a553e0-5556-4491-b35d-e0b4b31d45bf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2826224344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2826224344
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.432590452
Short name	T749
Test name
Test status
Simulation time	9789380 ps
CPU time	1.17 seconds
Started	Jan 10 12:43:41 PM PST 24
Finished	Jan 10 12:44:58 PM PST 24
Peak memory	201632 kb
Host	smart-8152625a-0bb1-4d73-9c1e-711d787c5eec
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432590452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.432590452
Directory	/workspace/31.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.199772038
Short name	T884
Test name
Test status
Simulation time	97217863 ps
CPU time	11.8 seconds
Started	Jan 10 12:43:36 PM PST 24
Finished	Jan 10 12:45:05 PM PST 24
Peak memory	201728 kb
Host	smart-291ae229-68f2-40d3-95bd-0a58610971f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=199772038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.199772038
Directory	/workspace/31.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2216867828
Short name	T191
Test name
Test status
Simulation time	21218544093 ps
CPU time	74.06 seconds
Started	Jan 10 12:43:44 PM PST 24
Finished	Jan 10 12:46:13 PM PST 24
Peak memory	202716 kb
Host	smart-c43153ed-2c0e-4567-81a0-ee4f91da88c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2216867828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2216867828
Directory	/workspace/31.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2989786082
Short name	T162
Test name
Test status
Simulation time	8321493500 ps
CPU time	43.99 seconds
Started	Jan 10 12:43:37 PM PST 24
Finished	Jan 10 12:45:36 PM PST 24
Peak memory	204184 kb
Host	smart-d736e254-a8e4-41b5-a6c8-d254bd1d67ff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2989786082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.2989786082
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3341133370
Short name	T873
Test name
Test status
Simulation time	1711654225 ps
CPU time	67.62 seconds
Started	Jan 10 12:43:37 PM PST 24
Finished	Jan 10 12:46:00 PM PST 24
Peak memory	204668 kb
Host	smart-548019a1-b6d9-49d9-8cc3-0a380dd68ff9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3341133370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.3341133370
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1392866146
Short name	T316
Test name
Test status
Simulation time	115433402 ps
CPU time	1.41 seconds
Started	Jan 10 12:43:39 PM PST 24
Finished	Jan 10 12:44:55 PM PST 24
Peak memory	201688 kb
Host	smart-7eb6960a-87f3-4c12-b397-f9741e99a68c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1392866146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1392866146
Directory	/workspace/31.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3663034059
Short name	T879
Test name
Test status
Simulation time	68037154 ps
CPU time	11.59 seconds
Started	Jan 10 12:43:40 PM PST 24
Finished	Jan 10 12:45:07 PM PST 24
Peak memory	201672 kb
Host	smart-cb2cc943-817a-4a50-9747-800f102c7400
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3663034059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3663034059
Directory	/workspace/32.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.75946304
Short name	T210
Test name
Test status
Simulation time	18167020421 ps
CPU time	110.93 seconds
Started	Jan 10 12:43:38 PM PST 24
Finished	Jan 10 12:46:44 PM PST 24
Peak memory	201720 kb
Host	smart-be2f75e9-c178-4f62-aa3d-19bd60881f5d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=75946304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow _rsp.75946304
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1467003452
Short name	T547
Test name
Test status
Simulation time	521908811 ps
CPU time	2.85 seconds
Started	Jan 10 12:43:53 PM PST 24
Finished	Jan 10 12:45:10 PM PST 24
Peak memory	201972 kb
Host	smart-a2d348ff-9b7a-49b3-976e-14019bf26997
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1467003452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1467003452
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_random.3974375258
Short name	T169
Test name
Test status
Simulation time	19941839 ps
CPU time	1.81 seconds
Started	Jan 10 12:43:41 PM PST 24
Finished	Jan 10 12:44:58 PM PST 24
Peak memory	201636 kb
Host	smart-e8342b09-d59a-498e-b358-e2e236dd26d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3974375258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3974375258
Directory	/workspace/32.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random.230310890
Short name	T258
Test name
Test status
Simulation time	768921724 ps
CPU time	9.24 seconds
Started	Jan 10 12:43:32 PM PST 24
Finished	Jan 10 12:44:57 PM PST 24
Peak memory	201752 kb
Host	smart-a7cfdac9-2dd3-450a-8b0f-91e4d830f020
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=230310890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.230310890
Directory	/workspace/32.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1805595904
Short name	T568
Test name
Test status
Simulation time	69055328185 ps
CPU time	149.19 seconds
Started	Jan 10 12:43:44 PM PST 24
Finished	Jan 10 12:47:29 PM PST 24
Peak memory	201700 kb
Host	smart-24687f98-d79c-4df8-b996-68b54e2b14f3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805595904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1805595904
Directory	/workspace/32.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.4073804248
Short name	T813
Test name
Test status
Simulation time	13404930522 ps
CPU time	83.81 seconds
Started	Jan 10 12:43:49 PM PST 24
Finished	Jan 10 12:46:27 PM PST 24
Peak memory	201792 kb
Host	smart-6981ef2c-b6e4-46b2-947e-c9410d3b90cf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4073804248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.4073804248
Directory	/workspace/32.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1847497997
Short name	T272
Test name
Test status
Simulation time	58740060 ps
CPU time	4.04 seconds
Started	Jan 10 12:43:41 PM PST 24
Finished	Jan 10 12:45:00 PM PST 24
Peak memory	201672 kb
Host	smart-81c99867-8546-4068-ae25-7daf7c8d257f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847497997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1847497997
Directory	/workspace/32.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_same_source.124028339
Short name	T60
Test name
Test status
Simulation time	839560439 ps
CPU time	8.58 seconds
Started	Jan 10 12:43:42 PM PST 24
Finished	Jan 10 12:45:06 PM PST 24
Peak memory	201556 kb
Host	smart-46d5af35-b20b-4c5f-a38a-7b64a3b53660
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=124028339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.124028339
Directory	/workspace/32.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke.4095398224
Short name	T66
Test name
Test status
Simulation time	15362998 ps
CPU time	1.06 seconds
Started	Jan 10 12:43:36 PM PST 24
Finished	Jan 10 12:44:55 PM PST 24
Peak memory	201676 kb
Host	smart-df647542-2f27-4db0-a01c-72fec5dd0ada
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4095398224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.4095398224
Directory	/workspace/32.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1165004500
Short name	T795
Test name
Test status
Simulation time	3145430044 ps
CPU time	11.06 seconds
Started	Jan 10 12:43:55 PM PST 24
Finished	Jan 10 12:45:21 PM PST 24
Peak memory	201760 kb
Host	smart-c093402b-1799-4676-a928-0c514b103bf4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165004500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1165004500
Directory	/workspace/32.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3703915438
Short name	T286
Test name
Test status
Simulation time	594549579 ps
CPU time	5.17 seconds
Started	Jan 10 12:43:40 PM PST 24
Finished	Jan 10 12:45:01 PM PST 24
Peak memory	201740 kb
Host	smart-5dcbe17c-077f-4624-816f-4bf37fde1074
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3703915438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3703915438
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.4197650186
Short name	T744
Test name
Test status
Simulation time	15407420 ps
CPU time	1.22 seconds
Started	Jan 10 12:43:46 PM PST 24
Finished	Jan 10 12:45:02 PM PST 24
Peak memory	201728 kb
Host	smart-12e0b2e1-b1b4-4ccb-b796-37f1184090a8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197650186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.4197650186
Directory	/workspace/32.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all.3816012436
Short name	T596
Test name
Test status
Simulation time	5527407960 ps
CPU time	12.42 seconds
Started	Jan 10 12:43:55 PM PST 24
Finished	Jan 10 12:45:21 PM PST 24
Peak memory	201564 kb
Host	smart-29827412-b5fb-419d-b280-3d5b83c4f52b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3816012436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3816012436
Directory	/workspace/32.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.795197803
Short name	T848
Test name
Test status
Simulation time	3825221184 ps
CPU time	19.78 seconds
Started	Jan 10 12:43:57 PM PST 24
Finished	Jan 10 12:45:32 PM PST 24
Peak memory	201556 kb
Host	smart-ac7dac95-e403-43c5-bdcf-01c4aab7b6b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=795197803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.795197803
Directory	/workspace/32.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.4220624365
Short name	T183
Test name
Test status
Simulation time	1289722055 ps
CPU time	72.61 seconds
Started	Jan 10 12:43:38 PM PST 24
Finished	Jan 10 12:46:06 PM PST 24
Peak memory	204200 kb
Host	smart-8667d28b-c0c8-4e7e-a01d-6d0dd8ba35ac
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4220624365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.4220624365
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1924912553
Short name	T438
Test name
Test status
Simulation time	1672915577 ps
CPU time	64.39 seconds
Started	Jan 10 12:43:48 PM PST 24
Finished	Jan 10 12:46:07 PM PST 24
Peak memory	203616 kb
Host	smart-8d83f343-6eb0-4563-8d27-9e1e53736128
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1924912553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.1924912553
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.2379627493
Short name	T522
Test name
Test status
Simulation time	31218316 ps
CPU time	2.04 seconds
Started	Jan 10 12:43:47 PM PST 24
Finished	Jan 10 12:45:04 PM PST 24
Peak memory	201496 kb
Host	smart-9a4851c6-965e-430a-91af-ed396e656dbe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2379627493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2379627493
Directory	/workspace/32.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3154203022
Short name	T611
Test name
Test status
Simulation time	1317184709 ps
CPU time	9.7 seconds
Started	Jan 10 12:43:52 PM PST 24
Finished	Jan 10 12:45:21 PM PST 24
Peak memory	201932 kb
Host	smart-ade50992-d33c-4486-a716-dd6756756a13
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3154203022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3154203022
Directory	/workspace/33.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3921249310
Short name	T582
Test name
Test status
Simulation time	28030053 ps
CPU time	1.62 seconds
Started	Jan 10 12:43:49 PM PST 24
Finished	Jan 10 12:45:05 PM PST 24
Peak memory	201488 kb
Host	smart-de5426ad-82dc-4271-aaf9-da3a1ad18582
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3921249310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3921249310
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_random.3101312107
Short name	T523
Test name
Test status
Simulation time	25382464 ps
CPU time	2.74 seconds
Started	Jan 10 12:43:52 PM PST 24
Finished	Jan 10 12:45:09 PM PST 24
Peak memory	201688 kb
Host	smart-1cb95bb2-eb91-49ba-a1a3-ec387efeb3ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3101312107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3101312107
Directory	/workspace/33.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random.3025482419
Short name	T842
Test name
Test status
Simulation time	1742383850 ps
CPU time	15.38 seconds
Started	Jan 10 12:43:40 PM PST 24
Finished	Jan 10 12:45:11 PM PST 24
Peak memory	201608 kb
Host	smart-2b8b73ab-3307-44ce-a637-dc9fce050c1f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3025482419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3025482419
Directory	/workspace/33.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.3390239559
Short name	T682
Test name
Test status
Simulation time	23690995368 ps
CPU time	100.92 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:47:07 PM PST 24
Peak memory	201668 kb
Host	smart-92626e18-929f-4923-a022-32fa5853cf54
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390239559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3390239559
Directory	/workspace/33.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3524310522
Short name	T198
Test name
Test status
Simulation time	13412337670 ps
CPU time	31.22 seconds
Started	Jan 10 12:43:48 PM PST 24
Finished	Jan 10 12:45:34 PM PST 24
Peak memory	201784 kb
Host	smart-bae4fe94-fd6c-41d6-9fff-e07cdb237efa
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3524310522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3524310522
Directory	/workspace/33.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2544172713
Short name	T328
Test name
Test status
Simulation time	60948285 ps
CPU time	6.7 seconds
Started	Jan 10 12:43:38 PM PST 24
Finished	Jan 10 12:45:00 PM PST 24
Peak memory	201684 kb
Host	smart-217038d6-0051-44ec-a1e2-b30871608c17
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544172713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2544172713
Directory	/workspace/33.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_same_source.2434606223
Short name	T590
Test name
Test status
Simulation time	3533364884 ps
CPU time	8.69 seconds
Started	Jan 10 12:43:48 PM PST 24
Finished	Jan 10 12:45:11 PM PST 24
Peak memory	201736 kb
Host	smart-4c35581d-3589-4eb8-b268-e86a4374e493
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2434606223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2434606223
Directory	/workspace/33.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke.588283361
Short name	T622
Test name
Test status
Simulation time	9129461 ps
CPU time	1.09 seconds
Started	Jan 10 12:43:57 PM PST 24
Finished	Jan 10 12:45:14 PM PST 24
Peak memory	201492 kb
Host	smart-99eaf573-b18c-48cb-8718-7f9fd87a7ab6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=588283361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.588283361
Directory	/workspace/33.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3713709537
Short name	T317
Test name
Test status
Simulation time	11747641122 ps
CPU time	11.03 seconds
Started	Jan 10 12:43:38 PM PST 24
Finished	Jan 10 12:45:03 PM PST 24
Peak memory	201752 kb
Host	smart-0eb561d8-ef1c-44af-861c-eac3345b4c4d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713709537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3713709537
Directory	/workspace/33.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3064912901
Short name	T877
Test name
Test status
Simulation time	2671264732 ps
CPU time	12.43 seconds
Started	Jan 10 12:43:41 PM PST 24
Finished	Jan 10 12:45:09 PM PST 24
Peak memory	202056 kb
Host	smart-b80830d6-3985-4ef0-becd-f84f9a7af52e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3064912901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3064912901
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.19880108
Short name	T436
Test name
Test status
Simulation time	8330332 ps
CPU time	1.02 seconds
Started	Jan 10 12:43:52 PM PST 24
Finished	Jan 10 12:45:08 PM PST 24
Peak memory	201508 kb
Host	smart-5c050eab-8109-4d59-80d9-9506a1d95d8a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19880108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.19880108
Directory	/workspace/33.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all.4035499578
Short name	T759
Test name
Test status
Simulation time	11662424412 ps
CPU time	27.36 seconds
Started	Jan 10 12:43:54 PM PST 24
Finished	Jan 10 12:45:37 PM PST 24
Peak memory	201772 kb
Host	smart-60b8f184-80ab-46c3-bafc-884847ce71a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4035499578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.4035499578
Directory	/workspace/33.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.978336033
Short name	T371
Test name
Test status
Simulation time	81024150 ps
CPU time	8.59 seconds
Started	Jan 10 12:43:55 PM PST 24
Finished	Jan 10 12:45:18 PM PST 24
Peak memory	201724 kb
Host	smart-cb47dfa8-af18-40ce-bc0e-a2ba4242a618
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=978336033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.978336033
Directory	/workspace/33.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3068757637
Short name	T170
Test name
Test status
Simulation time	1512946147 ps
CPU time	202.24 seconds
Started	Jan 10 12:43:42 PM PST 24
Finished	Jan 10 12:48:19 PM PST 24
Peak memory	208060 kb
Host	smart-5c67ac80-15ae-434c-ba1d-232177cba8a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3068757637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.3068757637
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.1144799548
Short name	T447
Test name
Test status
Simulation time	22484380 ps
CPU time	7.91 seconds
Started	Jan 10 12:43:42 PM PST 24
Finished	Jan 10 12:45:05 PM PST 24
Peak memory	201620 kb
Host	smart-e1e4ccbd-dd9b-4ca0-9d71-724f8cad7ccd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1144799548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.1144799548
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2036177111
Short name	T47
Test name
Test status
Simulation time	22442302 ps
CPU time	1.82 seconds
Started	Jan 10 12:43:52 PM PST 24
Finished	Jan 10 12:45:09 PM PST 24
Peak memory	201724 kb
Host	smart-194b3cea-5160-4456-88e0-20eb6189921f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2036177111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2036177111
Directory	/workspace/33.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2599262089
Short name	T378
Test name
Test status
Simulation time	499066115 ps
CPU time	6.53 seconds
Started	Jan 10 12:43:59 PM PST 24
Finished	Jan 10 12:45:21 PM PST 24
Peak memory	201732 kb
Host	smart-bb536b1b-0538-4eeb-bf7a-74a6a657c8fb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2599262089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2599262089
Directory	/workspace/34.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.423979479
Short name	T128
Test name
Test status
Simulation time	33944793431 ps
CPU time	108.69 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:47:22 PM PST 24
Peak memory	201684 kb
Host	smart-80d67e67-69f9-4bd8-b218-9ccd2d175a7e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=423979479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slo w_rsp.423979479
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.4219476223
Short name	T195
Test name
Test status
Simulation time	482164933 ps
CPU time	5.18 seconds
Started	Jan 10 12:43:51 PM PST 24
Finished	Jan 10 12:45:11 PM PST 24
Peak memory	201700 kb
Host	smart-ee512a05-cf19-4ab5-b900-2e025d13eb8d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4219476223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.4219476223
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_random.1482995014
Short name	T756
Test name
Test status
Simulation time	389637963 ps
CPU time	6.05 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:45:29 PM PST 24
Peak memory	201604 kb
Host	smart-13cb705a-677f-462e-980f-c1ba85d13060
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1482995014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1482995014
Directory	/workspace/34.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random.551219815
Short name	T494
Test name
Test status
Simulation time	124642449 ps
CPU time	6.79 seconds
Started	Jan 10 12:43:50 PM PST 24
Finished	Jan 10 12:45:11 PM PST 24
Peak memory	201748 kb
Host	smart-f8ad4768-0e77-441b-b865-7b2ec199c1e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=551219815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.551219815
Directory	/workspace/34.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.440942686
Short name	T27
Test name
Test status
Simulation time	153577952896 ps
CPU time	79.74 seconds
Started	Jan 10 12:43:42 PM PST 24
Finished	Jan 10 12:46:17 PM PST 24
Peak memory	201712 kb
Host	smart-1b9415b9-8bc4-4ed9-94cf-4bfc19ed7ccd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=440942686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.440942686
Directory	/workspace/34.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1002305314
Short name	T810
Test name
Test status
Simulation time	15641385451 ps
CPU time	74.81 seconds
Started	Jan 10 12:43:45 PM PST 24
Finished	Jan 10 12:46:15 PM PST 24
Peak memory	201704 kb
Host	smart-d14facfe-f004-4c92-9cde-792b6c182e94
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1002305314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1002305314
Directory	/workspace/34.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3733764104
Short name	T277
Test name
Test status
Simulation time	24364699 ps
CPU time	2.31 seconds
Started	Jan 10 12:43:53 PM PST 24
Finished	Jan 10 12:45:10 PM PST 24
Peak memory	201740 kb
Host	smart-b1a8fc96-d165-47e1-a33b-39222df9be88
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733764104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3733764104
Directory	/workspace/34.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_same_source.1932289880
Short name	T507
Test name
Test status
Simulation time	2471725836 ps
CPU time	11.32 seconds
Started	Jan 10 12:43:54 PM PST 24
Finished	Jan 10 12:45:20 PM PST 24
Peak memory	201696 kb
Host	smart-2abaa76a-b714-494f-9059-6329ed5dbc3f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1932289880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1932289880
Directory	/workspace/34.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke.2665913455
Short name	T433
Test name
Test status
Simulation time	15226763 ps
CPU time	1.06 seconds
Started	Jan 10 12:43:52 PM PST 24
Finished	Jan 10 12:45:07 PM PST 24
Peak memory	201700 kb
Host	smart-09892dd5-e75e-48d0-9b08-701fd5eada6c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2665913455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2665913455
Directory	/workspace/34.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2328252404
Short name	T504
Test name
Test status
Simulation time	2119036372 ps
CPU time	8.08 seconds
Started	Jan 10 12:43:54 PM PST 24
Finished	Jan 10 12:45:16 PM PST 24
Peak memory	201748 kb
Host	smart-6bd94ba9-e67f-444b-b814-707227c6ec30
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328252404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2328252404
Directory	/workspace/34.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3518624738
Short name	T573
Test name
Test status
Simulation time	1283067638 ps
CPU time	6.62 seconds
Started	Jan 10 12:43:57 PM PST 24
Finished	Jan 10 12:45:20 PM PST 24
Peak memory	201584 kb
Host	smart-c6d9d5f1-4aaf-4f40-b285-3b0be8c23e43
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3518624738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3518624738
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2349070053
Short name	T511
Test name
Test status
Simulation time	28603811 ps
CPU time	1.15 seconds
Started	Jan 10 12:43:55 PM PST 24
Finished	Jan 10 12:45:11 PM PST 24
Peak memory	201728 kb
Host	smart-f7299348-1bd3-4194-a50c-5a38c86797f9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349070053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2349070053
Directory	/workspace/34.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all.2176715399
Short name	T106
Test name
Test status
Simulation time	5306515555 ps
CPU time	57.09 seconds
Started	Jan 10 12:43:56 PM PST 24
Finished	Jan 10 12:46:07 PM PST 24
Peak memory	202672 kb
Host	smart-8895f5a6-a023-49d8-8e7c-96dbf6849ca6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2176715399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2176715399
Directory	/workspace/34.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3560829512
Short name	T804
Test name
Test status
Simulation time	1235622747 ps
CPU time	25.92 seconds
Started	Jan 10 12:43:59 PM PST 24
Finished	Jan 10 12:45:40 PM PST 24
Peak memory	201680 kb
Host	smart-28854a32-ca6a-41d7-9c0d-8ff1d755052a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3560829512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3560829512
Directory	/workspace/34.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3204183495
Short name	T394
Test name
Test status
Simulation time	4218482672 ps
CPU time	80.87 seconds
Started	Jan 10 12:43:58 PM PST 24
Finished	Jan 10 12:46:33 PM PST 24
Peak memory	203760 kb
Host	smart-18c83690-6941-49fa-bc6a-9bda0941bbae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3204183495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.3204183495
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2663391042
Short name	T769
Test name
Test status
Simulation time	8517353192 ps
CPU time	63.54 seconds
Started	Jan 10 12:43:55 PM PST 24
Finished	Jan 10 12:46:13 PM PST 24
Peak memory	202820 kb
Host	smart-65c7619e-efcc-4ff2-80ce-f8673b7185ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2663391042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.2663391042
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3566927039
Short name	T787
Test name
Test status
Simulation time	49319922 ps
CPU time	3.25 seconds
Started	Jan 10 12:43:57 PM PST 24
Finished	Jan 10 12:45:16 PM PST 24
Peak memory	201696 kb
Host	smart-742fedd5-d81a-4382-aa64-58f97c155822
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3566927039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3566927039
Directory	/workspace/34.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device.990687626
Short name	T637
Test name
Test status
Simulation time	4630222268 ps
CPU time	22.18 seconds
Started	Jan 10 12:43:53 PM PST 24
Finished	Jan 10 12:45:30 PM PST 24
Peak memory	201768 kb
Host	smart-ab169e45-9fe6-4e30-b00c-928934385908
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=990687626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.990687626
Directory	/workspace/35.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2238743032
Short name	T120
Test name
Test status
Simulation time	91411780 ps
CPU time	4.28 seconds
Started	Jan 10 12:43:55 PM PST 24
Finished	Jan 10 12:45:14 PM PST 24
Peak memory	201608 kb
Host	smart-e59ea718-e6eb-41d0-bf80-189851cfbe71
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2238743032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2238743032
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_random.4038762638
Short name	T898
Test name
Test status
Simulation time	34566476 ps
CPU time	1.53 seconds
Started	Jan 10 12:43:58 PM PST 24
Finished	Jan 10 12:45:13 PM PST 24
Peak memory	201724 kb
Host	smart-23882398-1448-4d69-b65d-2e5d54a2eafd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4038762638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.4038762638
Directory	/workspace/35.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random.2755428241
Short name	T505
Test name
Test status
Simulation time	515854696 ps
CPU time	7.07 seconds
Started	Jan 10 12:43:52 PM PST 24
Finished	Jan 10 12:45:14 PM PST 24
Peak memory	201680 kb
Host	smart-5f8f00b4-f41f-4e5b-b241-641146adf006
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2755428241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2755428241
Directory	/workspace/35.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3909321354
Short name	T202
Test name
Test status
Simulation time	100089521270 ps
CPU time	120.54 seconds
Started	Jan 10 12:43:53 PM PST 24
Finished	Jan 10 12:47:08 PM PST 24
Peak memory	201712 kb
Host	smart-54803e97-c150-424d-aebd-3a73e8fab2e5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909321354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3909321354
Directory	/workspace/35.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3968642182
Short name	T696
Test name
Test status
Simulation time	46937272697 ps
CPU time	83.46 seconds
Started	Jan 10 12:43:42 PM PST 24
Finished	Jan 10 12:46:21 PM PST 24
Peak memory	201796 kb
Host	smart-ec9a1d46-4ebf-4d5a-aaad-d95549d9a818
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3968642182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3968642182
Directory	/workspace/35.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.2728999823
Short name	T158
Test name
Test status
Simulation time	366032492 ps
CPU time	5.45 seconds
Started	Jan 10 12:43:45 PM PST 24
Finished	Jan 10 12:45:05 PM PST 24
Peak memory	201608 kb
Host	smart-5a9cb58c-cd72-4e14-8d62-15ea398d1bf4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728999823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2728999823
Directory	/workspace/35.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_same_source.1022384492
Short name	T786
Test name
Test status
Simulation time	152760372 ps
CPU time	2.96 seconds
Started	Jan 10 12:43:54 PM PST 24
Finished	Jan 10 12:45:13 PM PST 24
Peak memory	201708 kb
Host	smart-7dacbe5a-5f60-4959-9c33-cdfc7d5722bd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1022384492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1022384492
Directory	/workspace/35.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke.2648512278
Short name	T521
Test name
Test status
Simulation time	82598561 ps
CPU time	1.41 seconds
Started	Jan 10 12:43:53 PM PST 24
Finished	Jan 10 12:45:08 PM PST 24
Peak memory	201728 kb
Host	smart-6031a211-25a8-457f-a1e1-ddf8c3753541
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2648512278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2648512278
Directory	/workspace/35.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.244661737
Short name	T841
Test name
Test status
Simulation time	4483885823 ps
CPU time	11.39 seconds
Started	Jan 10 12:43:54 PM PST 24
Finished	Jan 10 12:45:20 PM PST 24
Peak memory	201688 kb
Host	smart-079e8417-d58b-4db3-8dab-ff87fe2d5aa1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=244661737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.244661737
Directory	/workspace/35.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.173107457
Short name	T308
Test name
Test status
Simulation time	954487322 ps
CPU time	7.88 seconds
Started	Jan 10 12:44:02 PM PST 24
Finished	Jan 10 12:45:25 PM PST 24
Peak memory	201684 kb
Host	smart-38699784-6cc2-417a-958a-820eebf0df35
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=173107457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.173107457
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.3772269287
Short name	T399
Test name
Test status
Simulation time	17712237 ps
CPU time	1.23 seconds
Started	Jan 10 12:44:04 PM PST 24
Finished	Jan 10 12:45:21 PM PST 24
Peak memory	201768 kb
Host	smart-ba258834-8160-45fe-83da-5df4f05e59fc
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772269287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.3772269287
Directory	/workspace/35.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all.4234247832
Short name	T562
Test name
Test status
Simulation time	200560420 ps
CPU time	10.76 seconds
Started	Jan 10 12:43:53 PM PST 24
Finished	Jan 10 12:45:18 PM PST 24
Peak memory	201680 kb
Host	smart-f19de048-f9f3-4453-bf09-56e63dbe6fc7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4234247832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.4234247832
Directory	/workspace/35.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3471512688
Short name	T275
Test name
Test status
Simulation time	980386281 ps
CPU time	41.62 seconds
Started	Jan 10 12:43:45 PM PST 24
Finished	Jan 10 12:45:42 PM PST 24
Peak memory	202764 kb
Host	smart-6903907b-8894-4242-b486-2e912f612660
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3471512688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3471512688
Directory	/workspace/35.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1535168879
Short name	T119
Test name
Test status
Simulation time	8493838492 ps
CPU time	55.16 seconds
Started	Jan 10 12:43:46 PM PST 24
Finished	Jan 10 12:45:56 PM PST 24
Peak memory	202700 kb
Host	smart-5a9395b4-a4cc-4b45-aba1-1403df321d38
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1535168879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.1535168879
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2722020402
Short name	T772
Test name
Test status
Simulation time	197341963 ps
CPU time	4.12 seconds
Started	Jan 10 12:43:53 PM PST 24
Finished	Jan 10 12:45:12 PM PST 24
Peak memory	201760 kb
Host	smart-32808771-2f89-41b1-83ab-17b2c589530c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2722020402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2722020402
Directory	/workspace/35.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device.4113525008
Short name	T304
Test name
Test status
Simulation time	944743490 ps
CPU time	17.83 seconds
Started	Jan 10 12:43:54 PM PST 24
Finished	Jan 10 12:45:28 PM PST 24
Peak memory	201728 kb
Host	smart-5c596a48-fe75-4891-bf31-875db9697a7f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4113525008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.4113525008
Directory	/workspace/36.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3711234044
Short name	T107
Test name
Test status
Simulation time	3152208702 ps
CPU time	16.61 seconds
Started	Jan 10 12:43:40 PM PST 24
Finished	Jan 10 12:45:12 PM PST 24
Peak memory	201668 kb
Host	smart-e97bc5ee-68bd-4cb2-8be1-6378c86d7c16
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3711234044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.3711234044
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2119659798
Short name	T608
Test name
Test status
Simulation time	47274963 ps
CPU time	4.16 seconds
Started	Jan 10 12:44:00 PM PST 24
Finished	Jan 10 12:45:19 PM PST 24
Peak memory	201576 kb
Host	smart-4e2f6989-58ca-4b20-a20b-e293a6cab19b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2119659798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2119659798
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_random.1425762614
Short name	T323
Test name
Test status
Simulation time	1097797726 ps
CPU time	6.81 seconds
Started	Jan 10 12:44:08 PM PST 24
Finished	Jan 10 12:45:31 PM PST 24
Peak memory	201720 kb
Host	smart-f47f0efa-99d1-409c-83ab-0b80c91c71fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1425762614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1425762614
Directory	/workspace/36.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random.905291091
Short name	T698
Test name
Test status
Simulation time	1236668590 ps
CPU time	8.59 seconds
Started	Jan 10 12:44:03 PM PST 24
Finished	Jan 10 12:45:27 PM PST 24
Peak memory	201548 kb
Host	smart-a97350f5-c55f-4f56-aa0f-ce5b53607001
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=905291091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.905291091
Directory	/workspace/36.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2610181101
Short name	T129
Test name
Test status
Simulation time	71929834473 ps
CPU time	124.13 seconds
Started	Jan 10 12:43:48 PM PST 24
Finished	Jan 10 12:47:07 PM PST 24
Peak memory	201752 kb
Host	smart-34fa382d-8a6a-4883-8496-99110e3cbbda
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610181101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2610181101
Directory	/workspace/36.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2856634008
Short name	T206
Test name
Test status
Simulation time	18505216954 ps
CPU time	46.8 seconds
Started	Jan 10 12:43:49 PM PST 24
Finished	Jan 10 12:45:50 PM PST 24
Peak memory	201780 kb
Host	smart-e0a070e5-05b1-4154-80fa-747f7ba4ed20
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2856634008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2856634008
Directory	/workspace/36.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.4141127898
Short name	T139
Test name
Test status
Simulation time	28105571 ps
CPU time	3.24 seconds
Started	Jan 10 12:43:44 PM PST 24
Finished	Jan 10 12:45:03 PM PST 24
Peak memory	201624 kb
Host	smart-65063217-803f-4a46-8aeb-7e226f19c810
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141127898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.4141127898
Directory	/workspace/36.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_same_source.2429830413
Short name	T294
Test name
Test status
Simulation time	179675389 ps
CPU time	4.61 seconds
Started	Jan 10 12:43:44 PM PST 24
Finished	Jan 10 12:45:04 PM PST 24
Peak memory	201556 kb
Host	smart-fe05c513-7e06-41e4-9437-89cd90bbec66
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2429830413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2429830413
Directory	/workspace/36.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke.1186959316
Short name	T420
Test name
Test status
Simulation time	9905334 ps
CPU time	1.17 seconds
Started	Jan 10 12:43:44 PM PST 24
Finished	Jan 10 12:45:01 PM PST 24
Peak memory	201700 kb
Host	smart-a728fec2-14e9-4f65-86d9-10dc6d68b43f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1186959316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1186959316
Directory	/workspace/36.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.335735303
Short name	T734
Test name
Test status
Simulation time	5322020293 ps
CPU time	6.89 seconds
Started	Jan 10 12:43:50 PM PST 24
Finished	Jan 10 12:45:12 PM PST 24
Peak memory	201708 kb
Host	smart-cdeff7f1-6bd6-4495-a4bf-f2a268761e42
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=335735303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.335735303
Directory	/workspace/36.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2012892337
Short name	T893
Test name
Test status
Simulation time	1153080393 ps
CPU time	6.09 seconds
Started	Jan 10 12:43:58 PM PST 24
Finished	Jan 10 12:45:19 PM PST 24
Peak memory	201616 kb
Host	smart-a0cec48f-22da-4f7b-ab58-2964723ee50d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2012892337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2012892337
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1183195212
Short name	T588
Test name
Test status
Simulation time	13158035 ps
CPU time	1.12 seconds
Started	Jan 10 12:43:56 PM PST 24
Finished	Jan 10 12:45:12 PM PST 24
Peak memory	201720 kb
Host	smart-6d458a54-a5e9-4e77-a206-46c677c33cda
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183195212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1183195212
Directory	/workspace/36.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all.847376183
Short name	T528
Test name
Test status
Simulation time	484501327 ps
CPU time	34.64 seconds
Started	Jan 10 12:43:55 PM PST 24
Finished	Jan 10 12:45:44 PM PST 24
Peak memory	202784 kb
Host	smart-648edd7c-b018-4dc1-a045-ec01cb48ee47
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=847376183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.847376183
Directory	/workspace/36.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2645567891
Short name	T384
Test name
Test status
Simulation time	156358423 ps
CPU time	7.71 seconds
Started	Jan 10 12:43:56 PM PST 24
Finished	Jan 10 12:45:18 PM PST 24
Peak memory	201572 kb
Host	smart-99ee2680-8a59-4d80-9cc7-3807827e84a5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2645567891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2645567891
Directory	/workspace/36.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2316488722
Short name	T64
Test name
Test status
Simulation time	2945484585 ps
CPU time	86.32 seconds
Started	Jan 10 12:44:05 PM PST 24
Finished	Jan 10 12:46:46 PM PST 24
Peak memory	204332 kb
Host	smart-fa19a00d-f73b-4835-b432-fc0ee6dce3d9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2316488722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.2316488722
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2840247170
Short name	T750
Test name
Test status
Simulation time	117651917 ps
CPU time	12.78 seconds
Started	Jan 10 12:43:52 PM PST 24
Finished	Jan 10 12:45:20 PM PST 24
Peak memory	201732 kb
Host	smart-d0eb515b-47fb-472a-b34b-8ea75c51017b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2840247170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.2840247170
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2341374742
Short name	T114
Test name
Test status
Simulation time	71368724 ps
CPU time	6.82 seconds
Started	Jan 10 12:43:44 PM PST 24
Finished	Jan 10 12:45:07 PM PST 24
Peak memory	201480 kb
Host	smart-e3d31648-354c-4745-bc19-db9e9303ee5d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2341374742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2341374742
Directory	/workspace/36.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device.2940701382
Short name	T113
Test name
Test status
Simulation time	1004160252 ps
CPU time	12.84 seconds
Started	Jan 10 12:43:59 PM PST 24
Finished	Jan 10 12:45:27 PM PST 24
Peak memory	201648 kb
Host	smart-35f10f38-aad4-4cd9-b60b-1ce30051eaef
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2940701382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2940701382
Directory	/workspace/37.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.727062821
Short name	T230
Test name
Test status
Simulation time	104083798802 ps
CPU time	154.57 seconds
Started	Jan 10 12:43:56 PM PST 24
Finished	Jan 10 12:47:45 PM PST 24
Peak memory	202488 kb
Host	smart-f9f2f2a9-cb19-4800-bf55-edc308cf4135
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=727062821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slo w_rsp.727062821
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3198979335
Short name	T152
Test name
Test status
Simulation time	425877022 ps
CPU time	9.31 seconds
Started	Jan 10 12:43:57 PM PST 24
Finished	Jan 10 12:45:22 PM PST 24
Peak memory	201680 kb
Host	smart-bc50f8b3-44b2-4193-b982-3cf30255b6fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3198979335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3198979335
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_random.3373078644
Short name	T451
Test name
Test status
Simulation time	12501849 ps
CPU time	1.28 seconds
Started	Jan 10 12:43:54 PM PST 24
Finished	Jan 10 12:45:09 PM PST 24
Peak memory	201732 kb
Host	smart-8670653f-7344-4271-bfe2-1b05787f30c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3373078644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3373078644
Directory	/workspace/37.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random.1351605285
Short name	T554
Test name
Test status
Simulation time	88414890 ps
CPU time	2.28 seconds
Started	Jan 10 12:43:53 PM PST 24
Finished	Jan 10 12:45:10 PM PST 24
Peak memory	201660 kb
Host	smart-b724b52f-21bf-4858-91bb-32448dc3e7f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1351605285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1351605285
Directory	/workspace/37.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.4269147016
Short name	T397
Test name
Test status
Simulation time	75091247019 ps
CPU time	139.99 seconds
Started	Jan 10 12:43:56 PM PST 24
Finished	Jan 10 12:47:31 PM PST 24
Peak memory	201780 kb
Host	smart-cd2d0e66-4807-40ed-aa5d-3981d3864d9f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269147016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.4269147016
Directory	/workspace/37.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3950222118
Short name	T5
Test name
Test status
Simulation time	26030962908 ps
CPU time	76.38 seconds
Started	Jan 10 12:43:53 PM PST 24
Finished	Jan 10 12:46:24 PM PST 24
Peak memory	201780 kb
Host	smart-ed267ada-c9c1-4f07-bcf1-02b475807a3f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3950222118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3950222118
Directory	/workspace/37.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2101730322
Short name	T409
Test name
Test status
Simulation time	149389892 ps
CPU time	5.96 seconds
Started	Jan 10 12:43:52 PM PST 24
Finished	Jan 10 12:45:12 PM PST 24
Peak memory	201704 kb
Host	smart-0968a140-4ae7-44a0-add7-5033375526ad
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101730322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2101730322
Directory	/workspace/37.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_same_source.908913501
Short name	T41
Test name
Test status
Simulation time	167123509 ps
CPU time	1.49 seconds
Started	Jan 10 12:44:02 PM PST 24
Finished	Jan 10 12:45:18 PM PST 24
Peak memory	201760 kb
Host	smart-99641031-76bd-4413-8df1-57b3cd81e141
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=908913501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.908913501
Directory	/workspace/37.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke.2203938940
Short name	T386
Test name
Test status
Simulation time	9697068 ps
CPU time	1.21 seconds
Started	Jan 10 12:43:48 PM PST 24
Finished	Jan 10 12:45:04 PM PST 24
Peak memory	201700 kb
Host	smart-0795af77-c3af-462a-889e-5beeef154652
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2203938940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2203938940
Directory	/workspace/37.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.4028353406
Short name	T469
Test name
Test status
Simulation time	1924718618 ps
CPU time	8.38 seconds
Started	Jan 10 12:43:48 PM PST 24
Finished	Jan 10 12:45:11 PM PST 24
Peak memory	201616 kb
Host	smart-950d0e5c-f49d-4633-a037-77ce2c321a45
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028353406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.4028353406
Directory	/workspace/37.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1354953660
Short name	T56
Test name
Test status
Simulation time	996643754 ps
CPU time	7.44 seconds
Started	Jan 10 12:43:54 PM PST 24
Finished	Jan 10 12:45:17 PM PST 24
Peak memory	201564 kb
Host	smart-4b285d4a-79af-4055-b93e-53ccaf053dfb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1354953660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1354953660
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3183647874
Short name	T282
Test name
Test status
Simulation time	10487935 ps
CPU time	1.15 seconds
Started	Jan 10 12:44:05 PM PST 24
Finished	Jan 10 12:45:22 PM PST 24
Peak memory	201628 kb
Host	smart-20210818-f219-4246-8051-2b34b67942b7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183647874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3183647874
Directory	/workspace/37.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all.1803284989
Short name	T839
Test name
Test status
Simulation time	787101538 ps
CPU time	7.31 seconds
Started	Jan 10 12:44:05 PM PST 24
Finished	Jan 10 12:45:27 PM PST 24
Peak memory	201596 kb
Host	smart-65ca4fb3-50c1-445b-bc1e-c715bf9ad0e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1803284989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1803284989
Directory	/workspace/37.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1642777649
Short name	T221
Test name
Test status
Simulation time	1578197692 ps
CPU time	24.61 seconds
Started	Jan 10 12:44:03 PM PST 24
Finished	Jan 10 12:45:43 PM PST 24
Peak memory	201588 kb
Host	smart-43f40736-44c1-49a8-85f8-217473a52c95
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1642777649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1642777649
Directory	/workspace/37.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2040651799
Short name	T161
Test name
Test status
Simulation time	4459505463 ps
CPU time	64.12 seconds
Started	Jan 10 12:44:02 PM PST 24
Finished	Jan 10 12:46:22 PM PST 24
Peak memory	204128 kb
Host	smart-98e77538-61d8-43b4-80b0-3c1a76edfc7d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2040651799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.2040651799
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.196380153
Short name	T819
Test name
Test status
Simulation time	193165315 ps
CPU time	13.51 seconds
Started	Jan 10 12:43:55 PM PST 24
Finished	Jan 10 12:45:22 PM PST 24
Peak memory	201668 kb
Host	smart-3181fbac-3522-4460-a6cf-a151f16220a4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=196380153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_res et_error.196380153
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.2388449702
Short name	T854
Test name
Test status
Simulation time	526345206 ps
CPU time	8.05 seconds
Started	Jan 10 12:43:49 PM PST 24
Finished	Jan 10 12:45:11 PM PST 24
Peak memory	201632 kb
Host	smart-186110bf-9b4d-4a42-9fd7-14566fc732c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2388449702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2388449702
Directory	/workspace/37.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device.892475322
Short name	T564
Test name
Test status
Simulation time	2081235085 ps
CPU time	17.41 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:45:39 PM PST 24
Peak memory	201720 kb
Host	smart-b57c1b54-4d21-4024-98d6-ae9a4ff9f8c7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=892475322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.892475322
Directory	/workspace/38.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3051298280
Short name	T232
Test name
Test status
Simulation time	131986554338 ps
CPU time	323.55 seconds
Started	Jan 10 12:43:53 PM PST 24
Finished	Jan 10 12:50:31 PM PST 24
Peak memory	203076 kb
Host	smart-b2cf3bf5-f4fe-47ac-9715-c0b335204b1f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3051298280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.3051298280
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1001924624
Short name	T535
Test name
Test status
Simulation time	114701371 ps
CPU time	2.68 seconds
Started	Jan 10 12:43:57 PM PST 24
Finished	Jan 10 12:45:16 PM PST 24
Peak memory	201724 kb
Host	smart-d2f80ae3-a372-4aa6-ab70-5859f2e268ed
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1001924624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1001924624
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_random.3277014520
Short name	T377
Test name
Test status
Simulation time	139221938 ps
CPU time	7.14 seconds
Started	Jan 10 12:43:55 PM PST 24
Finished	Jan 10 12:45:16 PM PST 24
Peak memory	201716 kb
Host	smart-b8750926-f3df-452a-afeb-b7dbd2ab70f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3277014520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3277014520
Directory	/workspace/38.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random.3743749220
Short name	T894
Test name
Test status
Simulation time	151939029 ps
CPU time	3.82 seconds
Started	Jan 10 12:43:58 PM PST 24
Finished	Jan 10 12:45:17 PM PST 24
Peak memory	201576 kb
Host	smart-fa0bd63e-409c-4bec-9ac2-7dfd915097f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3743749220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3743749220
Directory	/workspace/38.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3037004091
Short name	T875
Test name
Test status
Simulation time	8839879415 ps
CPU time	31.79 seconds
Started	Jan 10 12:43:59 PM PST 24
Finished	Jan 10 12:45:46 PM PST 24
Peak memory	201660 kb
Host	smart-dafba9f7-776b-400c-9388-5459b960daf0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037004091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3037004091
Directory	/workspace/38.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.575330210
Short name	T410
Test name
Test status
Simulation time	22782385555 ps
CPU time	100.22 seconds
Started	Jan 10 12:44:02 PM PST 24
Finished	Jan 10 12:46:58 PM PST 24
Peak memory	201712 kb
Host	smart-ce9dc073-0432-4dfd-bd24-c5462e311037
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=575330210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.575330210
Directory	/workspace/38.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.626818163
Short name	T558
Test name
Test status
Simulation time	29599640 ps
CPU time	3.05 seconds
Started	Jan 10 12:43:50 PM PST 24
Finished	Jan 10 12:45:08 PM PST 24
Peak memory	201588 kb
Host	smart-f60cd746-288a-46fb-8305-ac82cd17c265
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626818163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.626818163
Directory	/workspace/38.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_same_source.1982372430
Short name	T543
Test name
Test status
Simulation time	41973420 ps
CPU time	3.64 seconds
Started	Jan 10 12:43:54 PM PST 24
Finished	Jan 10 12:45:13 PM PST 24
Peak memory	201584 kb
Host	smart-8994baff-bb3b-410a-9fbc-c14697df11a2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1982372430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1982372430
Directory	/workspace/38.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke.317539049
Short name	T24
Test name
Test status
Simulation time	17343973 ps
CPU time	1.03 seconds
Started	Jan 10 12:43:51 PM PST 24
Finished	Jan 10 12:45:07 PM PST 24
Peak memory	201612 kb
Host	smart-85dd9e39-3df2-43f4-83c1-49862aad213d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=317539049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.317539049
Directory	/workspace/38.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.1325824955
Short name	T878
Test name
Test status
Simulation time	3167287883 ps
CPU time	6.2 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:45:28 PM PST 24
Peak memory	201704 kb
Host	smart-f2524352-bfa0-486c-9dfb-ccd522704c10
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325824955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1325824955
Directory	/workspace/38.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1655789818
Short name	T350
Test name
Test status
Simulation time	2158122775 ps
CPU time	11.49 seconds
Started	Jan 10 12:43:56 PM PST 24
Finished	Jan 10 12:45:22 PM PST 24
Peak memory	201740 kb
Host	smart-8f763b4a-0b50-4e86-afe3-463f5b2c5e35
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1655789818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1655789818
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3759076019
Short name	T280
Test name
Test status
Simulation time	11544820 ps
CPU time	1.02 seconds
Started	Jan 10 12:44:12 PM PST 24
Finished	Jan 10 12:45:29 PM PST 24
Peak memory	201524 kb
Host	smart-5152ff01-e124-48f2-8f85-b8c1fa723e79
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759076019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3759076019
Directory	/workspace/38.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.620026523
Short name	T89
Test name
Test status
Simulation time	11441879809 ps
CPU time	74.13 seconds
Started	Jan 10 12:43:58 PM PST 24
Finished	Jan 10 12:46:27 PM PST 24
Peak memory	201744 kb
Host	smart-739087eb-1607-402e-bc4f-7d5c794612cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=620026523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.620026523
Directory	/workspace/38.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1136821670
Short name	T224
Test name
Test status
Simulation time	5658162472 ps
CPU time	86.99 seconds
Started	Jan 10 12:43:59 PM PST 24
Finished	Jan 10 12:46:41 PM PST 24
Peak memory	201792 kb
Host	smart-cb0cbd09-823f-40a2-9a35-f2d9f1b1f740
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1136821670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1136821670
Directory	/workspace/38.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1701932617
Short name	T55
Test name
Test status
Simulation time	116478948 ps
CPU time	18.59 seconds
Started	Jan 10 12:43:56 PM PST 24
Finished	Jan 10 12:45:29 PM PST 24
Peak memory	202620 kb
Host	smart-7e00a019-0357-4033-881b-08ceb5e4c036
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1701932617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.1701932617
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3705009412
Short name	T809
Test name
Test status
Simulation time	3327701635 ps
CPU time	113.4 seconds
Started	Jan 10 12:43:57 PM PST 24
Finished	Jan 10 12:47:06 PM PST 24
Peak memory	205636 kb
Host	smart-3081d2be-7ac1-451e-9e2b-bd09818e6e37
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3705009412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.3705009412
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1265865130
Short name	T442
Test name
Test status
Simulation time	298170567 ps
CPU time	4.86 seconds
Started	Jan 10 12:44:00 PM PST 24
Finished	Jan 10 12:45:20 PM PST 24
Peak memory	201576 kb
Host	smart-238ac0a4-364f-4f33-8aa3-9f5dde7f4a62
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1265865130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1265865130
Directory	/workspace/38.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3254275402
Short name	T343
Test name
Test status
Simulation time	2003897803 ps
CPU time	19.68 seconds
Started	Jan 10 12:43:50 PM PST 24
Finished	Jan 10 12:45:24 PM PST 24
Peak memory	201728 kb
Host	smart-f98328cd-c284-48f7-b978-f213059041d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3254275402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3254275402
Directory	/workspace/39.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.743417592
Short name	T90
Test name
Test status
Simulation time	126189687755 ps
CPU time	278.59 seconds
Started	Jan 10 12:44:01 PM PST 24
Finished	Jan 10 12:49:54 PM PST 24
Peak memory	202772 kb
Host	smart-4b723e7b-355b-4c3e-8a49-8d09b0698e91
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=743417592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slo w_rsp.743417592
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.1010308070
Short name	T833
Test name
Test status
Simulation time	22879011 ps
CPU time	1.48 seconds
Started	Jan 10 12:43:58 PM PST 24
Finished	Jan 10 12:45:13 PM PST 24
Peak memory	201576 kb
Host	smart-d8657962-744d-441a-9f44-a9ea4f0d5f81
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1010308070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.1010308070
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_random.1822759161
Short name	T306
Test name
Test status
Simulation time	515930971 ps
CPU time	8.39 seconds
Started	Jan 10 12:44:02 PM PST 24
Finished	Jan 10 12:45:24 PM PST 24
Peak memory	201728 kb
Host	smart-b7f859d4-427a-41bc-bc92-178fcd4f07b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1822759161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1822759161
Directory	/workspace/39.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random.2448518402
Short name	T177
Test name
Test status
Simulation time	555202875 ps
CPU time	8.6 seconds
Started	Jan 10 12:43:58 PM PST 24
Finished	Jan 10 12:45:21 PM PST 24
Peak memory	201572 kb
Host	smart-24654831-f0d9-4f14-b1de-8a42bde54b4f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2448518402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2448518402
Directory	/workspace/39.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.3580960328
Short name	T515
Test name
Test status
Simulation time	14010180134 ps
CPU time	57.82 seconds
Started	Jan 10 12:43:55 PM PST 24
Finished	Jan 10 12:46:06 PM PST 24
Peak memory	201660 kb
Host	smart-7566b804-101b-4aca-a902-9f65874a4548
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580960328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3580960328
Directory	/workspace/39.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.744644857
Short name	T305
Test name
Test status
Simulation time	54263995221 ps
CPU time	112.31 seconds
Started	Jan 10 12:44:04 PM PST 24
Finished	Jan 10 12:47:22 PM PST 24
Peak memory	201800 kb
Host	smart-938c0297-a57e-4f30-8cdc-073f9386d0e4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=744644857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.744644857
Directory	/workspace/39.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.453811899
Short name	T284
Test name
Test status
Simulation time	527081859 ps
CPU time	9.33 seconds
Started	Jan 10 12:43:59 PM PST 24
Finished	Jan 10 12:45:24 PM PST 24
Peak memory	201636 kb
Host	smart-c0e5f9c4-ccd1-48be-83c2-246ff7a58b10
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453811899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.453811899
Directory	/workspace/39.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_same_source.2417961100
Short name	T253
Test name
Test status
Simulation time	23678335 ps
CPU time	1.88 seconds
Started	Jan 10 12:44:03 PM PST 24
Finished	Jan 10 12:45:20 PM PST 24
Peak memory	201628 kb
Host	smart-89293755-450f-402c-8f88-28e73b2f6882
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2417961100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2417961100
Directory	/workspace/39.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke.2151970339
Short name	T737
Test name
Test status
Simulation time	15718964 ps
CPU time	0.99 seconds
Started	Jan 10 12:44:05 PM PST 24
Finished	Jan 10 12:45:22 PM PST 24
Peak memory	201572 kb
Host	smart-5e78a960-c817-4d5d-8654-64260f45ed54
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2151970339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2151970339
Directory	/workspace/39.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.4106994295
Short name	T757
Test name
Test status
Simulation time	15492889553 ps
CPU time	14.09 seconds
Started	Jan 10 12:44:00 PM PST 24
Finished	Jan 10 12:45:29 PM PST 24
Peak memory	201704 kb
Host	smart-62a5d0e1-749b-42b3-8ed3-10bb29a68a23
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106994295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.4106994295
Directory	/workspace/39.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1481447953
Short name	T435
Test name
Test status
Simulation time	6252469016 ps
CPU time	14.11 seconds
Started	Jan 10 12:44:00 PM PST 24
Finished	Jan 10 12:45:29 PM PST 24
Peak memory	201668 kb
Host	smart-d3c23a5f-a88a-4265-bc44-5c5b941590fd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1481447953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1481447953
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1050728837
Short name	T706
Test name
Test status
Simulation time	11704354 ps
CPU time	1.1 seconds
Started	Jan 10 12:43:59 PM PST 24
Finished	Jan 10 12:45:15 PM PST 24
Peak memory	201600 kb
Host	smart-a928f42e-dcd9-4521-80d1-9703feca4dab
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050728837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1050728837
Directory	/workspace/39.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all.370727321
Short name	T422
Test name
Test status
Simulation time	3198462721 ps
CPU time	37.53 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:46:04 PM PST 24
Peak memory	201860 kb
Host	smart-062e1666-feaa-4009-bfec-9cce6bda74be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=370727321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.370727321
Directory	/workspace/39.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3170519525
Short name	T537
Test name
Test status
Simulation time	868359543 ps
CPU time	34.58 seconds
Started	Jan 10 12:44:05 PM PST 24
Finished	Jan 10 12:45:55 PM PST 24
Peak memory	201672 kb
Host	smart-c23dbc69-cdce-4183-922a-acde6e849f10
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3170519525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3170519525
Directory	/workspace/39.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3888941796
Short name	T868
Test name
Test status
Simulation time	423568611 ps
CPU time	64.55 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:46:31 PM PST 24
Peak memory	203088 kb
Host	smart-32997c90-1375-40cf-bc61-58ba56f9bfb7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3888941796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.3888941796
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.361602194
Short name	T390
Test name
Test status
Simulation time	1659678679 ps
CPU time	12.49 seconds
Started	Jan 10 12:43:56 PM PST 24
Finished	Jan 10 12:45:23 PM PST 24
Peak memory	201672 kb
Host	smart-451cda1c-80cb-478a-97b9-f40688e79af0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=361602194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.361602194
Directory	/workspace/39.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.1598417502
Short name	T193
Test name
Test status
Simulation time	128681696 ps
CPU time	8.46 seconds
Started	Jan 10 12:42:08 PM PST 24
Finished	Jan 10 12:43:30 PM PST 24
Peak memory	201728 kb
Host	smart-37ee48e0-e365-4ce0-bb5e-67a6f1bc0117
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1598417502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1598417502
Directory	/workspace/4.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.289102953
Short name	T764
Test name
Test status
Simulation time	1025932253 ps
CPU time	8.79 seconds
Started	Jan 10 12:42:13 PM PST 24
Finished	Jan 10 12:43:35 PM PST 24
Peak memory	201680 kb
Host	smart-e98ffaba-5052-4d0d-9acf-61d04a6ea7e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=289102953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.289102953
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_random.3262400987
Short name	T628
Test name
Test status
Simulation time	114835792 ps
CPU time	3.94 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:43:36 PM PST 24
Peak memory	201760 kb
Host	smart-92f33b83-fef5-43d7-a5fa-ca0d750eefb8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3262400987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3262400987
Directory	/workspace/4.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random.2182979982
Short name	T430
Test name
Test status
Simulation time	1320298766 ps
CPU time	8.2 seconds
Started	Jan 10 12:42:11 PM PST 24
Finished	Jan 10 12:43:31 PM PST 24
Peak memory	201972 kb
Host	smart-4f04999b-7977-443f-ba59-e0d66316d891
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2182979982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.2182979982
Directory	/workspace/4.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1767646537
Short name	T124
Test name
Test status
Simulation time	58893544066 ps
CPU time	144.95 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:45:47 PM PST 24
Peak memory	201628 kb
Host	smart-9bef4fd8-f9df-48dd-bdec-7607b3be8fd7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767646537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1767646537
Directory	/workspace/4.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.536286227
Short name	T883
Test name
Test status
Simulation time	18370937080 ps
CPU time	109.66 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:45:12 PM PST 24
Peak memory	201792 kb
Host	smart-0289c8a2-b6ce-44d1-b41d-6bb28c4154c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=536286227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.536286227
Directory	/workspace/4.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.3094379680
Short name	T771
Test name
Test status
Simulation time	205010900 ps
CPU time	7.13 seconds
Started	Jan 10 12:42:12 PM PST 24
Finished	Jan 10 12:43:31 PM PST 24
Peak memory	201700 kb
Host	smart-7007296f-6b18-4aec-b1da-3970a1abc3d2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094379680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3094379680
Directory	/workspace/4.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_same_source.47256557
Short name	T556
Test name
Test status
Simulation time	315289799 ps
CPU time	4.09 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:43:36 PM PST 24
Peak memory	201560 kb
Host	smart-e01e3c99-3eda-4c72-83ed-c75470813b47
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=47256557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.47256557
Directory	/workspace/4.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke.1971491124
Short name	T476
Test name
Test status
Simulation time	16835523 ps
CPU time	1.09 seconds
Started	Jan 10 12:42:14 PM PST 24
Finished	Jan 10 12:43:27 PM PST 24
Peak memory	201724 kb
Host	smart-1be894e3-a51c-4bc3-adc1-e7e4b1cfce4d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1971491124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1971491124
Directory	/workspace/4.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2638445660
Short name	T652
Test name
Test status
Simulation time	1458284131 ps
CPU time	6.52 seconds
Started	Jan 10 12:42:07 PM PST 24
Finished	Jan 10 12:43:26 PM PST 24
Peak memory	201740 kb
Host	smart-b8682b38-2b28-4549-8500-ef553dc05bff
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638445660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2638445660
Directory	/workspace/4.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3753493903
Short name	T733
Test name
Test status
Simulation time	9302095336 ps
CPU time	9.05 seconds
Started	Jan 10 12:42:09 PM PST 24
Finished	Jan 10 12:43:31 PM PST 24
Peak memory	201808 kb
Host	smart-cd8996d3-96ed-44d6-8e9f-c5d056cadc7b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3753493903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3753493903
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.163680076
Short name	T567
Test name
Test status
Simulation time	13359674 ps
CPU time	1.14 seconds
Started	Jan 10 12:42:10 PM PST 24
Finished	Jan 10 12:43:24 PM PST 24
Peak memory	201716 kb
Host	smart-69b53c3d-0354-460b-8b4c-904bd8796960
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163680076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.163680076
Directory	/workspace/4.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all.1092703738
Short name	T742
Test name
Test status
Simulation time	10344665845 ps
CPU time	49.9 seconds
Started	Jan 10 12:42:17 PM PST 24
Finished	Jan 10 12:44:20 PM PST 24
Peak memory	202812 kb
Host	smart-4051c294-2fa6-4e96-b543-b83f35a4c520
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1092703738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1092703738
Directory	/workspace/4.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.681117641
Short name	T732
Test name
Test status
Simulation time	1714063950 ps
CPU time	31.43 seconds
Started	Jan 10 12:42:18 PM PST 24
Finished	Jan 10 12:44:04 PM PST 24
Peak memory	201700 kb
Host	smart-720f20d9-dd8c-483d-8a5a-4563f189b129
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=681117641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.681117641
Directory	/workspace/4.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3596320158
Short name	T241
Test name
Test status
Simulation time	755393054 ps
CPU time	111.76 seconds
Started	Jan 10 12:42:17 PM PST 24
Finished	Jan 10 12:45:21 PM PST 24
Peak memory	203936 kb
Host	smart-dbe2ecd5-8f53-4c15-a1ce-dc98c66c02e1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3596320158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.3596320158
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3882793236
Short name	T240
Test name
Test status
Simulation time	325656890 ps
CPU time	30.97 seconds
Started	Jan 10 12:42:16 PM PST 24
Finished	Jan 10 12:44:00 PM PST 24
Peak memory	203032 kb
Host	smart-4a0f90a7-f5ff-49fd-a86c-1b8cd32f7161
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3882793236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.3882793236
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.866377807
Short name	T776
Test name
Test status
Simulation time	896172936 ps
CPU time	6.5 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:43:39 PM PST 24
Peak memory	201712 kb
Host	smart-28aaff8a-c7e0-448f-b7f4-89a1f74a4ee9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=866377807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.866377807
Directory	/workspace/4.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device.442136982
Short name	T380
Test name
Test status
Simulation time	33237517 ps
CPU time	5.1 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:45:31 PM PST 24
Peak memory	201556 kb
Host	smart-1aa764cb-b9a6-4d7d-b7ad-bcc0f048c814
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=442136982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.442136982
Directory	/workspace/40.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3263415181
Short name	T793
Test name
Test status
Simulation time	44166917 ps
CPU time	3.16 seconds
Started	Jan 10 12:44:10 PM PST 24
Finished	Jan 10 12:45:29 PM PST 24
Peak memory	201720 kb
Host	smart-1fa4d396-14ea-44e1-8af0-0870bdaa63d8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3263415181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3263415181
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_random.3917588920
Short name	T607
Test name
Test status
Simulation time	4114710801 ps
CPU time	9.63 seconds
Started	Jan 10 12:44:01 PM PST 24
Finished	Jan 10 12:45:26 PM PST 24
Peak memory	201708 kb
Host	smart-2eff8feb-e2fb-4fd1-8f27-b0fc62b733d0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3917588920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3917588920
Directory	/workspace/40.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random.2544493353
Short name	T585
Test name
Test status
Simulation time	111805332 ps
CPU time	4.37 seconds
Started	Jan 10 12:44:15 PM PST 24
Finished	Jan 10 12:45:35 PM PST 24
Peak memory	201508 kb
Host	smart-d49e9889-3f65-4562-be2d-84782ed0a211
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2544493353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2544493353
Directory	/workspace/40.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.2609397232
Short name	T307
Test name
Test status
Simulation time	22334623618 ps
CPU time	45.4 seconds
Started	Jan 10 12:44:04 PM PST 24
Finished	Jan 10 12:46:05 PM PST 24
Peak memory	201660 kb
Host	smart-99ea8e2a-2ed4-45ac-ae80-d6f8a92eab25
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609397232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2609397232
Directory	/workspace/40.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1233705055
Short name	T760
Test name
Test status
Simulation time	16670222731 ps
CPU time	111.83 seconds
Started	Jan 10 12:44:00 PM PST 24
Finished	Jan 10 12:47:06 PM PST 24
Peak memory	201808 kb
Host	smart-c67f84e6-5b49-49a2-b3b2-54db87cb3c51
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1233705055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1233705055
Directory	/workspace/40.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3000600377
Short name	T43
Test name
Test status
Simulation time	54373051 ps
CPU time	5.62 seconds
Started	Jan 10 12:43:58 PM PST 24
Finished	Jan 10 12:45:17 PM PST 24
Peak memory	201728 kb
Host	smart-e5eebae4-332f-4196-ab71-9b20c3c37a26
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000600377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3000600377
Directory	/workspace/40.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_same_source.1142820531
Short name	T597
Test name
Test status
Simulation time	1131059219 ps
CPU time	9.6 seconds
Started	Jan 10 12:44:05 PM PST 24
Finished	Jan 10 12:45:30 PM PST 24
Peak memory	201708 kb
Host	smart-e0c37e25-03ea-44fc-8532-15abd59d93f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1142820531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1142820531
Directory	/workspace/40.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke.589165927
Short name	T453
Test name
Test status
Simulation time	14834728 ps
CPU time	1.33 seconds
Started	Jan 10 12:43:59 PM PST 24
Finished	Jan 10 12:45:15 PM PST 24
Peak memory	201632 kb
Host	smart-2bd7b37b-17ea-45b5-a7e4-d9755a522b2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=589165927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.589165927
Directory	/workspace/40.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1614069551
Short name	T351
Test name
Test status
Simulation time	2407956162 ps
CPU time	10.39 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:45:44 PM PST 24
Peak memory	201804 kb
Host	smart-6bae5a82-e7be-47e3-b7a0-e0ae2707494b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614069551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1614069551
Directory	/workspace/40.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.374282285
Short name	T595
Test name
Test status
Simulation time	2923109774 ps
CPU time	11.33 seconds
Started	Jan 10 12:44:15 PM PST 24
Finished	Jan 10 12:45:42 PM PST 24
Peak memory	201592 kb
Host	smart-02582fde-48c3-48da-84ef-db5dc1bd5915
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=374282285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.374282285
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2592822833
Short name	T725
Test name
Test status
Simulation time	11347036 ps
CPU time	1.25 seconds
Started	Jan 10 12:44:04 PM PST 24
Finished	Jan 10 12:45:21 PM PST 24
Peak memory	201716 kb
Host	smart-027c990b-187c-45b8-8861-24da4cf00177
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592822833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2592822833
Directory	/workspace/40.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all.1832313167
Short name	T278
Test name
Test status
Simulation time	1190736817 ps
CPU time	44.76 seconds
Started	Jan 10 12:44:04 PM PST 24
Finished	Jan 10 12:46:05 PM PST 24
Peak memory	201728 kb
Host	smart-c68993ce-a02b-4ca0-ab4e-a9dd82379dc5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1832313167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1832313167
Directory	/workspace/40.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2471736275
Short name	T716
Test name
Test status
Simulation time	101674101 ps
CPU time	8.64 seconds
Started	Jan 10 12:44:01 PM PST 24
Finished	Jan 10 12:45:25 PM PST 24
Peak memory	201724 kb
Host	smart-467407a6-963d-4c93-be1c-8458db2cc934
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2471736275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2471736275
Directory	/workspace/40.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3569541758
Short name	T52
Test name
Test status
Simulation time	1077609971 ps
CPU time	209.15 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:49:03 PM PST 24
Peak memory	207248 kb
Host	smart-af4b636e-c8dd-4c02-9724-8f4f9f1db44f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3569541758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.3569541758
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.981153751
Short name	T816
Test name
Test status
Simulation time	1716311287 ps
CPU time	48.98 seconds
Started	Jan 10 12:43:59 PM PST 24
Finished	Jan 10 12:46:03 PM PST 24
Peak memory	203532 kb
Host	smart-f15a6b18-4119-475e-8bdf-cf7a6441965d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=981153751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res et_error.981153751
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.827961296
Short name	T678
Test name
Test status
Simulation time	183225037 ps
CPU time	3.95 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:45:25 PM PST 24
Peak memory	201736 kb
Host	smart-25720c58-ff3d-4eb3-b103-3c4e8d88f0ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=827961296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.827961296
Directory	/workspace/40.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1589625595
Short name	T791
Test name
Test status
Simulation time	1747677518 ps
CPU time	18.85 seconds
Started	Jan 10 12:44:12 PM PST 24
Finished	Jan 10 12:45:47 PM PST 24
Peak memory	201624 kb
Host	smart-b58c76e5-b249-47a3-a30c-21d2a464d610
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1589625595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1589625595
Directory	/workspace/41.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1053001371
Short name	T83
Test name
Test status
Simulation time	34135935808 ps
CPU time	152.37 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:48:06 PM PST 24
Peak memory	202804 kb
Host	smart-d7026861-e018-40b0-86d8-ba84bbeb0e5d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1053001371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1053001371
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2921439734
Short name	T423
Test name
Test status
Simulation time	258044705 ps
CPU time	4.43 seconds
Started	Jan 10 12:44:04 PM PST 24
Finished	Jan 10 12:45:35 PM PST 24
Peak memory	201480 kb
Host	smart-b2c8bbd6-fc53-4a0d-bbb6-ccfe5fc64a5d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2921439734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2921439734
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_random.3653858020
Short name	T303
Test name
Test status
Simulation time	818025796 ps
CPU time	13.66 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:45:35 PM PST 24
Peak memory	201724 kb
Host	smart-6b8a6976-9379-4002-9262-9c1c0125a219
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3653858020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3653858020
Directory	/workspace/41.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random.3409034999
Short name	T50
Test name
Test status
Simulation time	20271035 ps
CPU time	2.27 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:45:24 PM PST 24
Peak memory	201620 kb
Host	smart-4e1eea7c-bf3e-457c-a75c-b20660d68202
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3409034999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3409034999
Directory	/workspace/41.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3551900706
Short name	T67
Test name
Test status
Simulation time	34539851992 ps
CPU time	115.61 seconds
Started	Jan 10 12:44:00 PM PST 24
Finished	Jan 10 12:47:10 PM PST 24
Peak memory	201776 kb
Host	smart-467770a8-4592-4242-b354-155f383562a5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551900706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3551900706
Directory	/workspace/41.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2752231735
Short name	T665
Test name
Test status
Simulation time	31915998409 ps
CPU time	112.43 seconds
Started	Jan 10 12:44:02 PM PST 24
Finished	Jan 10 12:47:10 PM PST 24
Peak memory	201616 kb
Host	smart-3a16ba54-cc80-4793-a10a-a843c491350b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2752231735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2752231735
Directory	/workspace/41.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1069815470
Short name	T200
Test name
Test status
Simulation time	29591774 ps
CPU time	3.4 seconds
Started	Jan 10 12:44:09 PM PST 24
Finished	Jan 10 12:45:28 PM PST 24
Peak memory	201752 kb
Host	smart-32e16d82-fe4a-4738-97fb-3b6bf6420dea
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069815470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1069815470
Directory	/workspace/41.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_same_source.443683018
Short name	T443
Test name
Test status
Simulation time	15960779 ps
CPU time	1.1 seconds
Started	Jan 10 12:44:01 PM PST 24
Finished	Jan 10 12:45:19 PM PST 24
Peak memory	201592 kb
Host	smart-bbec3f09-434f-4539-9890-e69c8afb05d6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=443683018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.443683018
Directory	/workspace/41.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke.284864132
Short name	T631
Test name
Test status
Simulation time	10573640 ps
CPU time	1.18 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:45:23 PM PST 24
Peak memory	201484 kb
Host	smart-39507144-cab7-442e-b1f8-cd4011563c9b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=284864132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.284864132
Directory	/workspace/41.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2544408808
Short name	T318
Test name
Test status
Simulation time	2960466811 ps
CPU time	10.96 seconds
Started	Jan 10 12:44:01 PM PST 24
Finished	Jan 10 12:45:28 PM PST 24
Peak memory	201744 kb
Host	smart-568d2647-b6dc-470a-bb44-dcd7ac8cdbd3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544408808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2544408808
Directory	/workspace/41.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.559493964
Short name	T186
Test name
Test status
Simulation time	554185738 ps
CPU time	4.65 seconds
Started	Jan 10 12:44:02 PM PST 24
Finished	Jan 10 12:45:20 PM PST 24
Peak memory	201616 kb
Host	smart-2e89afe6-74ea-454d-816b-3c48cd4f6c9e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=559493964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.559493964
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.3713731489
Short name	T376
Test name
Test status
Simulation time	11125637 ps
CPU time	1.28 seconds
Started	Jan 10 12:44:01 PM PST 24
Finished	Jan 10 12:45:18 PM PST 24
Peak memory	201712 kb
Host	smart-5fb85a63-6680-4fda-83fe-1ed50f810cb4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713731489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3713731489
Directory	/workspace/41.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all.3745942617
Short name	T415
Test name
Test status
Simulation time	3138979565 ps
CPU time	64.41 seconds
Started	Jan 10 12:44:08 PM PST 24
Finished	Jan 10 12:46:29 PM PST 24
Peak memory	203684 kb
Host	smart-b58c1bce-3491-4e3e-b034-04c52873df67
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3745942617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3745942617
Directory	/workspace/41.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2912517159
Short name	T740
Test name
Test status
Simulation time	3705181836 ps
CPU time	28.86 seconds
Started	Jan 10 12:44:12 PM PST 24
Finished	Jan 10 12:45:57 PM PST 24
Peak memory	201688 kb
Host	smart-f59460dd-499d-45f9-b77b-4a135eb11e10
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2912517159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2912517159
Directory	/workspace/41.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.960331627
Short name	T495
Test name
Test status
Simulation time	643273039 ps
CPU time	55.58 seconds
Started	Jan 10 12:44:09 PM PST 24
Finished	Jan 10 12:46:20 PM PST 24
Peak memory	204040 kb
Host	smart-6a17e2c2-a875-4afa-a380-273a72de392f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=960331627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand _reset.960331627
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2409231347
Short name	T630
Test name
Test status
Simulation time	9564447331 ps
CPU time	113.14 seconds
Started	Jan 10 12:44:03 PM PST 24
Finished	Jan 10 12:47:12 PM PST 24
Peak memory	206764 kb
Host	smart-d10dccb0-10da-445b-b53a-be64318dd4f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2409231347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.2409231347
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1485019129
Short name	T33
Test name
Test status
Simulation time	686354419 ps
CPU time	13.35 seconds
Started	Jan 10 12:44:01 PM PST 24
Finished	Jan 10 12:45:30 PM PST 24
Peak memory	201632 kb
Host	smart-c9285994-6a0e-4115-a237-e60c579b979c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1485019129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1485019129
Directory	/workspace/41.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3507146260
Short name	T45
Test name
Test status
Simulation time	428081969 ps
CPU time	10.93 seconds
Started	Jan 10 12:44:05 PM PST 24
Finished	Jan 10 12:45:31 PM PST 24
Peak memory	201676 kb
Host	smart-61a6aaa6-9eb8-41c8-877e-8e7a8ab4e47c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3507146260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3507146260
Directory	/workspace/42.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3196399929
Short name	T484
Test name
Test status
Simulation time	8436916868 ps
CPU time	32.9 seconds
Started	Jan 10 12:44:09 PM PST 24
Finished	Jan 10 12:45:58 PM PST 24
Peak memory	201808 kb
Host	smart-b0ad0319-fcf4-421c-830d-8f8f0e050c31
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3196399929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.3196399929
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3664911616
Short name	T829
Test name
Test status
Simulation time	83523819 ps
CPU time	4.87 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:45:27 PM PST 24
Peak memory	201724 kb
Host	smart-d5a87458-0452-40ba-a2b3-52787fb0b59d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3664911616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3664911616
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_random.875177792
Short name	T758
Test name
Test status
Simulation time	1832022663 ps
CPU time	5.71 seconds
Started	Jan 10 12:44:02 PM PST 24
Finished	Jan 10 12:45:23 PM PST 24
Peak memory	201588 kb
Host	smart-b9b98978-67ec-4acb-982c-cf94e669497a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=875177792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.875177792
Directory	/workspace/42.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random.3655891159
Short name	T490
Test name
Test status
Simulation time	32122025 ps
CPU time	1.2 seconds
Started	Jan 10 12:44:11 PM PST 24
Finished	Jan 10 12:45:28 PM PST 24
Peak memory	201552 kb
Host	smart-9b7653b1-9a32-4b49-9356-febde0e1d892
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3655891159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.3655891159
Directory	/workspace/42.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.793352000
Short name	T96
Test name
Test status
Simulation time	60956665599 ps
CPU time	59.08 seconds
Started	Jan 10 12:44:01 PM PST 24
Finished	Jan 10 12:46:15 PM PST 24
Peak memory	201804 kb
Host	smart-e73eb1d0-f51f-498d-9186-35f63b55df48
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=793352000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.793352000
Directory	/workspace/42.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.4005041143
Short name	T483
Test name
Test status
Simulation time	14074651042 ps
CPU time	36.25 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:46:10 PM PST 24
Peak memory	201800 kb
Host	smart-c0ae0a9a-1efb-4b4a-8785-563e0c9fb32b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4005041143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.4005041143
Directory	/workspace/42.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1819399983
Short name	T850
Test name
Test status
Simulation time	25516917 ps
CPU time	2.82 seconds
Started	Jan 10 12:44:03 PM PST 24
Finished	Jan 10 12:45:21 PM PST 24
Peak memory	201516 kb
Host	smart-51422a2c-eee5-4498-aeec-9c6eb9dd35d1
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819399983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1819399983
Directory	/workspace/42.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_same_source.2828371003
Short name	T827
Test name
Test status
Simulation time	56703539 ps
CPU time	2.47 seconds
Started	Jan 10 12:44:04 PM PST 24
Finished	Jan 10 12:45:32 PM PST 24
Peak memory	201584 kb
Host	smart-6f4a6486-398e-4d6a-8413-66ae5ab17220
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2828371003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2828371003
Directory	/workspace/42.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke.88215418
Short name	T78
Test name
Test status
Simulation time	57714919 ps
CPU time	1.37 seconds
Started	Jan 10 12:44:12 PM PST 24
Finished	Jan 10 12:45:30 PM PST 24
Peak memory	201724 kb
Host	smart-7c3a720a-c9ff-4750-b4c3-1271c6638a91
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=88215418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.88215418
Directory	/workspace/42.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2493920286
Short name	T519
Test name
Test status
Simulation time	4825506852 ps
CPU time	9.98 seconds
Started	Jan 10 12:44:02 PM PST 24
Finished	Jan 10 12:45:28 PM PST 24
Peak memory	201840 kb
Host	smart-ed488842-d4c4-4e66-ae9d-60ac6958149a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493920286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2493920286
Directory	/workspace/42.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.970919486
Short name	T266
Test name
Test status
Simulation time	2032185713 ps
CPU time	8.28 seconds
Started	Jan 10 12:44:08 PM PST 24
Finished	Jan 10 12:45:31 PM PST 24
Peak memory	201624 kb
Host	smart-fcf0121b-9605-417a-80ff-14b2b05a7a36
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=970919486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.970919486
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.536980984
Short name	T151
Test name
Test status
Simulation time	12698772 ps
CPU time	1.06 seconds
Started	Jan 10 12:44:09 PM PST 24
Finished	Jan 10 12:45:25 PM PST 24
Peak memory	201496 kb
Host	smart-b516dc1c-683a-4782-8658-a3e966495094
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536980984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.536980984
Directory	/workspace/42.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.1101843409
Short name	T788
Test name
Test status
Simulation time	8503413552 ps
CPU time	36.26 seconds
Started	Jan 10 12:44:01 PM PST 24
Finished	Jan 10 12:45:53 PM PST 24
Peak memory	203840 kb
Host	smart-a54ce19b-e0a8-4c68-8710-ec6b4ad3665d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1101843409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1101843409
Directory	/workspace/42.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2061528907
Short name	T501
Test name
Test status
Simulation time	4403791019 ps
CPU time	52.45 seconds
Started	Jan 10 12:43:59 PM PST 24
Finished	Jan 10 12:46:06 PM PST 24
Peak memory	202048 kb
Host	smart-1f0d7e83-feff-4d1c-8b17-76a0449e3a91
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2061528907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2061528907
Directory	/workspace/42.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1768963726
Short name	T799
Test name
Test status
Simulation time	555188155 ps
CPU time	117.41 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:47:19 PM PST 24
Peak memory	205972 kb
Host	smart-bf25b88c-75a7-4be2-a47a-1b38c6a54f83
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1768963726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1768963726
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3924629059
Short name	T115
Test name
Test status
Simulation time	2381909543 ps
CPU time	64.82 seconds
Started	Jan 10 12:44:03 PM PST 24
Finished	Jan 10 12:46:23 PM PST 24
Peak memory	204500 kb
Host	smart-39ee6ce4-76ae-4474-887f-07f5b7555064
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3924629059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.3924629059
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.3745728687
Short name	T88
Test name
Test status
Simulation time	1166221904 ps
CPU time	10.28 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:45:36 PM PST 24
Peak memory	201628 kb
Host	smart-490f5001-d3b9-4ab4-9fbb-47b5accb7567
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3745728687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3745728687
Directory	/workspace/42.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1843730513
Short name	T216
Test name
Test status
Simulation time	730059257 ps
CPU time	8.85 seconds
Started	Jan 10 12:44:15 PM PST 24
Finished	Jan 10 12:45:39 PM PST 24
Peak memory	201300 kb
Host	smart-6a9bfdf8-24bf-495c-9da7-370cd2ea5186
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1843730513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1843730513
Directory	/workspace/43.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3924905421
Short name	T220
Test name
Test status
Simulation time	125940920976 ps
CPU time	217.41 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:49:03 PM PST 24
Peak memory	202800 kb
Host	smart-f9e2c812-8295-4033-8873-618bd049d966
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3924905421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3924905421
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2733985032
Short name	T538
Test name
Test status
Simulation time	25466110 ps
CPU time	1.82 seconds
Started	Jan 10 12:44:14 PM PST 24
Finished	Jan 10 12:45:32 PM PST 24
Peak memory	201984 kb
Host	smart-5247adc7-e95f-46f1-acbf-dc59d5d54daf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2733985032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2733985032
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_random.2412032071
Short name	T675
Test name
Test status
Simulation time	1715365266 ps
CPU time	8.99 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:45:31 PM PST 24
Peak memory	201588 kb
Host	smart-e12b4ed7-8962-4cc2-9fb0-99d26fedec05
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2412032071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2412032071
Directory	/workspace/43.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random.4155432823
Short name	T374
Test name
Test status
Simulation time	45112415 ps
CPU time	3.25 seconds
Started	Jan 10 12:44:12 PM PST 24
Finished	Jan 10 12:45:32 PM PST 24
Peak memory	201468 kb
Host	smart-58af5f26-c037-44da-8e25-30fb65ea375a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4155432823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.4155432823
Directory	/workspace/43.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.3589280673
Short name	T619
Test name
Test status
Simulation time	18369733174 ps
CPU time	47.6 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:46:10 PM PST 24
Peak memory	201776 kb
Host	smart-7785a8b0-24cd-4cb6-8e98-f3bc31754366
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589280673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3589280673
Directory	/workspace/43.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3816743340
Short name	T369
Test name
Test status
Simulation time	16851203343 ps
CPU time	119.48 seconds
Started	Jan 10 12:44:15 PM PST 24
Finished	Jan 10 12:47:29 PM PST 24
Peak memory	201372 kb
Host	smart-1bdf9de2-9d48-4eea-bc0a-d6f5eaab6f6f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3816743340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3816743340
Directory	/workspace/43.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3059384713
Short name	T153
Test name
Test status
Simulation time	56779704 ps
CPU time	5.63 seconds
Started	Jan 10 12:44:04 PM PST 24
Finished	Jan 10 12:45:26 PM PST 24
Peak memory	201624 kb
Host	smart-cc195cc3-4ed1-41d8-b310-76beb2d8bb49
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059384713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3059384713
Directory	/workspace/43.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_same_source.1337151778
Short name	T871
Test name
Test status
Simulation time	766287780 ps
CPU time	5.84 seconds
Started	Jan 10 12:44:11 PM PST 24
Finished	Jan 10 12:45:33 PM PST 24
Peak memory	201568 kb
Host	smart-6cc4f80e-a29e-410e-999f-ce561350629e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1337151778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1337151778
Directory	/workspace/43.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke.4251574905
Short name	T457
Test name
Test status
Simulation time	54442227 ps
CPU time	1.5 seconds
Started	Jan 10 12:44:05 PM PST 24
Finished	Jan 10 12:45:23 PM PST 24
Peak memory	201720 kb
Host	smart-f9f4ca46-baca-42e6-b04b-59638b55c3f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4251574905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.4251574905
Directory	/workspace/43.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2416843824
Short name	T602
Test name
Test status
Simulation time	2109790292 ps
CPU time	8.38 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:45:34 PM PST 24
Peak memory	201712 kb
Host	smart-4d6f08b3-eba1-43c2-bd92-80c21478faad
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416843824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2416843824
Directory	/workspace/43.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1212978921
Short name	T747
Test name
Test status
Simulation time	3357151560 ps
CPU time	8.18 seconds
Started	Jan 10 12:44:12 PM PST 24
Finished	Jan 10 12:45:37 PM PST 24
Peak memory	201548 kb
Host	smart-31826cd7-b90a-41b5-b0a2-cd537c5c5751
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1212978921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1212978921
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1358171371
Short name	T387
Test name
Test status
Simulation time	9297988 ps
CPU time	1.01 seconds
Started	Jan 10 12:44:02 PM PST 24
Finished	Jan 10 12:45:17 PM PST 24
Peak memory	201600 kb
Host	smart-78e45ec6-a13c-4d2b-8de0-894566cce6f5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358171371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1358171371
Directory	/workspace/43.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all.2433334412
Short name	T49
Test name
Test status
Simulation time	360836110 ps
CPU time	42.21 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:46:04 PM PST 24
Peak memory	203448 kb
Host	smart-e3351515-8055-41ec-ad43-95eef05a11b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2433334412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2433334412
Directory	/workspace/43.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.708137911
Short name	T208
Test name
Test status
Simulation time	21080339346 ps
CPU time	53.59 seconds
Started	Jan 10 12:44:08 PM PST 24
Finished	Jan 10 12:46:16 PM PST 24
Peak memory	202748 kb
Host	smart-d7458321-a1c5-414b-9ab6-995339b2c4f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=708137911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.708137911
Directory	/workspace/43.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1258773716
Short name	T779
Test name
Test status
Simulation time	103456168 ps
CPU time	2.62 seconds
Started	Jan 10 12:44:11 PM PST 24
Finished	Jan 10 12:45:30 PM PST 24
Peak memory	201604 kb
Host	smart-03225d81-63f6-48a5-969b-d0f1ae0866d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1258773716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.1258773716
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3989636792
Short name	T428
Test name
Test status
Simulation time	74496459 ps
CPU time	11.48 seconds
Started	Jan 10 12:44:11 PM PST 24
Finished	Jan 10 12:45:38 PM PST 24
Peak memory	201600 kb
Host	smart-80e82188-0012-4ca1-b19b-bce356622edc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3989636792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3989636792
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.866873933
Short name	T601
Test name
Test status
Simulation time	109626886 ps
CPU time	4.71 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:45:26 PM PST 24
Peak memory	201584 kb
Host	smart-e00b2e74-2c5a-4d4f-bc11-d9fbcc439ae1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=866873933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.866873933
Directory	/workspace/43.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1694125207
Short name	T580
Test name
Test status
Simulation time	295686521 ps
CPU time	10.18 seconds
Started	Jan 10 12:44:41 PM PST 24
Finished	Jan 10 12:46:08 PM PST 24
Peak memory	201596 kb
Host	smart-24a14e27-c925-40ab-912a-b9982333cf43
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1694125207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1694125207
Directory	/workspace/44.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.747407637
Short name	T137
Test name
Test status
Simulation time	42488966993 ps
CPU time	54.88 seconds
Started	Jan 10 12:44:10 PM PST 24
Finished	Jan 10 12:46:21 PM PST 24
Peak memory	201748 kb
Host	smart-738808b6-7d41-4daa-84d3-d8908e698184
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=747407637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo w_rsp.747407637
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3838654092
Short name	T283
Test name
Test status
Simulation time	549267014 ps
CPU time	8.9 seconds
Started	Jan 10 12:44:16 PM PST 24
Finished	Jan 10 12:45:41 PM PST 24
Peak memory	201580 kb
Host	smart-44a0c6f0-d725-4d4a-8388-0d0705980c1e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3838654092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3838654092
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_random.1797504466
Short name	T592
Test name
Test status
Simulation time	523834063 ps
CPU time	8.43 seconds
Started	Jan 10 12:44:18 PM PST 24
Finished	Jan 10 12:45:43 PM PST 24
Peak memory	201552 kb
Host	smart-e60d355f-5b85-41c7-8d4d-5e1fe49f48aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1797504466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1797504466
Directory	/workspace/44.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random.3762800230
Short name	T391
Test name
Test status
Simulation time	1511560715 ps
CPU time	7.69 seconds
Started	Jan 10 12:44:35 PM PST 24
Finished	Jan 10 12:46:00 PM PST 24
Peak memory	201720 kb
Host	smart-0d883070-2649-4262-b274-0de144dd18e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3762800230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.3762800230
Directory	/workspace/44.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.4012342422
Short name	T431
Test name
Test status
Simulation time	31222504954 ps
CPU time	64.21 seconds
Started	Jan 10 12:44:20 PM PST 24
Finished	Jan 10 12:46:40 PM PST 24
Peak memory	201624 kb
Host	smart-45afcc52-869a-4222-9757-ca255870b308
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012342422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.4012342422
Directory	/workspace/44.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3032350632
Short name	T688
Test name
Test status
Simulation time	15248100156 ps
CPU time	81.32 seconds
Started	Jan 10 12:44:20 PM PST 24
Finished	Jan 10 12:46:57 PM PST 24
Peak memory	201660 kb
Host	smart-83c6e597-05ad-4eb6-9ad7-0de2fb13d707
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3032350632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3032350632
Directory	/workspace/44.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1900074176
Short name	T18
Test name
Test status
Simulation time	34983620 ps
CPU time	3.61 seconds
Started	Jan 10 12:44:18 PM PST 24
Finished	Jan 10 12:45:39 PM PST 24
Peak memory	201536 kb
Host	smart-4c1288db-644d-4d72-8dbf-1ae584c40543
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900074176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1900074176
Directory	/workspace/44.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_same_source.3263052338
Short name	T899
Test name
Test status
Simulation time	688012947 ps
CPU time	8.6 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:45:34 PM PST 24
Peak memory	201704 kb
Host	smart-cf94ad89-74bb-46bc-a483-134317755f4c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3263052338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3263052338
Directory	/workspace/44.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke.2823757535
Short name	T69
Test name
Test status
Simulation time	12971758 ps
CPU time	1.17 seconds
Started	Jan 10 12:44:10 PM PST 24
Finished	Jan 10 12:45:28 PM PST 24
Peak memory	201588 kb
Host	smart-ed3c84a6-d7be-47aa-91c8-fc1abb433526
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2823757535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2823757535
Directory	/workspace/44.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3331809360
Short name	T362
Test name
Test status
Simulation time	2461511239 ps
CPU time	8.04 seconds
Started	Jan 10 12:44:20 PM PST 24
Finished	Jan 10 12:45:46 PM PST 24
Peak memory	201672 kb
Host	smart-27356be1-9c56-4e9f-8467-9f358525d509
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331809360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3331809360
Directory	/workspace/44.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2776469974
Short name	T847
Test name
Test status
Simulation time	1215188126 ps
CPU time	7.22 seconds
Started	Jan 10 12:44:18 PM PST 24
Finished	Jan 10 12:45:42 PM PST 24
Peak memory	201556 kb
Host	smart-10be191d-950e-40a9-b0ee-52b3694cd65d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2776469974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2776469974
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.351232077
Short name	T762
Test name
Test status
Simulation time	11688609 ps
CPU time	1.1 seconds
Started	Jan 10 12:44:19 PM PST 24
Finished	Jan 10 12:45:36 PM PST 24
Peak memory	201608 kb
Host	smart-98400146-7655-43e9-a05f-27d367927052
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351232077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.351232077
Directory	/workspace/44.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all.3534380214
Short name	T620
Test name
Test status
Simulation time	289498775 ps
CPU time	29.36 seconds
Started	Jan 10 12:44:18 PM PST 24
Finished	Jan 10 12:46:04 PM PST 24
Peak memory	201596 kb
Host	smart-eda0b717-0a8a-498b-9b36-26bdcc796f36
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3534380214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3534380214
Directory	/workspace/44.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1659347672
Short name	T276
Test name
Test status
Simulation time	702707426 ps
CPU time	23.14 seconds
Started	Jan 10 12:44:12 PM PST 24
Finished	Jan 10 12:45:51 PM PST 24
Peak memory	201580 kb
Host	smart-76b3b450-8666-47ef-a51f-34636eb76db4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1659347672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1659347672
Directory	/workspace/44.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.92415755
Short name	T125
Test name
Test status
Simulation time	5256792382 ps
CPU time	115.55 seconds
Started	Jan 10 12:44:30 PM PST 24
Finished	Jan 10 12:47:42 PM PST 24
Peak memory	205052 kb
Host	smart-5cc2322f-155f-44ca-9c9a-16d8565be05a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=92415755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_ reset.92415755
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.600224415
Short name	T832
Test name
Test status
Simulation time	375194070 ps
CPU time	31.53 seconds
Started	Jan 10 12:44:18 PM PST 24
Finished	Jan 10 12:46:07 PM PST 24
Peak memory	202996 kb
Host	smart-9e444f93-93ed-47fa-92e2-098f5151ba11
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=600224415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_res et_error.600224415
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.709734059
Short name	T166
Test name
Test status
Simulation time	1328390260 ps
CPU time	10.66 seconds
Started	Jan 10 12:44:30 PM PST 24
Finished	Jan 10 12:45:57 PM PST 24
Peak memory	201552 kb
Host	smart-b704223e-28b4-48f0-964d-b239e824cfbb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=709734059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.709734059
Directory	/workspace/44.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device.1515025915
Short name	T510
Test name
Test status
Simulation time	1562440289 ps
CPU time	15.93 seconds
Started	Jan 10 12:44:10 PM PST 24
Finished	Jan 10 12:45:42 PM PST 24
Peak memory	201728 kb
Host	smart-f30d42a6-5dd1-4a13-9259-7e19dcbf7084
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1515025915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1515025915
Directory	/workspace/45.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.131403660
Short name	T881
Test name
Test status
Simulation time	27448640098 ps
CPU time	167.28 seconds
Started	Jan 10 12:44:21 PM PST 24
Finished	Jan 10 12:48:24 PM PST 24
Peak memory	202644 kb
Host	smart-3d571bd0-454d-47e5-ab5e-06bf26cc038d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=131403660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo w_rsp.131403660
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3251429659
Short name	T843
Test name
Test status
Simulation time	352045712 ps
CPU time	5.76 seconds
Started	Jan 10 12:44:21 PM PST 24
Finished	Jan 10 12:45:43 PM PST 24
Peak memory	201540 kb
Host	smart-356745d6-64f7-45af-8bec-d7da3b50b049
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3251429659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3251429659
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_random.863017913
Short name	T400
Test name
Test status
Simulation time	23435166 ps
CPU time	1.3 seconds
Started	Jan 10 12:44:18 PM PST 24
Finished	Jan 10 12:45:35 PM PST 24
Peak memory	201596 kb
Host	smart-3557efc9-f44a-459b-b69f-aade5cb15fe4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=863017913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.863017913
Directory	/workspace/45.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random.3843032157
Short name	T603
Test name
Test status
Simulation time	1301775793 ps
CPU time	15.62 seconds
Started	Jan 10 12:44:10 PM PST 24
Finished	Jan 10 12:45:42 PM PST 24
Peak memory	201536 kb
Host	smart-5ab5a3d2-a468-43c1-97bb-5169ac7aa072
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3843032157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3843032157
Directory	/workspace/45.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.479208629
Short name	T73
Test name
Test status
Simulation time	52882984983 ps
CPU time	152.38 seconds
Started	Jan 10 12:44:06 PM PST 24
Finished	Jan 10 12:47:54 PM PST 24
Peak memory	201772 kb
Host	smart-abd85b6a-ac38-4aa6-b09a-a192dcb20b99
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=479208629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.479208629
Directory	/workspace/45.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2603951208
Short name	T375
Test name
Test status
Simulation time	24623853577 ps
CPU time	96.16 seconds
Started	Jan 10 12:44:33 PM PST 24
Finished	Jan 10 12:47:26 PM PST 24
Peak memory	201672 kb
Host	smart-88678d86-4cad-4570-8036-febad740839d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2603951208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2603951208
Directory	/workspace/45.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2290022239
Short name	T155
Test name
Test status
Simulation time	53183527 ps
CPU time	5.47 seconds
Started	Jan 10 12:44:18 PM PST 24
Finished	Jan 10 12:45:41 PM PST 24
Peak memory	201536 kb
Host	smart-661e270b-a8b1-4309-a2c6-50691f435563
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290022239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2290022239
Directory	/workspace/45.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_same_source.173936362
Short name	T508
Test name
Test status
Simulation time	15648487 ps
CPU time	1.56 seconds
Started	Jan 10 12:44:12 PM PST 24
Finished	Jan 10 12:45:30 PM PST 24
Peak memory	201736 kb
Host	smart-c7f25eda-5730-4bd1-bb75-62f66947167a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=173936362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.173936362
Directory	/workspace/45.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke.1787632855
Short name	T322
Test name
Test status
Simulation time	97759665 ps
CPU time	1.68 seconds
Started	Jan 10 12:44:07 PM PST 24
Finished	Jan 10 12:45:28 PM PST 24
Peak memory	201696 kb
Host	smart-88eae0d1-020e-4ad6-8553-9b7f98c7044f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1787632855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1787632855
Directory	/workspace/45.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2470499289
Short name	T814
Test name
Test status
Simulation time	2228636804 ps
CPU time	6.93 seconds
Started	Jan 10 12:44:21 PM PST 24
Finished	Jan 10 12:45:44 PM PST 24
Peak memory	201620 kb
Host	smart-055500aa-7f2a-4e04-8bc5-1f11cbbf5ce3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2470499289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2470499289
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1611571895
Short name	T188
Test name
Test status
Simulation time	43397230 ps
CPU time	1.3 seconds
Started	Jan 10 12:44:05 PM PST 24
Finished	Jan 10 12:45:21 PM PST 24
Peak memory	201604 kb
Host	smart-e4d59637-3486-4f68-b51d-29314431a799
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611571895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1611571895
Directory	/workspace/45.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all.4260897016
Short name	T551
Test name
Test status
Simulation time	57389749 ps
CPU time	5.28 seconds
Started	Jan 10 12:44:20 PM PST 24
Finished	Jan 10 12:45:41 PM PST 24
Peak memory	201600 kb
Host	smart-f9b97c2e-cd20-44e3-8bab-d68d7aa262ff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4260897016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.4260897016
Directory	/workspace/45.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.575536216
Short name	T268
Test name
Test status
Simulation time	1329031850 ps
CPU time	13.22 seconds
Started	Jan 10 12:44:15 PM PST 24
Finished	Jan 10 12:45:44 PM PST 24
Peak memory	201632 kb
Host	smart-2e3e635a-4c2e-494e-8b30-01f6793b659b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=575536216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.575536216
Directory	/workspace/45.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2124078918
Short name	T99
Test name
Test status
Simulation time	4264753282 ps
CPU time	98.66 seconds
Started	Jan 10 12:44:21 PM PST 24
Finished	Jan 10 12:47:16 PM PST 24
Peak memory	203800 kb
Host	smart-bc8ff41a-ea22-4505-b78d-b0eaf0418c49
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2124078918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.2124078918
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2840153088
Short name	T427
Test name
Test status
Simulation time	505382190 ps
CPU time	51.49 seconds
Started	Jan 10 12:44:34 PM PST 24
Finished	Jan 10 12:46:43 PM PST 24
Peak memory	203840 kb
Host	smart-3f9eadb4-c051-4b9c-812d-08e810298289
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2840153088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.2840153088
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.2162089758
Short name	T591
Test name
Test status
Simulation time	90308446 ps
CPU time	2.47 seconds
Started	Jan 10 12:44:13 PM PST 24
Finished	Jan 10 12:45:31 PM PST 24
Peak memory	201624 kb
Host	smart-29630c8e-6fee-4558-b470-7bfb4057d01a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2162089758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2162089758
Directory	/workspace/45.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device.19621590
Short name	T31
Test name
Test status
Simulation time	820029775 ps
CPU time	13.1 seconds
Started	Jan 10 12:44:17 PM PST 24
Finished	Jan 10 12:45:47 PM PST 24
Peak memory	201636 kb
Host	smart-f3171795-1782-4793-b1c1-8f308b90b007
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=19621590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.19621590
Directory	/workspace/46.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1838883810
Short name	T110
Test name
Test status
Simulation time	44476149385 ps
CPU time	154.91 seconds
Started	Jan 10 12:44:18 PM PST 24
Finished	Jan 10 12:48:09 PM PST 24
Peak memory	202828 kb
Host	smart-6d645c4c-54e6-4b91-be77-d0a14668b348
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1838883810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.1838883810
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.344978808
Short name	T3
Test name
Test status
Simulation time	28690705 ps
CPU time	2.67 seconds
Started	Jan 10 12:44:26 PM PST 24
Finished	Jan 10 12:45:45 PM PST 24
Peak memory	201720 kb
Host	smart-4e59cb11-695b-4f60-b688-642b7ba7caa2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=344978808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.344978808
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_random.1256828178
Short name	T525
Test name
Test status
Simulation time	68180200 ps
CPU time	5.83 seconds
Started	Jan 10 12:44:19 PM PST 24
Finished	Jan 10 12:45:44 PM PST 24
Peak memory	201720 kb
Host	smart-05518b4b-304b-4fe8-a591-57f28cb4965f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1256828178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1256828178
Directory	/workspace/46.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random.3070580275
Short name	T77
Test name
Test status
Simulation time	1579442151 ps
CPU time	11.29 seconds
Started	Jan 10 12:44:21 PM PST 24
Finished	Jan 10 12:45:54 PM PST 24
Peak memory	201600 kb
Host	smart-50a06eab-d126-43d3-ab48-2b984a440076
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3070580275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3070580275
Directory	/workspace/46.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.2296205795
Short name	T365
Test name
Test status
Simulation time	201113855131 ps
CPU time	203.09 seconds
Started	Jan 10 12:44:20 PM PST 24
Finished	Jan 10 12:48:59 PM PST 24
Peak memory	201764 kb
Host	smart-cb5af678-e2f7-4bc0-b4d7-7eaaa2af4e17
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296205795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2296205795
Directory	/workspace/46.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3486583367
Short name	T640
Test name
Test status
Simulation time	54274351463 ps
CPU time	82.66 seconds
Started	Jan 10 12:44:20 PM PST 24
Finished	Jan 10 12:46:59 PM PST 24
Peak memory	201832 kb
Host	smart-becd4241-3226-4c31-bc36-254094071fdb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3486583367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3486583367
Directory	/workspace/46.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2773799899
Short name	T872
Test name
Test status
Simulation time	58673164 ps
CPU time	3.91 seconds
Started	Jan 10 12:44:17 PM PST 24
Finished	Jan 10 12:45:37 PM PST 24
Peak memory	201720 kb
Host	smart-7a7189f4-deac-4a78-b9e0-42590875d19d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773799899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2773799899
Directory	/workspace/46.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_same_source.3793719007
Short name	T311
Test name
Test status
Simulation time	804811427 ps
CPU time	5.38 seconds
Started	Jan 10 12:44:19 PM PST 24
Finished	Jan 10 12:45:44 PM PST 24
Peak memory	201700 kb
Host	smart-84139458-2412-4b1d-8aa7-fe8cbc361363
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3793719007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3793719007
Directory	/workspace/46.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke.225740321
Short name	T417
Test name
Test status
Simulation time	51006304 ps
CPU time	1.21 seconds
Started	Jan 10 12:44:16 PM PST 24
Finished	Jan 10 12:45:33 PM PST 24
Peak memory	201708 kb
Host	smart-8859a5bc-b65c-46cd-a4a2-da29b019fb3c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=225740321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.225740321
Directory	/workspace/46.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2017802214
Short name	T117
Test name
Test status
Simulation time	1902177460 ps
CPU time	9.65 seconds
Started	Jan 10 12:44:20 PM PST 24
Finished	Jan 10 12:45:45 PM PST 24
Peak memory	201584 kb
Host	smart-2e3e8b86-255c-433e-b419-0c0ecfdfd266
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017802214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2017802214
Directory	/workspace/46.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3957987221
Short name	T406
Test name
Test status
Simulation time	1805902321 ps
CPU time	4.79 seconds
Started	Jan 10 12:44:20 PM PST 24
Finished	Jan 10 12:45:41 PM PST 24
Peak memory	201728 kb
Host	smart-ebafaff3-c43f-42e3-a0ea-ba6f629b44b6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3957987221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3957987221
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3138728901
Short name	T340
Test name
Test status
Simulation time	9481585 ps
CPU time	1.22 seconds
Started	Jan 10 12:44:13 PM PST 24
Finished	Jan 10 12:45:31 PM PST 24
Peak memory	201760 kb
Host	smart-90f8281b-5b42-4ee2-a3a9-30e341b286ed
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138728901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3138728901
Directory	/workspace/46.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all.1262317891
Short name	T726
Test name
Test status
Simulation time	3820985811 ps
CPU time	62.63 seconds
Started	Jan 10 12:44:19 PM PST 24
Finished	Jan 10 12:46:41 PM PST 24
Peak memory	201804 kb
Host	smart-9ceddae9-cd9b-4a78-9276-1249c30e4f3c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1262317891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1262317891
Directory	/workspace/46.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1656617078
Short name	T199
Test name
Test status
Simulation time	22860257494 ps
CPU time	86.63 seconds
Started	Jan 10 12:44:18 PM PST 24
Finished	Jan 10 12:47:00 PM PST 24
Peak memory	201804 kb
Host	smart-3ff20083-016a-4c7c-a95d-922abbb40c86
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1656617078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1656617078
Directory	/workspace/46.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2403620805
Short name	T566
Test name
Test status
Simulation time	142428227 ps
CPU time	21.01 seconds
Started	Jan 10 12:44:25 PM PST 24
Finished	Jan 10 12:46:02 PM PST 24
Peak memory	203532 kb
Host	smart-6ec57f8c-c404-45ea-937b-ace0bc17a43a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2403620805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.2403620805
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.4078199380
Short name	T685
Test name
Test status
Simulation time	20018418 ps
CPU time	4.34 seconds
Started	Jan 10 12:44:33 PM PST 24
Finished	Jan 10 12:45:55 PM PST 24
Peak memory	201708 kb
Host	smart-4c9c9c2e-6d10-4d8c-b999-ef0a622f86cb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4078199380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.4078199380
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1840190855
Short name	T102
Test name
Test status
Simulation time	552887514 ps
CPU time	3.45 seconds
Started	Jan 10 12:44:29 PM PST 24
Finished	Jan 10 12:45:49 PM PST 24
Peak memory	201724 kb
Host	smart-421af666-3040-4e68-8950-916854512dcc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1840190855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1840190855
Directory	/workspace/46.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device.4283418674
Short name	T100
Test name
Test status
Simulation time	449656593 ps
CPU time	7.87 seconds
Started	Jan 10 12:44:30 PM PST 24
Finished	Jan 10 12:45:54 PM PST 24
Peak memory	201620 kb
Host	smart-d12660f1-1163-46aa-b835-4ad2942036f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4283418674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.4283418674
Directory	/workspace/47.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1938729458
Short name	T163
Test name
Test status
Simulation time	19462887509 ps
CPU time	64.06 seconds
Started	Jan 10 12:44:21 PM PST 24
Finished	Jan 10 12:46:41 PM PST 24
Peak memory	201772 kb
Host	smart-fc0d2e70-86be-4a6c-b268-eda07a6d88a9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1938729458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.1938729458
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3609532483
Short name	T821
Test name
Test status
Simulation time	9724686 ps
CPU time	1.01 seconds
Started	Jan 10 12:44:26 PM PST 24
Finished	Jan 10 12:45:44 PM PST 24
Peak memory	201672 kb
Host	smart-b8283b9f-e027-449c-95f9-6353188b3919
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3609532483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3609532483
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_random.3511528277
Short name	T432
Test name
Test status
Simulation time	2536429825 ps
CPU time	10.19 seconds
Started	Jan 10 12:44:21 PM PST 24
Finished	Jan 10 12:45:47 PM PST 24
Peak memory	201684 kb
Host	smart-67ef45d5-f3fb-4b43-9326-83885eccf610
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3511528277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3511528277
Directory	/workspace/47.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random.3959038965
Short name	T464
Test name
Test status
Simulation time	39549214 ps
CPU time	4.25 seconds
Started	Jan 10 12:44:20 PM PST 24
Finished	Jan 10 12:45:40 PM PST 24
Peak memory	201972 kb
Host	smart-eb25cd18-4dbf-4890-a48f-1f4edbedb262
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3959038965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3959038965
Directory	/workspace/47.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1802426047
Short name	T147
Test name
Test status
Simulation time	26614952227 ps
CPU time	123.65 seconds
Started	Jan 10 12:44:23 PM PST 24
Finished	Jan 10 12:47:43 PM PST 24
Peak memory	201716 kb
Host	smart-80f55b88-9e53-4b91-a746-108edd19d6c5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802426047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1802426047
Directory	/workspace/47.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.926083318
Short name	T123
Test name
Test status
Simulation time	15318198217 ps
CPU time	78.89 seconds
Started	Jan 10 12:44:26 PM PST 24
Finished	Jan 10 12:47:02 PM PST 24
Peak memory	201688 kb
Host	smart-1eae4538-4561-4883-9822-8e451f9c18bf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=926083318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.926083318
Directory	/workspace/47.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3058907602
Short name	T270
Test name
Test status
Simulation time	78138671 ps
CPU time	4.44 seconds
Started	Jan 10 12:44:17 PM PST 24
Finished	Jan 10 12:45:37 PM PST 24
Peak memory	201584 kb
Host	smart-08d4b531-01f6-418c-a07c-e2ce5ad98359
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058907602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3058907602
Directory	/workspace/47.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_same_source.2251713566
Short name	T295
Test name
Test status
Simulation time	6921922023 ps
CPU time	11.67 seconds
Started	Jan 10 12:44:20 PM PST 24
Finished	Jan 10 12:45:47 PM PST 24
Peak memory	201816 kb
Host	smart-4d42d0e2-dfea-4f63-ad0f-43b99822ee78
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2251713566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2251713566
Directory	/workspace/47.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke.3520362633
Short name	T398
Test name
Test status
Simulation time	275446145 ps
CPU time	1.81 seconds
Started	Jan 10 12:44:18 PM PST 24
Finished	Jan 10 12:45:36 PM PST 24
Peak memory	201740 kb
Host	smart-1e847b56-b334-48da-8133-1b303f299093
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3520362633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3520362633
Directory	/workspace/47.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1723540044
Short name	T470
Test name
Test status
Simulation time	1373179843 ps
CPU time	5.76 seconds
Started	Jan 10 12:44:19 PM PST 24
Finished	Jan 10 12:45:44 PM PST 24
Peak memory	201740 kb
Host	smart-f64bfe14-f6f4-4e67-918a-ba85aeffc69e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723540044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1723540044
Directory	/workspace/47.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3781362480
Short name	T86
Test name
Test status
Simulation time	8339569988 ps
CPU time	9.05 seconds
Started	Jan 10 12:44:23 PM PST 24
Finished	Jan 10 12:45:48 PM PST 24
Peak memory	201628 kb
Host	smart-42215032-5477-41ee-89cc-6dd8f18fddaa
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3781362480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3781362480
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3545136061
Short name	T248
Test name
Test status
Simulation time	12935044 ps
CPU time	1.24 seconds
Started	Jan 10 12:44:23 PM PST 24
Finished	Jan 10 12:45:40 PM PST 24
Peak memory	201724 kb
Host	smart-c737a352-f504-4a2a-8692-b3d63cfa279e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545136061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3545136061
Directory	/workspace/47.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all.3810638372
Short name	T335
Test name
Test status
Simulation time	12545835459 ps
CPU time	23.48 seconds
Started	Jan 10 12:44:17 PM PST 24
Finished	Jan 10 12:45:56 PM PST 24
Peak memory	201708 kb
Host	smart-661e5c0c-83a0-4627-9fde-da72d3493cb0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3810638372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3810638372
Directory	/workspace/47.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2796535372
Short name	T468
Test name
Test status
Simulation time	22430846270 ps
CPU time	75.77 seconds
Started	Jan 10 12:44:26 PM PST 24
Finished	Jan 10 12:46:58 PM PST 24
Peak memory	201748 kb
Host	smart-4a22ed5b-c093-4421-97e9-a0660360b81b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2796535372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2796535372
Directory	/workspace/47.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2179632069
Short name	T530
Test name
Test status
Simulation time	203708326 ps
CPU time	19.67 seconds
Started	Jan 10 12:44:24 PM PST 24
Finished	Jan 10 12:46:00 PM PST 24
Peak memory	202852 kb
Host	smart-858d6e5d-9d30-4956-9284-29374efcd58f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2179632069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.2179632069
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1251282319
Short name	T600
Test name
Test status
Simulation time	862646879 ps
CPU time	72.54 seconds
Started	Jan 10 12:44:32 PM PST 24
Finished	Jan 10 12:47:02 PM PST 24
Peak memory	204244 kb
Host	smart-b4b181c6-fee7-4d3b-a009-e7a9205e8dc4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1251282319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.1251282319
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1532578355
Short name	T130
Test name
Test status
Simulation time	625443907 ps
CPU time	5.32 seconds
Started	Jan 10 12:44:35 PM PST 24
Finished	Jan 10 12:45:57 PM PST 24
Peak memory	201540 kb
Host	smart-94baa4b6-b587-4466-b306-a63fbceede88
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1532578355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1532578355
Directory	/workspace/47.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3232732661
Short name	T58
Test name
Test status
Simulation time	2827853625 ps
CPU time	21.96 seconds
Started	Jan 10 12:44:41 PM PST 24
Finished	Jan 10 12:46:20 PM PST 24
Peak memory	201668 kb
Host	smart-5edeb765-f0d0-4cec-a881-dd72c81bed2c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3232732661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3232732661
Directory	/workspace/48.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3570643027
Short name	T869
Test name
Test status
Simulation time	6643228460 ps
CPU time	36.03 seconds
Started	Jan 10 12:44:25 PM PST 24
Finished	Jan 10 12:46:17 PM PST 24
Peak memory	201796 kb
Host	smart-fd65471a-c1d0-4392-8637-1c204b98bcb7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3570643027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.3570643027
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3268117775
Short name	T574
Test name
Test status
Simulation time	330232609 ps
CPU time	3.87 seconds
Started	Jan 10 12:44:37 PM PST 24
Finished	Jan 10 12:45:58 PM PST 24
Peak memory	201596 kb
Host	smart-f4cab64d-bf4b-4b18-af42-1ae0ccac6cf7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3268117775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3268117775
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_random.2561388945
Short name	T516
Test name
Test status
Simulation time	2772929162 ps
CPU time	5.27 seconds
Started	Jan 10 12:44:26 PM PST 24
Finished	Jan 10 12:45:48 PM PST 24
Peak memory	201760 kb
Host	smart-eb683ee7-2067-497d-829a-08024c1f78aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2561388945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2561388945
Directory	/workspace/48.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random.1277083557
Short name	T866
Test name
Test status
Simulation time	28258422 ps
CPU time	2.95 seconds
Started	Jan 10 12:44:24 PM PST 24
Finished	Jan 10 12:45:43 PM PST 24
Peak memory	201724 kb
Host	smart-67c27043-2452-40d9-997a-f225e057f1e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1277083557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1277083557
Directory	/workspace/48.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.343367394
Short name	T264
Test name
Test status
Simulation time	5367143827 ps
CPU time	20.79 seconds
Started	Jan 10 12:44:28 PM PST 24
Finished	Jan 10 12:46:05 PM PST 24
Peak memory	201716 kb
Host	smart-65aa86e3-b288-4fad-bc96-ec2e113f09f6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=343367394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.343367394
Directory	/workspace/48.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.937235442
Short name	T459
Test name
Test status
Simulation time	4789449658 ps
CPU time	30.17 seconds
Started	Jan 10 12:44:44 PM PST 24
Finished	Jan 10 12:46:31 PM PST 24
Peak memory	201792 kb
Host	smart-8d4ebd60-4a9a-4a01-9a5a-22c185c696c6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=937235442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.937235442
Directory	/workspace/48.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3432311225
Short name	T312
Test name
Test status
Simulation time	162251719 ps
CPU time	8.41 seconds
Started	Jan 10 12:44:27 PM PST 24
Finished	Jan 10 12:45:52 PM PST 24
Peak memory	201716 kb
Host	smart-76466e54-a220-41fe-8af9-d3d15adaa894
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432311225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3432311225
Directory	/workspace/48.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_same_source.2323271509
Short name	T71
Test name
Test status
Simulation time	1576844636 ps
CPU time	7.62 seconds
Started	Jan 10 12:44:35 PM PST 24
Finished	Jan 10 12:46:00 PM PST 24
Peak memory	201548 kb
Host	smart-718f7134-6118-4814-a521-53256ceae7b0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2323271509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2323271509
Directory	/workspace/48.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke.2557441281
Short name	T381
Test name
Test status
Simulation time	49109902 ps
CPU time	1.37 seconds
Started	Jan 10 12:44:36 PM PST 24
Finished	Jan 10 12:45:55 PM PST 24
Peak memory	201728 kb
Host	smart-3c33e92a-8374-4784-ac14-b15eb948b111
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2557441281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2557441281
Directory	/workspace/48.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.387255899
Short name	T655
Test name
Test status
Simulation time	2345289954 ps
CPU time	8.26 seconds
Started	Jan 10 12:44:43 PM PST 24
Finished	Jan 10 12:46:08 PM PST 24
Peak memory	201680 kb
Host	smart-d1452b17-b5e4-4715-9b84-839ca3b5a475
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=387255899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.387255899
Directory	/workspace/48.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3161228929
Short name	T626
Test name
Test status
Simulation time	1155556961 ps
CPU time	5.78 seconds
Started	Jan 10 12:44:48 PM PST 24
Finished	Jan 10 12:46:12 PM PST 24
Peak memory	201524 kb
Host	smart-b75574ef-7461-473c-9cec-c8df66eb1158
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3161228929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3161228929
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3672063506
Short name	T721
Test name
Test status
Simulation time	10670590 ps
CPU time	1 seconds
Started	Jan 10 12:44:27 PM PST 24
Finished	Jan 10 12:45:45 PM PST 24
Peak memory	201676 kb
Host	smart-1208e577-7b0c-4532-ba87-d89db0dff794
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672063506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3672063506
Directory	/workspace/48.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all.3861906639
Short name	T527
Test name
Test status
Simulation time	448916678 ps
CPU time	47.54 seconds
Started	Jan 10 12:44:23 PM PST 24
Finished	Jan 10 12:46:26 PM PST 24
Peak memory	202736 kb
Host	smart-943efd5d-fa6f-4bb2-9bae-f3b02adc8429
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3861906639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3861906639
Directory	/workspace/48.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2511544825
Short name	T209
Test name
Test status
Simulation time	3422858535 ps
CPU time	43.03 seconds
Started	Jan 10 12:44:33 PM PST 24
Finished	Jan 10 12:46:33 PM PST 24
Peak memory	201692 kb
Host	smart-c9849f21-a311-4634-b7a0-172a732bbfec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2511544825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2511544825
Directory	/workspace/48.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1433694829
Short name	T421
Test name
Test status
Simulation time	905126204 ps
CPU time	144.89 seconds
Started	Jan 10 12:44:31 PM PST 24
Finished	Jan 10 12:48:12 PM PST 24
Peak memory	205536 kb
Host	smart-6bdbdbc8-8cec-4179-98f8-6ea25d580164
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1433694829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.1433694829
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.157783517
Short name	T835
Test name
Test status
Simulation time	7678866587 ps
CPU time	69.7 seconds
Started	Jan 10 12:44:29 PM PST 24
Finished	Jan 10 12:46:55 PM PST 24
Peak memory	203328 kb
Host	smart-903cd45b-fecd-4e0f-9d72-4bc7722a6c67
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=157783517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_res et_error.157783517
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3036878499
Short name	T116
Test name
Test status
Simulation time	39033430 ps
CPU time	5.63 seconds
Started	Jan 10 12:44:27 PM PST 24
Finished	Jan 10 12:45:49 PM PST 24
Peak memory	201724 kb
Host	smart-054db05d-77ce-4202-a418-42e187256e40
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3036878499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3036878499
Directory	/workspace/48.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2390101731
Short name	T87
Test name
Test status
Simulation time	939123565 ps
CPU time	10.03 seconds
Started	Jan 10 12:44:26 PM PST 24
Finished	Jan 10 12:45:52 PM PST 24
Peak memory	201628 kb
Host	smart-fd09d757-21ec-4d56-8da0-6610730ff745
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2390101731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2390101731
Directory	/workspace/49.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.4260129510
Short name	T211
Test name
Test status
Simulation time	120236462982 ps
CPU time	152.16 seconds
Started	Jan 10 12:44:31 PM PST 24
Finished	Jan 10 12:48:19 PM PST 24
Peak memory	202836 kb
Host	smart-f70264d8-a466-4c4e-ad46-616ceeb19d0a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4260129510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.4260129510
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.215928575
Short name	T319
Test name
Test status
Simulation time	445974752 ps
CPU time	6.12 seconds
Started	Jan 10 12:44:35 PM PST 24
Finished	Jan 10 12:45:59 PM PST 24
Peak memory	201544 kb
Host	smart-629cf17b-b2bb-4d60-a475-3ead75c56ba0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=215928575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.215928575
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_random.3410525967
Short name	T845
Test name
Test status
Simulation time	83050144 ps
CPU time	1.85 seconds
Started	Jan 10 12:44:35 PM PST 24
Finished	Jan 10 12:45:54 PM PST 24
Peak memory	201612 kb
Host	smart-ac60ac90-8bc0-4e07-a13a-cf13ba7eaa95
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3410525967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3410525967
Directory	/workspace/49.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random.1816478307
Short name	T325
Test name
Test status
Simulation time	132794716 ps
CPU time	2.36 seconds
Started	Jan 10 12:44:48 PM PST 24
Finished	Jan 10 12:46:08 PM PST 24
Peak memory	201508 kb
Host	smart-b4ed2dbf-a12c-4f4e-b73d-5a116dc0b476
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1816478307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1816478307
Directory	/workspace/49.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3717034266
Short name	T30
Test name
Test status
Simulation time	9360848726 ps
CPU time	23.76 seconds
Started	Jan 10 12:44:25 PM PST 24
Finished	Jan 10 12:46:05 PM PST 24
Peak memory	201756 kb
Host	smart-c367724c-c097-455b-8c04-397d75eece8d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717034266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3717034266
Directory	/workspace/49.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1657579083
Short name	T650
Test name
Test status
Simulation time	12401885762 ps
CPU time	86.81 seconds
Started	Jan 10 12:44:31 PM PST 24
Finished	Jan 10 12:47:14 PM PST 24
Peak memory	201776 kb
Host	smart-35351f0c-a346-4101-bd70-eec1301ecb1e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1657579083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1657579083
Directory	/workspace/49.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1161712842
Short name	T321
Test name
Test status
Simulation time	55393532 ps
CPU time	5.45 seconds
Started	Jan 10 12:44:29 PM PST 24
Finished	Jan 10 12:45:50 PM PST 24
Peak memory	201612 kb
Host	smart-41f3dc83-7a9f-470e-879c-1c88bcaf6fc3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161712842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1161712842
Directory	/workspace/49.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke.3449741252
Short name	T699
Test name
Test status
Simulation time	10479736 ps
CPU time	1.23 seconds
Started	Jan 10 12:44:40 PM PST 24
Finished	Jan 10 12:45:59 PM PST 24
Peak memory	201556 kb
Host	smart-31b0937b-7ded-4539-8e01-adf36295a6a2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3449741252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3449741252
Directory	/workspace/49.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1531202772
Short name	T890
Test name
Test status
Simulation time	6781176115 ps
CPU time	8.36 seconds
Started	Jan 10 12:44:29 PM PST 24
Finished	Jan 10 12:45:54 PM PST 24
Peak memory	201788 kb
Host	smart-1f4ac185-3644-45d4-aa4b-a434866d4391
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531202772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1531202772
Directory	/workspace/49.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2860846042
Short name	T382
Test name
Test status
Simulation time	2731507995 ps
CPU time	7.89 seconds
Started	Jan 10 12:44:28 PM PST 24
Finished	Jan 10 12:45:52 PM PST 24
Peak memory	201760 kb
Host	smart-62ab48bd-01ec-440d-a8ac-7cc28222028c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2860846042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2860846042
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2772524271
Short name	T141
Test name
Test status
Simulation time	12878755 ps
CPU time	1.07 seconds
Started	Jan 10 12:44:25 PM PST 24
Finished	Jan 10 12:45:42 PM PST 24
Peak memory	201604 kb
Host	smart-148d61ea-ca4d-461c-b68c-41cf83b927d8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772524271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2772524271
Directory	/workspace/49.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all.3059348930
Short name	T455
Test name
Test status
Simulation time	104597861 ps
CPU time	10.02 seconds
Started	Jan 10 12:44:26 PM PST 24
Finished	Jan 10 12:45:53 PM PST 24
Peak memory	201732 kb
Host	smart-2d41cc49-8d1e-49bc-ba12-8b5c703e5ac8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3059348930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3059348930
Directory	/workspace/49.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2639988389
Short name	T584
Test name
Test status
Simulation time	4769701397 ps
CPU time	38.68 seconds
Started	Jan 10 12:44:48 PM PST 24
Finished	Jan 10 12:46:45 PM PST 24
Peak memory	201576 kb
Host	smart-65e2acd5-0adf-42fd-b3ec-29e8479237f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2639988389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2639988389
Directory	/workspace/49.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3709063434
Short name	T497
Test name
Test status
Simulation time	1420259938 ps
CPU time	129.93 seconds
Started	Jan 10 12:44:24 PM PST 24
Finished	Jan 10 12:47:50 PM PST 24
Peak memory	207404 kb
Host	smart-8e2f3922-c470-4672-a15e-eefd9b429989
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3709063434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.3709063434
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3800001711
Short name	T204
Test name
Test status
Simulation time	358502046 ps
CPU time	56.38 seconds
Started	Jan 10 12:44:41 PM PST 24
Finished	Jan 10 12:46:55 PM PST 24
Peak memory	203828 kb
Host	smart-435401d1-e3b6-4ce8-81e9-b88ce13f0d30
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3800001711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.3800001711
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1643807601
Short name	T63
Test name
Test status
Simulation time	998621431 ps
CPU time	12.63 seconds
Started	Jan 10 12:44:29 PM PST 24
Finished	Jan 10 12:45:58 PM PST 24
Peak memory	201744 kb
Host	smart-bfaa9e0f-5832-47bb-9ecb-da1cfe936291
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1643807601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1643807601
Directory	/workspace/49.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2857877300
Short name	T226
Test name
Test status
Simulation time	8634127143 ps
CPU time	67.83 seconds
Started	Jan 10 12:42:15 PM PST 24
Finished	Jan 10 12:44:36 PM PST 24
Peak memory	201724 kb
Host	smart-8288e6d8-09ad-4294-b342-2d132b623c7a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2857877300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.2857877300
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.39639386
Short name	T337
Test name
Test status
Simulation time	108148387 ps
CPU time	2.7 seconds
Started	Jan 10 12:42:24 PM PST 24
Finished	Jan 10 12:43:39 PM PST 24
Peak memory	201552 kb
Host	smart-f081e4b4-ee2f-4bb0-809e-a0d137fe2a8b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=39639386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.39639386
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_random.3166339520
Short name	T344
Test name
Test status
Simulation time	68801252 ps
CPU time	3.69 seconds
Started	Jan 10 12:42:17 PM PST 24
Finished	Jan 10 12:43:33 PM PST 24
Peak memory	201748 kb
Host	smart-fafa5bba-4b59-4358-93e1-132d82dfd23b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3166339520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3166339520
Directory	/workspace/5.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random.1670835693
Short name	T805
Test name
Test status
Simulation time	43004969 ps
CPU time	1.28 seconds
Started	Jan 10 12:42:27 PM PST 24
Finished	Jan 10 12:43:41 PM PST 24
Peak memory	201632 kb
Host	smart-52876e44-85f4-4721-994a-30312cfb0ac2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1670835693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1670835693
Directory	/workspace/5.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.4022027694
Short name	T101
Test name
Test status
Simulation time	175430411932 ps
CPU time	105.04 seconds
Started	Jan 10 12:42:18 PM PST 24
Finished	Jan 10 12:45:16 PM PST 24
Peak memory	201808 kb
Host	smart-8cc01305-7701-4a2f-af47-625ac65e8729
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022027694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4022027694
Directory	/workspace/5.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3401777652
Short name	T656
Test name
Test status
Simulation time	6108206267 ps
CPU time	28.48 seconds
Started	Jan 10 12:42:30 PM PST 24
Finished	Jan 10 12:44:12 PM PST 24
Peak memory	201748 kb
Host	smart-615646e3-b0c8-42b3-b378-4c91bc1aab07
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3401777652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3401777652
Directory	/workspace/5.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1828160968
Short name	T705
Test name
Test status
Simulation time	33420292 ps
CPU time	3.45 seconds
Started	Jan 10 12:42:17 PM PST 24
Finished	Jan 10 12:43:33 PM PST 24
Peak memory	201696 kb
Host	smart-48bf66b1-9373-455c-b632-cb2a93049296
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828160968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1828160968
Directory	/workspace/5.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_same_source.1727616176
Short name	T855
Test name
Test status
Simulation time	896479636 ps
CPU time	8.1 seconds
Started	Jan 10 12:42:16 PM PST 24
Finished	Jan 10 12:43:37 PM PST 24
Peak memory	201644 kb
Host	smart-3f694832-289f-4da6-8dbb-265d3d5dc2d9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1727616176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1727616176
Directory	/workspace/5.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke.788007912
Short name	T360
Test name
Test status
Simulation time	64314258 ps
CPU time	1.59 seconds
Started	Jan 10 12:42:20 PM PST 24
Finished	Jan 10 12:43:38 PM PST 24
Peak memory	201636 kb
Host	smart-f1271f04-535f-4bbc-bef3-8e1f78796c0b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=788007912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.788007912
Directory	/workspace/5.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3593913907
Short name	T291
Test name
Test status
Simulation time	5492339687 ps
CPU time	9.76 seconds
Started	Jan 10 12:42:16 PM PST 24
Finished	Jan 10 12:43:38 PM PST 24
Peak memory	201620 kb
Host	smart-4dfce20a-6f8e-4fa8-9e8d-90d2ece05983
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593913907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3593913907
Directory	/workspace/5.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3850592515
Short name	T194
Test name
Test status
Simulation time	1236511763 ps
CPU time	6.92 seconds
Started	Jan 10 12:42:23 PM PST 24
Finished	Jan 10 12:43:44 PM PST 24
Peak memory	201624 kb
Host	smart-d43f2701-1c00-4ca2-8d45-7b5ae29f1c39
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3850592515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3850592515
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.192393716
Short name	T874
Test name
Test status
Simulation time	9971778 ps
CPU time	1.14 seconds
Started	Jan 10 12:42:25 PM PST 24
Finished	Jan 10 12:43:42 PM PST 24
Peak memory	201712 kb
Host	smart-e5f9851f-fbbd-4afe-a937-a2787a0a641f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192393716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.192393716
Directory	/workspace/5.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all.1176894119
Short name	T777
Test name
Test status
Simulation time	634055348 ps
CPU time	72.71 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:44:48 PM PST 24
Peak memory	202512 kb
Host	smart-767e23d7-b291-442c-ac9b-2991009c5b40
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1176894119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1176894119
Directory	/workspace/5.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.837963772
Short name	T368
Test name
Test status
Simulation time	1122588369 ps
CPU time	40.2 seconds
Started	Jan 10 12:42:18 PM PST 24
Finished	Jan 10 12:44:11 PM PST 24
Peak memory	201632 kb
Host	smart-f2d3f9cb-c737-4dd7-bb7f-1d428ca1ad1c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=837963772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.837963772
Directory	/workspace/5.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1087801621
Short name	T103
Test name
Test status
Simulation time	657249142 ps
CPU time	38.02 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:44:10 PM PST 24
Peak memory	204164 kb
Host	smart-c11fb14c-03ab-4ea3-992a-cbeb01f1f165
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1087801621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.1087801621
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1782979452
Short name	T353
Test name
Test status
Simulation time	73093290 ps
CPU time	13.29 seconds
Started	Jan 10 12:42:16 PM PST 24
Finished	Jan 10 12:43:42 PM PST 24
Peak memory	202768 kb
Host	smart-411b9a69-8be5-4a43-885c-3b9d2d48649e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1782979452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.1782979452
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3759991869
Short name	T801
Test name
Test status
Simulation time	446677608 ps
CPU time	4.72 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:43:36 PM PST 24
Peak memory	201472 kb
Host	smart-658f0865-3da9-4ccc-b0f4-a38aa596cf30
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3759991869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3759991869
Directory	/workspace/5.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device.1242744833
Short name	T569
Test name
Test status
Simulation time	40232981 ps
CPU time	6.54 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:43:39 PM PST 24
Peak memory	201612 kb
Host	smart-47b121c9-df1b-47ee-8098-538ecc822e74
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1242744833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1242744833
Directory	/workspace/6.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.4094129578
Short name	T886
Test name
Test status
Simulation time	53348509735 ps
CPU time	307.6 seconds
Started	Jan 10 12:42:17 PM PST 24
Finished	Jan 10 12:48:37 PM PST 24
Peak memory	203872 kb
Host	smart-df73fd18-b08f-439e-a06e-6994b8cb3c3f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4094129578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.4094129578
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3384607787
Short name	T485
Test name
Test status
Simulation time	183720710 ps
CPU time	3.37 seconds
Started	Jan 10 12:42:18 PM PST 24
Finished	Jan 10 12:43:34 PM PST 24
Peak memory	201716 kb
Host	smart-3cccfc98-3297-4a66-b2ff-42d93e95c340
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3384607787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3384607787
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_random.4164199130
Short name	T449
Test name
Test status
Simulation time	1223315238 ps
CPU time	10.07 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:43:43 PM PST 24
Peak memory	201748 kb
Host	smart-da5b74a2-bb29-4c6c-9aed-eddbeaaa46f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4164199130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.4164199130
Directory	/workspace/6.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random.428598738
Short name	T565
Test name
Test status
Simulation time	1853234236 ps
CPU time	5.08 seconds
Started	Jan 10 12:42:14 PM PST 24
Finished	Jan 10 12:43:32 PM PST 24
Peak memory	201608 kb
Host	smart-b688a697-cdb1-4d59-b031-82a09eeb5a2b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=428598738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.428598738
Directory	/workspace/6.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2675767577
Short name	T751
Test name
Test status
Simulation time	35001983092 ps
CPU time	40.02 seconds
Started	Jan 10 12:42:18 PM PST 24
Finished	Jan 10 12:44:11 PM PST 24
Peak memory	201792 kb
Host	smart-098b4d3b-0474-4632-9f1e-911f0711bdbc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675767577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2675767577
Directory	/workspace/6.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3549657414
Short name	T865
Test name
Test status
Simulation time	3620691140 ps
CPU time	22.61 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:43:58 PM PST 24
Peak memory	201452 kb
Host	smart-ab7f3f67-63bf-4c94-af61-87838aa986d4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3549657414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3549657414
Directory	/workspace/6.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.4200664065
Short name	T358
Test name
Test status
Simulation time	60804559 ps
CPU time	7.29 seconds
Started	Jan 10 12:42:17 PM PST 24
Finished	Jan 10 12:43:37 PM PST 24
Peak memory	201668 kb
Host	smart-aa019d9f-726a-4ecd-8348-42c89f3b5f31
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200664065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.4200664065
Directory	/workspace/6.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_same_source.2621702853
Short name	T533
Test name
Test status
Simulation time	2673097569 ps
CPU time	13.21 seconds
Started	Jan 10 12:42:30 PM PST 24
Finished	Jan 10 12:43:56 PM PST 24
Peak memory	201756 kb
Host	smart-a7fbb036-e29a-450c-86f1-41ba44800df3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2621702853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2621702853
Directory	/workspace/6.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke.1715323628
Short name	T657
Test name
Test status
Simulation time	35864709 ps
CPU time	1.29 seconds
Started	Jan 10 12:42:16 PM PST 24
Finished	Jan 10 12:43:30 PM PST 24
Peak memory	201756 kb
Host	smart-c6c08ac5-c17e-478e-a849-1d7994609824
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1715323628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1715323628
Directory	/workspace/6.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1867332259
Short name	T712
Test name
Test status
Simulation time	2580312649 ps
CPU time	8.29 seconds
Started	Jan 10 12:42:14 PM PST 24
Finished	Jan 10 12:43:35 PM PST 24
Peak memory	201796 kb
Host	smart-9a335d8e-6e74-461c-ab99-d2b88557ed11
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867332259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1867332259
Directory	/workspace/6.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1975115501
Short name	T349
Test name
Test status
Simulation time	3360713639 ps
CPU time	7.5 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:43:44 PM PST 24
Peak memory	201824 kb
Host	smart-abbc0671-43b5-4158-a710-c37a3fbf72d2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1975115501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1975115501
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.928814120
Short name	T536
Test name
Test status
Simulation time	10352437 ps
CPU time	1.21 seconds
Started	Jan 10 12:42:25 PM PST 24
Finished	Jan 10 12:43:42 PM PST 24
Peak memory	201604 kb
Host	smart-11246e9f-287d-42e6-8847-b91d1941175e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928814120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.928814120
Directory	/workspace/6.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all.3439122388
Short name	T144
Test name
Test status
Simulation time	7758827928 ps
CPU time	97.28 seconds
Started	Jan 10 12:42:16 PM PST 24
Finished	Jan 10 12:45:06 PM PST 24
Peak memory	202804 kb
Host	smart-3d4db95d-a720-484e-beae-7086ce1ce904
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3439122388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3439122388
Directory	/workspace/6.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.132036274
Short name	T540
Test name
Test status
Simulation time	4481206516 ps
CPU time	19.89 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:43:52 PM PST 24
Peak memory	201608 kb
Host	smart-fbb6130f-2686-4f01-a4d8-2656f7b46c5e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=132036274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.132036274
Directory	/workspace/6.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.941137653
Short name	T236
Test name
Test status
Simulation time	4318524603 ps
CPU time	83.84 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:44:57 PM PST 24
Peak memory	204300 kb
Host	smart-e7eb4ecd-81ba-4705-bc6f-9b016f16052e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=941137653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rese t_error.941137653
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.856259437
Short name	T715
Test name
Test status
Simulation time	55828652 ps
CPU time	3.93 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:43:39 PM PST 24
Peak memory	201704 kb
Host	smart-893df401-a25c-44d0-b2a2-13fee57b5968
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=856259437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.856259437
Directory	/workspace/6.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2178787608
Short name	T701
Test name
Test status
Simulation time	1365830632 ps
CPU time	16.46 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:43:49 PM PST 24
Peak memory	201520 kb
Host	smart-605443ee-d22f-4968-8fc1-52f463879f22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2178787608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2178787608
Directory	/workspace/7.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3470700421
Short name	T214
Test name
Test status
Simulation time	163165417263 ps
CPU time	388.92 seconds
Started	Jan 10 12:42:22 PM PST 24
Finished	Jan 10 12:50:08 PM PST 24
Peak memory	204396 kb
Host	smart-b133a3de-e733-42c0-b718-6f5fb42ee7c4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3470700421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.3470700421
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.4084203272
Short name	T254
Test name
Test status
Simulation time	598291853 ps
CPU time	6.11 seconds
Started	Jan 10 12:42:23 PM PST 24
Finished	Jan 10 12:43:45 PM PST 24
Peak memory	201668 kb
Host	smart-23491637-dbc0-4fd2-9449-32079ef856e9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4084203272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.4084203272
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_random.3066873143
Short name	T366
Test name
Test status
Simulation time	645709246 ps
CPU time	12.53 seconds
Started	Jan 10 12:42:18 PM PST 24
Finished	Jan 10 12:43:44 PM PST 24
Peak memory	201600 kb
Host	smart-5a042374-fd25-4334-bce2-0fa3cbf3d8f0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3066873143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3066873143
Directory	/workspace/7.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random.1807979783
Short name	T29
Test name
Test status
Simulation time	632754587 ps
CPU time	10.05 seconds
Started	Jan 10 12:42:22 PM PST 24
Finished	Jan 10 12:43:45 PM PST 24
Peak memory	201576 kb
Host	smart-6d9d6721-bc2e-4c5d-b9b0-fc2638075a63
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1807979783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1807979783
Directory	/workspace/7.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1164720281
Short name	T68
Test name
Test status
Simulation time	22597307903 ps
CPU time	28.39 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:44:04 PM PST 24
Peak memory	201812 kb
Host	smart-fd8f639b-4851-4699-baba-21a2fe47a569
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164720281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1164720281
Directory	/workspace/7.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.155606069
Short name	T891
Test name
Test status
Simulation time	29417868637 ps
CPU time	95.69 seconds
Started	Jan 10 12:42:18 PM PST 24
Finished	Jan 10 12:45:09 PM PST 24
Peak memory	201776 kb
Host	smart-7a388e3d-f3aa-482a-aa73-ee2b4f0b330a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=155606069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.155606069
Directory	/workspace/7.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.2794089140
Short name	T713
Test name
Test status
Simulation time	61053397 ps
CPU time	8 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:43:43 PM PST 24
Peak memory	201600 kb
Host	smart-77c073e5-d808-482d-ab11-2bfe2324b7de
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794089140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.2794089140
Directory	/workspace/7.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_same_source.1820732273
Short name	T37
Test name
Test status
Simulation time	3025585008 ps
CPU time	8.43 seconds
Started	Jan 10 12:42:18 PM PST 24
Finished	Jan 10 12:43:39 PM PST 24
Peak memory	201672 kb
Host	smart-3a54f222-863b-4275-93f8-77e5d79c24ac
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1820732273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1820732273
Directory	/workspace/7.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke.2014556441
Short name	T895
Test name
Test status
Simulation time	45473731 ps
CPU time	1.55 seconds
Started	Jan 10 12:42:17 PM PST 24
Finished	Jan 10 12:43:32 PM PST 24
Peak memory	201636 kb
Host	smart-fe8361aa-e825-45ff-a54c-310ade555698
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2014556441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2014556441
Directory	/workspace/7.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2941370140
Short name	T156
Test name
Test status
Simulation time	3539125860 ps
CPU time	10.33 seconds
Started	Jan 10 12:42:18 PM PST 24
Finished	Jan 10 12:43:41 PM PST 24
Peak memory	202012 kb
Host	smart-706d28f4-806d-42c3-ae1d-a8517d5f0a20
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941370140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2941370140
Directory	/workspace/7.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3641800370
Short name	T615
Test name
Test status
Simulation time	1722309682 ps
CPU time	6.5 seconds
Started	Jan 10 12:42:22 PM PST 24
Finished	Jan 10 12:43:46 PM PST 24
Peak memory	201740 kb
Host	smart-c900268b-37fb-43c3-9fb8-d12282a1880e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3641800370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3641800370
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2720237670
Short name	T897
Test name
Test status
Simulation time	13015988 ps
CPU time	1.28 seconds
Started	Jan 10 12:42:25 PM PST 24
Finished	Jan 10 12:43:42 PM PST 24
Peak memory	201756 kb
Host	smart-42bf3d3f-e4a1-4a8b-92f3-87c244742079
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720237670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2720237670
Directory	/workspace/7.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all.253284116
Short name	T604
Test name
Test status
Simulation time	343859307 ps
CPU time	22.32 seconds
Started	Jan 10 12:42:17 PM PST 24
Finished	Jan 10 12:43:52 PM PST 24
Peak memory	201604 kb
Host	smart-f0c3af9b-9173-41fe-b577-d625e70d2e3e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=253284116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.253284116
Directory	/workspace/7.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2416963032
Short name	T599
Test name
Test status
Simulation time	11531724241 ps
CPU time	59.97 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:44:35 PM PST 24
Peak memory	201816 kb
Host	smart-1b66666a-8ca2-423a-964e-83424bfaa0f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2416963032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2416963032
Directory	/workspace/7.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.121380110
Short name	T472
Test name
Test status
Simulation time	347711341 ps
CPU time	60.58 seconds
Started	Jan 10 12:42:24 PM PST 24
Finished	Jan 10 12:44:38 PM PST 24
Peak memory	203976 kb
Host	smart-8bae0ea1-a5e0-47eb-b10c-ece73fc4b738
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=121380110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_ reset.121380110
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2213235742
Short name	T347
Test name
Test status
Simulation time	369174571 ps
CPU time	41.19 seconds
Started	Jan 10 12:42:26 PM PST 24
Finished	Jan 10 12:44:23 PM PST 24
Peak memory	203140 kb
Host	smart-7e7c84fb-6eba-4e12-82d3-8ef947921b73
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2213235742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.2213235742
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.4227835800
Short name	T541
Test name
Test status
Simulation time	10897506 ps
CPU time	0.98 seconds
Started	Jan 10 12:42:30 PM PST 24
Finished	Jan 10 12:43:44 PM PST 24
Peak memory	201684 kb
Host	smart-170ecdbb-a4bb-4f27-aebe-eb664e152a0a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4227835800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.4227835800
Directory	/workspace/7.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3247182779
Short name	T149
Test name
Test status
Simulation time	1536324537 ps
CPU time	13.96 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:43:49 PM PST 24
Peak memory	201720 kb
Host	smart-ee8812e2-6e29-45ea-920c-4b84a5cc0973
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3247182779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3247182779
Directory	/workspace/8.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3709384099
Short name	T228
Test name
Test status
Simulation time	49386088098 ps
CPU time	71.29 seconds
Started	Jan 10 12:42:31 PM PST 24
Finished	Jan 10 12:45:05 PM PST 24
Peak memory	201816 kb
Host	smart-193746d9-3e13-4d98-8d5b-2c7447ee3575
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3709384099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.3709384099
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.470046633
Short name	T460
Test name
Test status
Simulation time	36276657 ps
CPU time	3.73 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:43:39 PM PST 24
Peak memory	201576 kb
Host	smart-edb0e568-cdd6-4946-8a4c-8e972ff3ff42
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=470046633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.470046633
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_random.2123119891
Short name	T745
Test name
Test status
Simulation time	10338889 ps
CPU time	1.19 seconds
Started	Jan 10 12:42:35 PM PST 24
Finished	Jan 10 12:43:50 PM PST 24
Peak memory	201564 kb
Host	smart-4659f77e-ef68-4565-907e-bf937157be1a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2123119891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2123119891
Directory	/workspace/8.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random.456304445
Short name	T488
Test name
Test status
Simulation time	142645862 ps
CPU time	1.26 seconds
Started	Jan 10 12:42:34 PM PST 24
Finished	Jan 10 12:43:49 PM PST 24
Peak memory	201588 kb
Host	smart-1abfd986-78f9-46a8-8c9c-ac789e0a5f7f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=456304445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.456304445
Directory	/workspace/8.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2126481296
Short name	T506
Test name
Test status
Simulation time	47456159288 ps
CPU time	142.87 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:46:01 PM PST 24
Peak memory	201812 kb
Host	smart-0e3132ad-99ce-4aa4-9188-56815c4f4125
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126481296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2126481296
Directory	/workspace/8.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2031747827
Short name	T648
Test name
Test status
Simulation time	1307501044 ps
CPU time	8.19 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:43:43 PM PST 24
Peak memory	201764 kb
Host	smart-51a65504-61fd-433e-948d-6a42d5219512
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2031747827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2031747827
Directory	/workspace/8.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.2342923805
Short name	T40
Test name
Test status
Simulation time	71542896 ps
CPU time	5.73 seconds
Started	Jan 10 12:42:31 PM PST 24
Finished	Jan 10 12:43:53 PM PST 24
Peak memory	201688 kb
Host	smart-6561500d-f921-4c8c-bfa9-210fedf2fe0d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342923805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2342923805
Directory	/workspace/8.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_same_source.628126646
Short name	T851
Test name
Test status
Simulation time	100796308 ps
CPU time	3.38 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:43:38 PM PST 24
Peak memory	201684 kb
Host	smart-848cc6c4-c33c-4736-aa5b-fa8c830d5b7b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=628126646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.628126646
Directory	/workspace/8.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke.1031086227
Short name	T471
Test name
Test status
Simulation time	68910000 ps
CPU time	1.58 seconds
Started	Jan 10 12:42:27 PM PST 24
Finished	Jan 10 12:43:41 PM PST 24
Peak memory	201600 kb
Host	smart-decfece0-ca89-4105-8abc-a8fecd9f61b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1031086227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1031086227
Directory	/workspace/8.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1388379017
Short name	T59
Test name
Test status
Simulation time	2937196619 ps
CPU time	13.05 seconds
Started	Jan 10 12:42:31 PM PST 24
Finished	Jan 10 12:44:00 PM PST 24
Peak memory	201764 kb
Host	smart-f4a53717-9965-49f5-8b43-f3a811b296c7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388379017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1388379017
Directory	/workspace/8.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2953380331
Short name	T570
Test name
Test status
Simulation time	1429346443 ps
CPU time	5.52 seconds
Started	Jan 10 12:42:19 PM PST 24
Finished	Jan 10 12:43:37 PM PST 24
Peak memory	201384 kb
Host	smart-b19047a0-9573-4909-b82c-c49f03a524a1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2953380331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2953380331
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.630594121
Short name	T812
Test name
Test status
Simulation time	11858151 ps
CPU time	1.21 seconds
Started	Jan 10 12:42:16 PM PST 24
Finished	Jan 10 12:43:30 PM PST 24
Peak memory	201636 kb
Host	smart-fa7eb37c-bb53-4f1c-bd69-5c536a1f72e8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630594121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.630594121
Directory	/workspace/8.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all.2374167988
Short name	T539
Test name
Test status
Simulation time	8650168849 ps
CPU time	32.01 seconds
Started	Jan 10 12:42:28 PM PST 24
Finished	Jan 10 12:44:12 PM PST 24
Peak memory	201696 kb
Host	smart-e5a6340f-8400-4de6-8341-1031acd1beba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2374167988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2374167988
Directory	/workspace/8.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.3768556225
Short name	T720
Test name
Test status
Simulation time	282824618 ps
CPU time	25.65 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:44:15 PM PST 24
Peak memory	200796 kb
Host	smart-d983b088-1cfe-4496-a3cb-4663b6623d8b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3768556225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3768556225
Directory	/workspace/8.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2223674826
Short name	T614
Test name
Test status
Simulation time	222305241 ps
CPU time	25.26 seconds
Started	Jan 10 12:42:27 PM PST 24
Finished	Jan 10 12:44:05 PM PST 24
Peak memory	202652 kb
Host	smart-4ac1aa8e-39fc-4e52-948f-4ba378c2bbe1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2223674826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2223674826
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3723835611
Short name	T92
Test name
Test status
Simulation time	1353397692 ps
CPU time	7.05 seconds
Started	Jan 10 12:42:37 PM PST 24
Finished	Jan 10 12:43:58 PM PST 24
Peak memory	201576 kb
Host	smart-5a090b61-b4e8-4172-817f-1934faac551c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3723835611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3723835611
Directory	/workspace/8.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1378952307
Short name	T173
Test name
Test status
Simulation time	1939689420 ps
CPU time	9.6 seconds
Started	Jan 10 12:42:32 PM PST 24
Finished	Jan 10 12:43:55 PM PST 24
Peak memory	201604 kb
Host	smart-a490f63b-5348-489f-a973-7ebd3aabf6c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1378952307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1378952307
Directory	/workspace/9.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1643468746
Short name	T104
Test name
Test status
Simulation time	14686836795 ps
CPU time	76.98 seconds
Started	Jan 10 12:42:24 PM PST 24
Finished	Jan 10 12:45:06 PM PST 24
Peak memory	201708 kb
Host	smart-94266d27-2041-4e94-81f1-ea6e779ce121
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1643468746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.1643468746
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1360354586
Short name	T681
Test name
Test status
Simulation time	158835730 ps
CPU time	3.31 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:43:38 PM PST 24
Peak memory	201608 kb
Host	smart-94145208-616d-4366-910a-accd93655cf3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1360354586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1360354586
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_random.4231861838
Short name	T259
Test name
Test status
Simulation time	59795806 ps
CPU time	6.83 seconds
Started	Jan 10 12:42:22 PM PST 24
Finished	Jan 10 12:43:42 PM PST 24
Peak memory	201740 kb
Host	smart-d6198bf7-c5ac-4989-bd82-d6100d0711a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4231861838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.4231861838
Directory	/workspace/9.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random.3836279236
Short name	T255
Test name
Test status
Simulation time	87521580 ps
CPU time	6.14 seconds
Started	Jan 10 12:42:21 PM PST 24
Finished	Jan 10 12:43:44 PM PST 24
Peak memory	201596 kb
Host	smart-e6afef31-7b0b-4bbb-babf-84395c1ec117
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3836279236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3836279236
Directory	/workspace/9.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.907207357
Short name	T414
Test name
Test status
Simulation time	24548581299 ps
CPU time	94.99 seconds
Started	Jan 10 12:42:28 PM PST 24
Finished	Jan 10 12:45:18 PM PST 24
Peak memory	201744 kb
Host	smart-2acb6ce7-7cd2-4b5a-87a8-599192c79b97
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=907207357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.907207357
Directory	/workspace/9.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1014410141
Short name	T403
Test name
Test status
Simulation time	10887523943 ps
CPU time	68.22 seconds
Started	Jan 10 12:42:27 PM PST 24
Finished	Jan 10 12:44:48 PM PST 24
Peak memory	201808 kb
Host	smart-e41691df-c2e2-4786-8959-9ad099cb5ec5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1014410141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1014410141
Directory	/workspace/9.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.863507801
Short name	T754
Test name
Test status
Simulation time	173759259 ps
CPU time	4.84 seconds
Started	Jan 10 12:42:37 PM PST 24
Finished	Jan 10 12:43:59 PM PST 24
Peak memory	201616 kb
Host	smart-1b448484-a68a-4d4f-9088-0bd90676287e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863507801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.863507801
Directory	/workspace/9.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_same_source.3673891586
Short name	T370
Test name
Test status
Simulation time	3067908864 ps
CPU time	6.37 seconds
Started	Jan 10 12:42:24 PM PST 24
Finished	Jan 10 12:43:43 PM PST 24
Peak memory	201828 kb
Host	smart-c26b04e1-bee6-44ec-863d-e3f39ece18b7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3673891586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3673891586
Directory	/workspace/9.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke.3333947749
Short name	T299
Test name
Test status
Simulation time	9475236 ps
CPU time	1.15 seconds
Started	Jan 10 12:42:24 PM PST 24
Finished	Jan 10 12:43:38 PM PST 24
Peak memory	201756 kb
Host	smart-af31602f-6886-4c66-9d31-6f8a1458fba4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3333947749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3333947749
Directory	/workspace/9.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.2823055405
Short name	T342
Test name
Test status
Simulation time	1758482043 ps
CPU time	6.7 seconds
Started	Jan 10 12:42:27 PM PST 24
Finished	Jan 10 12:43:46 PM PST 24
Peak memory	201608 kb
Host	smart-5b04dae8-88ef-497f-bc6e-a0cbe7778fa2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823055405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2823055405
Directory	/workspace/9.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1377533340
Short name	T19
Test name
Test status
Simulation time	1147488024 ps
CPU time	8.4 seconds
Started	Jan 10 12:42:22 PM PST 24
Finished	Jan 10 12:43:44 PM PST 24
Peak memory	201640 kb
Host	smart-5ed8af99-6d37-41fc-91be-eb1180aed665
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1377533340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1377533340
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3309956313
Short name	T332
Test name
Test status
Simulation time	7749380 ps
CPU time	1.07 seconds
Started	Jan 10 12:42:27 PM PST 24
Finished	Jan 10 12:43:41 PM PST 24
Peak memory	201628 kb
Host	smart-2b992766-5d60-42ff-8dd0-af46163f37e3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309956313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3309956313
Directory	/workspace/9.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all.1079842743
Short name	T638
Test name
Test status
Simulation time	346444566 ps
CPU time	19.48 seconds
Started	Jan 10 12:42:24 PM PST 24
Finished	Jan 10 12:43:57 PM PST 24
Peak memory	201596 kb
Host	smart-dd750773-00ca-424b-ba79-a0a9d149cd08
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1079842743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1079842743
Directory	/workspace/9.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.630745913
Short name	T164
Test name
Test status
Simulation time	2791733890 ps
CPU time	62.19 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:44:52 PM PST 24
Peak memory	203980 kb
Host	smart-b8adff8a-edc1-46a5-86dd-21193b2d1118
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=630745913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_ reset.630745913
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.1808154689
Short name	T661
Test name
Test status
Simulation time	257217790 ps
CPU time	24.27 seconds
Started	Jan 10 12:42:36 PM PST 24
Finished	Jan 10 12:44:14 PM PST 24
Peak memory	202632 kb
Host	smart-9f28112c-9629-482e-8009-723368285603
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1808154689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.1808154689
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.562688194
Short name	T79
Test name
Test status
Simulation time	589019299 ps
CPU time	7.16 seconds
Started	Jan 10 12:42:28 PM PST 24
Finished	Jan 10 12:43:47 PM PST 24
Peak memory	201628 kb
Host	smart-f0ac8631-45ae-4665-9152-2e63a7732452
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=562688194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.562688194
Directory	/workspace/9.xbar_unmapped_addr/latest