Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=26}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	27	0	27	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	27	0	27	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	468	1			T4	1		T17	5		T18	1
all_values[1]	501	1			T4	2		T17	8		T18	5
all_values[2]	451	1			T17	9		T16	4		T25	1
all_values[3]	503	1			T3	2		T20	2		T17	6
all_values[4]	495	1			T17	4		T18	1		T15	1
all_values[5]	401	1			T4	1		T17	6		T15	1
all_values[6]	478	1			T20	2		T17	16		T18	1
all_values[7]	472	1			T17	8		T16	2		T23	1
all_values[8]	477	1			T17	14		T18	1		T16	2
all_values[9]	487	1			T4	2		T17	5		T18	3
all_values[10]	479	1			T20	1		T17	10		T23	1
all_values[11]	453	1			T17	5		T18	4		T25	2
all_values[12]	480	1			T4	1		T20	2		T17	10
all_values[13]	488	1			T20	1		T17	5		T16	2
all_values[14]	491	1			T4	3		T17	8		T18	2
all_values[15]	451	1			T4	1		T20	2		T17	9
all_values[16]	469	1			T17	8		T18	1		T15	2
all_values[17]	491	1			T4	3		T3	1		T17	8
all_values[18]	467	1			T17	12		T16	2		T23	2
all_values[19]	481	1			T20	1		T17	10		T18	2
all_values[20]	461	1			T4	2		T3	1		T17	13
all_values[21]	500	1			T4	1		T20	1		T17	12
all_values[22]	457	1			T20	1		T17	9		T18	2
all_values[23]	463	1			T4	1		T3	1		T20	1
all_values[24]	468	1			T4	1		T17	9		T18	2
all_values[25]	464	1			T4	1		T20	1		T17	12
all_values[26]	487	1			T17	11		T15	1		T16	2